video: tegra: dsi: fix unused variable warning
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31 #include <mach/nvhost.h>
32 #include <../gpio-names.h>
33
34 #include "dc_reg.h"
35 #include "dc_priv.h"
36 #include "dsi_regs.h"
37 #include "dsi.h"
38
39 #define DSI_USE_SYNC_POINTS 1
40
41 #define DSI_STOP_DC_DURATION_MSEC 1000
42
43 #define DSI_MODULE_NOT_INIT             0x0
44 #define DSI_MODULE_INIT                 0x1
45
46 #define DSI_LPHS_NOT_INIT               0x0
47 #define DSI_LPHS_IN_LP_MODE             0x1
48 #define DSI_LPHS_IN_HS_MODE             0x2
49
50 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
51 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
52 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
53
54 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
55 #define DSI_DRIVEN_MODE_DC              0x1
56 #define DSI_DRIVEN_MODE_HOST            0x2
57
58 #define DSI_PHYCLK_OUT_DIS              0x0
59 #define DSI_PHYCLK_OUT_EN               0x1
60
61 #define DSI_PHYCLK_NOT_INIT             0x0
62 #define DSI_PHYCLK_CONTINUOUS           0x1
63 #define DSI_PHYCLK_TX_ONLY              0x2
64
65 #define DSI_CLK_BURST_NOT_INIT          0x0
66 #define DSI_CLK_BURST_NONE_BURST        0x1
67 #define DSI_CLK_BURST_BURST_MODE        0x2
68
69 #define DSI_DC_STREAM_DISABLE           0x0
70 #define DSI_DC_STREAM_ENABLE            0x1
71
72 struct dsi_status {
73         unsigned        init:2;
74
75         unsigned        lphs:2;
76
77         unsigned        vtype:2;
78         unsigned        driven:2;
79
80         unsigned        clk_out:2;
81         unsigned        clk_mode:2;
82         unsigned        clk_burst:2;
83
84         unsigned        dc_stream:1;
85 };
86
87 /* source of video data */
88 enum{
89         TEGRA_DSI_DRIVEN_BY_DC,
90         TEGRA_DSI_DRIVEN_BY_HOST,
91 };
92
93 struct tegra_dc_dsi_data {
94         struct tegra_dc *dc;
95         void __iomem    *base;
96         struct resource *base_res;
97
98         struct clk              *dc_clk;
99         struct clk              *dsi_clk;
100         bool                    clk_ref;
101
102         struct mutex    lock;
103
104         /* data from board info */
105         struct tegra_dsi_out info;
106
107         struct dsi_status       status;
108
109         u8              driven_mode;
110         u8              controller_index;
111
112         u8              pixel_scaler_mul;
113         u8              pixel_scaler_div;
114
115         u32             default_shift_clk_div;
116         u32             default_pixel_clk_khz;
117         u32             default_hs_clk_khz;
118
119         u32             shift_clk_div;
120         u32             target_hs_clk_khz;
121         u32             target_lp_clk_khz;
122
123         u32             syncpt_id;
124         u32             syncpt_val;
125
126         u16             current_bit_clk_ns;
127         u32             current_dsi_clk_khz;
128
129         u32             dsi_control_val;
130
131         bool            ulpm;
132         bool            enabled;
133 };
134
135 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
136         DSI_PKT_SEQ_0_LO,
137         DSI_PKT_SEQ_0_HI,
138         DSI_PKT_SEQ_1_LO,
139         DSI_PKT_SEQ_1_HI,
140         DSI_PKT_SEQ_2_LO,
141         DSI_PKT_SEQ_2_HI,
142         DSI_PKT_SEQ_3_LO,
143         DSI_PKT_SEQ_3_HI,
144         DSI_PKT_SEQ_4_LO,
145         DSI_PKT_SEQ_4_HI,
146         DSI_PKT_SEQ_5_LO,
147         DSI_PKT_SEQ_5_HI,
148 };
149
150 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
151         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
152         0,
153         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
154         0,
155         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
156         0,
157         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
158                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
159         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
160                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
164                 PKT_ID2(CMD_HE) | PKT_LEN2(0),
165         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
166                 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
167 };
168
169 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
170         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
171         0,
172         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
175         0,
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
177                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
178         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
180         0,
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
182                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
183         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
184 };
185
186 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
187         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
188         0,
189         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
194         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
195         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
199         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
200         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
201 };
202
203 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
204         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
205         0,
206         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
207         0,
208         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
213         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
214         0,
215         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
216         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
217         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
218 };
219
220 /* TODO: verify with hw about this format */
221 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
222         0,
223         0,
224         0,
225         0,
226         0,
227         0,
228         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
229         0,
230         0,
231         0,
232         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
233         0,
234 };
235
236 const u32 init_reg[] = {
237         DSI_INT_ENABLE,
238         DSI_INT_STATUS,
239         DSI_INT_MASK,
240         DSI_INIT_SEQ_DATA_0,
241         DSI_INIT_SEQ_DATA_1,
242         DSI_INIT_SEQ_DATA_2,
243         DSI_INIT_SEQ_DATA_3,
244         DSI_DCS_CMDS,
245         DSI_PKT_SEQ_0_LO,
246         DSI_PKT_SEQ_1_LO,
247         DSI_PKT_SEQ_2_LO,
248         DSI_PKT_SEQ_3_LO,
249         DSI_PKT_SEQ_4_LO,
250         DSI_PKT_SEQ_5_LO,
251         DSI_PKT_SEQ_0_HI,
252         DSI_PKT_SEQ_1_HI,
253         DSI_PKT_SEQ_2_HI,
254         DSI_PKT_SEQ_3_HI,
255         DSI_PKT_SEQ_4_HI,
256         DSI_PKT_SEQ_5_HI,
257         DSI_CONTROL,
258         DSI_HOST_DSI_CONTROL,
259         DSI_PAD_CONTROL,
260         DSI_PAD_CONTROL_CD,
261         DSI_SOL_DELAY,
262         DSI_MAX_THRESHOLD,
263         DSI_TRIGGER,
264         DSI_TX_CRC,
265         DSI_INIT_SEQ_CONTROL,
266         DSI_PKT_LEN_0_1,
267         DSI_PKT_LEN_2_3,
268         DSI_PKT_LEN_4_5,
269         DSI_PKT_LEN_6_7,
270 };
271
272 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
273 {
274         return readl(dsi->base + reg * 4);
275 }
276 EXPORT_SYMBOL(tegra_dsi_readl);
277
278 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
279 {
280         writel(val, dsi->base + reg * 4);
281 }
282 EXPORT_SYMBOL(tegra_dsi_writel);
283
284 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
285 {
286         u32 val;
287         int ret;
288
289         ret = 0;
290
291         dsi->syncpt_val = nvhost_syncpt_read(
292                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
293
294         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
295                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
296         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
297
298         /* TODO: Use interrupt rather than polling */
299         ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
300                 dsi->syncpt_id, dsi->syncpt_val + 1);
301         if (ret < 0) {
302                 printk(KERN_ERR "DSI sync point failure\n");
303                 goto fail;
304         }
305
306         (dsi->syncpt_val)++;
307         return 0;
308 fail:
309         return ret;
310 }
311
312 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
313 {
314         u32 dsi_clock_rate_khz;
315
316         switch (dsi->info.video_burst_mode) {
317         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
318         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
319         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
320         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
321                 /* Calculate DSI HS clock rate for DSI burst mode */
322                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
323                                                         dsi->shift_clk_div;
324                 break;
325         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
326         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
327         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
328         default:
329                 /* Clock rate is default DSI clock rate for non-burst mode */
330                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
331                 break;
332         }
333
334         return dsi_clock_rate_khz;
335 }
336
337 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi)
338 {
339         u32 dsi_clock_rate_khz;
340
341         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
342                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
343                         dsi_clock_rate_khz =
344                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
345                 else
346                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
347         else
348                 dsi_clock_rate_khz = dsi->info.lp_cmd_mode_freq_khz;
349
350         return dsi_clock_rate_khz;
351 }
352
353 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
354 {
355         u32 shift_clk_div;
356         u32 max_shift_clk_div;
357         u32 burst_width;
358         u32 burst_width_max;
359
360         /* Get the real value of default shift_clk_div. default_shift_clk_div
361          * holds the real value of shift_clk_div. */
362         shift_clk_div = dsi->default_shift_clk_div;
363
364         /* Calculate shift_clk_div which can matche the video_burst_mode.*/
365         if (dsi->info.video_burst_mode >=
366                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
367                 /* The max_shift_clk_div is multiplied by 10 to save the
368                  * fraction */
369                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
370                         max_shift_clk_div = dsi->info.max_panel_freq_khz
371                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
372                 else
373                         max_shift_clk_div = shift_clk_div * 10;
374
375                 burst_width = dsi->info.video_burst_mode
376                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
377                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
378                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
379
380                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
381                         burst_width / (burst_width_max * 10) + shift_clk_div;
382         }
383
384         return shift_clk_div;
385 }
386
387 static void tegra_dsi_init_sw(struct tegra_dc *dc,
388                                                 struct tegra_dc_dsi_data *dsi)
389 {
390         u32 h_width_pixels;
391         u32 v_width_lines;
392         u32 pixel_clk_hz;
393         u32 byte_clk_hz;
394         u32 plld_clk_mhz;
395
396         switch (dsi->info.pixel_format) {
397         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
398                 /* 2 bytes per pixel */
399                 dsi->pixel_scaler_mul = 2;
400                 dsi->pixel_scaler_div = 1;
401                 break;
402         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
403                 /* 2.25 bytes per pixel */
404                 dsi->pixel_scaler_mul = 9;
405                 dsi->pixel_scaler_div = 4;
406                 break;
407         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
408         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
409                 /* 3 bytes per pixel */
410                 dsi->pixel_scaler_mul = 3;
411                 dsi->pixel_scaler_div = 1;
412                 break;
413         default:
414                 break;
415         }
416
417         dsi->controller_index = dc->ndev->id;
418         dsi->ulpm = false;
419         dsi->enabled = false;
420         dsi->clk_ref = false;
421
422         dsi->dsi_control_val =
423                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
424                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
425                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
426                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
427
428         /* Below we are going to calculate dsi and dc clock rate.
429          * Calcuate the horizontal and vertical width. */
430         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
431                         dc->mode.h_sync_width + dc->mode.h_active;
432         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
433                         dc->mode.v_sync_width + dc->mode.v_active;
434
435         /* Calculate minimum required pixel rate. */
436         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
437
438         dc->pixel_clk = pixel_clk_hz;
439
440         /* Calculate minimum byte rate on DSI interface. */
441         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
442                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
443
444         /* Round up to multiple of mega hz. */
445         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
446                                                                 1000000);
447
448         /* Calculate default real shift_clk_div. */
449         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
450                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
451                 dsi->info.n_data_lanes);
452         /* Calculate default DSI hs clock. DSI interface is double data rate.
453          * Data is transferred on both rising and falling edge of clk, div by 2
454          * to get the actual clock rate.
455          * */
456         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
457         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
458                                                 / dsi->default_shift_clk_div;
459
460         /* Get the actual shift_clk_div and clock rates. */
461         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
462         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi);
463         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
464
465         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
466                                                         dsi->target_hs_clk_khz);
467
468         dsi->controller_index = dc->ndev->id;
469
470 #if DSI_USE_SYNC_POINTS
471         dsi->syncpt_id = NVSYNCPT_DSI;
472 #endif
473
474         /*
475          * Force video clock to be continuous mode if
476          * enable_hs_clock_on_lp_cmd_mode is set
477          */
478         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
479                 if (dsi->info.video_clock_mode !=
480                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
481                         printk("Force to clock continuous mode\n");
482
483                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
484         }
485
486 }
487
488 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
489                                 struct dsi_phy_timing_inclk *phy_timing_clk,
490                                 u32 clk_ns)
491 {
492
493         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
494                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
495                         (T_HSEXIT_DEFAULT(clk_ns));
496
497         phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ?
498                         (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
499                         (T_HSTRAIL_DEFAULT(clk_ns));
500
501         phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ?
502                         (dsi->info.phy_timing.t_datzero_ns / clk_ns) :
503                         (T_DATZERO_DEFAULT(clk_ns));
504
505         phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ?
506                         (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) :
507                         (T_HSPREPR_DEFAULT(clk_ns));
508
509         phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ?
510                                 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) :
511                                 (T_CLKTRAIL_DEFAULT(clk_ns));
512
513         phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ?
514                                 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) :
515                                 (T_CLKPOST_DEFAULT(clk_ns));
516
517         phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ?
518                                 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) :
519                                 (T_CLKZERO_DEFAULT(clk_ns));
520
521         phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ?
522                                 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) :
523                                 (T_TLPX_DEFAULT(clk_ns));
524
525         phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns);
526         phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns);
527         phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns);
528
529         phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx;
530         phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx;
531         phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx;
532 }
533
534 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
535 {
536         u32 val;
537         struct dsi_phy_timing_inclk     phy_timing;
538
539         tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns);
540
541         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
542                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
543                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
544                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr);
545         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
546
547         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
548                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
549                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
550                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
551         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
552
553         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
554                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
555                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
556         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
557
558         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
559                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
560                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
561         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
562 }
563
564 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
565                                                 struct tegra_dc_dsi_data *dsi)
566 {
567         u32 dsi_to_pixel_clk_ratio;
568         u32 temp;
569         u32 temp1;
570         u32 mipi_clk_adj_kHz;
571         u32 sol_delay;
572         struct tegra_dc_mode *dc_modes = &dc->mode;
573
574         /* Get Fdsi/Fpixel ration (note: Fdsi si in bit format) */
575         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
576                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
577
578         /* Convert Fdsi to byte format */
579         dsi_to_pixel_clk_ratio *= 1000/8;
580
581         /* Multiplying by 1000 so that we don't loose the fraction part */
582         temp = dc_modes->h_active * 1000;
583         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
584                         dc_modes->h_sync_width;
585
586         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
587                         temp * dsi->pixel_scaler_mul /
588                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
589
590         /* Do rounding on sol delay */
591         sol_delay = (sol_delay + 1000 - 1)/1000;
592
593         /* TODO:
594          * 1. find out the correct sol fifo depth to use
595          * 2. verify with hw about the clamping function
596          */
597         if (sol_delay > (480 * 4)) {
598                 sol_delay = (480 * 4);
599                 mipi_clk_adj_kHz = sol_delay +
600                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
601                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
602
603                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
604
605                 mipi_clk_adj_kHz *= 4;
606         }
607
608         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
609
610         return sol_delay;
611 }
612
613 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
614                                                 struct tegra_dc_dsi_data *dsi)
615 {
616         u32 sol_delay;
617
618         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
619                 dsi->info.video_burst_mode ==
620                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
621                 sol_delay = NUMOF_BIT_PER_BYTE * dsi->pixel_scaler_mul /
622                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
623                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
624         } else {
625                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
626                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
627         }
628
629         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
630                                                                 DSI_SOL_DELAY);
631 }
632
633 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
634 {
635         u32 val;
636         u32 bytes_per_frame;
637         u32 timeout = 0;
638
639         /* TODO: verify the following eq */
640         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
641                                                 (dsi->info.refresh_rate * 8);
642         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
643         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
644
645         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
646                         DSI_TIMEOUT_0_HTX_TO(timeout);
647         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
648
649         if (dsi->info.panel_reset_timeout_msec)
650                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
651                                         / dsi->current_bit_clk_ns;
652         else
653                 timeout = DSI_PR_TO_VALUE;
654
655         val = DSI_TIMEOUT_1_PR_TO(timeout) |
656                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
657         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
658
659         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
660                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
661                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
662                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
663         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
664 }
665
666 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
667                                                 struct tegra_dc_dsi_data *dsi)
668 {
669         u32 val;
670         u32 hact_pkt_len;
671         u32 hsa_pkt_len;
672         u32 hbp_pkt_len;
673         u32 hfp_pkt_len;
674
675         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
676                                                         dsi->pixel_scaler_div;
677         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
678                                                         dsi->pixel_scaler_div;
679         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
680                                                         dsi->pixel_scaler_div;
681         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
682                                                         dsi->pixel_scaler_div;
683
684         if (dsi->info.video_burst_mode !=
685                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
686                 hbp_pkt_len += hsa_pkt_len;
687
688         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
689         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
690         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
691
692         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
693                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
694         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
695
696         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
697                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
698         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
699
700         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
701                         DSI_PKT_LEN_4_5_LENGTH_5(0);
702         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
703
704         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
705         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
706 }
707
708 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
709                                                 struct tegra_dc_dsi_data *dsi)
710 {
711         unsigned long   val;
712         unsigned long   act_bytes;
713
714         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
715                         dsi->pixel_scaler_div + 1;
716
717         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
718         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
719
720         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
721         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
722
723         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
724         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
725
726         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
727         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
728 }
729
730 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
731                                                 struct tegra_dc_dsi_data *dsi)
732 {
733         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
734                 return;
735
736         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
737                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
738         else
739                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
740 }
741
742 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
743                                                 struct tegra_dc_dsi_data *dsi)
744 {
745         const u32 *pkt_seq;
746         u32 rgb_info;
747         u32 pkt_seq_3_5_rgb_lo;
748         u32 pkt_seq_3_5_rgb_hi;
749         u32     val;
750         u32 reg;
751         u8  i;
752
753         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
754                 return;
755
756         switch (dsi->info.pixel_format) {
757         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
758                 rgb_info = CMD_RGB_16BPP;
759                 break;
760         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
761                 rgb_info = CMD_RGB_18BPP;
762                 break;
763         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
764                 rgb_info = CMD_RGB_18BPPNP;
765                 break;
766         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
767         default:
768                 rgb_info = CMD_RGB_24BPP;
769                 break;
770         }
771
772         pkt_seq_3_5_rgb_lo = 0;
773         pkt_seq_3_5_rgb_hi = 0;
774         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
775                 pkt_seq = dsi_pkt_seq_cmd_mode;
776         else {
777                 switch (dsi->info.video_burst_mode) {
778                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
779                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
780                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
781                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
782                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
783                         pkt_seq_3_5_rgb_lo =
784                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
785                         if (!dsi->info.no_pkt_seq_eot)
786                                 pkt_seq = dsi_pkt_seq_video_burst;
787                         else
788                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
789                         break;
790                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
791                         pkt_seq_3_5_rgb_hi =
792                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
793                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
794                         break;
795                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
796                 default:
797                         pkt_seq_3_5_rgb_lo =
798                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
799                         pkt_seq = dsi_pkt_seq_video_non_burst;
800                         break;
801                 }
802         }
803
804         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
805                 val = pkt_seq[i];
806                 reg = dsi_pkt_seq_reg[i];
807                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
808                         val |= pkt_seq_3_5_rgb_lo;
809                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
810                         val |= pkt_seq_3_5_rgb_hi;
811                 tegra_dsi_writel(dsi, val, reg);
812         }
813 }
814
815 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
816                                                 struct tegra_dc_dsi_data *dsi)
817 {
818         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
819         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
820         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
821
822         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
823 }
824
825 void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
826                                                 struct tegra_dc_dsi_data *dsi)
827 {
828         int val;
829         long timeout;
830
831         /* stop dc */
832         tegra_dsi_stop_dc_stream(dc, dsi);
833
834         /* enable vblank interrupt */
835         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
836         val |= V_BLANK_INT;
837         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
838
839         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
840         val |= V_BLANK_INT;
841         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
842
843         /* wait for vblank completion */
844         timeout = wait_for_completion_interruptible_timeout(
845                 &dc->vblank_complete, DSI_STOP_DC_DURATION_MSEC);
846
847         /* disable vblank interrupt */
848         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
849         val &= ~V_BLANK_INT;
850         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
851
852         if (timeout == 0)
853                 printk("Warning: dc dosen't stop at the end of the frame.\n");
854 }
855
856 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
857                                                 struct tegra_dc_dsi_data *dsi)
858 {
859         u32 val;
860
861         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
862
863         /* TODO: clean up */
864         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
865                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
866                         DC_CMD_DISPLAY_POWER_CONTROL);
867
868         /* Configure one-shot mode or continuous mode */
869         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
870                 /* disable LSPI/LCD_DE output */
871                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
872                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
873
874                 /* enable MSF & set MSF polarity */
875                 val = MSF_ENABLE | MSF_LSPI;
876                 if (!dsi->info.te_polarity_low)
877                         val |= MSF_POLARITY_HIGH;
878                 else
879                         val |= MSF_POLARITY_LOW;
880                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
881
882                 /* set non-continuous mode */
883                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
884                                                 DC_CMD_DISPLAY_COMMAND);
885                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
886                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
887                                                 DC_CMD_STATE_CONTROL);
888         } else {
889                 /* set continuous mode */
890                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
891                                                 DC_CMD_DISPLAY_COMMAND);
892                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
893                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
894         }
895
896         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
897 }
898
899 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
900                                                 struct tegra_dc_dsi_data *dsi)
901 {
902         u32 shift_clk_div_register;
903         u32 val;
904
905         /* Get the corresponding register value of shift_clk_div. */
906         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
907
908 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
909         shift_clk_div_register = 1;
910 #endif
911
912         /* TODO: find out if PCD3 option is required */
913         val = PIXEL_CLK_DIVIDER_PCD1 |
914                                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
915         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
916 }
917
918 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
919                                         struct tegra_dc_dsi_data *dsi, u32 clk)
920 {
921         u32 rm;
922
923         rm = clk % 1000;
924         if (rm != 0)
925                 clk -= rm;
926
927         clk *= 2;       /*
928                          * Value for PLLD routine is required to be twice as
929                          * the desired clock rate
930                          */
931
932         dc->mode.pclk = clk*1000;
933         tegra_dc_setup_clk(dc, dsi->dsi_clk);
934         if (dsi->clk_ref == true)
935                 clk_disable(dsi->dsi_clk);
936         else
937                 dsi->clk_ref = true;
938         clk_enable(dsi->dsi_clk);
939         tegra_periph_reset_deassert(dsi->dsi_clk);
940
941         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
942
943         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
944 }
945
946 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
947 {
948         u32 val;
949
950         val = tegra_dsi_readl(dsi, DSI_CONTROL);
951         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
952
953         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
954                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
955                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
956         } else {
957                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
958                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
959         }
960         tegra_dsi_writel(dsi, val, DSI_CONTROL);
961
962         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
963         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
964         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
965         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
966
967         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
968 }
969
970 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
971 {
972         u32 val;
973         tegra_dsi_hs_clk_out_enable(dsi);
974
975         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
976         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
977         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
978         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
979 }
980
981 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
982                                                 struct tegra_dc_dsi_data *dsi)
983 {
984         u32 val;
985
986         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
987                 tegra_dsi_stop_dc_stream(dc, dsi);
988
989         val = tegra_dsi_readl(dsi, DSI_CONTROL);
990         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
991         val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
992         tegra_dsi_writel(dsi, val, DSI_CONTROL);
993
994         /* TODO: issue a cmd */
995
996         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
997         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
998         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
999         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1000
1001         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1002         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1003 }
1004
1005 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1006 {
1007         u32 dsi_control;
1008         u32 host_dsi_control;
1009         u32 max_threshold;
1010
1011         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1012         host_dsi_control = HOST_DSI_CTRL_COMMON |
1013                         HOST_DSI_CTRL_HOST_DRIVEN |
1014                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1015         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1016
1017         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1018         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1019         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1020
1021         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1022         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1023         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1024 }
1025
1026 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1027 {
1028         u32 dsi_control;
1029         u32 host_dsi_control;
1030         u32 max_threshold;
1031         u32 dcs_cmd;
1032
1033         dsi_control = dsi->dsi_control_val;
1034         host_dsi_control = HOST_DSI_CTRL_COMMON;
1035         max_threshold = 0;
1036         dcs_cmd = 0;
1037
1038         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1039                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1040                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1041                 max_threshold =
1042                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1043                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1044         } else {
1045                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1046                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1047                 max_threshold =
1048                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1049                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1050         }
1051
1052         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1053                 dsi_control |= DSI_CTRL_CMD_MODE;
1054                 host_dsi_control |= HOST_DSI_CTRL_CMD_MODE;
1055                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1056                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1057                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1058
1059         } else {
1060                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1061                 host_dsi_control |= HOST_DSI_CTRL_VIDEO_MODE;
1062                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1063         }
1064
1065         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1066         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1067         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1068         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1069 }
1070
1071 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1072                                                 struct tegra_dc_dsi_data *dsi)
1073 {
1074         u32 val;
1075         u32 i;
1076
1077         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1078         if (dsi->info.dsi_instance) {
1079                 /* TODO:Set the misc register*/
1080         }
1081
1082         /* TODO: only need to change the timing for bta */
1083         tegra_dsi_set_phy_timing(dsi);
1084
1085         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1086                 tegra_dsi_stop_dc_stream(dc, dsi);
1087
1088         /* Initializing DSI registers */
1089         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1090                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1091
1092         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1093         /* Initialize DSI_PAD_CONTROL register. */
1094         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1095                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1096                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1097                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1098                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1099
1100         if (!dsi->ulpm) {
1101                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1102                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1103                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1104         } else {
1105                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1106                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1107                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1108         }
1109         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1110
1111         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1112         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1113
1114         while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val)
1115                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1116
1117         dsi->status.init = DSI_MODULE_INIT;
1118         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1119         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1120         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1121         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1122         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1123         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1124         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1125
1126         return 0;
1127 }
1128
1129 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1130                                                 struct tegra_dc_dsi_data *dsi)
1131 {
1132         int     err;
1133
1134         if (dsi->status.init != DSI_MODULE_INIT) {
1135                 err = -EPERM;
1136                 goto fail;
1137         }
1138
1139         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE)
1140                 goto success;
1141
1142         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1143                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1144
1145         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1146         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1147                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1148                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1149
1150         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1151                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1152                 tegra_dsi_set_timeout(dsi);
1153         }
1154
1155         tegra_dsi_set_control_reg_lp(dsi);
1156
1157         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1158                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1159                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1160
1161 success:
1162         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1163         err = 0;
1164 fail:
1165         return err;
1166 }
1167
1168 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1169                                                 struct tegra_dc_dsi_data *dsi)
1170 {
1171         int err;
1172
1173         if (dsi->status.init != DSI_MODULE_INIT) {
1174                 err = -EPERM;
1175                 goto fail;
1176         }
1177
1178         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1179                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1180
1181         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1182                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1183                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1184
1185         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1186                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1187                 tegra_dsi_set_timeout(dsi);
1188         }
1189
1190         tegra_dsi_set_phy_timing(dsi);
1191
1192         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1193                 tegra_dsi_set_pkt_seq(dc, dsi);
1194                 tegra_dsi_set_pkt_length(dc, dsi);
1195                 tegra_dsi_set_sol_delay(dc, dsi);
1196                 tegra_dsi_set_dc_clk(dc, dsi);
1197         }
1198
1199         tegra_dsi_set_control_reg_hs(dsi);
1200
1201         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
1202                 tegra_dsi_hs_clk_out_enable(dsi);
1203
1204         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1205         err = 0;
1206 fail:
1207         return err;
1208 }
1209
1210 static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1211 {
1212         u32 timeout = 0;
1213         bool retVal;
1214
1215         retVal = false;
1216         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1217                 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1218                         retVal = true;
1219                         break;
1220                 }
1221                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1222                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1223         }
1224
1225         return retVal;
1226 }
1227
1228 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1229 {
1230         int status = 0;
1231
1232         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1233                 status = -EBUSY;
1234                 goto fail;
1235         }
1236
1237         tegra_dsi_writel(dsi,
1238                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1239
1240 #if DSI_USE_SYNC_POINTS
1241         status = tegra_dsi_syncpt(dsi);
1242         if (status < 0) {
1243                 printk(KERN_ERR "DSI syncpt for host trigger failed\n");
1244                 goto fail;
1245         }
1246 #else
1247         if (!tegra_dsi_is_controller_idle(dsi))
1248                 status = -EIO;
1249 #endif
1250
1251 fail:
1252         return status;
1253 }
1254
1255 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1256                                         u8 *pdata, u8 data_id, u16 data_len)
1257 {
1258         u8 virtual_channel;
1259         u8 *pval;
1260         u32 val;
1261         int err;
1262
1263         err = 0;
1264
1265         virtual_channel = dsi->info.virtual_channel <<
1266                                                 DSI_VIR_CHANNEL_BIT_POSITION;
1267
1268         /* always use hw for ecc */
1269         val = (virtual_channel | data_id) << 0 |
1270                         data_len << 8;
1271         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1272
1273         /* if pdata != NULL, pkt type is long pkt */
1274         if (pdata != NULL) {
1275                 while (data_len) {
1276                         if (data_len >= 4) {
1277                                 val = ((u32 *) pdata)[0];
1278                                 data_len -= 4;
1279                                 pdata += 4;
1280                         } else {
1281                                 val = 0;
1282                                 pval = (u8 *) &val;
1283                                 do
1284                                         *pval++ = *pdata++;
1285                                 while (--data_len);
1286                         }
1287                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1288                 }
1289         }
1290
1291         err = tegra_dsi_host_trigger(dsi);
1292         if (err < 0)
1293                 printk(KERN_ERR "DSI host trigger failed\n");
1294
1295         return err;
1296 }
1297
1298 int tegra_dsi_write_data(struct tegra_dc *dc,
1299                                         struct tegra_dc_dsi_data *dsi,
1300                                         u8 *pdata, u8 data_id, u16 data_len)
1301 {
1302         bool switch_back_to_hs_mode;
1303         bool switch_back_to_dc_mode;
1304         int err;
1305
1306         err = 0;
1307         switch_back_to_hs_mode = false;
1308         switch_back_to_dc_mode = false;
1309
1310         if ((dsi->status.init != DSI_MODULE_INIT) ||
1311                 (dsi->status.lphs == DSI_LPHS_NOT_INIT)) {
1312                 err = -EPERM;
1313                 goto fail;
1314         }
1315
1316         if (!tegra_dsi_is_controller_idle(dsi)) {
1317                 err = -EBUSY;
1318                 goto fail;
1319         }
1320
1321         err = 0;
1322
1323         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1324                 if (dsi->info.hs_cmd_mode_supported) {
1325                         if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1326                                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1327                                 tegra_dsi_set_to_hs_mode(dc, dsi);
1328                                 switch_back_to_dc_mode = true;
1329                         }
1330                 } else {
1331                         tegra_dsi_set_to_lp_mode(dc, dsi);
1332                         switch_back_to_hs_mode = true;
1333                 }
1334         }
1335
1336         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1337
1338
1339         if (switch_back_to_dc_mode)
1340                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1341         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1342                 tegra_dsi_set_to_hs_mode(dc, dsi);
1343
1344 fail:
1345         return err;
1346 }
1347 EXPORT_SYMBOL(tegra_dsi_write_data);
1348
1349 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1350                                                 struct tegra_dc_dsi_data *dsi,
1351                                                 struct tegra_dsi_cmd *cmd,
1352                                                 u32 n_cmd)
1353 {
1354         u32 i;
1355         int err;
1356
1357         err = 0;
1358         for (i = 0; i < n_cmd; i++) {
1359                 struct tegra_dsi_cmd *cur_cmd;
1360                 cur_cmd = &cmd[i];
1361
1362                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1363                         mdelay(cur_cmd->sp_len_dly.delay_ms);
1364                 else {
1365                         err = tegra_dsi_write_data(dc, dsi,
1366                                                 cur_cmd->pdata,
1367                                                 cur_cmd->data_id,
1368                                                 cur_cmd->sp_len_dly.data_len);
1369                         if (err < 0)
1370                                 break;
1371                 }
1372         }
1373         return err;
1374 }
1375
1376 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1377 {
1378         u32 val;
1379         u32 poll_time;
1380         int err;
1381
1382         poll_time = 0;
1383         err = 0;
1384
1385         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1386         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1387         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1388
1389 #if DSI_USE_SYNC_POINTS
1390         /* FIXME: Workaround for nvhost_syncpt_read */
1391         dsi->syncpt_val = nvhost_syncpt_update_min(
1392                         &dsi->dc->ndev->host->syncpt, dsi->syncpt_id);
1393
1394         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
1395                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
1396         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
1397
1398         /* TODO: Use interrupt rather than polling */
1399         err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1400                 dsi->syncpt_id, dsi->syncpt_val + 1);
1401         if (err < 0)
1402                 printk(KERN_ERR "DSI sync point failure\n");
1403         else
1404                 (dsi->syncpt_val)++;
1405 #else
1406         while (poll_time <  DSI_STATUS_POLLING_DURATION_USEC) {
1407                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1408                 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1409                 if (!val)
1410                         break;
1411                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1412                 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1413         }
1414         if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1415                 err = -EBUSY;
1416 #endif
1417
1418         return err;
1419 }
1420
1421 static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1422                         struct tegra_dc_dsi_data *dsi,
1423                         u32 rd_fifo_cnt,
1424                         u8 *read_fifo)
1425 {
1426         u32 val;
1427         u32 i;
1428
1429         /* Read data from FIFO */
1430         for (i = 0; i < rd_fifo_cnt; i++) {
1431                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1432                 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1433                 memcpy(read_fifo, &val, 4);
1434                 read_fifo += 4;
1435         }
1436
1437         /* Make sure all the data is read from the FIFO */
1438         val = tegra_dsi_readl(dsi, DSI_STATUS);
1439         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1440         if (val)
1441                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1442                 " even after reading FIFO_RD_CNT words from read fifo\n");
1443 }
1444
1445 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1446                                 u32 rd_fifo_cnt, u8 *read_fifo)
1447 {
1448         int err;
1449         u32 payload_size;
1450
1451         payload_size = 0;
1452         err = 0;
1453
1454         printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]);
1455         switch (read_fifo[4] & 0xff) {
1456         case GEN_LONG_RD_RES:
1457                 /* Fall through */
1458         case DCS_LONG_RD_RES:
1459                 payload_size = (read_fifo[5] |
1460                                 (read_fifo[6] << 8)) & 0xFFFF;
1461                 printk(KERN_INFO "Long read response Packet\n"
1462                                 "payload_size[0x%x]\n", payload_size);
1463                 break;
1464         case GEN_1_BYTE_SHORT_RD_RES:
1465                 /* Fall through */
1466         case DCS_1_BYTE_SHORT_RD_RES:
1467                 payload_size = 1;
1468                 printk(KERN_INFO "Short read response Packet\n"
1469                         "payload_size[0x%x]\n", payload_size);
1470                 break;
1471         case GEN_2_BYTE_SHORT_RD_RES:
1472                 /* Fall through */
1473         case DCS_2_BYTE_SHORT_RD_RES:
1474                 payload_size = 2;
1475                 printk(KERN_INFO "Short read response Packet\n"
1476                         "payload_size[0x%x]\n", payload_size);
1477                 break;
1478         case ACK_ERR_RES:
1479                 payload_size = 2;
1480                 printk(KERN_INFO "Acknowledge error report response\n"
1481                         "Packet payload_size[0x%x]\n", payload_size);
1482                 break;
1483         default:
1484                 /*reading from RD_FIFO_COUNT*/
1485                 printk(KERN_INFO "Invalid read response payload_size\n");
1486                 err = -EINVAL;
1487                 break;
1488         }
1489         return err;
1490 }
1491
1492 int tegra_dsi_read_data(struct tegra_dc *dc,
1493                                 struct tegra_dc_dsi_data *dsi,
1494                                 u32 max_ret_payload_size,
1495                                 u32 panel_reg_addr, u8 *read_data)
1496 {
1497         u32 val;
1498         int err;
1499         u32 poll_time;
1500         u32 rd_fifo_cnt;
1501         bool switch_back_to_hs_mode;
1502         bool restart_dc_stream;
1503         bool switch_back_to_dc_mode;
1504
1505         err = 0;
1506         switch_back_to_hs_mode = false;
1507         restart_dc_stream = false;
1508         switch_back_to_dc_mode = false;
1509
1510         if ((dsi->status.init != DSI_MODULE_INIT) ||
1511                 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1512                 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) {
1513                 err = -EPERM;
1514                 goto fail;
1515         }
1516
1517         val = tegra_dsi_readl(dsi, DSI_STATUS);
1518         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1519         if (val) {
1520                 err = -EBUSY;
1521                 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1522                 goto fail;
1523         }
1524
1525         if (!tegra_dsi_is_controller_idle(dsi)) {
1526                 err = -EBUSY;
1527                 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n");
1528                 goto fail;
1529         }
1530
1531         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1532                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1533                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1534                                 restart_dc_stream = true;
1535                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1536                         switch_back_to_dc_mode = true;
1537                         if (dsi->info.hs_cmd_mode_supported) {
1538                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1539                                 if (err < 0) {
1540                                         dev_err(&dc->ndev->dev,
1541                                         "DSI failed to go to HS mode host driven\n");
1542                                         goto fail;
1543                                 }
1544                         }
1545                 }
1546                 if (!dsi->info.hs_cmd_mode_supported) {
1547                         err = tegra_dsi_set_to_lp_mode(dc, dsi);
1548                         if (err < 0) {
1549                                 dev_err(&dc->ndev->dev,
1550                                 "DSI failed to go to LP mode\n");
1551                                 goto fail;
1552                         }
1553                         switch_back_to_hs_mode = true;
1554                 }
1555         }
1556
1557         /* Set max return payload size in words */
1558         err = _tegra_dsi_write_data(dsi, NULL,
1559                 dsi_command_max_return_pkt_size,
1560                 max_ret_payload_size);
1561         if (err < 0) {
1562                 dev_err(&dc->ndev->dev,
1563                                 "DSI write failed\n");
1564                 goto fail;
1565         }
1566
1567         /* DCS to read given panel register */
1568         err = _tegra_dsi_write_data(dsi, NULL,
1569                 dsi_command_dcs_read_with_no_params,
1570                 panel_reg_addr);
1571         if (err < 0) {
1572                 dev_err(&dc->ndev->dev,
1573                                 "DSI write failed\n");
1574                 goto fail;
1575         }
1576
1577         err = tegra_dsi_bta(dsi);
1578         if (err < 0) {
1579                 dev_err(&dc->ndev->dev,
1580                         "DSI IMM BTA timeout\n");
1581                 goto fail;
1582         }
1583
1584         poll_time = 0;
1585         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
1586                 mdelay(1);
1587                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1588                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1589                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1590                         dev_err(&dc->ndev->dev,
1591                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1592                         break;
1593                 poll_time++;
1594         }
1595
1596         if (rd_fifo_cnt == 0) {
1597                 dev_info(&dc->ndev->dev,
1598                         "DSI RD_FIFO_CNT is zero\n");
1599                 err = -EINVAL;
1600                 goto fail;
1601         }
1602
1603         if (val & DSI_STATUS_LB_UNDERFLOW(0x1) ||
1604                 val & DSI_STATUS_LB_OVERFLOW(0x1)) {
1605                 dev_err(&dc->ndev->dev,
1606                         "DSI overflow/underflow error\n");
1607                 err = -EINVAL;
1608                 goto fail;
1609         }
1610
1611         tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data);
1612
1613         err = tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_data);
1614 fail:
1615         if (switch_back_to_dc_mode)
1616                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1617         if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1618                 tegra_dsi_set_to_hs_mode(dc, dsi);
1619         if (restart_dc_stream)
1620                 tegra_dsi_start_dc_stream(dc, dsi);
1621
1622         return err;
1623 }
1624 EXPORT_SYMBOL(tegra_dsi_read_data);
1625
1626 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1627 {
1628         u32 val;
1629         int ret;
1630
1631         ret = 0;
1632
1633         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1634         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1635         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
1636         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1637
1638 #if DSI_USE_SYNC_POINTS
1639         ret = tegra_dsi_syncpt(dsi);
1640         if (ret < 0) {
1641                 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n");
1642                 goto fail;
1643         }
1644 #else
1645         /* TODO: Find exact delay required */
1646         mdelay(10);
1647 #endif
1648         dsi->ulpm = true;
1649 fail:
1650         return ret;
1651 }
1652
1653 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1654 {
1655         u32 val;
1656         int ret;
1657
1658         ret = 0;
1659
1660         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1661         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
1662         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
1663         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1664
1665 #if DSI_USE_SYNC_POINTS
1666         ret = tegra_dsi_syncpt(dsi);
1667         if (ret < 0) {
1668                 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n");
1669                 goto fail;
1670         }
1671 #else
1672         /* TODO: Find exact delay required */
1673         mdelay(10);
1674 #endif
1675         dsi->ulpm = false;
1676
1677         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1678         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
1679         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
1680         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1681 fail:
1682         return ret;
1683
1684 }
1685
1686 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1687 {
1688         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1689         int err;
1690         u32 val;
1691
1692         tegra_dc_io_start(dc);
1693         mutex_lock(&dsi->lock);
1694
1695         /* Stop DC stream before configuring DSI registers
1696          * to avoid visible glitches on panel during transition
1697          * from bootloader to kernel driver
1698          */
1699         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1700
1701         if (dsi->enabled) {
1702                 if (dsi->ulpm) {
1703                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1704                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1705                                 goto fail;
1706                         }
1707                 }
1708
1709                 if (dsi->info.panel_reset) {
1710                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1711                                                         dsi->info.dsi_init_cmd,
1712                                                         dsi->info.n_init_cmd);
1713                         if (err < 0) {
1714                                 dev_err(&dc->ndev->dev,
1715                                 "dsi: error sending dsi init cmd\n");
1716                                 goto fail;
1717                         }
1718                 } else if (dsi->info.dsi_late_resume_cmd) {
1719                         err = tegra_dsi_send_panel_cmd(dc, dsi,
1720                                                 dsi->info.dsi_late_resume_cmd,
1721                                                 dsi->info.n_late_resume_cmd);
1722                         if (err < 0) {
1723                                 dev_err(&dc->ndev->dev,
1724                                 "dsi: error sending late resume cmd\n");
1725                                 goto fail;
1726                         }
1727                 }
1728         } else {
1729                 err = tegra_dsi_init_hw(dc, dsi);
1730                 if (err < 0) {
1731                         dev_err(&dc->ndev->dev,
1732                                 "dsi: not able to init dsi hardware\n");
1733                         goto fail;
1734                 }
1735
1736                 if (dsi->ulpm) {
1737                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
1738                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
1739                                 goto fail;
1740                         }
1741                         val = DSI_PAD_CONTROL_PAD_PDIO(0) |
1742                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1743                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1744                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1745                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
1746                                 printk(KERN_ERR "DSI failed to exit ulpm\n");
1747                                 goto fail;
1748                         }
1749                 }
1750
1751                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
1752                 if (err < 0) {
1753                         dev_err(&dc->ndev->dev,
1754                                 "dsi: not able to set to lp mode\n");
1755                         goto fail;
1756                 }
1757
1758                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
1759                                                 dsi->info.n_init_cmd);
1760                 if (err < 0) {
1761                         dev_err(&dc->ndev->dev,
1762                                 "dsi: error while sending dsi init cmd\n");
1763                         goto fail;
1764                 }
1765
1766                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1767                 if (err < 0) {
1768                         dev_err(&dc->ndev->dev,
1769                                 "dsi: not able to set to hs mode\n");
1770                         goto fail;
1771                 }
1772
1773                 dsi->enabled = true;
1774         }
1775
1776         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
1777                 tegra_dsi_start_dc_stream(dc, dsi);
1778 fail:
1779         mutex_unlock(&dsi->lock);
1780         tegra_dc_io_end(dc);
1781 }
1782
1783 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
1784 {
1785         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1786
1787         tegra_dsi_init_sw(dc, dsi);
1788         /* TODO: Configure the CSI pad configuration */
1789 }
1790
1791 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
1792                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
1793 {
1794         u16 i;
1795         u16 len;
1796
1797         memcpy(dst, src, sizeof(*dst) * n_cmd);
1798
1799         for (i = 0; i < n_cmd; i++)
1800                 if (src[i].pdata) {
1801                         len = sizeof(*src[i].pdata) *
1802                                         src[i].sp_len_dly.data_len;
1803                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
1804                         if (!dst[i].pdata)
1805                                 goto free_cmd_pdata;
1806                         memcpy(dst[i].pdata, src[i].pdata, len);
1807                 }
1808
1809         return 0;
1810
1811 free_cmd_pdata:
1812         for (--i; i >= 0; i--)
1813                 if (dst[i].pdata)
1814                         kfree(dst[i].pdata);
1815         return -ENOMEM;
1816 }
1817
1818 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
1819                                                 struct tegra_dsi_out *p_dsi)
1820 {
1821         struct tegra_dsi_cmd *p_init_cmd;
1822         struct tegra_dsi_cmd *p_early_suspend_cmd;
1823         struct tegra_dsi_cmd *p_late_resume_cmd;
1824         struct tegra_dsi_cmd *p_suspend_cmd;
1825         int err;
1826
1827         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
1828                 return -EINVAL;
1829
1830         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
1831                                 p_dsi->n_init_cmd, GFP_KERNEL);
1832         if (!p_init_cmd)
1833                 return -ENOMEM;
1834
1835         if (p_dsi->dsi_early_suspend_cmd) {
1836                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
1837                                         p_dsi->n_early_suspend_cmd,
1838                                         GFP_KERNEL);
1839                 if (!p_early_suspend_cmd) {
1840                         err = -ENOMEM;
1841                         goto err_free_init_cmd;
1842                 }
1843         }
1844
1845         if (p_dsi->dsi_late_resume_cmd) {
1846                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
1847                                         p_dsi->n_late_resume_cmd,
1848                                         GFP_KERNEL);
1849                 if (!p_late_resume_cmd) {
1850                         err = -ENOMEM;
1851                         goto err_free_p_early_suspend_cmd;
1852                 }
1853         }
1854
1855         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
1856                                 GFP_KERNEL);
1857         if (!p_suspend_cmd) {
1858                 err = -ENOMEM;
1859                 goto err_free_p_late_resume_cmd;
1860         }
1861
1862         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
1863
1864         /* Copy panel init cmd */
1865         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
1866                                                 p_init_cmd, p_dsi->n_init_cmd);
1867         if (err < 0)
1868                 goto err_free;
1869         dsi->info.dsi_init_cmd = p_init_cmd;
1870
1871         /* Copy panel early suspend cmd */
1872         if (p_dsi->dsi_early_suspend_cmd) {
1873                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
1874                                         p_early_suspend_cmd,
1875                                         p_dsi->n_early_suspend_cmd);
1876                 if (err < 0)
1877                         goto err_free;
1878                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
1879         }
1880
1881         /* Copy panel late resume cmd */
1882         if (p_dsi->dsi_late_resume_cmd) {
1883                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
1884                                                 p_late_resume_cmd,
1885                                                 p_dsi->n_late_resume_cmd);
1886                 if (err < 0)
1887                         goto err_free;
1888                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
1889         }
1890
1891         /* Copy panel suspend cmd */
1892         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
1893                                         p_dsi->n_suspend_cmd);
1894         if (err < 0)
1895                 goto err_free;
1896         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
1897
1898         if (!dsi->info.panel_reset_timeout_msec)
1899                 dsi->info.panel_reset_timeout_msec =
1900                                                 DEFAULT_PANEL_RESET_TIMEOUT;
1901
1902         if (!dsi->info.panel_buffer_size_byte)
1903                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
1904
1905         if (!dsi->info.max_panel_freq_khz) {
1906                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
1907
1908                 if (dsi->info.video_burst_mode >
1909                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
1910                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
1911                                         "is not set for DSI burst mode.\n");
1912                         dsi->info.video_burst_mode =
1913                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
1914                 }
1915         }
1916
1917         if (!dsi->info.lp_cmd_mode_freq_khz)
1918                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
1919
1920         /* host mode is for testing only*/
1921         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1922
1923         return 0;
1924
1925 err_free:
1926         kfree(p_suspend_cmd);
1927 err_free_p_late_resume_cmd:
1928         kfree(p_late_resume_cmd);
1929 err_free_p_early_suspend_cmd:
1930         kfree(p_early_suspend_cmd);
1931 err_free_init_cmd:
1932         kfree(p_init_cmd);
1933         return err;
1934 }
1935
1936 static int tegra_dc_dsi_init(struct tegra_dc *dc)
1937 {
1938         struct tegra_dc_dsi_data *dsi;
1939         struct resource *res;
1940         struct resource *base_res;
1941         void __iomem *base;
1942         struct clk *dc_clk = NULL;
1943         struct clk *dsi_clk = NULL;
1944         struct tegra_dsi_out *dsi_pdata;
1945         int err;
1946
1947         err = 0;
1948
1949         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1950         if (!dsi)
1951                 return -ENOMEM;
1952
1953         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
1954                                         "dsi_regs");
1955         if (!res) {
1956                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
1957                 err = -ENOENT;
1958                 goto err_free_dsi;
1959         }
1960
1961         base_res = request_mem_region(res->start, resource_size(res),
1962                                 dc->ndev->name);
1963         if (!base_res) {
1964                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
1965                 err = -EBUSY;
1966                 goto err_free_dsi;
1967         }
1968
1969         base = ioremap(res->start, resource_size(res));
1970         if (!base) {
1971                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
1972                 err = -EBUSY;
1973                 goto err_release_regs;
1974         }
1975
1976         dsi_pdata = dc->pdata->default_out->dsi;
1977         if (!dsi_pdata) {
1978                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
1979                 goto err_release_regs;
1980         }
1981
1982         if (dsi_pdata->dsi_instance)
1983                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
1984         else
1985                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
1986
1987         if (IS_ERR_OR_NULL(dsi_clk)) {
1988                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
1989                 err = -EBUSY;
1990                 goto err_release_regs;
1991         }
1992
1993         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
1994         if (IS_ERR_OR_NULL(dc_clk)) {
1995                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
1996                         dev_name(&dc->ndev->dev));
1997                 err = -EBUSY;
1998                 goto err_clk_put;
1999         }
2000
2001         mutex_init(&dsi->lock);
2002         dsi->dc = dc;
2003         dsi->base = base;
2004         dsi->base_res = base_res;
2005         dsi->dc_clk = dc_clk;
2006         dsi->dsi_clk = dsi_clk;
2007
2008         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2009         if (err < 0)
2010                 goto err_dsi_data;
2011
2012         tegra_dc_set_outdata(dc, dsi);
2013         _tegra_dc_dsi_init(dc);
2014
2015         return 0;
2016
2017 err_dsi_data:
2018 err_clk_put:
2019         clk_put(dsi_clk);
2020 err_release_regs:
2021         release_resource(base_res);
2022 err_free_dsi:
2023         kfree(dsi);
2024
2025         return err;
2026 }
2027
2028 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2029 {
2030         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2031         u16 i;
2032         u32 val;
2033
2034         mutex_lock(&dsi->lock);
2035
2036         /* free up the pdata*/
2037         for (i = 0; i < dsi->info.n_init_cmd; i++) {
2038                 if (dsi->info.dsi_init_cmd[i].pdata)
2039                         kfree(dsi->info.dsi_init_cmd[i].pdata);
2040         }
2041         kfree(dsi->info.dsi_init_cmd);
2042
2043         /* Disable dc stream*/
2044         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2045                 tegra_dsi_stop_dc_stream(dc, dsi);
2046
2047         /* Disable dsi phy clock*/
2048         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2049                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2050
2051         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2052         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2053
2054         iounmap(dsi->base);
2055         release_resource(dsi->base_res);
2056
2057         clk_put(dsi->dc_clk);
2058         clk_put(dsi->dsi_clk);
2059
2060         mutex_unlock(&dsi->lock);
2061
2062         mutex_destroy(&dsi->lock);
2063         kfree(dsi);
2064 }
2065
2066 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2067 {
2068         int err;
2069         u32 val;
2070         struct clk *base_clk;
2071         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2072
2073         tegra_dc_io_start(dc);
2074         mutex_lock(&dsi->lock);
2075
2076         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2077                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2078
2079         if (dsi->info.power_saving_suspend) {
2080                 if (!dsi->enabled)
2081                         goto fail;
2082
2083                 err = tegra_dsi_set_to_lp_mode(dc, dsi);
2084                 if (err < 0) {
2085                         dev_err(&dc->ndev->dev,
2086                         "DSI failed to go to LP mode\n");
2087                         goto fail;
2088                 }
2089
2090                 err = tegra_dsi_send_panel_cmd(dc, dsi,
2091                                 dsi->info.dsi_suspend_cmd,
2092                                 dsi->info.n_suspend_cmd);
2093                 if (err < 0) {
2094                         dev_err(&dc->ndev->dev,
2095                                 "dsi: Error sending suspend cmd\n");
2096                         goto fail;
2097                 }
2098
2099                 if (!dsi->ulpm) {
2100                         if (tegra_dsi_enter_ulpm(dsi) < 0)
2101                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2102                 }
2103
2104                 /* Suspend pad */
2105                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2106                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2107                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2108                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2109                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2110
2111                 /* Suspend core-logic */
2112                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2113                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2114
2115                 /* Disable phy clock */
2116                 base_clk = clk_get_parent(dsi->dsi_clk);
2117                 if (dsi->info.dsi_instance)
2118                         tegra_clk_cfg_ex(base_clk,
2119                                         TEGRA_CLK_PLLD_CSI_OUT_ENB,
2120                                         0);
2121                 else
2122                         tegra_clk_cfg_ex(base_clk,
2123                                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
2124                                         0);
2125
2126                 /* Disable DSI source clock */
2127                 clk_disable(dsi->dsi_clk);
2128                 dsi->clk_ref = false;
2129                 dsi->enabled = false;
2130         } else {
2131                 if (dsi->info.dsi_early_suspend_cmd) {
2132                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2133                                 dsi->info.dsi_early_suspend_cmd,
2134                                 dsi->info.n_early_suspend_cmd);
2135                         if (err < 0) {
2136                                 dev_err(&dc->ndev->dev,
2137                                 "dsi: Error sending early suspend cmd\n");
2138                                 goto fail;
2139                         }
2140                 }
2141
2142                 if (!dsi->ulpm) {
2143                         if (tegra_dsi_enter_ulpm(dsi) < 0)
2144                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2145                 }
2146         }
2147
2148 fail:
2149         mutex_unlock(&dsi->lock);
2150         tegra_dc_io_end(dc);
2151 }
2152
2153 #ifdef CONFIG_PM
2154 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2155 {
2156         struct tegra_dc_dsi_data *dsi;
2157         int err;
2158         u32 val;
2159
2160         dsi = tegra_dc_get_outdata(dc);
2161
2162         tegra_dc_io_start(dc);
2163         mutex_lock(&dsi->lock);
2164
2165         if (!dsi->enabled)
2166                 goto fail;
2167
2168         if (!dsi->info.power_saving_suspend) {
2169                 if (dsi->ulpm) {
2170                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2171                                 printk(KERN_ERR "DSI failed to exit ulpm");
2172                                 goto fail;
2173                         }
2174                 }
2175
2176                 /* Suspend Panel */
2177                 err = tegra_dsi_send_panel_cmd(dc, dsi,
2178                                 dsi->info.dsi_suspend_cmd,
2179                                 dsi->info.n_suspend_cmd);
2180                 if (err < 0) {
2181                         dev_err(&dc->ndev->dev,
2182                                 "dsi: Error sending suspend cmd\n");
2183                         goto fail;
2184                 }
2185                 if (!dsi->ulpm) {
2186                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2187                                 printk(KERN_ERR "DSI failed to enter ulpm\n");
2188                                 goto fail;
2189                         }
2190                 }
2191
2192                 /* Suspend pad */
2193                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2194                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2195                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2196                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2197                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2198
2199                 /* Suspend core-logic */
2200                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2201                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2202
2203                 dsi->enabled = false;
2204
2205                 clk_disable(dsi->dsi_clk);
2206                 dsi->clk_ref = false;
2207         }
2208 fail:
2209         mutex_unlock(&dsi->lock);
2210         tegra_dc_io_end(dc);
2211 }
2212
2213 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2214 {
2215         /* Not required since tegra_dc_dsi_enable
2216          * will reconfigure the controller from scratch
2217          */
2218 }
2219 #endif
2220
2221 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2222         .init = tegra_dc_dsi_init,
2223         .destroy = tegra_dc_dsi_destroy,
2224         .enable = tegra_dc_dsi_enable,
2225         .disable = tegra_dc_dsi_disable,
2226 #ifdef CONFIG_PM
2227         .suspend = tegra_dc_dsi_suspend,
2228         .resume = tegra_dc_dsi_resume,
2229 #endif
2230 };