video: tegra: dsi: Enable panel read functionality
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/moduleparam.h>
28 #include <linux/export.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/nvhost.h>
32 #include <linux/lcm.h>
33 #include <linux/regulator/consumer.h>
34
35 #include <mach/clk.h>
36 #include <mach/dc.h>
37 #include <mach/fb.h>
38 #include <mach/csi.h>
39 #include <mach/iomap.h>
40 #include <linux/nvhost.h>
41
42 #include "dc_reg.h"
43 #include "dc_priv.h"
44 #include "dev.h"
45 #include "dsi_regs.h"
46 #include "dsi.h"
47 #include "mipi_cal.h"
48
49 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
50 #define DSIB_MODE_ENABLE                0x2
51
52 #define DSI_USE_SYNC_POINTS             0
53 #define S_TO_MS(x)                      (1000 * (x))
54 #define MS_TO_US(x)                     (1000 * (x))
55
56 #define DSI_MODULE_NOT_INIT             0x0
57 #define DSI_MODULE_INIT                 0x1
58
59 #define DSI_LPHS_NOT_INIT               0x0
60 #define DSI_LPHS_IN_LP_MODE             0x1
61 #define DSI_LPHS_IN_HS_MODE             0x2
62
63 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
64 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
65 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
66
67 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
68 #define DSI_DRIVEN_MODE_DC              0x1
69 #define DSI_DRIVEN_MODE_HOST            0x2
70
71 #define DSI_PHYCLK_OUT_DIS              0x0
72 #define DSI_PHYCLK_OUT_EN               0x1
73
74 #define DSI_PHYCLK_NOT_INIT             0x0
75 #define DSI_PHYCLK_CONTINUOUS           0x1
76 #define DSI_PHYCLK_TX_ONLY              0x2
77
78 #define DSI_CLK_BURST_NOT_INIT          0x0
79 #define DSI_CLK_BURST_NONE_BURST        0x1
80 #define DSI_CLK_BURST_BURST_MODE        0x2
81
82 #define DSI_DC_STREAM_DISABLE           0x0
83 #define DSI_DC_STREAM_ENABLE            0x1
84
85 #define DSI_LP_OP_NOT_INIT              0x0
86 #define DSI_LP_OP_WRITE                 0x1
87 #define DSI_LP_OP_READ                  0x2
88
89 #define DSI_HOST_IDLE_PERIOD            1000
90 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
91
92 static bool enable_read_debug;
93 module_param(enable_read_debug, bool, 0644);
94 MODULE_PARM_DESC(enable_read_debug,
95                 "Enable to print read fifo and return packet type");
96
97 atomic_t __maybe_unused display_ready = ATOMIC_INIT(0);
98 EXPORT_SYMBOL(display_ready);
99
100 /* source of video data */
101 enum {
102         TEGRA_DSI_DRIVEN_BY_DC,
103         TEGRA_DSI_DRIVEN_BY_HOST,
104 };
105
106 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
107
108 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
109         DSI_PKT_SEQ_0_LO,
110         DSI_PKT_SEQ_0_HI,
111         DSI_PKT_SEQ_1_LO,
112         DSI_PKT_SEQ_1_HI,
113         DSI_PKT_SEQ_2_LO,
114         DSI_PKT_SEQ_2_HI,
115         DSI_PKT_SEQ_3_LO,
116         DSI_PKT_SEQ_3_HI,
117         DSI_PKT_SEQ_4_LO,
118         DSI_PKT_SEQ_4_HI,
119         DSI_PKT_SEQ_5_LO,
120         DSI_PKT_SEQ_5_HI,
121 };
122
123 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
124         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
125         0,
126         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
127         0,
128         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
129         0,
130         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
131         PKT_ID2(CMD_HE) | PKT_LEN2(0),
132         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
133         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
134         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
135         0,
136         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
137         PKT_ID2(CMD_HE) | PKT_LEN2(0),
138         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
139         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
140 };
141
142 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
143         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
144         0,
145         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
146         0,
147         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
148         0,
149         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
150         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
151         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
152         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
155         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
156         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
157 };
158
159 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
160         PKT_ID0(CMD_VS) | PKT_LEN0(0),
161         0,
162         PKT_ID0(CMD_HS) | PKT_LEN0(0),
163         0,
164         PKT_ID0(CMD_HS) | PKT_LEN0(0),
165         0,
166         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
167         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
168         0,
169         PKT_ID0(CMD_HS) | PKT_LEN0(0),
170         0,
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
172         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
173         0,
174 };
175
176 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
177         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
178         0,
179         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
180         0,
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
182         0,
183         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
184         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
185         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
189         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
190         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
191 };
192
193 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
194         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
195         0,
196         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
199         0,
200         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
201         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
202         0,
203         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
204         0,
205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
206         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
207         0,
208 };
209
210 /* TODO: verify with hw about this format */
211 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
212         0,
213         0,
214         0,
215         0,
216         0,
217         0,
218         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
219         0,
220         0,
221         0,
222         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
223         0,
224 };
225
226 const u32 init_reg[] = {
227         DSI_INT_ENABLE,
228         DSI_INT_STATUS,
229         DSI_INT_MASK,
230         DSI_INIT_SEQ_DATA_0,
231         DSI_INIT_SEQ_DATA_1,
232         DSI_INIT_SEQ_DATA_2,
233         DSI_INIT_SEQ_DATA_3,
234         DSI_INIT_SEQ_DATA_4,
235         DSI_INIT_SEQ_DATA_5,
236         DSI_INIT_SEQ_DATA_6,
237         DSI_INIT_SEQ_DATA_7,
238         DSI_DCS_CMDS,
239         DSI_PKT_SEQ_0_LO,
240         DSI_PKT_SEQ_1_LO,
241         DSI_PKT_SEQ_2_LO,
242         DSI_PKT_SEQ_3_LO,
243         DSI_PKT_SEQ_4_LO,
244         DSI_PKT_SEQ_5_LO,
245         DSI_PKT_SEQ_0_HI,
246         DSI_PKT_SEQ_1_HI,
247         DSI_PKT_SEQ_2_HI,
248         DSI_PKT_SEQ_3_HI,
249         DSI_PKT_SEQ_4_HI,
250         DSI_PKT_SEQ_5_HI,
251         DSI_CONTROL,
252         DSI_HOST_DSI_CONTROL,
253         DSI_PAD_CONTROL,
254         DSI_PAD_CONTROL_CD,
255         DSI_SOL_DELAY,
256         DSI_MAX_THRESHOLD,
257         DSI_TRIGGER,
258         DSI_TX_CRC,
259         DSI_INIT_SEQ_CONTROL,
260         DSI_PKT_LEN_0_1,
261         DSI_PKT_LEN_2_3,
262         DSI_PKT_LEN_4_5,
263         DSI_PKT_LEN_6_7,
264 };
265
266 const u32 init_reg_vs1_ext[] = {
267         DSI_PAD_CONTROL_0_VS1,
268         DSI_PAD_CONTROL_CD_VS1,
269         DSI_PAD_CD_STATUS_VS1,
270         DSI_PAD_CONTROL_1_VS1,
271         DSI_PAD_CONTROL_2_VS1,
272         DSI_PAD_CONTROL_3_VS1,
273         DSI_PAD_CONTROL_4_VS1,
274         DSI_GANGED_MODE_CONTROL,
275         DSI_GANGED_MODE_START,
276         DSI_GANGED_MODE_SIZE,
277 };
278
279 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
280 static int tegra_dsi_host_resume(struct tegra_dc *dc);
281 static void tegra_dc_dsi_idle_work(struct work_struct *work);
282 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
283                                      struct tegra_dc_dsi_data *dsi,
284                                      int no_of_frames);
285
286 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
287 {
288         unsigned long ret;
289
290         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
291         ret = readl(dsi->base + reg * 4);
292         trace_display_readl(dsi->dc, ret, dsi->base + reg * 4);
293         return ret;
294 }
295 EXPORT_SYMBOL(tegra_dsi_readl);
296
297 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
298 {
299         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
300         trace_display_writel(dsi->dc, val, dsi->base + reg * 4);
301         writel(val, dsi->base + reg * 4);
302 }
303 EXPORT_SYMBOL(tegra_dsi_writel);
304
305 #ifdef CONFIG_DEBUG_FS
306 static int dbg_dsi_show(struct seq_file *s, void *unused)
307 {
308         struct tegra_dc_dsi_data *dsi = s->private;
309
310 #define DUMP_REG(a) do {                                                \
311                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
312                        #a, a, tegra_dsi_readl(dsi, a));         \
313         } while (0)
314
315         tegra_dc_io_start(dsi->dc);
316         clk_prepare_enable(dsi->dsi_clk);
317
318         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
319         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
320         DUMP_REG(DSI_CTXSW);
321         DUMP_REG(DSI_POWER_CONTROL);
322         DUMP_REG(DSI_INT_ENABLE);
323         DUMP_REG(DSI_HOST_DSI_CONTROL);
324         DUMP_REG(DSI_CONTROL);
325         DUMP_REG(DSI_SOL_DELAY);
326         DUMP_REG(DSI_MAX_THRESHOLD);
327         DUMP_REG(DSI_TRIGGER);
328         DUMP_REG(DSI_TX_CRC);
329         DUMP_REG(DSI_STATUS);
330         DUMP_REG(DSI_INIT_SEQ_CONTROL);
331         DUMP_REG(DSI_INIT_SEQ_DATA_0);
332         DUMP_REG(DSI_INIT_SEQ_DATA_1);
333         DUMP_REG(DSI_INIT_SEQ_DATA_2);
334         DUMP_REG(DSI_INIT_SEQ_DATA_3);
335         DUMP_REG(DSI_INIT_SEQ_DATA_4);
336         DUMP_REG(DSI_INIT_SEQ_DATA_5);
337         DUMP_REG(DSI_INIT_SEQ_DATA_6);
338         DUMP_REG(DSI_INIT_SEQ_DATA_7);
339         DUMP_REG(DSI_PKT_SEQ_0_LO);
340         DUMP_REG(DSI_PKT_SEQ_0_HI);
341         DUMP_REG(DSI_PKT_SEQ_1_LO);
342         DUMP_REG(DSI_PKT_SEQ_1_HI);
343         DUMP_REG(DSI_PKT_SEQ_2_LO);
344         DUMP_REG(DSI_PKT_SEQ_2_HI);
345         DUMP_REG(DSI_PKT_SEQ_3_LO);
346         DUMP_REG(DSI_PKT_SEQ_3_HI);
347         DUMP_REG(DSI_PKT_SEQ_4_LO);
348         DUMP_REG(DSI_PKT_SEQ_4_HI);
349         DUMP_REG(DSI_PKT_SEQ_5_LO);
350         DUMP_REG(DSI_PKT_SEQ_5_HI);
351         DUMP_REG(DSI_DCS_CMDS);
352         DUMP_REG(DSI_PKT_LEN_0_1);
353         DUMP_REG(DSI_PKT_LEN_2_3);
354         DUMP_REG(DSI_PKT_LEN_4_5);
355         DUMP_REG(DSI_PKT_LEN_6_7);
356         DUMP_REG(DSI_PHY_TIMING_0);
357         DUMP_REG(DSI_PHY_TIMING_1);
358         DUMP_REG(DSI_PHY_TIMING_2);
359         DUMP_REG(DSI_BTA_TIMING);
360         DUMP_REG(DSI_TIMEOUT_0);
361         DUMP_REG(DSI_TIMEOUT_1);
362         DUMP_REG(DSI_TO_TALLY);
363         DUMP_REG(DSI_PAD_CONTROL);
364         DUMP_REG(DSI_PAD_CONTROL_CD);
365         DUMP_REG(DSI_PAD_CD_STATUS);
366         DUMP_REG(DSI_VID_MODE_CONTROL);
367 #undef DUMP_REG
368
369         clk_disable_unprepare(dsi->dsi_clk);
370         tegra_dc_io_end(dsi->dc);
371
372         return 0;
373 }
374
375 static int dbg_dsi_open(struct inode *inode, struct file *file)
376 {
377         return single_open(file, dbg_dsi_show, inode->i_private);
378 }
379
380 static const struct file_operations dbg_fops = {
381         .open           = dbg_dsi_open,
382         .read           = seq_read,
383         .llseek         = seq_lseek,
384         .release        = single_release,
385 };
386
387 static struct dentry *dsidir;
388
389 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
390 {
391         struct dentry *retval;
392
393         dsidir = debugfs_create_dir("tegra_dsi", NULL);
394         if (!dsidir)
395                 return;
396         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
397                 &dbg_fops);
398         if (!retval)
399                 goto free_out;
400         return;
401 free_out:
402         debugfs_remove_recursive(dsidir);
403         dsidir = NULL;
404         return;
405 }
406 #else
407 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
408 { }
409 #endif
410
411 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
412 {
413         if (!tegra_is_clk_enabled(dsi->dsi_clk))
414                 clk_prepare_enable(dsi->dsi_clk);
415 }
416
417 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
418 {
419         if (tegra_is_clk_enabled(dsi->dsi_clk))
420                 clk_disable_unprepare(dsi->dsi_clk);
421 }
422
423 static void __maybe_unused tegra_dsi_syncpt_reset(
424                                 struct tegra_dc_dsi_data *dsi)
425 {
426         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
427         /* stabilization delay */
428         udelay(300);
429         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
430         /* stabilization delay */
431         udelay(300);
432 }
433
434 static int __maybe_unused tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
435 {
436         u32 val;
437         int ret = 0;
438
439         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
440
441         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
442                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
443         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
444
445         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
446                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
447         if (ret < 0) {
448                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
449                 goto fail;
450         }
451
452         (dsi->syncpt_val)++;
453         return 0;
454 fail:
455         return ret;
456 }
457
458 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
459 {
460         u32 dsi_clock_rate_khz;
461
462         switch (dsi->info.video_burst_mode) {
463         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
464         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
465         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
466         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
467                 /* Calculate DSI HS clock rate for DSI burst mode */
468                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
469                                         dsi->shift_clk_div.mul /
470                                         dsi->shift_clk_div.div;
471                 break;
472         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
473         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
474         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
475         default:
476                 /* Clock rate is default DSI clock rate for non-burst mode */
477                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
478                 break;
479         }
480
481         return dsi_clock_rate_khz;
482 }
483
484 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
485 {
486         u32 dsi_clock_rate_khz;
487
488         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
489                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
490                         dsi_clock_rate_khz =
491                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
492                 else
493                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
494         else
495                 if (lp_op == DSI_LP_OP_READ)
496                         dsi_clock_rate_khz =
497                                 dsi->info.lp_read_cmd_mode_freq_khz;
498                 else
499                         dsi_clock_rate_khz =
500                                 dsi->info.lp_cmd_mode_freq_khz;
501
502         return dsi_clock_rate_khz;
503 }
504
505 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
506                                                 struct tegra_dc_dsi_data *dsi)
507 {
508         struct tegra_dc_shift_clk_div shift_clk_div;
509         struct tegra_dc_shift_clk_div max_shift_clk_div;
510         u32 temp_lcm;
511         u32 burst_width;
512         u32 burst_width_max;
513
514         /* Get the real value of default shift_clk_div. default_shift_clk_div
515          * holds the real value of shift_clk_div.
516          */
517         shift_clk_div = dsi->default_shift_clk_div;
518
519         /* Calculate shift_clk_div which can match the video_burst_mode. */
520         if (dsi->info.video_burst_mode >=
521                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
522                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz) {
523                         /* formula:
524                          * dsi->info.max_panel_freq_khz * shift_clk_div /
525                          * dsi->default_hs_clk_khz
526                          */
527                         max_shift_clk_div.mul = dsi->info.max_panel_freq_khz *
528                                                 shift_clk_div.mul;
529                         max_shift_clk_div.div = dsi->default_hs_clk_khz *
530                                                 dsi->default_shift_clk_div.div;
531                 } else {
532                         max_shift_clk_div = shift_clk_div;
533                 }
534
535                 burst_width = dsi->info.video_burst_mode
536                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
537                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
538                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
539
540                 /* formula:
541                  * (max_shift_clk_div - shift_clk_div) *
542                  * burst_width / burst_width_max
543                  */
544                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
545                 shift_clk_div.mul = (max_shift_clk_div.mul * temp_lcm /
546                                         max_shift_clk_div.div -
547                                         shift_clk_div.mul * temp_lcm /
548                                         shift_clk_div.div)*
549                                         burst_width;
550                 shift_clk_div.div = temp_lcm * burst_width_max;
551         }
552
553         return shift_clk_div;
554 }
555
556 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
557                                         struct tegra_dc_dsi_data *dsi)
558 {
559         u32 h_width_pixels;
560         u32 h_act_corr = 0;
561         u32 hfp_corr = 0;
562         u32 temp = 0;
563
564         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
565                         dc->mode.h_sync_width + dc->mode.h_active;
566
567         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
568                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
569                 if (temp) {
570                         h_act_corr = dsi->info.n_data_lanes - temp;
571                         h_width_pixels += h_act_corr;
572                 }
573         }
574
575         temp = h_width_pixels % dsi->info.n_data_lanes;
576         if (temp) {
577                 hfp_corr = dsi->info.n_data_lanes - temp;
578                 h_width_pixels += hfp_corr;
579         }
580
581         while (1) {
582                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
583                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
584                 if (temp) {
585                         hfp_corr += dsi->info.n_data_lanes;
586                         h_width_pixels += dsi->info.n_data_lanes;
587                 }
588                 else
589                         break;
590         }
591
592         dc->mode.h_front_porch += hfp_corr;
593         dc->mode.h_active += h_act_corr;
594 }
595
596 static void tegra_dsi_init_sw(struct tegra_dc *dc,
597                         struct tegra_dc_dsi_data *dsi)
598 {
599         u32 h_width_pixels;
600         u32 v_width_lines;
601         u32 pixel_clk_hz;
602         u32 byte_clk_hz;
603         u32 plld_clk_mhz;
604         u8 n_data_lanes;
605
606         switch (dsi->info.pixel_format) {
607         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
608                 /* 2 bytes per pixel */
609                 dsi->pixel_scaler_mul = 2;
610                 dsi->pixel_scaler_div = 1;
611                 break;
612         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
613                 /* 2.25 bytes per pixel */
614                 dsi->pixel_scaler_mul = 9;
615                 dsi->pixel_scaler_div = 4;
616                 break;
617         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
618         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
619                 /* 3 bytes per pixel */
620                 dsi->pixel_scaler_mul = 3;
621                 dsi->pixel_scaler_div = 1;
622                 break;
623         default:
624                 break;
625         }
626
627         dsi->ulpm = false;
628         dsi->enabled = false;
629         dsi->clk_ref = false;
630
631         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
632                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
633                 n_data_lanes = dsi->info.n_data_lanes / 2;
634
635         dsi->dsi_control_val =
636                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
637                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
638                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
639                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
640
641         if (dsi->info.ganged_type)
642                 tegra_dsi_pix_correction(dc, dsi);
643
644         /* Below we are going to calculate dsi and dc clock rate.
645          * Calcuate the horizontal and vertical width.
646          */
647         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
648                         dc->mode.h_sync_width + dc->mode.h_active;
649
650         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
651                         dc->mode.v_sync_width + dc->mode.v_active;
652
653         /* Calculate minimum required pixel rate. */
654         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
655         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
656                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
657                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
658                                 "should be larger than rated refresh rate.\n");
659                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
660                                                 dsi->info.rated_refresh_rate;
661         }
662
663         /* Calculate minimum byte rate on DSI interface. */
664         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
665                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
666
667         /* Round up to multiple of mega hz. */
668         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
669                                                                 1000000);
670
671         /* Calculate default real shift_clk_div. */
672         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
673                                         dsi->pixel_scaler_mul;
674         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
675                                         dsi->info.n_data_lanes;
676
677         /* Calculate default DSI hs clock. DSI interface is double data rate.
678          * Data is transferred on both rising and falling edge of clk, div by 2
679          * to get the actual clock rate.
680          */
681         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
682
683         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
684                                         dsi->default_shift_clk_div.div) /
685                                         (2 * dsi->default_shift_clk_div.mul);
686
687         /* Get the actual shift_clk_div and clock rates. */
688         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
689         dsi->target_lp_clk_khz =
690                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
691         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
692
693         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
694                                         dsi->target_hs_clk_khz);
695
696 #if DSI_USE_SYNC_POINTS
697         dsi->syncpt_id = NVSYNCPT_DSI;
698 #endif
699
700         /*
701          * Force video clock to be continuous mode if
702          * enable_hs_clock_on_lp_cmd_mode is set
703          */
704         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
705                 if (dsi->info.video_clock_mode !=
706                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
707                         dev_warn(&dc->ndev->dev,
708                                 "Force clock continuous mode\n");
709
710                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
711         }
712
713         atomic_set(&dsi->host_ref, 0);
714         dsi->host_suspended = false;
715         mutex_init(&dsi->host_lock);
716         init_completion(&dc->out->user_vblank_comp);
717         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
718         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
719 }
720
721 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
722 (platform_t_phy_ns) ? ( \
723 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
724 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
725 ((default_phy) < 0 ? 0 : (default_phy)))
726
727 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
728                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
729 {
730         phy_timing_clk->t_tlpx = SELECT_T_PHY(
731                 dsi->info.phy_timing.t_tlpx_ns,
732                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
733
734         phy_timing_clk->t_clktrail = SELECT_T_PHY(
735                 dsi->info.phy_timing.t_clktrail_ns,
736                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
737
738         phy_timing_clk->t_clkpost = SELECT_T_PHY(
739                 dsi->info.phy_timing.t_clkpost_ns,
740                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
741
742         phy_timing_clk->t_clkzero = SELECT_T_PHY(
743                 dsi->info.phy_timing.t_clkzero_ns,
744                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
745
746         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
747                 dsi->info.phy_timing.t_clkprepare_ns,
748                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
749
750         phy_timing_clk->t_clkpre = SELECT_T_PHY(
751                 dsi->info.phy_timing.t_clkpre_ns,
752                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
753 }
754
755 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
756                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
757 {
758         phy_timing_clk->t_tlpx = SELECT_T_PHY(
759                 dsi->info.phy_timing.t_tlpx_ns,
760                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
761
762         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
763                 dsi->info.phy_timing.t_hsdexit_ns,
764                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
765
766         phy_timing_clk->t_hstrail = SELECT_T_PHY(
767                 dsi->info.phy_timing.t_hstrail_ns,
768                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
769
770         phy_timing_clk->t_datzero = SELECT_T_PHY(
771                 dsi->info.phy_timing.t_datzero_ns,
772                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
773
774         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
775                 dsi->info.phy_timing.t_hsprepare_ns,
776                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
777 }
778
779 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
780                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
781 {
782         phy_timing_clk->t_tlpx = SELECT_T_PHY(
783                 dsi->info.phy_timing.t_tlpx_ns,
784                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
785 }
786
787 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
788                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
789 {
790         phy_timing_clk->t_tlpx = SELECT_T_PHY(
791                 dsi->info.phy_timing.t_tlpx_ns,
792                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
793
794         phy_timing_clk->t_taget = SELECT_T_PHY(
795                 dsi->info.phy_timing.t_taget_ns,
796                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
797
798         phy_timing_clk->t_tasure = SELECT_T_PHY(
799                 dsi->info.phy_timing.t_tasure_ns,
800                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
801
802         phy_timing_clk->t_tago = SELECT_T_PHY(
803                 dsi->info.phy_timing.t_tago_ns,
804                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
805 }
806
807 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
808                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
809 {
810         phy_timing_clk->t_tlpx = SELECT_T_PHY(
811                 dsi->info.phy_timing.t_tlpx_ns,
812                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
813
814         phy_timing_clk->t_wakeup = SELECT_T_PHY(
815                 dsi->info.phy_timing.t_wakeup_ns,
816                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
817 }
818
819 #undef SELECT_T_PHY
820
821 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
822                                 struct dsi_phy_timing_inclk *phy_timing_clk,
823                                 u32 clk_ns, u8 lphs)
824 {
825         if (!(dsi->info.ganged_type)) {
826 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
827                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
828                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
829 #endif
830         }
831
832         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
833                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
834                         (T_HSEXIT_DEFAULT(clk_ns));
835
836         if (lphs == DSI_LPHS_IN_HS_MODE) {
837                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
838                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
839         } else {
840                 /* default is LP mode */
841                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
842                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
843                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
844                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
845                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
846         }
847 }
848
849 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
850                                 struct dsi_phy_timing_inclk *phy_timing,
851                                 u32 clk_ns, u8 lphs)
852 {
853         int err = 0;
854
855 #define CHECK_RANGE(val, min, max) ( \
856                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
857                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
858
859 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
860         clk_ns = dsi->info.fpga_freq_khz ?
861                 ((1000 * 1000) / dsi->info.fpga_freq_khz) :
862                 DEFAULT_FPGA_FREQ_KHZ;
863 #endif
864
865         err = CHECK_RANGE(
866         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
867                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
868                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
869         if (err < 0) {
870                 dev_warn(&dsi->dc->ndev->dev,
871                         "dsi: Tlpx mipi range violated\n");
872                 goto fail;
873         }
874
875         if (lphs == DSI_LPHS_IN_HS_MODE) {
876                 err = CHECK_RANGE(
877                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
878                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
879                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
880                 if (err < 0) {
881                         dev_warn(&dsi->dc->ndev->dev,
882                                 "dsi: HsExit mipi range violated\n");
883                         goto fail;
884                 }
885
886                 err = CHECK_RANGE(
887                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
888                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
889                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
890                 if (err < 0) {
891                         dev_warn(&dsi->dc->ndev->dev,
892                                 "dsi: HsTrail mipi range violated\n");
893                         goto fail;
894                 }
895
896                 err = CHECK_RANGE(
897                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
898                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
899                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
900                 if (err < 0) {
901                         dev_warn(&dsi->dc->ndev->dev,
902                                 "dsi: HsZero mipi range violated\n");
903                         goto fail;
904                 }
905
906                 err = CHECK_RANGE(
907                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
908                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
909                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
910                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
911                 if (err < 0) {
912                         dev_warn(&dsi->dc->ndev->dev,
913                                 "dsi: HsPrepare mipi range violated\n");
914                         goto fail;
915                 }
916
917                 err = CHECK_RANGE(
918                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
919                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
920                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
921                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
922                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
923                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
924                 if (err < 0) {
925                         dev_warn(&dsi->dc->ndev->dev,
926                         "dsi: HsPrepare + HsZero mipi range violated\n");
927                         goto fail;
928                 }
929         } else {
930                 /* default is LP mode */
931                 err = CHECK_RANGE(
932                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
933                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
934                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
935                 if (err < 0) {
936                         dev_warn(&dsi->dc->ndev->dev,
937                                 "dsi: WakeUp mipi range violated\n");
938                         goto fail;
939                 }
940
941                 err = CHECK_RANGE(
942                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
943                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
944                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
945                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
946                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
947                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
948                 if (err < 0) {
949                         dev_warn(&dsi->dc->ndev->dev,
950                                 "dsi: TaSure mipi range violated\n");
951                         goto fail;
952                 }
953         }
954
955         if (lphs == DSI_LPHS_IN_HS_MODE ||
956                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
957                 err = CHECK_RANGE(
958                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
959                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
960                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
961                 if (err < 0) {
962                         dev_warn(&dsi->dc->ndev->dev,
963                                 "dsi: ClkTrail mipi range violated\n");
964                         goto fail;
965                 }
966
967                 err = CHECK_RANGE(
968                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
969                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
970                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
971                 if (err < 0) {
972                         dev_warn(&dsi->dc->ndev->dev,
973                                 "dsi: ClkPost mipi range violated\n");
974                         goto fail;
975                 }
976
977                 err = CHECK_RANGE(
978                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
979                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
980                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
981                 if (err < 0) {
982                         dev_warn(&dsi->dc->ndev->dev,
983                                 "dsi: ClkZero mipi range violated\n");
984                         goto fail;
985                 }
986
987                 err = CHECK_RANGE(
988                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
989                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
990                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
991                 if (err < 0) {
992                         dev_warn(&dsi->dc->ndev->dev,
993                                 "dsi: ClkPrepare mipi range violated\n");
994                         goto fail;
995                 }
996
997                 err = CHECK_RANGE(
998                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
999                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
1000                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
1001                 if (err < 0) {
1002                         dev_warn(&dsi->dc->ndev->dev,
1003                                 "dsi: ClkPre mipi range violated\n");
1004                         goto fail;
1005                 }
1006
1007                 err = CHECK_RANGE(
1008                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1009                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1010                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1011                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
1012                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
1013                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
1014                 if (err < 0) {
1015                         dev_warn(&dsi->dc->ndev->dev,
1016                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1017                         goto fail;
1018                 }
1019         }
1020 fail:
1021 #undef CHECK_RANGE
1022         return err;
1023 }
1024
1025 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1026                                 struct dsi_phy_timing_inclk *phy_timing,
1027                                 u32 clk_ns, u8 lphs)
1028 {
1029         u32 hs_t_phy_ns = 0;
1030         u32 clk_t_phy_ns = 0;
1031         u32 t_phy_ns;
1032         u32 h_blank_ns;
1033         struct tegra_dc_mode *modes;
1034         u32 t_pix_ns;
1035         int err = 0;
1036
1037         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1038                 goto fail;
1039
1040         if (dsi->info.video_data_type ==
1041                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1042                 dsi->info.video_burst_mode <=
1043                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1044                 goto fail;
1045
1046         modes = dsi->dc->out->modes;
1047         t_pix_ns = clk_ns * BITS_PER_BYTE *
1048                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1049
1050         hs_t_phy_ns =
1051                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1052                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1053                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1054                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1055                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1056                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1057                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1058                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1059                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1060                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1061                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1062                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1063
1064         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1065                 clk_t_phy_ns =
1066                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1067                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1068                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1069                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1070                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1071                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1072                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1073                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1074                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1075                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1076                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1077                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1078                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1079                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1080
1081                 /* clk_pre overlaps LP-11 hs mode start sequence */
1082                 hs_t_phy_ns -= DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1083                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC);
1084         }
1085
1086         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1087                                                 modes->h_front_porch);
1088
1089         /* Extra tlpx and byte cycle required by dsi HW */
1090         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1091                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1092                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1093                 clk_ns * BITS_PER_BYTE);
1094
1095         if (h_blank_ns < t_phy_ns) {
1096                 err = -EINVAL;
1097                 dev_WARN(&dsi->dc->ndev->dev,
1098                         "dsi: Hblank is smaller than HS trans phy timing\n");
1099                 goto fail;
1100         }
1101
1102         return 0;
1103 fail:
1104         return err;
1105 }
1106
1107 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1108                                 struct dsi_phy_timing_inclk *phy_timing,
1109                                 u32 clk_ns, u8 lphs)
1110 {
1111         int err = 0;
1112
1113         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1114         if (err < 0) {
1115                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1116                 goto fail;
1117         }
1118
1119         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1120         if (err < 0) {
1121                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1122                 goto fail;
1123         }
1124
1125         /* TODO: add more contraints */
1126 fail:
1127         return err;
1128 }
1129
1130 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1131 {
1132         u32 val;
1133         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1134
1135         tegra_dsi_get_phy_timing
1136                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1137
1138         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1139                                         dsi->current_bit_clk_ns, lphs);
1140
1141         if (dsi->info.ganged_type) {
1142 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1143                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1144                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1145                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1146                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1147
1148                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1149                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1150                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1151                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1152
1153                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1154                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1155                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1156
1157                 phy_timing.t_taget += T_TAGET_HW_INC;
1158                 phy_timing.t_tasure += T_TASURE_HW_INC;
1159                 phy_timing.t_tago += T_TAGO_HW_INC;
1160 #endif
1161         }
1162         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1163                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1164                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1165                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1166         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1167
1168         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1169                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1170                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1171                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1172         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1173
1174         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1175                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1176                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1177         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1178
1179         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1180                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1181                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1182         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1183
1184         dsi->phy_timing = phy_timing;
1185 }
1186
1187 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1188                                 struct tegra_dc_dsi_data *dsi)
1189 {
1190         u32 dsi_to_pixel_clk_ratio;
1191         u32 temp;
1192         u32 temp1;
1193         u32 mipi_clk_adj_kHz = 0;
1194         u32 sol_delay;
1195         struct tegra_dc_mode *dc_modes = &dc->mode;
1196
1197         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1198         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1199                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1200
1201         /* Convert Fdsi to byte format */
1202         dsi_to_pixel_clk_ratio *= 1000/8;
1203
1204         /* Multiplying by 1000 so that we don't loose the fraction part */
1205         temp = dc_modes->h_active * 1000;
1206         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1207                         dc_modes->h_sync_width;
1208
1209         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1210                         temp * dsi->pixel_scaler_mul /
1211                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1212
1213         /* Do rounding on sol delay */
1214         sol_delay = (sol_delay + 1000 - 1)/1000;
1215
1216         /* TODO:
1217          * 1. find out the correct sol fifo depth to use
1218          * 2. verify with hw about the clamping function
1219          */
1220         if (sol_delay > (480 * 4)) {
1221                 sol_delay = (480 * 4);
1222                 mipi_clk_adj_kHz = sol_delay +
1223                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1224                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1225
1226                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1227
1228                 mipi_clk_adj_kHz *= 4;
1229         }
1230
1231         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1232
1233         return sol_delay;
1234 }
1235
1236 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1237                                 struct tegra_dc_dsi_data *dsi)
1238 {
1239         u32 sol_delay;
1240         u32 internal_delay;
1241         u32 h_width_byte_clk;
1242         u32 h_width_pixels;
1243         u32 h_width_ganged_byte_clk;
1244         u8 n_data_lanes_this_cont = 0;
1245         u8 n_data_lanes_ganged = 0;
1246
1247         if (!(dsi->info.ganged_type)) {
1248                 if (dsi->info.video_burst_mode ==
1249                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1250                         dsi->info.video_burst_mode ==
1251                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1252 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1253                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1254                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1255 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1256                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1257                 } else {
1258                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1259                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1260                 }
1261         } else {
1262 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1263 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1264 #define FIFO_WR_PIX_CLK_DELAY 2
1265 #define FIFO_RD_BYTE_CLK_DELAY 6
1266 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1267                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1268                                 FIFO_WR_PIX_CLK_DELAY)
1269
1270                 internal_delay = DIV_ROUND_UP(
1271                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1272                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1273                                 + FIFO_RD_BYTE_CLK_DELAY;
1274
1275                 h_width_pixels = dc->mode.h_sync_width +
1276                                         dc->mode.h_back_porch +
1277                                         dc->mode.h_active +
1278                                         dc->mode.h_front_porch;
1279
1280                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1281                                         dsi->pixel_scaler_mul,
1282                                         dsi->pixel_scaler_div *
1283                                         dsi->info.n_data_lanes);
1284
1285                 if (dsi->info.ganged_type ==
1286                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1287                         dsi->info.ganged_type ==
1288                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1289                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1290                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1291                 }
1292
1293                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1294                                         n_data_lanes_this_cont *
1295                                         h_width_byte_clk,
1296                                         n_data_lanes_ganged);
1297
1298                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1299                                                         internal_delay;
1300                 sol_delay = (dsi->info.video_data_type ==
1301                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1302                                 sol_delay + 20: sol_delay;
1303
1304 #undef SOL_TO_VALID_PIX_CLK_DELAY
1305 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1306 #undef FIFO_WR_PIX_CLK_DELAY
1307 #undef FIFO_RD_BYTE_CLK_DELAY
1308 #undef TOT_INTERNAL_PIX_DELAY
1309         }
1310
1311         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1312                                                 DSI_SOL_DELAY);
1313 }
1314
1315 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1316 {
1317         u32 val;
1318         u32 bytes_per_frame;
1319         u32 timeout = 0;
1320
1321         /* TODO: verify the following equation */
1322         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1323                                                 (dsi->info.refresh_rate * 8);
1324         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1325         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1326
1327         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1328                         DSI_TIMEOUT_0_HTX_TO(timeout);
1329         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1330
1331         if (dsi->info.panel_reset_timeout_msec)
1332                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1333                                         / dsi->current_bit_clk_ns;
1334         else
1335                 timeout = DSI_PR_TO_VALUE;
1336
1337         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1338                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1339         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1340
1341         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1342                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1343                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1344                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1345         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1346 }
1347
1348 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1349                                                 struct tegra_dc_dsi_data *dsi)
1350 {
1351         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1352         u32 hact_pkt_len_pix = 0;
1353         u32 hact_pkt_len_bytes = 0;
1354         u32 hfp_pkt_len_bytes = 0;
1355         u32 pix_per_line_orig = 0;
1356         u32 pix_per_line = 0;
1357         u32 val = 0;
1358
1359 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1360 #define HEADER_OVERHEAD 16
1361
1362         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1363                         dc->mode.h_active + dc->mode.h_front_porch;
1364
1365         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1366                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1367                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1368                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1369                 if (dsi->controller_index) {
1370                         hact_pkt_len_pix =
1371                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1372                         pix_per_line = pix_per_line_orig - pix_per_line;
1373                 }
1374                 hact_pkt_len_bytes = hact_pkt_len_pix *
1375                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1376                 hfp_pkt_len_bytes = pix_per_line *
1377                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1378                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1379         }
1380
1381         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1382                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1383         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1384
1385         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1386                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1387         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1388
1389         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1390                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1391         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1392
1393         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1394                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1395         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1396
1397 #undef HEADER_OVERHEAD
1398 }
1399
1400 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1401                                                 struct tegra_dc_dsi_data *dsi)
1402 {
1403         u32 val;
1404         u32 hact_pkt_len;
1405         u32 hsa_pkt_len;
1406         u32 hbp_pkt_len;
1407         u32 hfp_pkt_len;
1408
1409         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1410                                                         dsi->pixel_scaler_div;
1411         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1412                                                         dsi->pixel_scaler_div;
1413         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1414                                                         dsi->pixel_scaler_div;
1415         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1416                                                         dsi->pixel_scaler_div;
1417
1418         if (dsi->info.video_burst_mode !=
1419                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1420                 hbp_pkt_len += hsa_pkt_len;
1421
1422         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1423         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1424         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1425
1426         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1427                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1428         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1429
1430         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1431                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1432         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1433
1434         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1435                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1436         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1437
1438         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1439         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1440 }
1441
1442 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1443                                                 struct tegra_dc_dsi_data *dsi)
1444 {
1445         unsigned long   val;
1446         unsigned long   act_bytes;
1447
1448         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1449                         dsi->pixel_scaler_div + 1;
1450
1451         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1452         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1453
1454         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1455         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1456
1457         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1458         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1459
1460         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1461         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1462 }
1463
1464 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1465                                 struct tegra_dc_dsi_data *dsi)
1466 {
1467         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1468                 return;
1469
1470         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1471                 if (dsi->info.ganged_type)
1472                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1473                 else
1474                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1475         } else {
1476                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1477         }
1478 }
1479
1480 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1481                                 struct tegra_dc_dsi_data *dsi)
1482 {
1483         const u32 *pkt_seq;
1484         u32 rgb_info;
1485         u32 pkt_seq_3_5_rgb_lo;
1486         u32 pkt_seq_3_5_rgb_hi;
1487         u32     val;
1488         u32 reg;
1489         u8  i;
1490
1491         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1492                 return;
1493
1494         switch (dsi->info.pixel_format) {
1495         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1496                 rgb_info = CMD_RGB_16BPP;
1497                 break;
1498         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1499                 rgb_info = CMD_RGB_18BPP;
1500                 break;
1501         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1502                 rgb_info = CMD_RGB_18BPPNP;
1503                 break;
1504         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1505         default:
1506                 rgb_info = CMD_RGB_24BPP;
1507                 break;
1508         }
1509
1510         pkt_seq_3_5_rgb_lo = 0;
1511         pkt_seq_3_5_rgb_hi = 0;
1512         if (dsi->info.pkt_seq)
1513                 pkt_seq = dsi->info.pkt_seq;
1514         else if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1515                 pkt_seq = dsi_pkt_seq_cmd_mode;
1516         else {
1517                 switch (dsi->info.video_burst_mode) {
1518                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1519                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1520                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1521                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1522                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1523                         pkt_seq_3_5_rgb_lo =
1524                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1525                         if (!dsi->info.no_pkt_seq_eot)
1526                                 pkt_seq = dsi_pkt_seq_video_burst;
1527                         else
1528                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1529                         break;
1530                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1531                         pkt_seq_3_5_rgb_hi =
1532                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1533                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1534                         break;
1535                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1536                 default:
1537                         if (dsi->info.ganged_type) {
1538                                 pkt_seq_3_5_rgb_lo =
1539                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1540                                 pkt_seq =
1541                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1542                         } else {
1543                                 pkt_seq_3_5_rgb_lo =
1544                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1545                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1546                         }
1547                         break;
1548                 }
1549         }
1550
1551         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1552                 val = pkt_seq[i];
1553                 reg = dsi_pkt_seq_reg[i];
1554                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1555                         val |= pkt_seq_3_5_rgb_lo;
1556                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1557                         val |= pkt_seq_3_5_rgb_hi;
1558                 tegra_dsi_writel(dsi, val, reg);
1559         }
1560 }
1561
1562 static void tegra_dsi_reset_underflow_overflow
1563                                 (struct tegra_dc_dsi_data *dsi)
1564 {
1565         u32 val;
1566
1567         val = tegra_dsi_readl(dsi, DSI_STATUS);
1568         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1569         if (val) {
1570                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1571                         dev_warn(&dsi->dc->ndev->dev,
1572                                 "dsi: video fifo overflow. Resetting flag\n");
1573                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1574                         dev_warn(&dsi->dc->ndev->dev,
1575                                 "dsi: video fifo underflow. Resetting flag\n");
1576                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1577                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1578                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1579                 udelay(5);
1580         }
1581 }
1582
1583 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1584 {
1585         u32 trigger;
1586         u32 val;
1587         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1588         struct tegra_dc_mode mode = dsi->dc->mode;
1589         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1590                                 mode.v_active + mode.v_front_porch;
1591         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1592         u32 timeout_cnt = 0;
1593
1594 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1595 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1596
1597         val = tegra_dsi_readl(dsi, DSI_STATUS);
1598         while (!(val & DSI_STATUS_IDLE(0x1))) {
1599                 cpu_relax();
1600                 udelay(line_period);
1601                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1602                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1603                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1604                         break;
1605                 }
1606         }
1607
1608         tegra_dsi_writel(dsi,
1609                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1610                 DSI_POWER_CONTROL);
1611         /* stabilization delay */
1612         udelay(300);
1613
1614         tegra_dsi_writel(dsi,
1615                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1616                 DSI_POWER_CONTROL);
1617         /* stabilization delay */
1618         udelay(300);
1619
1620         /* dsi HW does not clear host trigger bit automatically
1621          * on dsi interface disable if host fifo is empty or in mid
1622          * of host transmission
1623          */
1624         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1625         if (trigger)
1626                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1627
1628 #undef DSI_IDLE_TIMEOUT
1629 }
1630
1631 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1632                                         struct tegra_dc_dsi_data *dsi)
1633 {
1634         /* extra reference to dc clk */
1635         clk_prepare_enable(dc->clk);
1636
1637         /* Mask the MSF interrupt. */
1638         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1639                 tegra_dc_mask_interrupt(dc, MSF_INT);
1640
1641         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1642         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1643         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1644         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1645
1646         /* balance extra dc clk reference */
1647         clk_disable_unprepare(dc->clk);
1648
1649         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1650 }
1651
1652 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1653  * whichever happens to occur first
1654  */
1655 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1656                                 struct tegra_dc_dsi_data *dsi,
1657                                 u32 timeout_n_frames)
1658 {
1659         int val;
1660         long timeout;
1661         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1662         struct tegra_dc_mode mode = dc->mode;
1663         u32 line_period = DIV_ROUND_UP(
1664                                 MS_TO_US(frame_period),
1665                                 mode.v_sync_width + mode.v_back_porch +
1666                                 mode.v_active + mode.v_front_porch);
1667
1668         if (timeout_n_frames < 2)
1669                 dev_WARN(&dc->ndev->dev,
1670                 "dsi: to stop at next frame give at least 2 frame delay\n");
1671
1672         INIT_COMPLETION(dc->frame_end_complete);
1673
1674         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
1675         /* unmask frame end interrupt */
1676         val = tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1677
1678         timeout = wait_for_completion_interruptible_timeout(
1679                         &dc->frame_end_complete,
1680                         msecs_to_jiffies(timeout_n_frames * frame_period));
1681
1682         /* reinstate interrupt mask */
1683         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1684
1685         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1686         udelay(mode.v_ref_to_sync * line_period);
1687
1688         return timeout;
1689 }
1690
1691 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1692                                                 struct tegra_dc_dsi_data *dsi,
1693                                                 u32 timeout_n_frames)
1694 {
1695         tegra_dsi_stop_dc_stream(dc, dsi);
1696
1697         tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1698
1699         tegra_dsi_soft_reset(dsi);
1700
1701         tegra_dsi_reset_underflow_overflow(dsi);
1702 }
1703
1704 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1705                                         struct tegra_dc_dsi_data *dsi)
1706 {
1707         u32 val;
1708
1709         /* take extra reference to dc clk */
1710         clk_prepare_enable(dc->clk);
1711
1712         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1713
1714         /* TODO: clean up */
1715         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1716                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1717                         DC_CMD_DISPLAY_POWER_CONTROL);
1718
1719         /* Configure one-shot mode or continuous mode */
1720         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1721                 /* disable LSPI/LCD_DE output */
1722                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1723                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1724
1725                 /* enable MSF & set MSF polarity */
1726                 val = MSF_ENABLE | MSF_LSPI;
1727                 if (!dsi->info.te_polarity_low)
1728                         val |= MSF_POLARITY_HIGH;
1729                 else
1730                         val |= MSF_POLARITY_LOW;
1731                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1732
1733                 /* set non-continuous mode */
1734                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1735                                                 DC_CMD_DISPLAY_COMMAND);
1736                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1737                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1738                                                 DC_CMD_STATE_CONTROL);
1739
1740                 /* Unmask the MSF interrupt. */
1741                 tegra_dc_unmask_interrupt(dc, MSF_INT);
1742         } else {
1743                 /* set continuous mode */
1744                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1745                                                 DC_CMD_DISPLAY_COMMAND);
1746                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1747                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1748         }
1749
1750         /* balance extra dc clk reference */
1751         clk_disable_unprepare(dc->clk);
1752
1753         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1754 }
1755
1756 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1757                                 struct tegra_dc_dsi_data *dsi)
1758 {
1759         u32 shift_clk_div_register;
1760         u32 val;
1761
1762         /* formula: (dsi->shift_clk_div - 1) * 2 */
1763         shift_clk_div_register = (dsi->shift_clk_div.mul -
1764                                 dsi->shift_clk_div.div) * 2 /
1765                                 dsi->shift_clk_div.div;
1766
1767 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1768         shift_clk_div_register = 1;
1769         if (dsi->info.ganged_type)
1770                 shift_clk_div_register = 0;
1771 #endif
1772
1773         /* TODO: find out if PCD3 option is required */
1774         val = PIXEL_CLK_DIVIDER_PCD1 |
1775                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1776         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1777 }
1778
1779 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1780                         struct tegra_dc_dsi_data *dsi, u32 clk)
1781 {
1782         u32 rm;
1783         u32 pclk_khz;
1784
1785         /* Round up to MHz */
1786         rm = clk % 1000;
1787         if (rm != 0)
1788                 clk -= rm;
1789
1790         /* Set up pixel clock */
1791         pclk_khz = (clk * dsi->shift_clk_div.div) /
1792                                 dsi->shift_clk_div.mul;
1793
1794         dc->mode.pclk = pclk_khz * 1000;
1795
1796         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1797         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1798
1799         /* TODO: Define one shot work delay in board file. */
1800         /* Since for one-shot mode, refresh rate is usually set larger than
1801          * expected refresh rate, it needs at least 3 frame period. Less
1802          * delay one shot work is, more powering saving we have. */
1803         dc->one_shot_delay_ms = 4 *
1804                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1805
1806         /* Enable DSI clock */
1807         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1808         tegra_dsi_clk_enable(dsi);
1809         tegra_periph_reset_deassert(dsi->dsi_clk);
1810
1811         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1812         dsi->current_bit_clk_ns =  DIV_ROUND_CLOSEST((1000 * 1000),
1813                                                 (dsi->current_dsi_clk_khz * 2));
1814 }
1815
1816 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1817 {
1818         u32 val;
1819
1820         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1821         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1822
1823         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1824                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1825                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1826         } else {
1827                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1828                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1829         }
1830         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1831
1832         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1833         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1834         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1835         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1836
1837         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1838 }
1839
1840 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1841 {
1842         u32 val;
1843         tegra_dsi_hs_clk_out_enable(dsi);
1844
1845         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1846         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1847         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1848         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1849 }
1850
1851 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1852                                                 struct tegra_dc_dsi_data *dsi)
1853 {
1854         u32 val;
1855
1856         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1857                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1858
1859         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1860         /* stabilization delay */
1861         udelay(300);
1862
1863         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1864         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1865         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1866         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1867
1868         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1869         /* stabilization delay */
1870         udelay(300);
1871
1872         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1873         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1874 }
1875
1876 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1877 {
1878         u32 dsi_control;
1879         u32 host_dsi_control;
1880         u32 max_threshold;
1881
1882         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1883         host_dsi_control = HOST_DSI_CTRL_COMMON |
1884                         HOST_DSI_CTRL_HOST_DRIVEN |
1885                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1886         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1887
1888         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1889         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1890         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1891
1892         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1893         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1894         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1895 }
1896
1897 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1898                                                 u8 driven_mode)
1899 {
1900         u32 dsi_control;
1901         u32 host_dsi_control;
1902         u32 max_threshold;
1903         u32 dcs_cmd;
1904
1905         dsi_control = dsi->dsi_control_val;
1906         host_dsi_control = HOST_DSI_CTRL_COMMON;
1907         max_threshold = 0;
1908         dcs_cmd = 0;
1909
1910         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1911                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1912                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1913                 max_threshold =
1914                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1915                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1916         } else {
1917                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1918                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1919                 max_threshold =
1920                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1921                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1922
1923                 if (dsi->info.video_data_type ==
1924                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1925                         dsi_control |= DSI_CTRL_CMD_MODE;
1926                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1927                                 DSI_WRITE_MEMORY_START)|
1928                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1929                                 DSI_WRITE_MEMORY_CONTINUE);
1930                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1931                 } else {
1932                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1933                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1934                 }
1935         }
1936
1937         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1938         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1939         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1940         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1941 }
1942
1943 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1944 {
1945         u32 val;
1946
1947         if (dsi->info.controller_vs == DSI_VS_1) {
1948                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1949                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1950                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1951                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1952                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1953                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1954                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
1955                                                 (TEGRA_DSI_PAD_DISABLE) |
1956                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1957                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
1958                                                 (TEGRA_DSI_PAD_DISABLE);
1959                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1960         } else {
1961                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1962                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1963                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1964                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1965                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1966                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
1967                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
1968                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1969         }
1970 }
1971
1972 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
1973 {
1974         u32 val;
1975
1976         if (dsi->info.controller_vs == DSI_VS_1) {
1977                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1978                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1979                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1980                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1981                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1982                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1983                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
1984                                                 TEGRA_DSI_PAD_ENABLE) |
1985                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
1986                                                 TEGRA_DSI_PAD_ENABLE) |
1987                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
1988                                                 TEGRA_DSI_PAD_ENABLE);
1989                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1990         } else {
1991                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1992                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1993                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1994                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1995                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1996                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
1997                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
1998                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1999         }
2000 }
2001 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2002 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2003 {
2004         u32 val;
2005         /* Calibration settings begin */
2006         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2007                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2008                 DSI_PAD_OUTADJCLK(0x0));
2009         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2010
2011         if (!dsi->controller_index) {
2012                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2013                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2014                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2015                         MIPI_CAL_SELDSIA(0x1) |
2016                         MIPI_CAL_HSPDOSDSIA(0x0) |
2017                         MIPI_CAL_HSPUOSDSIA(0x4) |
2018                         MIPI_CAL_TERMOSDSIA(0x5);
2019                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2020                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2021                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2022                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2023
2024                 /* Deselect PAD C */
2025                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2026                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2027                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2028                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2029                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2030
2031                 /* Deselect PAD D */
2032                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2033                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2034                 val &= ~(MIPI_CAL_SELDSID(0x1));
2035                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2036                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2037         } else {
2038                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2039                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2040                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2041                         MIPI_CAL_SELDSIC(0x1) |
2042                         MIPI_CAL_HSPDOSDSIC(0x0) |
2043                         MIPI_CAL_HSPUOSDSIC(0x4) |
2044                         MIPI_CAL_TERMOSDSIC(0x5);
2045                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2046                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2047                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2048                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2049
2050                 /* Deselect PAD A */
2051                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2052                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2053                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2054                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2055                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2056
2057                 /* Deselect PAD B */
2058                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2059                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2060                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2061                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2062                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2063         }
2064
2065         val = tegra_mipi_cal_read(dsi->mipi_cal,
2066                 MIPI_CAL_MIPI_CAL_CTRL_0);
2067         val = MIPI_CAL_NOISE_FLT(0xa) |
2068                   MIPI_CAL_PRESCALE(0x2) |
2069                   MIPI_CAL_CLKEN_OVR(0x1) |
2070                   MIPI_CAL_AUTOCAL_EN(0x0);
2071         tegra_mipi_cal_write(dsi->mipi_cal, val,
2072                 MIPI_CAL_MIPI_CAL_CTRL_0);
2073
2074 }
2075 #endif
2076
2077 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2078 {
2079         u32 val;
2080         u32 timeout = 0;
2081
2082         if (!dsi->ulpm)
2083                 tegra_dsi_pad_enable(dsi);
2084         else
2085                 tegra_dsi_pad_disable(dsi);
2086
2087         if (dsi->info.controller_vs == DSI_VS_1) {
2088
2089                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2090
2091                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2092
2093                 tegra_mipi_cal_write(dsi->mipi_cal,
2094                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2095                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2096                 tegra_mipi_cal_write(dsi->mipi_cal,
2097                         PAD_PDVREG(0x0),
2098                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2099
2100 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2101                 tegra_dsi_mipi_calibration_11x(dsi);
2102 #endif
2103
2104                 /* Start calibration */
2105                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2106                         MIPI_CAL_MIPI_CAL_CTRL_0);
2107                 val |= (MIPI_CAL_STARTCAL(0x1));
2108                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2109                         MIPI_CAL_MIPI_CAL_CTRL_0);
2110
2111                 for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2112                                 timeout; timeout -= 100) {
2113                         val = tegra_mipi_cal_read(dsi->mipi_cal,
2114                         MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2115                         if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2116                                 (val & MIPI_AUTO_CAL_DONE(0x1))) {
2117                                         dev_err(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2118                                         break;
2119                         }
2120                         usleep_range(10, 100);
2121                 }
2122                 if (timeout <= 0)
2123                         dev_err(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2124
2125                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2126         } else {
2127                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2128                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2129                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2130                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2131                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2132                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2133
2134                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2135                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2136                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2137                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2138                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2139
2140                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2141
2142                 val = MIPI_CAL_TERMOSA(0x4);
2143                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2144
2145                 val = MIPI_CAL_TERMOSB(0x4);
2146                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2147
2148                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2149                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2150
2151                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2152                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2153         }
2154
2155         val = PAD_CIL_PDVREG(0x0);
2156         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2157 }
2158
2159 static void tegra_dsi_panelB_enable(void)
2160 {
2161         unsigned int val;
2162
2163         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2164         val |= DSIB_MODE_ENABLE;
2165         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2166 }
2167
2168 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2169                                 struct tegra_dc_dsi_data *dsi)
2170 {
2171         u32 i;
2172
2173         regulator_enable(dsi->avdd_dsi_csi);
2174         /* stablization delay */
2175         mdelay(50);
2176
2177         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2178
2179         /* Stop DC stream before configuring DSI registers
2180          * to avoid visible glitches on panel during transition
2181          * from bootloader to kernel driver
2182          */
2183         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2184
2185         tegra_dsi_writel(dsi,
2186                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2187                 DSI_POWER_CONTROL);
2188         /* stabilization delay */
2189         udelay(300);
2190
2191         if (dsi->info.dsi_instance)
2192                 tegra_dsi_panelB_enable();
2193
2194         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2195
2196         /* Initialize DSI registers */
2197         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2198                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2199         if (dsi->info.controller_vs == DSI_VS_1) {
2200                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2201                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2202         }
2203
2204         tegra_dsi_pad_calibration(dsi);
2205
2206         tegra_dsi_writel(dsi,
2207                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2208                 DSI_POWER_CONTROL);
2209         /* stabilization delay */
2210         udelay(300);
2211
2212         dsi->status.init = DSI_MODULE_INIT;
2213         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2214         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2215         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2216         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2217         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2218         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2219         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2220         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2221
2222         return 0;
2223 }
2224
2225 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2226                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2227 {
2228         int err;
2229
2230         if (dsi->status.init != DSI_MODULE_INIT) {
2231                 err = -EPERM;
2232                 goto fail;
2233         }
2234
2235         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2236                         dsi->status.lp_op == lp_op)
2237                 goto success;
2238
2239         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2240                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2241
2242         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2243         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2244                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2245                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2246
2247         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2248         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2249                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2250                 tegra_dsi_set_timeout(dsi);
2251         }
2252
2253         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2254
2255         tegra_dsi_set_control_reg_lp(dsi);
2256
2257         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2258                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2259                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2260
2261         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2262         dsi->status.lp_op = lp_op;
2263         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2264 success:
2265         err = 0;
2266 fail:
2267         return err;
2268 }
2269
2270 static void tegra_dsi_ganged(struct tegra_dc *dc,
2271                                 struct tegra_dc_dsi_data *dsi)
2272 {
2273         u32 start = 0;
2274         u32 low_width = 0;
2275         u32 high_width = 0;
2276         u32 h_active = dc->out->modes->h_active;
2277         u32 val = 0;
2278
2279         if (dsi->info.controller_vs < DSI_VS_1) {
2280                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2281                 "supported with current controller version\n");
2282                 return;
2283         }
2284
2285         if (dsi->info.ganged_type ==
2286                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2287                 low_width = DIV_ROUND_UP(h_active, 2);
2288                 high_width = h_active - low_width;
2289                 if (dsi->controller_index)
2290                         start = h_active / 2;
2291                 else
2292                         start = 0;
2293         } else if (dsi->info.ganged_type ==
2294                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2295                 low_width = 0x1;
2296                 high_width = 0x1;
2297                 if (dsi->controller_index)
2298                         start = 1;
2299                 else
2300                         start = 0;
2301         }
2302
2303         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2304                                                 DSI_GANGED_MODE_START);
2305
2306         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2307                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2308         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2309
2310         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2311                                                 DSI_GANGED_MODE_CONTROL);
2312 }
2313
2314 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2315                                         struct tegra_dc_dsi_data *dsi,
2316                                         u8 driven_mode)
2317 {
2318         int err;
2319
2320         if (dsi->status.init != DSI_MODULE_INIT) {
2321                 err = -EPERM;
2322                 goto fail;
2323         }
2324
2325         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2326                 dsi->driven_mode == driven_mode)
2327                 goto success;
2328
2329         dsi->driven_mode = driven_mode;
2330
2331         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2332                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2333
2334         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2335                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2336                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2337
2338         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2339                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2340                 tegra_dsi_set_timeout(dsi);
2341         }
2342
2343         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2344
2345         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2346                 tegra_dsi_set_pkt_seq(dc, dsi);
2347                 tegra_dsi_set_pkt_length(dc, dsi);
2348                 tegra_dsi_set_sol_delay(dc, dsi);
2349                 tegra_dsi_set_dc_clk(dc, dsi);
2350         }
2351
2352         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2353
2354         if (dsi->info.ganged_type)
2355                 tegra_dsi_ganged(dc, dsi);
2356
2357         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2358                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2359                 tegra_dsi_hs_clk_out_enable(dsi);
2360
2361         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2362 success:
2363         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2364         err = 0;
2365 fail:
2366         return err;
2367 }
2368
2369 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2370 {
2371         u32 timeout = 0;
2372         bool retVal = true;
2373
2374         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2375                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2376                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2377                         retVal = false;
2378                         break;
2379                 }
2380                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2381                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2382         }
2383
2384         return retVal;
2385 }
2386
2387 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2388 {
2389         u32 timeout = 0;
2390         bool retVal = true;
2391
2392         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2393                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2394                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2395                         retVal = false;
2396                         break;
2397                 }
2398                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2399                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2400         }
2401
2402         return retVal;
2403 }
2404
2405 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2406 {
2407         int err = 0;
2408
2409         if (tegra_dsi_write_busy(dsi)) {
2410                 err = -EBUSY;
2411                 dev_err(&dsi->dc->ndev->dev,
2412                         "DSI trigger bit already set\n");
2413                 goto fail;
2414         }
2415
2416         if (tegra_dsi_read_busy(dsi)) {
2417                 err = -EBUSY;
2418                 dev_err(&dsi->dc->ndev->dev,
2419                         "DSI immediate bta bit already set\n");
2420                 goto fail;
2421         }
2422 fail:
2423         return (err < 0 ? true : false);
2424 }
2425
2426 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2427 {
2428         u32 val;
2429
2430         val = tegra_dsi_readl(dsi, DSI_STATUS);
2431         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2432         if (val) {
2433                 dev_warn(&dsi->dc->ndev->dev,
2434                         "DSI read count not zero, resetting\n");
2435                 tegra_dsi_soft_reset(dsi);
2436         }
2437 }
2438
2439 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2440                                                 struct tegra_dc_dsi_data *dsi,
2441                                                 struct tegra_dc *dc,
2442                                                 u8 lp_op)
2443 {
2444         struct dsi_status *init_status = NULL;
2445         int err;
2446
2447         if (dsi->status.init != DSI_MODULE_INIT ||
2448                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2449                 err = -EPERM;
2450                 goto fail;
2451         }
2452
2453         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2454         if (!init_status)
2455                 return ERR_PTR(-ENOMEM);
2456
2457         *init_status = dsi->status;
2458
2459         if (dsi->info.hs_cmd_mode_supported) {
2460                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2461                                 TEGRA_DSI_DRIVEN_BY_HOST);
2462                 if (err < 0) {
2463                         dev_err(&dc->ndev->dev,
2464                         "Switch to HS host mode failed\n");
2465                         goto fail;
2466                 }
2467
2468                 goto success;
2469         }
2470
2471         if (dsi->status.lp_op != lp_op) {
2472                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2473                 if (err < 0) {
2474                         dev_err(&dc->ndev->dev,
2475                         "DSI failed to go to LP mode\n");
2476                         goto fail;
2477                 }
2478         }
2479 success:
2480         return init_status;
2481 fail:
2482         kfree(init_status);
2483         return ERR_PTR(err);
2484 }
2485
2486 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2487                                 struct tegra_dc *dc,
2488                                 struct tegra_dc_dsi_data *dsi,
2489                                 u8 lp_op)
2490 {
2491         int err = 0;
2492         struct dsi_status *init_status;
2493         bool restart_dc_stream = false;
2494
2495         if (dsi->status.init != DSI_MODULE_INIT ||
2496                 dsi->ulpm) {
2497                 err = -EPERM;
2498                 goto fail;
2499         }
2500
2501         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2502                 restart_dc_stream = true;
2503                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2504         }
2505
2506         if (tegra_dsi_host_busy(dsi)) {
2507                 tegra_dsi_soft_reset(dsi);
2508                 if (tegra_dsi_host_busy(dsi)) {
2509                         err = -EBUSY;
2510                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2511                         goto fail;
2512                 }
2513         }
2514
2515         if (lp_op == DSI_LP_OP_READ)
2516                 tegra_dsi_reset_read_count(dsi);
2517
2518         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2519                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2520                 if (err < 0) {
2521                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2522                         goto fail;
2523                 }
2524         }
2525
2526         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2527                                         (dsi, dc, lp_op);
2528         if (IS_ERR_OR_NULL(init_status)) {
2529                 err = PTR_ERR(init_status);
2530                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2531                 goto fail;
2532         }
2533
2534         if (restart_dc_stream)
2535                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2536
2537         if (atomic_read(&dsi_syncpt_rst))
2538                 tegra_dsi_syncpt_reset(dsi);
2539
2540         return init_status;
2541 fail:
2542         return ERR_PTR(err);
2543 }
2544
2545 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2546                                 struct tegra_dc_dsi_data *dsi,
2547                                 struct dsi_status *init_status)
2548 {
2549         int err = 0;
2550
2551         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2552                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2553                 if (err < 0) {
2554                         dev_err(&dc->ndev->dev,
2555                                 "Failed to config LP mode\n");
2556                         goto fail;
2557                 }
2558                 goto success;
2559         }
2560
2561         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2562                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2563                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2564                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2565                 if (err < 0) {
2566                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2567                         goto fail;
2568                 }
2569         }
2570
2571         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2572                 tegra_dsi_start_dc_stream(dc, dsi);
2573 success:
2574 fail:
2575         kfree(init_status);
2576         return err;
2577 }
2578
2579 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2580 {
2581         int status = 0;
2582
2583         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2584                 status = -EBUSY;
2585                 goto fail;
2586         }
2587
2588         tegra_dsi_writel(dsi,
2589                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2590
2591 #if DSI_USE_SYNC_POINTS
2592         status = tegra_dsi_syncpt(dsi);
2593         if (status < 0) {
2594                 dev_err(&dsi->dc->ndev->dev,
2595                         "DSI syncpt for host trigger failed\n");
2596                 goto fail;
2597         }
2598 #else
2599         if (tegra_dsi_write_busy(dsi)) {
2600                 status = -EBUSY;
2601                 dev_err(&dsi->dc->ndev->dev,
2602                         "Timeout waiting on write completion\n");
2603         }
2604 #endif
2605
2606 fail:
2607         return status;
2608 }
2609
2610 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2611                                         u8 *pdata, u8 data_id, u16 data_len)
2612 {
2613         u8 virtual_channel;
2614         u32 val;
2615         int err;
2616
2617         err = 0;
2618
2619         virtual_channel = dsi->info.virtual_channel <<
2620                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2621
2622         /* always use hw for ecc */
2623         val = (virtual_channel | data_id) << 0 |
2624                         data_len << 8;
2625         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2626
2627         /* if pdata != NULL, pkt type is long pkt */
2628         if (pdata != NULL) {
2629                 while (data_len) {
2630                         if (data_len >= 4) {
2631                                 val = ((u32 *) pdata)[0];
2632                                 data_len -= 4;
2633                                 pdata += 4;
2634                         } else {
2635                                 val = 0;
2636                                 memcpy(&val, pdata, data_len);
2637                                 pdata += data_len;
2638                                 data_len = 0;
2639                         }
2640                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2641                 }
2642         }
2643
2644         err = tegra_dsi_host_trigger(dsi);
2645         if (err < 0)
2646                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2647
2648         return err;
2649 }
2650
2651 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2652 {
2653         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2654
2655         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2656                 atomic_inc(&dsi->host_ref);
2657                 tegra_dsi_host_resume(dc);
2658         }
2659 }
2660
2661 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2662 {
2663         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2664
2665         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2666                 atomic_dec(&dsi->host_ref);
2667
2668                 if (!atomic_read(&dsi->host_ref) &&
2669                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
2670                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
2671         }
2672 }
2673
2674 static void tegra_dc_dsi_idle_work(struct work_struct *work)
2675 {
2676         struct tegra_dc_dsi_data *dsi = container_of(
2677                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
2678
2679         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2680                 tegra_dsi_host_suspend(dsi->dc);
2681 }
2682
2683 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
2684                         struct tegra_dc_dsi_data *dsi,
2685                         u8 *pdata, u8 data_id, u16 data_len)
2686 {
2687         int err = 0;
2688         struct dsi_status *init_status;
2689
2690         init_status = tegra_dsi_prepare_host_transmission(
2691                                 dc, dsi, DSI_LP_OP_WRITE);
2692         if (IS_ERR_OR_NULL(init_status)) {
2693                 err = PTR_ERR(init_status);
2694                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2695                 goto fail;
2696         }
2697
2698         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2699 fail:
2700         err = tegra_dsi_restore_state(dc, dsi, init_status);
2701         if (err < 0)
2702                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2703
2704         return err;
2705 }
2706
2707 int tegra_dsi_write_data(struct tegra_dc *dc,
2708                         struct tegra_dc_dsi_data *dsi,
2709                         u8 *pdata, u8 data_id, u16 data_len)
2710 {
2711         int err;
2712
2713         tegra_dc_io_start(dc);
2714         tegra_dc_dsi_hold_host(dc);
2715
2716         err = tegra_dsi_write_data_nosync(dc, dsi, pdata, data_id, data_len);
2717
2718         tegra_dc_dsi_release_host(dc);
2719         tegra_dc_io_end(dc);
2720
2721         return err;
2722 }
2723
2724 EXPORT_SYMBOL(tegra_dsi_write_data);
2725
2726 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2727                                         struct tegra_dc_dsi_data *dsi,
2728                                         struct tegra_dsi_cmd *cmd,
2729                                         u32 n_cmd)
2730 {
2731         u32 i;
2732         int err;
2733
2734         err = 0;
2735         for (i = 0; i < n_cmd; i++) {
2736                 struct tegra_dsi_cmd *cur_cmd;
2737                 cur_cmd = &cmd[i];
2738
2739                 /*
2740                  * Some Panels need reset midway in the command sequence.
2741                  */
2742                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
2743                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
2744                                        cur_cmd->data_id);
2745                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
2746                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2747                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
2748                                 tegra_dsi_send_dc_frames(dc,
2749                                                 dsi,
2750                                                 cur_cmd->sp_len_dly.frame_cnt);
2751                 } else {
2752                         err = tegra_dsi_write_data_nosync(dc, dsi,
2753                                                 cur_cmd->pdata,
2754                                                 cur_cmd->data_id,
2755                                                 cur_cmd->sp_len_dly.data_len);
2756                         mdelay(1);
2757                         if (err < 0)
2758                                 break;
2759                 }
2760         }
2761         return err;
2762 }
2763
2764 static u8 tegra_dsi_ecc(u32 header)
2765 {
2766         char ecc_parity[24] = {
2767                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2768                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2769                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2770         };
2771         u8 ecc_byte;
2772         int i;
2773
2774         ecc_byte = 0;
2775         for (i = 0; i < 24; i++)
2776                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2777
2778         return ecc_byte;
2779 }
2780
2781 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2782 {
2783         u16 byte_cnt;
2784         u8 bit_cnt;
2785         char curr_byte;
2786         u16 crc = 0xFFFF;
2787         u16 poly = 0x8408;
2788
2789         if (data_len > 0) {
2790                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2791                         curr_byte = pdata[byte_cnt];
2792                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2793                                 if (((crc & 0x0001 ) ^
2794                                         (curr_byte & 0x0001)) > 0)
2795                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2796                                 else
2797                                         crc = (crc >> 1) & 0x7FFF;
2798
2799                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2800                         }
2801                 }
2802         }
2803         return crc;
2804 }
2805
2806 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2807                                                 struct tegra_dsi_cmd *cmd)
2808 {
2809         u8 virtual_channel;
2810         u32 val;
2811         u16 data_len = cmd->sp_len_dly.data_len;
2812         u8 seq_ctrl_reg = 0;
2813
2814         virtual_channel = dsi->info.virtual_channel <<
2815                                 DSI_VIR_CHANNEL_BIT_POSITION;
2816
2817         val = (virtual_channel | cmd->data_id) << 0 |
2818                 data_len << 8;
2819
2820         val |= tegra_dsi_ecc(val) << 24;
2821
2822         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2823
2824         /* if pdata != NULL, pkt type is long pkt */
2825         if (cmd->pdata != NULL) {
2826                 u8 *pdata;
2827                 u8 *pdata_mem;
2828                 /* allocate memory for pdata + 2 bytes checksum */
2829                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2830                 if (!pdata_mem) {
2831                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2832                         tegra_dsi_soft_reset(dsi);
2833                         return -ENOMEM;
2834                 }
2835
2836                 memcpy(pdata_mem, cmd->pdata, data_len);
2837                 pdata = pdata_mem;
2838                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2839
2840                 /* data_len = length of pdata + 2 byte checksum */
2841                 data_len += 2;
2842
2843                 while (data_len) {
2844                         if (data_len >= 4) {
2845                                 val = ((u32 *) pdata)[0];
2846                                 data_len -= 4;
2847                                 pdata += 4;
2848                         } else {
2849                                 val = 0;
2850                                 memcpy(&val, pdata, data_len);
2851                                 pdata += data_len;
2852                                 data_len = 0;
2853                         }
2854                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2855                                                         seq_ctrl_reg++);
2856                 }
2857                 kfree(pdata_mem);
2858         }
2859
2860         return 0;
2861 }
2862
2863 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2864                                                 struct tegra_dsi_cmd *cmd)
2865 {
2866 #define PKT_HEADER_LEN_BYTE     4
2867 #define CHECKSUM_LEN_BYTE       2
2868
2869         int err = 0;
2870         u32 val;
2871         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2872         struct tegra_dc *dc = dsi->dc;
2873
2874         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2875                 return -EINVAL;
2876
2877         mutex_lock(&dsi->lock);
2878         tegra_dc_io_start(dc);
2879         tegra_dc_dsi_hold_host(dc);
2880
2881 #if DSI_USE_SYNC_POINTS
2882         atomic_set(&dsi_syncpt_rst, 1);
2883 #endif
2884
2885         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2886         if (err < 0) {
2887                 dev_err(&dsi->dc->ndev->dev,
2888                         "dsi: dcs pkt seq ctrl init failed\n");
2889                 goto fail;
2890         }
2891
2892         if (cmd->pdata) {
2893                 u16 data_len = cmd->sp_len_dly.data_len;
2894                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2895         }
2896
2897         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2898                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2899                                                 TEGRA_DSI_ENABLE);
2900         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2901
2902 fail:
2903         tegra_dc_dsi_release_host(dc);
2904         tegra_dc_io_end(dc);
2905         mutex_unlock(&dsi->lock);
2906         return err;
2907
2908 #undef PKT_HEADER_LEN_BYTE
2909 #undef CHECKSUM_LEN_BYTE
2910 }
2911 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2912
2913 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2914 {
2915         struct tegra_dc *dc = dsi->dc;
2916         u32 cnt;
2917
2918         mutex_lock(&dsi->lock);
2919         tegra_dc_io_start(dc);
2920         tegra_dc_dsi_hold_host(dc);
2921
2922         if (atomic_read(&dsi_syncpt_rst)) {
2923                 tegra_dsi_wait_frame_end(dc, dsi, 2);
2924                 tegra_dsi_syncpt_reset(dsi);
2925                 atomic_set(&dsi_syncpt_rst, 0);
2926         }
2927
2928         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2929
2930         /* clear seq data registers */
2931         for (cnt = 0; cnt < 8; cnt++)
2932                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2933
2934         tegra_dc_dsi_release_host(dc);
2935         tegra_dc_io_end(dc);
2936
2937         mutex_unlock(&dsi->lock);
2938 }
2939 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2940
2941 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2942 {
2943         u32 val;
2944         int err = 0;
2945
2946         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2947         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2948         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2949
2950 #if DSI_USE_SYNC_POINTS
2951         err = tegra_dsi_syncpt(dsi);
2952         if (err < 0) {
2953                 dev_err(&dsi->dc->ndev->dev,
2954                         "DSI syncpt for bta failed\n");
2955         }
2956 #else
2957         if (tegra_dsi_read_busy(dsi)) {
2958                 err = -EBUSY;
2959                 dev_err(&dsi->dc->ndev->dev,
2960                         "Timeout wating on read completion\n");
2961         }
2962 #endif
2963
2964         return err;
2965 }
2966
2967 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2968                                         u32 rd_fifo_cnt, u8 *read_fifo)
2969 {
2970         int err;
2971         u32 payload_size;
2972
2973         payload_size = 0;
2974         err = 0;
2975
2976         switch (read_fifo[0]) {
2977         case DSI_ESCAPE_CMD:
2978                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2979                 break;
2980         case DSI_ACK_NO_ERR:
2981                 dev_info(&dc->ndev->dev,
2982                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2983                 return err;
2984         default:
2985                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2986                 break;
2987         }
2988
2989         switch (read_fifo[4] & 0xff) {
2990         case GEN_LONG_RD_RES:
2991                 /* Fall through */
2992         case DCS_LONG_RD_RES:
2993                 payload_size = (read_fifo[5] |
2994                                 (read_fifo[6] << 8)) & 0xFFFF;
2995                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2996                                 "payload_size[0x%x]\n", payload_size);
2997                 break;
2998         case GEN_1_BYTE_SHORT_RD_RES:
2999                 /* Fall through */
3000         case DCS_1_BYTE_SHORT_RD_RES:
3001                 payload_size = 1;
3002                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3003                         "payload_size[0x%x]\n", payload_size);
3004                 break;
3005         case GEN_2_BYTE_SHORT_RD_RES:
3006                 /* Fall through */
3007         case DCS_2_BYTE_SHORT_RD_RES:
3008                 payload_size = 2;
3009                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3010                         "payload_size[0x%x]\n", payload_size);
3011                 break;
3012         case ACK_ERR_RES:
3013                 payload_size = 2;
3014                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3015                         "Packet payload_size[0x%x]\n", payload_size);
3016                 break;
3017         default:
3018                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3019                 err = -EINVAL;
3020                 break;
3021         }
3022         return err;
3023 }
3024
3025 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3026                         struct tegra_dc_dsi_data *dsi,
3027                         u8 *read_fifo)
3028 {
3029         u32 val;
3030         u32 i;
3031         u32 poll_time = 0;
3032         u32 rd_fifo_cnt;
3033         int err = 0;
3034         u8 *read_fifo_cp = read_fifo;
3035
3036         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3037                 mdelay(1);
3038                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3039                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3040                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3041                         dev_err(&dc->ndev->dev,
3042                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3043                         break;
3044                 }
3045                 poll_time++;
3046         }
3047
3048         if (rd_fifo_cnt == 0) {
3049                 dev_info(&dc->ndev->dev,
3050                         "DSI RD_FIFO_CNT is zero\n");
3051                 err = -EINVAL;
3052                 goto fail;
3053         }
3054
3055         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3056                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3057                 dev_warn(&dc->ndev->dev,
3058                         "DSI overflow/underflow error\n");
3059         }
3060
3061         /* Read data from FIFO */
3062         for (i = 0; i < rd_fifo_cnt; i++) {
3063                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3064                 if (enable_read_debug)
3065                         dev_info(&dc->ndev->dev,
3066                         "Read data[%d]: 0x%x\n", i, val);
3067                 memcpy(read_fifo, &val, 4);
3068                 read_fifo += 4;
3069         }
3070
3071         /* Make sure all the data is read from the FIFO */
3072         val = tegra_dsi_readl(dsi, DSI_STATUS);
3073         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3074         if (val)
3075                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3076                 " even after reading FIFO_RD_CNT words from read fifo\n");
3077
3078         if (enable_read_debug) {
3079                 err =
3080                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3081                 if (err < 0)
3082                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3083         }
3084 fail:
3085         return err;
3086 }
3087
3088 int tegra_dsi_read_data(struct tegra_dc *dc,
3089                                 struct tegra_dc_dsi_data *dsi,
3090                                 u32 max_ret_payload_size,
3091                                 u32 panel_reg_addr, u8 *read_data)
3092 {
3093         int err = 0;
3094         struct dsi_status *init_status;
3095
3096         if (!dsi->enabled) {
3097                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3098                 return -EINVAL;
3099         }
3100         tegra_dc_dsi_hold_host(dc);
3101         mutex_lock(&dsi->lock);
3102         tegra_dc_io_start(dc);
3103         clk_prepare_enable(dsi->dsi_fixed_clk);
3104         clk_prepare_enable(dsi->dsi_lp_clk);
3105         init_status = tegra_dsi_prepare_host_transmission(
3106                                 dc, dsi, DSI_LP_OP_WRITE);
3107         if (IS_ERR_OR_NULL(init_status)) {
3108                 err = PTR_ERR(init_status);
3109                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3110                 goto fail;
3111         }
3112
3113         /* Set max return payload size in words */
3114         err = _tegra_dsi_write_data(dsi, NULL,
3115                 dsi_command_max_return_pkt_size,
3116                 max_ret_payload_size);
3117         if (err < 0) {
3118                 dev_err(&dc->ndev->dev,
3119                                 "DSI write failed\n");
3120                 goto fail;
3121         }
3122
3123         /* DCS to read given panel register */
3124         err = _tegra_dsi_write_data(dsi, NULL,
3125                 dsi_command_dcs_read_with_no_params,
3126                 panel_reg_addr);
3127         if (err < 0) {
3128                 dev_err(&dc->ndev->dev,
3129                                 "DSI write failed\n");
3130                 goto fail;
3131         }
3132
3133         tegra_dsi_reset_read_count(dsi);
3134
3135         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3136                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3137                 if (err < 0) {
3138                         dev_err(&dc->ndev->dev,
3139                         "DSI failed to go to LP read mode\n");
3140                         goto fail;
3141                 }
3142         }
3143
3144         err = tegra_dsi_bta(dsi);
3145         if (err < 0) {
3146                 dev_err(&dc->ndev->dev,
3147                         "DSI IMM BTA timeout\n");
3148                 goto fail;
3149         }
3150
3151         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3152         if (err < 0) {
3153                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3154                 goto fail;
3155         }
3156 fail:
3157         err = tegra_dsi_restore_state(dc, dsi, init_status);
3158         if (err < 0)
3159                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3160         clk_disable_unprepare(dsi->dsi_lp_clk);
3161         clk_disable_unprepare(dsi->dsi_fixed_clk);
3162         tegra_dc_io_end(dc);
3163         mutex_unlock(&dsi->lock);
3164         tegra_dc_dsi_release_host(dc);
3165         return err;
3166 }
3167 EXPORT_SYMBOL(tegra_dsi_read_data);
3168
3169 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3170                                 struct tegra_dc_dsi_data *dsi)
3171 {
3172         int err = 0;
3173         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3174         struct dsi_status *init_status;
3175         static struct tegra_dsi_cmd dsi_nop_cmd =
3176                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3177
3178         if (!dsi->enabled) {
3179                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3180                 return -EINVAL;
3181         }
3182         tegra_dc_dsi_hold_host(dc);
3183         tegra_dc_io_start(dc);
3184         clk_prepare_enable(dsi->dsi_fixed_clk);
3185         clk_prepare_enable(dsi->dsi_lp_clk);
3186
3187         init_status = tegra_dsi_prepare_host_transmission(
3188                                         dc, dsi, DSI_LP_OP_WRITE);
3189         if (IS_ERR_OR_NULL(init_status)) {
3190                 err = PTR_ERR(init_status);
3191                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3192                 goto fail;
3193         }
3194
3195         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
3196         if (err < 0) {
3197                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3198                 goto fail;
3199         }
3200
3201         tegra_dsi_reset_read_count(dsi);
3202
3203         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3204                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3205                 if (err < 0) {
3206                         dev_err(&dc->ndev->dev,
3207                         "DSI failed to go to LP read mode\n");
3208                         goto fail;
3209                 }
3210         }
3211
3212         err = tegra_dsi_bta(dsi);
3213         if (err < 0) {
3214                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3215                 goto fail;
3216         }
3217
3218         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3219         if (err < 0) {
3220                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3221                 goto fail;
3222         }
3223
3224         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3225                 dev_warn(&dc->ndev->dev,
3226                         "Ack no error trigger message not received\n");
3227                 err = -EAGAIN;
3228         }
3229 fail:
3230         err = tegra_dsi_restore_state(dc, dsi, init_status);
3231         if (err < 0)
3232                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3233         clk_disable_unprepare(dsi->dsi_lp_clk);
3234         clk_disable_unprepare(dsi->dsi_fixed_clk);
3235         tegra_dc_io_end(dc);
3236         tegra_dc_dsi_release_host(dc);
3237         return err;
3238 }
3239 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3240
3241 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3242 {
3243         u32 val;
3244         int ret = 0;
3245
3246         if (atomic_read(&dsi_syncpt_rst))
3247                 tegra_dsi_syncpt_reset(dsi);
3248
3249         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3250         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3251         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3252         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3253
3254 #if DSI_USE_SYNC_POINTS
3255         ret = tegra_dsi_syncpt(dsi);
3256         if (ret < 0) {
3257                 dev_err(&dsi->dc->ndev->dev,
3258                         "DSI syncpt for ulpm enter failed\n");
3259                 return ret;
3260         }
3261 #else
3262         /* TODO: Find exact delay required */
3263         mdelay(10);
3264 #endif
3265         dsi->ulpm = true;
3266
3267         return ret;
3268 }
3269
3270 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3271 {
3272         u32 val;
3273         int ret = 0;
3274
3275         if (atomic_read(&dsi_syncpt_rst))
3276                 tegra_dsi_syncpt_reset(dsi);
3277
3278         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3279         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3280         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3281         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3282
3283 #if DSI_USE_SYNC_POINTS
3284         ret = tegra_dsi_syncpt(dsi);
3285         if (ret < 0) {
3286                 dev_err(&dsi->dc->ndev->dev,
3287                         "DSI syncpt for ulpm exit failed\n");
3288                 return ret;
3289         }
3290 #else
3291         /* TODO: Find exact delay required */
3292         mdelay(10);
3293 #endif
3294         dsi->ulpm = false;
3295
3296         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3297         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3298         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3299         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3300
3301         return ret;
3302 }
3303
3304 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3305                                      struct tegra_dc_dsi_data *dsi,
3306                                      int no_of_frames)
3307 {
3308         int err;
3309         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3310         u8 lp_op = dsi->status.lp_op;
3311         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3312
3313         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3314                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3315                                 TEGRA_DSI_DRIVEN_BY_DC);
3316                 if (err < 0) {
3317                         dev_err(&dc->ndev->dev,
3318                                 "Switch to HS host mode failed\n");
3319                         return;
3320                 }
3321         }
3322
3323         /*
3324          * Some panels need DC frames be sent under certain
3325          * conditions. We are working on the right fix for this
3326          * requirement, while using this current fix.
3327          */
3328         tegra_dsi_start_dc_stream(dc, dsi);
3329
3330         /*
3331          * Send frames in Continuous or One-shot mode.
3332          */
3333         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3334                 while (no_of_frames--) {
3335                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3336                                         DC_CMD_STATE_CONTROL);
3337                         mdelay(frame_period);
3338                 }
3339         } else
3340                 mdelay(no_of_frames * frame_period);
3341
3342         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3343
3344         if (switch_to_lp) {
3345                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3346                 if (err < 0)
3347                         dev_err(&dc->ndev->dev,
3348                                 "DSI failed to go to LP mode\n");
3349         }
3350 }
3351
3352 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
3353 {
3354         regulator_enable(dsi->avdd_dsi_csi);
3355
3356         dsi->status.init = DSI_MODULE_INIT;
3357         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
3358         dsi->status.driven = DSI_DRIVEN_MODE_DC;
3359         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3360         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
3361         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
3362         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
3363
3364         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
3365                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
3366         else
3367                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
3368
3369         if (!(dsi->info.ganged_type)) {
3370                 if (dsi->info.video_burst_mode ==
3371                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
3372                         dsi->info.video_burst_mode ==
3373                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
3374                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
3375                 else
3376                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
3377         }
3378
3379         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
3380                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
3381         else
3382                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
3383
3384         tegra_dsi_clk_enable(dsi);
3385
3386         dsi->enabled = true;
3387 }
3388
3389 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3390 {
3391         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3392         int err = 0;
3393
3394         mutex_lock(&dsi->lock);
3395         tegra_dc_io_start(dc);
3396
3397         /*
3398          * Do not program this panel as the bootloader as has already
3399          * initialized it. This avoids periods of blanking during boot.
3400          */
3401         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
3402                 tegra_dsi_setup_initialized_panel(dsi);
3403                 goto fail;
3404         }
3405
3406         /* Stop DC stream before configuring DSI registers
3407          * to avoid visible glitches on panel during transition
3408          * from bootloader to kernel driver
3409          */
3410         tegra_dsi_stop_dc_stream(dc, dsi);
3411
3412         if (dsi->enabled) {
3413                 if (dsi->ulpm) {
3414                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3415                                 dev_err(&dc->ndev->dev,
3416                                         "DSI failed to exit ulpm\n");
3417                                 goto fail;
3418                         }
3419                 }
3420
3421                 if (dsi->info.panel_reset) {
3422                         /*
3423                          * Certain panels need dc frames be sent before
3424                          * waking panel.
3425                          */
3426                         if (dsi->info.panel_send_dc_frames)
3427                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3428
3429                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3430                                                         dsi->info.dsi_init_cmd,
3431                                                         dsi->info.n_init_cmd);
3432                         if (err < 0) {
3433                                 dev_err(&dc->ndev->dev,
3434                                 "dsi: error sending dsi init cmd\n");
3435                                 goto fail;
3436                         }
3437                 } else if (dsi->info.dsi_late_resume_cmd) {
3438                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3439                                                 dsi->info.dsi_late_resume_cmd,
3440                                                 dsi->info.n_late_resume_cmd);
3441                         if (err < 0) {
3442                                 dev_err(&dc->ndev->dev,
3443                                 "dsi: error sending late resume cmd\n");
3444                                 goto fail;
3445                         }
3446                 }
3447         } else {
3448                 err = tegra_dsi_init_hw(dc, dsi);
3449                 if (err < 0) {
3450                         dev_err(&dc->ndev->dev,
3451                                 "dsi: not able to init dsi hardware\n");
3452                         goto fail;
3453                 }
3454
3455                 if (dsi->ulpm) {
3456                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3457                                 dev_err(&dc->ndev->dev,
3458                                         "DSI failed to enter ulpm\n");
3459                                 goto fail;
3460                         }
3461
3462                         tegra_dsi_pad_enable(dsi);
3463
3464                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3465                                 dev_err(&dc->ndev->dev,
3466                                         "DSI failed to exit ulpm\n");
3467                                 goto fail;
3468                         }
3469                 }
3470
3471                 /*
3472                  * Certain panels need dc frames be sent before
3473                  * waking panel.
3474                  */
3475                 if (dsi->info.panel_send_dc_frames)
3476                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3477
3478                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3479                 if (err < 0) {
3480                         dev_err(&dc->ndev->dev,
3481                                 "dsi: not able to set to lp mode\n");
3482                         goto fail;
3483                 }
3484
3485                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3486                                                 dsi->info.n_init_cmd);
3487                 if (err < 0) {
3488                         dev_err(&dc->ndev->dev,
3489                                 "dsi: error while sending dsi init cmd\n");
3490                         goto fail;
3491                 }
3492
3493                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3494                                 TEGRA_DSI_DRIVEN_BY_DC);
3495                 if (err < 0) {
3496                         dev_err(&dc->ndev->dev,
3497                                 "dsi: not able to set to hs mode\n");
3498                         goto fail;
3499                 }
3500
3501                 dsi->enabled = true;
3502         }
3503
3504         if (dsi->out_ops && dsi->out_ops->enable)
3505                 dsi->out_ops->enable(dsi);
3506
3507         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3508                 tegra_dsi_start_dc_stream(dc, dsi);
3509
3510         dsi->host_suspended = false;
3511         atomic_set(&display_ready, 1);
3512 fail:
3513         tegra_dc_io_end(dc);
3514         mutex_unlock(&dsi->lock);
3515 }
3516
3517 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3518 {
3519         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3520
3521         tegra_dc_dsi_debug_create(dsi);
3522
3523         if (dsi->info.dsi2lvds_bridge_enable)
3524                 dsi->out_ops = &tegra_dsi2lvds_ops;
3525         else if (dsi->info.dsi2edp_bridge_enable)
3526                 dsi->out_ops = &tegra_dsi2edp_ops;
3527         else
3528                 dsi->out_ops = NULL;
3529
3530         if (dsi->out_ops && dsi->out_ops->init)
3531                 dsi->out_ops->init(dsi);
3532
3533         tegra_dsi_init_sw(dc, dsi);
3534 }
3535
3536 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3537                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3538 {
3539         u16 i;
3540         u16 len;
3541
3542         memcpy(dst, src, sizeof(*dst) * n_cmd);
3543
3544         for (i = 0; i < n_cmd; i++)
3545                 if (src[i].pdata) {
3546                         len = sizeof(*src[i].pdata) *
3547                                         src[i].sp_len_dly.data_len;
3548                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3549                         if (!dst[i].pdata)
3550                                 goto free_cmd_pdata;
3551                         memcpy(dst[i].pdata, src[i].pdata, len);
3552                 }
3553
3554         return 0;
3555
3556 free_cmd_pdata:
3557         while (i--)
3558                 if (dst[i].pdata)
3559                         kfree(dst[i].pdata);
3560         return -ENOMEM;
3561 }
3562
3563 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
3564                                         struct tegra_dsi_out *p_dsi)
3565 {
3566         struct tegra_dsi_cmd *p_init_cmd;
3567         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3568         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3569         struct tegra_dsi_cmd *p_suspend_cmd;
3570         int err;
3571
3572         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
3573                 return -EINVAL;
3574
3575         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3576                                 p_dsi->n_init_cmd, GFP_KERNEL);
3577         if (!p_init_cmd)
3578                 return -ENOMEM;
3579
3580         if (p_dsi->dsi_early_suspend_cmd) {
3581                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3582                                         p_dsi->n_early_suspend_cmd,
3583                                         GFP_KERNEL);
3584                 if (!p_early_suspend_cmd) {
3585                         err = -ENOMEM;
3586                         goto err_free_init_cmd;
3587                 }
3588         }
3589
3590         if (p_dsi->dsi_late_resume_cmd) {
3591                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3592                                         p_dsi->n_late_resume_cmd,
3593                                         GFP_KERNEL);
3594                 if (!p_late_resume_cmd) {
3595                         err = -ENOMEM;
3596                         goto err_free_p_early_suspend_cmd;
3597                 }
3598         }
3599
3600         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3601                                 GFP_KERNEL);
3602         if (!p_suspend_cmd) {
3603                 err = -ENOMEM;
3604                 goto err_free_p_late_resume_cmd;
3605         }
3606
3607         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3608
3609         /* Copy panel init cmd */
3610         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3611                                                 p_init_cmd, p_dsi->n_init_cmd);
3612         if (err < 0)
3613                 goto err_free;
3614         dsi->info.dsi_init_cmd = p_init_cmd;
3615
3616         /* Copy panel early suspend cmd */
3617         if (p_dsi->dsi_early_suspend_cmd) {
3618                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3619                                         p_early_suspend_cmd,
3620                                         p_dsi->n_early_suspend_cmd);
3621                 if (err < 0)
3622                         goto err_free;
3623                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3624         }
3625
3626         /* Copy panel late resume cmd */
3627         if (p_dsi->dsi_late_resume_cmd) {
3628                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3629                                                 p_late_resume_cmd,
3630                                                 p_dsi->n_late_resume_cmd);
3631                 if (err < 0)
3632                         goto err_free;
3633                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3634         }
3635
3636         /* Copy panel suspend cmd */
3637         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3638                                         p_dsi->n_suspend_cmd);
3639         if (err < 0)
3640                 goto err_free;
3641         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3642
3643         if (!dsi->info.panel_reset_timeout_msec)
3644                 dsi->info.panel_reset_timeout_msec =
3645                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3646
3647         if (!dsi->info.panel_buffer_size_byte)
3648                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3649
3650         if (!dsi->info.max_panel_freq_khz) {
3651                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3652
3653                 if (dsi->info.video_burst_mode >
3654                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3655                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3656                                         "is not set for DSI burst mode.\n");
3657                         dsi->info.video_burst_mode =
3658                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3659                 }
3660         }
3661
3662         if (!dsi->info.lp_cmd_mode_freq_khz)
3663                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3664
3665         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3666                 dev_warn(&dsi->dc->ndev->dev,
3667                         "DSI: Failed to get chip info\n");
3668
3669         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3670                 dsi->info.lp_read_cmd_mode_freq_khz =
3671                         dsi->info.lp_cmd_mode_freq_khz;
3672
3673         /* host mode is for testing only */
3674         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3675         return 0;
3676
3677 err_free:
3678         kfree(p_suspend_cmd);
3679 err_free_p_late_resume_cmd:
3680         kfree(p_late_resume_cmd);
3681 err_free_p_early_suspend_cmd:
3682         kfree(p_early_suspend_cmd);
3683 err_free_init_cmd:
3684         kfree(p_init_cmd);
3685         return err;
3686 }
3687
3688 /* returns next null enumeration from  tegra_dsi_instance */
3689 static inline int tegra_dsi_get_enumeration(void)
3690 {
3691         int i = 0;
3692         for (; i < MAX_DSI_INSTANCE; i++) {
3693                 if (!tegra_dsi_instance[i])
3694                         return i;
3695         }
3696         return -EINVAL;
3697 }
3698
3699 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3700 {
3701         struct tegra_dc_dsi_data *dsi;
3702         struct resource *res;
3703         struct resource *base_res;
3704         void __iomem *base;
3705         struct clk *dc_clk = NULL;
3706         struct clk *dsi_clk = NULL;
3707         struct clk *dsi_fixed_clk = NULL;
3708         struct clk *dsi_lp_clk = NULL;
3709         struct tegra_dsi_out *dsi_pdata;
3710         int err = 0;
3711         int dsi_enum = -1;
3712
3713         if (dc->pdata->default_out->dsi->dsi_instance)
3714                 dsi_enum = 1;
3715         else
3716                 dsi_enum = tegra_dsi_get_enumeration();
3717         if (dsi_enum < 0) {
3718                 err = -EINVAL;
3719                 dev_err(&dc->ndev->dev, "dsi: invalid enum retured\n");
3720                 return err;
3721         }
3722
3723         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3724         if (!dsi) {
3725                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3726                 return -ENOMEM;
3727         }
3728         tegra_dsi_instance[dsi_enum] = dsi;
3729
3730         if (dc->out->dsi->ganged_type) {
3731                 if (dsi_enum)
3732                         res = platform_get_resource_byname(dc->ndev,
3733                                                 IORESOURCE_MEM,
3734                                                 "ganged_dsib_regs");
3735                 else
3736                         res = platform_get_resource_byname(dc->ndev,
3737                                                 IORESOURCE_MEM,
3738                                                 "ganged_dsia_regs");
3739         } else {
3740                 res = platform_get_resource_byname(dc->ndev,
3741                                         IORESOURCE_MEM,
3742                                         "dsi_regs");
3743         }
3744
3745         if (!res) {
3746                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3747                 err = -ENOENT;
3748                 goto err_free_dsi;
3749         }
3750
3751         base_res = request_mem_region(res->start, resource_size(res),
3752                                 dc->ndev->name);
3753         if (!base_res) {
3754                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3755                 err = -EBUSY;
3756                 goto err_free_dsi;
3757         }
3758
3759         base = ioremap(res->start, resource_size(res));
3760         if (!base) {
3761                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3762                 err = -EBUSY;
3763                 goto err_release_regs;
3764         }
3765
3766         dsi_pdata = dc->pdata->default_out->dsi;
3767         if (!dsi_pdata) {
3768                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
3769                 goto err_release_regs;
3770         }
3771         if (dsi_enum) {
3772                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3773                 dsi_lp_clk = clk_get(&dc->ndev->dev, "dsiblp");
3774         } else {
3775                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3776                 dsi_lp_clk = clk_get(&dc->ndev->dev, "dsialp");
3777         }
3778
3779         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3780
3781         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3782                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3783                 err = -EBUSY;
3784                 goto err_release_regs;
3785         }
3786
3787         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3788         if (IS_ERR_OR_NULL(dc_clk)) {
3789                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3790                         dev_name(&dc->ndev->dev));
3791                 err = -EBUSY;
3792                 goto err_dsi_clk_put;
3793         }
3794
3795         mutex_init(&dsi->lock);
3796         dsi->controller_index = dsi_enum;
3797         dsi->dc = dc;
3798         dsi->base = base;
3799         dsi->base_res = base_res;
3800         dsi->dc_clk = dc_clk;
3801         dsi->dsi_clk = dsi_clk;
3802         dsi->dsi_fixed_clk = dsi_fixed_clk;
3803         dsi->dsi_lp_clk = dsi_lp_clk;
3804
3805         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3806         if (err < 0)
3807                 goto err_dc_clk_put;
3808
3809         tegra_dc_set_outdata(dc, dsi);
3810         __tegra_dc_dsi_init(dc);
3811
3812         return 0;
3813
3814 err_dc_clk_put:
3815         clk_put(dc_clk);
3816 err_dsi_clk_put:
3817         clk_put(dsi_clk);
3818         clk_put(dsi_fixed_clk);
3819 err_release_regs:
3820         release_resource(base_res);
3821 err_free_dsi:
3822         kfree(dsi);
3823
3824         return err;
3825 }
3826
3827 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
3828 {
3829         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3830         u16 i;
3831         u32 val;
3832
3833         mutex_lock(&dsi->lock);
3834
3835         if (dsi->out_ops && dsi->out_ops->destroy)
3836                 dsi->out_ops->destroy(dsi);
3837
3838         /* free up the pdata */
3839         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3840                 if (dsi->info.dsi_init_cmd[i].pdata)
3841                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3842         }
3843         kfree(dsi->info.dsi_init_cmd);
3844
3845         /* Disable dc stream */
3846         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3847                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3848
3849         /* Disable dsi phy clock */
3850         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3851                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3852
3853         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3854         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3855
3856         iounmap(dsi->base);
3857         release_resource(dsi->base_res);
3858
3859         clk_put(dsi->dc_clk);
3860         clk_put(dsi->dsi_clk);
3861
3862         mutex_unlock(&dsi->lock);
3863
3864         mutex_destroy(&dsi->lock);
3865         kfree(dsi);
3866 }
3867
3868 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3869                                                         u32 settings)
3870 {
3871         struct clk *parent_clk = NULL;
3872         struct clk *base_clk = NULL;
3873
3874         parent_clk = clk_get_parent(dsi->dsi_clk);
3875         base_clk = clk_get_parent(parent_clk);
3876 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3877         if (dsi->info.dsi_instance)
3878                 tegra_clk_cfg_ex(base_clk,
3879                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3880                                 settings);
3881         else
3882                 tegra_clk_cfg_ex(base_clk,
3883                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3884                                 settings);
3885 #else
3886         tegra_clk_cfg_ex(base_clk,
3887                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
3888                         settings);
3889 #endif
3890 }
3891
3892 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
3893                                         struct tegra_dc_dsi_data *dsi,
3894                                         u32 suspend_aggr)
3895 {
3896         u32 val = 0;
3897         int err = 0;
3898
3899         switch (suspend_aggr) {
3900         case DSI_HOST_SUSPEND_LV2:
3901                 if (!dsi->ulpm) {
3902                         err = tegra_dsi_enter_ulpm(dsi);
3903                         if (err < 0) {
3904                                 dev_err(&dc->ndev->dev,
3905                                         "DSI failed to enter ulpm\n");
3906                                 goto fail;
3907                         }
3908                 }
3909
3910                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3911                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3912                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3913                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1);
3914                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3915
3916                 /* Suspend core-logic */
3917                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3918                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3919                 /* fall through */
3920         case DSI_HOST_SUSPEND_LV1:
3921                 /* Disable dsi fast and slow clock */
3922                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3923                 /* fall through */
3924         case DSI_HOST_SUSPEND_LV0:
3925                 /* Disable dsi source clock */
3926                 tegra_dsi_clk_disable(dsi);
3927                 break;
3928         case DSI_NO_SUSPEND:
3929                 break;
3930         default:
3931                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3932                                                 "is not supported.\n");
3933         }
3934
3935         return 0;
3936 fail:
3937         return err;
3938 }
3939
3940 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
3941                                         struct tegra_dc_dsi_data *dsi,
3942                                         u32 suspend_aggr)
3943 {
3944         u32 val;
3945         int err;
3946
3947         switch (dsi->info.suspend_aggr) {
3948         case DSI_HOST_SUSPEND_LV0:
3949                 tegra_dsi_clk_enable(dsi);
3950                 break;
3951         case DSI_HOST_SUSPEND_LV1:
3952                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3953                 tegra_dsi_clk_enable(dsi);
3954                 break;
3955         case DSI_HOST_SUSPEND_LV2:
3956                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3957                 tegra_dsi_clk_enable(dsi);
3958
3959                 tegra_dsi_writel(dsi,
3960                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3961                         DSI_POWER_CONTROL);
3962
3963                 if (dsi->ulpm) {
3964                         err = tegra_dsi_enter_ulpm(dsi);
3965                         if (err < 0) {
3966                                 dev_err(&dc->ndev->dev,
3967                                         "DSI failed to enter ulpm\n");
3968                                 goto fail;
3969                         }
3970
3971                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3972                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3973                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3974                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3975                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3976
3977                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3978                                 dev_err(&dc->ndev->dev,
3979                                         "DSI failed to exit ulpm\n");
3980                                 goto fail;
3981                         }
3982                 }
3983                 break;
3984         case DSI_NO_SUSPEND:
3985                 break;
3986         default:
3987                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3988                                                 "is not supported.\n");
3989         }
3990
3991         return 0;
3992 fail:
3993         return err;
3994 }
3995
3996 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
3997 {
3998         int err = 0;
3999         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4000
4001         if (!dsi->enabled)
4002                 return -EINVAL;
4003
4004         if (dsi->host_suspended)
4005                 return 0;
4006
4007         mutex_lock(&dsi->host_lock);
4008         tegra_dc_io_start(dc);
4009         dsi->host_suspended = true;
4010
4011         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4012
4013         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
4014         if (err < 0)
4015                 dev_err(&dc->ndev->dev,
4016                         "DSI host suspend failed\n");
4017
4018         tegra_dc_io_end(dc);
4019         mutex_unlock(&dsi->host_lock);
4020         return err;
4021 }
4022
4023 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
4024                                 struct tegra_dc_dsi_data *dsi)
4025 {
4026         int val = 0;
4027         int err = 0;
4028
4029         if (!dsi->enabled)
4030                 return 0;
4031
4032         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4033         if (err < 0) {
4034                 dev_err(&dc->ndev->dev,
4035                 "DSI failed to go to LP mode\n");
4036                 goto fail;
4037         }
4038
4039         /* Suspend DSI panel */
4040         err = tegra_dsi_send_panel_cmd(dc, dsi,
4041                         dsi->info.dsi_suspend_cmd,
4042                         dsi->info.n_suspend_cmd);
4043
4044         /*
4045          * Certain panels need dc frames be sent after
4046          * putting panel to sleep.
4047          */
4048         if (dsi->info.panel_send_dc_frames)
4049                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4050
4051         if (err < 0) {
4052                 dev_err(&dc->ndev->dev,
4053                         "dsi: Error sending suspend cmd\n");
4054                 goto fail;
4055         }
4056
4057         if (!dsi->ulpm) {
4058                 err = tegra_dsi_enter_ulpm(dsi);
4059                 if (err < 0) {
4060                         dev_err(&dc->ndev->dev,
4061                                 "DSI failed to enter ulpm\n");
4062                         goto fail;
4063                 }
4064         }
4065
4066         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
4067                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
4068                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
4069         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
4070
4071         /* Suspend core-logic */
4072         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4073         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4074
4075         /* Disable dsi fast and slow clock */
4076         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4077
4078         /* Disable dsi source clock */
4079         tegra_dsi_clk_disable(dsi);
4080
4081         regulator_disable(dsi->avdd_dsi_csi);
4082
4083         dsi->enabled = false;
4084         dsi->host_suspended = true;
4085         atomic_set(&display_ready, 0);
4086
4087         return 0;
4088 fail:
4089         return err;
4090 }
4091
4092 static int tegra_dsi_host_resume(struct tegra_dc *dc)
4093 {
4094         int err = 0;
4095         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4096
4097         if (!dsi->enabled)
4098                 return -EINVAL;
4099
4100         mutex_lock(&dsi->host_lock);
4101         cancel_delayed_work_sync(&dsi->idle_work);
4102         if (!dsi->host_suspended) {
4103                 mutex_unlock(&dsi->host_lock);
4104                 return 0;
4105         }
4106
4107         tegra_dc_io_start(dc);
4108
4109         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
4110         if (err < 0) {
4111                 dev_err(&dc->ndev->dev,
4112                         "DSI host resume failed\n");
4113                 goto fail;
4114         }
4115
4116         tegra_dsi_start_dc_stream(dc, dsi);
4117         dsi->host_suspended = false;
4118 fail:
4119         tegra_dc_io_end(dc);
4120         mutex_unlock(&dsi->host_lock);
4121         return err;
4122 }
4123
4124 static void _tegra_dc_dsi_disable(struct tegra_dc *dc)
4125 {
4126         int err;
4127         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4128
4129         if (dsi->host_suspended)
4130                 tegra_dsi_host_resume(dc);
4131
4132         mutex_lock(&dsi->lock);
4133         tegra_dc_io_start(dc);
4134
4135         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4136                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4137
4138         if (dsi->out_ops && dsi->out_ops->disable)
4139                 dsi->out_ops->disable(dsi);
4140
4141         if (dsi->info.power_saving_suspend) {
4142                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4143                         dev_err(&dc->ndev->dev,
4144                                 "DSI failed to enter deep sleep\n");
4145                         goto fail;
4146                 }
4147         } else {
4148                 if (dsi->info.dsi_early_suspend_cmd) {
4149                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4150                                 dsi->info.dsi_early_suspend_cmd,
4151                                 dsi->info.n_early_suspend_cmd);
4152                         if (err < 0) {
4153                                 dev_err(&dc->ndev->dev,
4154                                 "dsi: Error sending early suspend cmd\n");
4155                                 goto fail;
4156                         }
4157                 }
4158
4159                 if (!dsi->ulpm) {
4160                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4161                                 dev_err(&dc->ndev->dev,
4162                                         "DSI failed to enter ulpm\n");
4163                                 goto fail;
4164                         }
4165                 }
4166         }
4167 fail:
4168         mutex_unlock(&dsi->lock);
4169         tegra_dc_io_end(dc);
4170 }
4171
4172 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
4173 {
4174         _tegra_dc_dsi_disable(dc);
4175
4176         if (dc->out->dsi->ganged_type) {
4177                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4178                 _tegra_dc_dsi_disable(dc);
4179                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4180         }
4181 }
4182
4183
4184 #ifdef CONFIG_PM
4185 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
4186 {
4187         struct tegra_dc_dsi_data *dsi;
4188
4189         dsi = tegra_dc_get_outdata(dc);
4190
4191         if (!dsi->enabled)
4192                 return;
4193
4194         if (dsi->host_suspended)
4195                 tegra_dsi_host_resume(dc);
4196
4197         tegra_dc_io_start(dc);
4198         mutex_lock(&dsi->lock);
4199
4200         if (dsi->out_ops && dsi->out_ops->suspend)
4201                 dsi->out_ops->suspend(dsi);
4202
4203         if (!dsi->info.power_saving_suspend) {
4204                 if (dsi->ulpm) {
4205                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4206                                 dev_err(&dc->ndev->dev,
4207                                         "DSI failed to exit ulpm");
4208                                 goto fail;
4209                         }
4210                 }
4211
4212                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4213                         dev_err(&dc->ndev->dev,
4214                                 "DSI failed to enter deep sleep\n");
4215                         goto fail;
4216                 }
4217         }
4218 fail:
4219         mutex_unlock(&dsi->lock);
4220         tegra_dc_io_end(dc);
4221 }
4222
4223 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
4224 {
4225         struct tegra_dc_dsi_data *dsi;
4226
4227         dsi = tegra_dc_get_outdata(dc);
4228
4229         /* No dsi config required since tegra_dc_dsi_enable
4230          * will reconfigure the controller from scratch
4231          */
4232
4233          if (dsi->out_ops && dsi->out_ops->resume)
4234                 dsi->out_ops->resume(dsi);
4235 }
4236
4237 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
4238 {
4239         _tegra_dc_dsi_suspend(dc);
4240
4241         if (dc->out->dsi->ganged_type) {
4242                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4243                 _tegra_dc_dsi_suspend(dc);
4244                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4245         }
4246 }
4247
4248 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
4249 {
4250         _tegra_dc_dsi_resume(dc);
4251
4252         if (dc->out->dsi->ganged_type) {
4253                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4254                 _tegra_dc_dsi_resume(dc);
4255                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4256         }
4257 }
4258 #endif
4259
4260 static int tegra_dc_dsi_init(struct tegra_dc *dc)
4261 {
4262         struct tegra_dc_dsi_data *dsi;
4263         int err = 0;
4264
4265         err = _tegra_dc_dsi_init(dc);
4266         if (err < 0) {
4267                 dev_err(&dc->ndev->dev,
4268                         "dsi: Instance A init failed\n");
4269                 goto err;
4270         }
4271
4272         dsi = tegra_dc_get_outdata(dc);
4273
4274         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
4275         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
4276                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
4277                 err = PTR_ERR(dsi->avdd_dsi_csi);
4278                 goto err_reg;
4279         }
4280
4281         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
4282         if (IS_ERR(dsi->mipi_cal)) {
4283                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
4284                 err = PTR_ERR(dsi->mipi_cal);
4285                 goto err_mipi;
4286         }
4287
4288         if (dc->out->dsi->ganged_type) {
4289                 err = _tegra_dc_dsi_init(dc);
4290                 if (err < 0) {
4291                         dev_err(&dc->ndev->dev,
4292                                 "dsi: Instance B init failed\n");
4293                         goto err_ganged;
4294                 }
4295                 tegra_dsi_instance[DSI_INSTANCE_1]->avdd_dsi_csi =
4296                                                         dsi->avdd_dsi_csi;
4297                 tegra_dsi_instance[DSI_INSTANCE_1]->mipi_cal =
4298                                                         dsi->mipi_cal;
4299                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4300         }
4301         return 0;
4302 err_ganged:
4303         tegra_mipi_cal_destroy(dc);
4304 err_mipi:
4305         regulator_put(dsi->avdd_dsi_csi);
4306 err_reg:
4307         _tegra_dc_dsi_destroy(dc);
4308 err:
4309         return err;
4310 }
4311
4312 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
4313 {
4314         struct regulator *avdd_dsi_csi;
4315         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4316
4317         avdd_dsi_csi = dsi->avdd_dsi_csi;
4318
4319         _tegra_dc_dsi_destroy(dc);
4320
4321         if (dc->out->dsi->ganged_type) {
4322                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4323                 _tegra_dc_dsi_destroy(dc);
4324                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4325         }
4326
4327         regulator_put(avdd_dsi_csi);
4328         tegra_mipi_cal_destroy(dc);
4329 }
4330
4331 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4332 {
4333         _tegra_dc_dsi_enable(dc);
4334
4335         if (dc->out->dsi->ganged_type) {
4336                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4337                 _tegra_dc_dsi_enable(dc);
4338                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4339         }
4340 }
4341
4342 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
4343 {
4344         unsigned long rate;
4345         struct clk *parent_clk;
4346         struct clk *base_clk;
4347         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4348
4349         /* divide by 1000 to avoid overflow */
4350         dc->mode.pclk /= 1000;
4351         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
4352                                 / dc->shift_clk_div.div;
4353         rate *= 1000;
4354         dc->mode.pclk *= 1000;
4355
4356         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
4357                 goto skip_setup;
4358
4359         if (clk == dc->clk) {
4360                 parent_clk = clk_get_sys(NULL,
4361                                 dc->out->parent_clk ? : "pll_d_out0");
4362                 base_clk = clk_get_parent(parent_clk);
4363         } else {
4364                 if (dc->pdata->default_out->dsi->dsi_instance) {
4365                         parent_clk = clk_get_sys(NULL,
4366                                 dc->out->parent_clk ? : "pll_d2_out0");
4367                         base_clk = clk_get_parent(parent_clk);
4368                 } else {
4369                         parent_clk = clk_get_sys(NULL,
4370                                 dc->out->parent_clk ? : "pll_d_out0");
4371                         base_clk = clk_get_parent(parent_clk);
4372                 }
4373         }
4374         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4375
4376         if (rate != clk_get_rate(base_clk))
4377                 clk_set_rate(base_clk, rate);
4378
4379         if (clk_get_parent(clk) != parent_clk)
4380                 clk_set_parent(clk, parent_clk);
4381
4382 skip_setup:
4383         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
4384 }
4385
4386 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4387         .init = tegra_dc_dsi_init,
4388         .destroy = tegra_dc_dsi_destroy,
4389         .enable = tegra_dc_dsi_enable,
4390         .disable = tegra_dc_dsi_disable,
4391         .hold = tegra_dc_dsi_hold_host,
4392         .release = tegra_dc_dsi_release_host,
4393 #ifdef CONFIG_PM
4394         .suspend = tegra_dc_dsi_suspend,
4395         .resume = tegra_dc_dsi_resume,
4396 #endif
4397         .setup_clk = tegra_dc_dsi_setup_clk,
4398 };