video: tegra: dsi: 720p panel power fix
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/debugfs.h>
28 #include <linux/seq_file.h>
29 #include <linux/nvhost.h>
30
31 #include <mach/clk.h>
32 #include <mach/dc.h>
33 #include <mach/fb.h>
34 #include <mach/csi.h>
35 #include <mach/iomap.h>
36 #include <linux/nvhost.h>
37
38 #include "dc_reg.h"
39 #include "dc_priv.h"
40 #include "dsi_regs.h"
41 #include "dsi.h"
42
43 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
44 #define DSIB_MODE_ENABLE                0x2
45
46 #define DSI_USE_SYNC_POINTS             1
47 #define S_TO_MS(x)                      (1000 * (x))
48
49 #define DSI_MODULE_NOT_INIT             0x0
50 #define DSI_MODULE_INIT                 0x1
51
52 #define DSI_LPHS_NOT_INIT               0x0
53 #define DSI_LPHS_IN_LP_MODE             0x1
54 #define DSI_LPHS_IN_HS_MODE             0x2
55
56 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
57 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
58 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
59
60 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
61 #define DSI_DRIVEN_MODE_DC              0x1
62 #define DSI_DRIVEN_MODE_HOST            0x2
63
64 #define DSI_PHYCLK_OUT_DIS              0x0
65 #define DSI_PHYCLK_OUT_EN               0x1
66
67 #define DSI_PHYCLK_NOT_INIT             0x0
68 #define DSI_PHYCLK_CONTINUOUS           0x1
69 #define DSI_PHYCLK_TX_ONLY              0x2
70
71 #define DSI_CLK_BURST_NOT_INIT          0x0
72 #define DSI_CLK_BURST_NONE_BURST        0x1
73 #define DSI_CLK_BURST_BURST_MODE        0x2
74
75 #define DSI_DC_STREAM_DISABLE           0x0
76 #define DSI_DC_STREAM_ENABLE            0x1
77
78 #define DSI_LP_OP_NOT_INIT              0x0
79 #define DSI_LP_OP_WRITE                 0x1
80 #define DSI_LP_OP_READ                  0x2
81
82 static bool enable_read_debug;
83 module_param(enable_read_debug, bool, 0644);
84 MODULE_PARM_DESC(enable_read_debug,
85                 "Enable to print read fifo and return packet type");
86
87 struct dsi_status {
88         unsigned init:2;
89
90         unsigned lphs:2;
91
92         unsigned vtype:2;
93         unsigned driven:2;
94
95         unsigned clk_out:2;
96         unsigned clk_mode:2;
97         unsigned clk_burst:2;
98
99         unsigned lp_op:2;
100
101         unsigned dc_stream:1;
102 };
103
104 /* source of video data */
105 enum {
106         TEGRA_DSI_DRIVEN_BY_DC,
107         TEGRA_DSI_DRIVEN_BY_HOST,
108 };
109
110 struct tegra_dc_dsi_data {
111         struct tegra_dc *dc;
112         void __iomem *base;
113         struct resource *base_res;
114
115         struct clk *dc_clk;
116         struct clk *dsi_clk;
117         struct clk *dsi_fixed_clk;
118         bool clk_ref;
119
120         struct mutex lock;
121
122         /* data from board info */
123         struct tegra_dsi_out info;
124
125         struct dsi_status status;
126
127         struct dsi_phy_timing_inclk phy_timing;
128
129         bool ulpm;
130         bool enabled;
131         bool host_suspended;
132
133         u8 driven_mode;
134         u8 controller_index;
135
136         u8 pixel_scaler_mul;
137         u8 pixel_scaler_div;
138
139         u32 default_shift_clk_div;
140         u32 default_pixel_clk_khz;
141         u32 default_hs_clk_khz;
142
143         u32 shift_clk_div;
144         u32 target_hs_clk_khz;
145         u32 target_lp_clk_khz;
146
147         u32 syncpt_id;
148         u32 syncpt_val;
149
150         u16 current_bit_clk_ns;
151         u32 current_dsi_clk_khz;
152
153         u32 dsi_control_val;
154 };
155
156 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
157         DSI_PKT_SEQ_0_LO,
158         DSI_PKT_SEQ_0_HI,
159         DSI_PKT_SEQ_1_LO,
160         DSI_PKT_SEQ_1_HI,
161         DSI_PKT_SEQ_2_LO,
162         DSI_PKT_SEQ_2_HI,
163         DSI_PKT_SEQ_3_LO,
164         DSI_PKT_SEQ_3_HI,
165         DSI_PKT_SEQ_4_LO,
166         DSI_PKT_SEQ_4_HI,
167         DSI_PKT_SEQ_5_LO,
168         DSI_PKT_SEQ_5_HI,
169 };
170
171 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
172         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
173         0,
174         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
175         0,
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
177         0,
178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
179         PKT_ID2(CMD_HE) | PKT_LEN2(0),
180         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
181         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
183         0,
184         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
185         PKT_ID2(CMD_HE) | PKT_LEN2(0),
186         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
187         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
188 };
189
190 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
191         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
194         0,
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
196         0,
197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
198         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
199         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
200         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
201         0,
202         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
203         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
204         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
205 };
206
207 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
208         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
209         0,
210         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
211         0,
212         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
213         0,
214         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
215         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
216         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
217         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
218         0,
219         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
220         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
221         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
222 };
223
224 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
225         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
226         0,
227         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
228         0,
229         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
230         0,
231         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
232         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
233         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
234         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
235         0,
236         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
237         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
238         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
239 };
240
241 /* TODO: verify with hw about this format */
242 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
243         0,
244         0,
245         0,
246         0,
247         0,
248         0,
249         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
250         0,
251         0,
252         0,
253         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
254         0,
255 };
256
257 const u32 init_reg[] = {
258         DSI_INT_ENABLE,
259         DSI_INT_STATUS,
260         DSI_INT_MASK,
261         DSI_INIT_SEQ_DATA_0,
262         DSI_INIT_SEQ_DATA_1,
263         DSI_INIT_SEQ_DATA_2,
264         DSI_INIT_SEQ_DATA_3,
265         DSI_INIT_SEQ_DATA_4,
266         DSI_INIT_SEQ_DATA_5,
267         DSI_INIT_SEQ_DATA_6,
268         DSI_INIT_SEQ_DATA_7,
269         DSI_DCS_CMDS,
270         DSI_PKT_SEQ_0_LO,
271         DSI_PKT_SEQ_1_LO,
272         DSI_PKT_SEQ_2_LO,
273         DSI_PKT_SEQ_3_LO,
274         DSI_PKT_SEQ_4_LO,
275         DSI_PKT_SEQ_5_LO,
276         DSI_PKT_SEQ_0_HI,
277         DSI_PKT_SEQ_1_HI,
278         DSI_PKT_SEQ_2_HI,
279         DSI_PKT_SEQ_3_HI,
280         DSI_PKT_SEQ_4_HI,
281         DSI_PKT_SEQ_5_HI,
282         DSI_CONTROL,
283         DSI_HOST_DSI_CONTROL,
284         DSI_PAD_CONTROL,
285         DSI_PAD_CONTROL_CD,
286         DSI_SOL_DELAY,
287         DSI_MAX_THRESHOLD,
288         DSI_TRIGGER,
289         DSI_TX_CRC,
290         DSI_INIT_SEQ_CONTROL,
291         DSI_PKT_LEN_0_1,
292         DSI_PKT_LEN_2_3,
293         DSI_PKT_LEN_4_5,
294         DSI_PKT_LEN_6_7,
295 };
296
297 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
298 {
299         unsigned long ret;
300
301         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
302         ret = readl(dsi->base + reg * 4);
303         trace_printk("readl %p=%#08lx\n", dsi->base + reg * 4, ret);
304         return ret;
305 }
306 EXPORT_SYMBOL(tegra_dsi_readl);
307
308 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
309 {
310         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
311         trace_printk("writel %p=%#08x\n", dsi->base + reg * 4, val);
312         writel(val, dsi->base + reg * 4);
313 }
314 EXPORT_SYMBOL(tegra_dsi_writel);
315
316 #ifdef CONFIG_DEBUG_FS
317 static int dbg_dsi_show(struct seq_file *s, void *unused)
318 {
319         struct tegra_dc_dsi_data *dsi = s->private;
320
321 #define DUMP_REG(a) do {                                                \
322                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
323                        #a, a, tegra_dsi_readl(dsi, a));         \
324         } while (0)
325
326         tegra_dc_io_start(dsi->dc);
327         clk_enable(dsi->dsi_clk);
328
329         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
330         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
331         DUMP_REG(DSI_CTXSW);
332         DUMP_REG(DSI_POWER_CONTROL);
333         DUMP_REG(DSI_INT_ENABLE);
334         DUMP_REG(DSI_CONTROL);
335         DUMP_REG(DSI_SOL_DELAY);
336         DUMP_REG(DSI_MAX_THRESHOLD);
337         DUMP_REG(DSI_TRIGGER);
338         DUMP_REG(DSI_TX_CRC);
339         DUMP_REG(DSI_STATUS);
340         DUMP_REG(DSI_INIT_SEQ_CONTROL);
341         DUMP_REG(DSI_INIT_SEQ_DATA_0);
342         DUMP_REG(DSI_INIT_SEQ_DATA_1);
343         DUMP_REG(DSI_INIT_SEQ_DATA_2);
344         DUMP_REG(DSI_INIT_SEQ_DATA_3);
345         DUMP_REG(DSI_INIT_SEQ_DATA_4);
346         DUMP_REG(DSI_INIT_SEQ_DATA_5);
347         DUMP_REG(DSI_INIT_SEQ_DATA_6);
348         DUMP_REG(DSI_INIT_SEQ_DATA_7);
349         DUMP_REG(DSI_PKT_SEQ_0_LO);
350         DUMP_REG(DSI_PKT_SEQ_0_HI);
351         DUMP_REG(DSI_PKT_SEQ_1_LO);
352         DUMP_REG(DSI_PKT_SEQ_1_HI);
353         DUMP_REG(DSI_PKT_SEQ_2_LO);
354         DUMP_REG(DSI_PKT_SEQ_2_HI);
355         DUMP_REG(DSI_PKT_SEQ_3_LO);
356         DUMP_REG(DSI_PKT_SEQ_3_HI);
357         DUMP_REG(DSI_PKT_SEQ_4_LO);
358         DUMP_REG(DSI_PKT_SEQ_4_HI);
359         DUMP_REG(DSI_PKT_SEQ_5_LO);
360         DUMP_REG(DSI_PKT_SEQ_5_HI);
361         DUMP_REG(DSI_DCS_CMDS);
362         DUMP_REG(DSI_PKT_LEN_0_1);
363         DUMP_REG(DSI_PKT_LEN_2_3);
364         DUMP_REG(DSI_PKT_LEN_4_5);
365         DUMP_REG(DSI_PKT_LEN_6_7);
366         DUMP_REG(DSI_PHY_TIMING_0);
367         DUMP_REG(DSI_PHY_TIMING_1);
368         DUMP_REG(DSI_PHY_TIMING_2);
369         DUMP_REG(DSI_BTA_TIMING);
370         DUMP_REG(DSI_TIMEOUT_0);
371         DUMP_REG(DSI_TIMEOUT_1);
372         DUMP_REG(DSI_TO_TALLY);
373         DUMP_REG(DSI_PAD_CONTROL);
374         DUMP_REG(DSI_PAD_CONTROL_CD);
375         DUMP_REG(DSI_PAD_CD_STATUS);
376         DUMP_REG(DSI_VID_MODE_CONTROL);
377 #undef DUMP_REG
378
379         clk_disable(dsi->dsi_clk);
380         tegra_dc_io_end(dsi->dc);
381
382         return 0;
383 }
384
385 static int dbg_dsi_open(struct inode *inode, struct file *file)
386 {
387         return single_open(file, dbg_dsi_show, inode->i_private);
388 }
389
390 static const struct file_operations dbg_fops = {
391         .open           = dbg_dsi_open,
392         .read           = seq_read,
393         .llseek         = seq_lseek,
394         .release        = single_release,
395 };
396
397 static struct dentry *dsidir;
398
399 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
400 {
401         struct dentry *retval;
402
403         dsidir = debugfs_create_dir("tegra_dsi", NULL);
404         if (!dsidir)
405                 return;
406         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
407                 &dbg_fops);
408         if (!retval)
409                 goto free_out;
410         return;
411 free_out:
412         debugfs_remove_recursive(dsidir);
413         dsidir = NULL;
414         return;
415 }
416 #else
417 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
418 { }
419 #endif
420
421 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
422 {
423         if (!tegra_is_clk_enabled(dsi->dsi_clk)) {
424                 clk_enable(dsi->dsi_clk);
425                 clk_enable(dsi->dsi_fixed_clk);
426         }
427 }
428
429 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
430 {
431         if (tegra_is_clk_enabled(dsi->dsi_clk)) {
432                 clk_disable(dsi->dsi_clk);
433                 clk_disable(dsi->dsi_fixed_clk);
434         }
435 }
436
437 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
438 {
439         u32 val;
440         int ret;
441
442         ret = 0;
443
444         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
445
446         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
447                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
448         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
449
450         /* TODO: Use interrupt rather than polling */
451         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
452                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
453         if (ret < 0) {
454                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
455                 goto fail;
456         }
457
458         (dsi->syncpt_val)++;
459         return 0;
460 fail:
461         return ret;
462 }
463
464 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
465 {
466         u32 dsi_clock_rate_khz;
467
468         switch (dsi->info.video_burst_mode) {
469         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
470         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
471         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
472         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
473                 /* Calculate DSI HS clock rate for DSI burst mode */
474                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
475                                                         dsi->shift_clk_div;
476                 break;
477         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
478         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
479         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
480         default:
481                 /* Clock rate is default DSI clock rate for non-burst mode */
482                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
483                 break;
484         }
485
486         return dsi_clock_rate_khz;
487 }
488
489 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
490 {
491         u32 dsi_clock_rate_khz;
492
493         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
494                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
495                         dsi_clock_rate_khz =
496                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
497                 else
498                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
499         else
500                 if (lp_op == DSI_LP_OP_READ)
501                         dsi_clock_rate_khz =
502                                 dsi->info.lp_read_cmd_mode_freq_khz;
503                 else
504                         dsi_clock_rate_khz =
505                                 dsi->info.lp_cmd_mode_freq_khz;
506
507         return dsi_clock_rate_khz;
508 }
509
510 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
511 {
512         u32 shift_clk_div;
513         u32 max_shift_clk_div;
514         u32 burst_width;
515         u32 burst_width_max;
516
517         /* Get the real value of default shift_clk_div. default_shift_clk_div
518          * holds the real value of shift_clk_div.
519          */
520         shift_clk_div = dsi->default_shift_clk_div;
521
522         /* Calculate shift_clk_div which can matche the video_burst_mode. */
523         if (dsi->info.video_burst_mode >=
524                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
525                 /* The max_shift_clk_div is multiplied by 10 to save the
526                  * fraction
527                  */
528                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
529                         max_shift_clk_div = dsi->info.max_panel_freq_khz
530                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
531                 else
532                         max_shift_clk_div = shift_clk_div * 10;
533
534                 burst_width = dsi->info.video_burst_mode
535                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
536                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
537                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
538
539                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
540                         burst_width / (burst_width_max * 10) + shift_clk_div;
541         }
542
543         return shift_clk_div;
544 }
545
546 static void tegra_dsi_init_sw(struct tegra_dc *dc,
547                         struct tegra_dc_dsi_data *dsi)
548 {
549         u32 h_width_pixels;
550         u32 v_width_lines;
551         u32 pixel_clk_hz;
552         u32 byte_clk_hz;
553         u32 plld_clk_mhz;
554
555         switch (dsi->info.pixel_format) {
556         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
557                 /* 2 bytes per pixel */
558                 dsi->pixel_scaler_mul = 2;
559                 dsi->pixel_scaler_div = 1;
560                 break;
561         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
562                 /* 2.25 bytes per pixel */
563                 dsi->pixel_scaler_mul = 9;
564                 dsi->pixel_scaler_div = 4;
565                 break;
566         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
567         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
568                 /* 3 bytes per pixel */
569                 dsi->pixel_scaler_mul = 3;
570                 dsi->pixel_scaler_div = 1;
571                 break;
572         default:
573                 break;
574         }
575
576         dsi->controller_index = dc->ndev->id;
577         dsi->ulpm = false;
578         dsi->enabled = false;
579         dsi->clk_ref = false;
580
581         dsi->dsi_control_val =
582                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
583                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
584                         DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
585                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
586
587         /* Below we are going to calculate dsi and dc clock rate.
588          * Calcuate the horizontal and vertical width.
589          */
590         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
591                         dc->mode.h_sync_width + dc->mode.h_active;
592         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
593                         dc->mode.v_sync_width + dc->mode.v_active;
594
595         /* Calculate minimum required pixel rate. */
596         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
597         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
598                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
599                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
600                                 "should be larger than rated refresh rate.\n");
601                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
602                                                 dsi->info.rated_refresh_rate;
603         }
604
605         /* Calculate minimum byte rate on DSI interface. */
606         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
607                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
608
609         /* Round up to multiple of mega hz. */
610         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
611                                                                 1000000);
612
613         /* Calculate default real shift_clk_div. */
614         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
615                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
616                 dsi->info.n_data_lanes);
617         /* Calculate default DSI hs clock. DSI interface is double data rate.
618          * Data is transferred on both rising and falling edge of clk, div by 2
619          * to get the actual clock rate.
620          */
621         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
622         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
623                                                 / dsi->default_shift_clk_div;
624
625         /* Get the actual shift_clk_div and clock rates. */
626         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
627         dsi->target_lp_clk_khz =
628                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
629         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
630
631         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
632                                                         dsi->target_hs_clk_khz);
633
634         dsi->controller_index = dc->ndev->id;
635
636 #if DSI_USE_SYNC_POINTS
637         dsi->syncpt_id = NVSYNCPT_DSI;
638 #endif
639
640         /*
641          * Force video clock to be continuous mode if
642          * enable_hs_clock_on_lp_cmd_mode is set
643          */
644         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
645                 if (dsi->info.video_clock_mode !=
646                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
647                         dev_warn(&dc->ndev->dev,
648                                 "Force clock continuous mode\n");
649
650                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
651         }
652
653 }
654
655 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
656 (platform_t_phy_ns) ? ( \
657 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
658 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
659 ((default_phy) < 0 ? 0 : (default_phy)))
660
661 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
662                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
663 {
664         phy_timing_clk->t_tlpx = SELECT_T_PHY(
665                 dsi->info.phy_timing.t_tlpx_ns,
666                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
667
668         phy_timing_clk->t_clktrail = SELECT_T_PHY(
669                 dsi->info.phy_timing.t_clktrail_ns,
670                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
671
672         phy_timing_clk->t_clkpost = SELECT_T_PHY(
673                 dsi->info.phy_timing.t_clkpost_ns,
674                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
675
676         phy_timing_clk->t_clkzero = SELECT_T_PHY(
677                 dsi->info.phy_timing.t_clkzero_ns,
678                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
679
680         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
681                 dsi->info.phy_timing.t_clkprepare_ns,
682                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
683
684         phy_timing_clk->t_clkpre = SELECT_T_PHY(
685                 dsi->info.phy_timing.t_clkpre_ns,
686                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
687 }
688
689 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
690                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
691 {
692         phy_timing_clk->t_tlpx = SELECT_T_PHY(
693                 dsi->info.phy_timing.t_tlpx_ns,
694                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
695
696         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
697                 dsi->info.phy_timing.t_hsdexit_ns,
698                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
699
700         phy_timing_clk->t_hstrail = SELECT_T_PHY(
701                 dsi->info.phy_timing.t_hstrail_ns,
702                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
703
704         phy_timing_clk->t_datzero = SELECT_T_PHY(
705                 dsi->info.phy_timing.t_datzero_ns,
706                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
707
708         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
709                 dsi->info.phy_timing.t_hsprepare_ns,
710                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
711 }
712
713 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
714                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
715 {
716         phy_timing_clk->t_tlpx = SELECT_T_PHY(
717                 dsi->info.phy_timing.t_tlpx_ns,
718                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
719 }
720
721 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
722                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
723 {
724         phy_timing_clk->t_tlpx = SELECT_T_PHY(
725                 dsi->info.phy_timing.t_tlpx_ns,
726                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
727
728         phy_timing_clk->t_taget = SELECT_T_PHY(
729                 dsi->info.phy_timing.t_taget_ns,
730                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
731
732         phy_timing_clk->t_tasure = SELECT_T_PHY(
733                 dsi->info.phy_timing.t_tasure_ns,
734                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
735
736         phy_timing_clk->t_tago = SELECT_T_PHY(
737                 dsi->info.phy_timing.t_tago_ns,
738                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
739 }
740
741 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
742                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
743 {
744         phy_timing_clk->t_tlpx = SELECT_T_PHY(
745                 dsi->info.phy_timing.t_tlpx_ns,
746                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
747
748         phy_timing_clk->t_wakeup = SELECT_T_PHY(
749                 dsi->info.phy_timing.t_wakeup_ns,
750                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
751 }
752
753 #undef SELECT_T_PHY
754
755 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
756                                 struct dsi_phy_timing_inclk *phy_timing_clk,
757                                 u32 clk_ns, u8 lphs)
758 {
759         if (lphs == DSI_LPHS_IN_HS_MODE) {
760                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
761                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
762         } else {
763                 /* default is LP mode */
764                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
765                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
766                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
767                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
768                         tegra_dsi_get_clk_phy_timing
769                                 (dsi, phy_timing_clk, clk_ns);
770         }
771 }
772
773 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
774                                 struct dsi_phy_timing_inclk *phy_timing,
775                                 u32 clk_ns, u8 lphs)
776 {
777 #define CHECK_RANGE(val, min, max) ( \
778                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
779                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
780
781         int err = 0;
782
783         err = CHECK_RANGE(
784         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
785                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
786                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
787         if (err < 0) {
788                 dev_warn(&dsi->dc->ndev->dev,
789                         "dsi: Tlpx mipi range violated\n");
790                 goto fail;
791         }
792
793         if (lphs == DSI_LPHS_IN_HS_MODE) {
794                 err = CHECK_RANGE(
795                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
796                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
797                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
798                 if (err < 0) {
799                         dev_warn(&dsi->dc->ndev->dev,
800                                 "dsi: HsExit mipi range violated\n");
801                         goto fail;
802                 }
803
804                 err = CHECK_RANGE(
805                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
806                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
807                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
808                 if (err < 0) {
809                         dev_warn(&dsi->dc->ndev->dev,
810                                 "dsi: HsTrail mipi range violated\n");
811                         goto fail;
812                 }
813
814                 err = CHECK_RANGE(
815                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
816                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
817                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
818                 if (err < 0) {
819                         dev_warn(&dsi->dc->ndev->dev,
820                                 "dsi: HsZero mipi range violated\n");
821                         goto fail;
822                 }
823
824                 err = CHECK_RANGE(
825                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
826                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
827                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
828                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
829                 if (err < 0) {
830                         dev_warn(&dsi->dc->ndev->dev,
831                                 "dsi: HsPrepare mipi range violated\n");
832                         goto fail;
833                 }
834
835                 err = CHECK_RANGE(
836                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
837                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
838                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
839                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
840                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
841                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
842                 if (err < 0) {
843                         dev_warn(&dsi->dc->ndev->dev,
844                         "dsi: HsPrepare + HsZero mipi range violated\n");
845                         goto fail;
846                 }
847         } else {
848                 /* default is LP mode */
849                 err = CHECK_RANGE(
850                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
851                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
852                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
853                 if (err < 0) {
854                         dev_warn(&dsi->dc->ndev->dev,
855                                 "dsi: WakeUp mipi range violated\n");
856                         goto fail;
857                 }
858
859                 err = CHECK_RANGE(
860                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
861                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
862                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
863                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
864                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
865                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
866                 if (err < 0) {
867                         dev_warn(&dsi->dc->ndev->dev,
868                                 "dsi: TaSure mipi range violated\n");
869                         goto fail;
870                 }
871         }
872
873         if (lphs == DSI_LPHS_IN_HS_MODE ||
874                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
875                 err = CHECK_RANGE(
876                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
877                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
878                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
879                 if (err < 0) {
880                         dev_warn(&dsi->dc->ndev->dev,
881                                 "dsi: ClkTrail mipi range violated\n");
882                         goto fail;
883                 }
884
885                 err = CHECK_RANGE(
886                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
887                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
888                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
889                 if (err < 0) {
890                         dev_warn(&dsi->dc->ndev->dev,
891                                 "dsi: ClkPost mipi range violated\n");
892                         goto fail;
893                 }
894
895                 err = CHECK_RANGE(
896                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
897                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
898                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
899                 if (err < 0) {
900                         dev_warn(&dsi->dc->ndev->dev,
901                                 "dsi: ClkZero mipi range violated\n");
902                         goto fail;
903                 }
904
905                 err = CHECK_RANGE(
906                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
907                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
908                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
909                 if (err < 0) {
910                         dev_warn(&dsi->dc->ndev->dev,
911                                 "dsi: ClkPrepare mipi range violated\n");
912                         goto fail;
913                 }
914
915                 err = CHECK_RANGE(
916                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
917                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
918                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
919                 if (err < 0) {
920                         dev_warn(&dsi->dc->ndev->dev,
921                                 "dsi: ClkPre mipi range violated\n");
922                         goto fail;
923                 }
924
925                 err = CHECK_RANGE(
926                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
927                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
928                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
929                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
930                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
931                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
932                 if (err < 0) {
933                         dev_warn(&dsi->dc->ndev->dev,
934                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
935                         goto fail;
936                 }
937         }
938 fail:
939 #undef CHECK_RANGE
940         return err;
941 }
942
943 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
944                                 struct dsi_phy_timing_inclk *phy_timing,
945                                 u32 clk_ns, u8 lphs)
946 {
947         u32 hs_t_phy_ns;
948         u32 clk_t_phy_ns;
949         u32 t_phy_ns;
950         u32 h_blank_ns;
951         struct tegra_dc_mode *modes;
952         u32 t_pix_ns;
953         int err = 0;
954
955         if (!(lphs == DSI_LPHS_IN_HS_MODE))
956                 goto fail;
957
958         modes = dsi->dc->out->modes;
959         t_pix_ns = clk_ns * BITS_PER_BYTE *
960                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
961
962         hs_t_phy_ns =
963                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
964                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
965                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
966                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
967                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
968                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
969                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
970                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
971                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
972                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
973
974         clk_t_phy_ns =
975                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
976                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
977                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
978                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
979                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
980                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
981                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
982                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
983                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
984                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
985                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
986                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
987                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
988                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
989
990         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
991                                                 modes->h_front_porch);
992
993         /* Extra tlpx and byte cycle required by dsi HW */
994         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
995                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
996                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
997                 clk_ns * BITS_PER_BYTE);
998
999         if (h_blank_ns < t_phy_ns) {
1000                 err = -EINVAL;
1001                 dev_err(&dsi->dc->ndev->dev,
1002                         "dsi: Hblank is smaller than HS trans phy timing\n");
1003                 goto fail;
1004         }
1005
1006         return 0;
1007 fail:
1008         return err;
1009 }
1010
1011 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1012                                 struct dsi_phy_timing_inclk *phy_timing,
1013                                 u32 clk_ns, u8 lphs)
1014 {
1015         int err = 0;
1016
1017         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1018         if (err < 0) {
1019                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1020                 goto fail;
1021         }
1022
1023         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1024         if (err < 0) {
1025                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1026                 goto fail;
1027         }
1028
1029         /* TODO: add more contraints */
1030 fail:
1031         return err;
1032 }
1033
1034 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1035 {
1036         u32 val;
1037         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1038
1039         tegra_dsi_get_phy_timing
1040                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1041
1042         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1043                                         dsi->current_bit_clk_ns, lphs);
1044
1045         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1046                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1047                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1048                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1049         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1050
1051         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1052                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1053                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1054                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1055         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1056
1057         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1058                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1059                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1060         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1061
1062         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1063                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1064                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1065         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1066
1067         dsi->phy_timing = phy_timing;
1068 }
1069
1070 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1071                                 struct tegra_dc_dsi_data *dsi)
1072 {
1073         u32 dsi_to_pixel_clk_ratio;
1074         u32 temp;
1075         u32 temp1;
1076         u32 mipi_clk_adj_kHz;
1077         u32 sol_delay;
1078         struct tegra_dc_mode *dc_modes = &dc->mode;
1079
1080         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1081         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1082                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1083
1084         /* Convert Fdsi to byte format */
1085         dsi_to_pixel_clk_ratio *= 1000/8;
1086
1087         /* Multiplying by 1000 so that we don't loose the fraction part */
1088         temp = dc_modes->h_active * 1000;
1089         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1090                         dc_modes->h_sync_width;
1091
1092         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1093                         temp * dsi->pixel_scaler_mul /
1094                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1095
1096         /* Do rounding on sol delay */
1097         sol_delay = (sol_delay + 1000 - 1)/1000;
1098
1099         /* TODO:
1100          * 1. find out the correct sol fifo depth to use
1101          * 2. verify with hw about the clamping function
1102          */
1103         if (sol_delay > (480 * 4)) {
1104                 sol_delay = (480 * 4);
1105                 mipi_clk_adj_kHz = sol_delay +
1106                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1107                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1108
1109                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1110
1111                 mipi_clk_adj_kHz *= 4;
1112         }
1113
1114         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1115
1116         return sol_delay;
1117 }
1118
1119 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1120                                 struct tegra_dc_dsi_data *dsi)
1121 {
1122         u32 sol_delay;
1123
1124         if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1125                 dsi->info.video_burst_mode ==
1126                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1127 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1128                 sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1129                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1130 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1131                 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1132         } else {
1133                 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1134                 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1135         }
1136
1137         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1138                                                                 DSI_SOL_DELAY);
1139 }
1140
1141 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1142 {
1143         u32 val;
1144         u32 bytes_per_frame;
1145         u32 timeout = 0;
1146
1147         /* TODO: verify the following equation */
1148         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1149                                                 (dsi->info.refresh_rate * 8);
1150         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1151         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1152
1153         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1154                         DSI_TIMEOUT_0_HTX_TO(timeout);
1155         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1156
1157         if (dsi->info.panel_reset_timeout_msec)
1158                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1159                                         / dsi->current_bit_clk_ns;
1160         else
1161                 timeout = DSI_PR_TO_VALUE;
1162
1163         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1164                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1165         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1166
1167         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1168                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1169                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1170                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1171         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1172 }
1173
1174 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1175                                                 struct tegra_dc_dsi_data *dsi)
1176 {
1177         u32 val;
1178         u32 hact_pkt_len;
1179         u32 hsa_pkt_len;
1180         u32 hbp_pkt_len;
1181         u32 hfp_pkt_len;
1182
1183         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1184                                                         dsi->pixel_scaler_div;
1185         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1186                                                         dsi->pixel_scaler_div;
1187         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1188                                                         dsi->pixel_scaler_div;
1189         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1190                                                         dsi->pixel_scaler_div;
1191
1192         if (dsi->info.video_burst_mode !=
1193                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1194                 hbp_pkt_len += hsa_pkt_len;
1195
1196         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1197         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1198         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1199
1200         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1201                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1202         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1203
1204         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1205                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1206         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1207
1208         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1209                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1210         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1211
1212         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
1213         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1214 }
1215
1216 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1217                                                 struct tegra_dc_dsi_data *dsi)
1218 {
1219         unsigned long   val;
1220         unsigned long   act_bytes;
1221
1222         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1223                         dsi->pixel_scaler_div + 1;
1224
1225         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1226         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1227
1228         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1229         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1230
1231         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1232         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1233
1234         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1235         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1236 }
1237
1238 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1239                                 struct tegra_dc_dsi_data *dsi)
1240 {
1241         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1242                 return;
1243
1244         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1245                 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1246         else
1247                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1248 }
1249
1250 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1251                                 struct tegra_dc_dsi_data *dsi)
1252 {
1253         const u32 *pkt_seq;
1254         u32 rgb_info;
1255         u32 pkt_seq_3_5_rgb_lo;
1256         u32 pkt_seq_3_5_rgb_hi;
1257         u32     val;
1258         u32 reg;
1259         u8  i;
1260
1261         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1262                 return;
1263
1264         switch (dsi->info.pixel_format) {
1265         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1266                 rgb_info = CMD_RGB_16BPP;
1267                 break;
1268         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1269                 rgb_info = CMD_RGB_18BPP;
1270                 break;
1271         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1272                 rgb_info = CMD_RGB_18BPPNP;
1273                 break;
1274         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1275         default:
1276                 rgb_info = CMD_RGB_24BPP;
1277                 break;
1278         }
1279
1280         pkt_seq_3_5_rgb_lo = 0;
1281         pkt_seq_3_5_rgb_hi = 0;
1282         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1283                 pkt_seq = dsi_pkt_seq_cmd_mode;
1284         else {
1285                 switch (dsi->info.video_burst_mode) {
1286                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1287                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1288                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1289                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1290                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1291                         pkt_seq_3_5_rgb_lo =
1292                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1293                         if (!dsi->info.no_pkt_seq_eot)
1294                                 pkt_seq = dsi_pkt_seq_video_burst;
1295                         else
1296                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1297                         break;
1298                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1299                         pkt_seq_3_5_rgb_hi =
1300                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1301                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1302                         break;
1303                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1304                 default:
1305                         pkt_seq_3_5_rgb_lo =
1306                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1307                         pkt_seq = dsi_pkt_seq_video_non_burst;
1308                         break;
1309                 }
1310         }
1311
1312         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1313                 val = pkt_seq[i];
1314                 reg = dsi_pkt_seq_reg[i];
1315                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1316                         val |= pkt_seq_3_5_rgb_lo;
1317                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1318                         val |= pkt_seq_3_5_rgb_hi;
1319                 tegra_dsi_writel(dsi, val, reg);
1320         }
1321 }
1322
1323 static void tegra_dsi_reset_underflow_overflow
1324                                 (struct tegra_dc_dsi_data *dsi)
1325 {
1326         u32 val;
1327
1328         val = tegra_dsi_readl(dsi, DSI_STATUS);
1329         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1330         if (val) {
1331                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1332                         dev_warn(&dsi->dc->ndev->dev,
1333                                 "dsi: video fifo overflow. Resetting flag\n");
1334                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1335                         dev_warn(&dsi->dc->ndev->dev,
1336                                 "dsi: video fifo underflow. Resetting flag\n");
1337                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1338                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1339                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1340                 udelay(5);
1341         }
1342 }
1343
1344 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1345                                         struct tegra_dc_dsi_data *dsi)
1346 {
1347         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1348         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1349         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1350         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1351
1352         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1353 }
1354
1355 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1356                                                 struct tegra_dc_dsi_data *dsi)
1357 {
1358         int val;
1359         long timeout;
1360         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1361
1362         /* stop dc */
1363         tegra_dsi_stop_dc_stream(dc, dsi);
1364
1365         /* enable frame end interrupt */
1366         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1367         val |= FRAME_END_INT;
1368         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1369
1370         /* wait for frame_end completion.
1371          * timeout is 2 frame duration to accomodate for
1372          * internal delay.
1373          */
1374         timeout = wait_for_completion_interruptible_timeout(
1375                         &dc->frame_end_complete,
1376                         msecs_to_jiffies(2 * frame_period));
1377
1378         /* disable frame end interrupt */
1379         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1380         val &= ~FRAME_END_INT;
1381         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1382
1383         if (timeout == 0)
1384                 dev_warn(&dc->ndev->dev,
1385                         "DC doesn't stop at end of frame.\n");
1386
1387         tegra_dsi_reset_underflow_overflow(dsi);
1388 }
1389
1390 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1391                                         struct tegra_dc_dsi_data *dsi)
1392 {
1393         u32 val;
1394
1395         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1396
1397         /* TODO: clean up */
1398         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1399                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1400                         DC_CMD_DISPLAY_POWER_CONTROL);
1401
1402         /* Configure one-shot mode or continuous mode */
1403         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1404                 /* disable LSPI/LCD_DE output */
1405                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1406                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1407
1408                 /* enable MSF & set MSF polarity */
1409                 val = MSF_ENABLE | MSF_LSPI;
1410                 if (!dsi->info.te_polarity_low)
1411                         val |= MSF_POLARITY_HIGH;
1412                 else
1413                         val |= MSF_POLARITY_LOW;
1414                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1415
1416                 /* set non-continuous mode */
1417                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1418                                                 DC_CMD_DISPLAY_COMMAND);
1419                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1420                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1421                                                 DC_CMD_STATE_CONTROL);
1422         } else {
1423                 /* set continuous mode */
1424                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1425                                                 DC_CMD_DISPLAY_COMMAND);
1426                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1427                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1428         }
1429
1430         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1431 }
1432
1433 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1434                                 struct tegra_dc_dsi_data *dsi)
1435 {
1436         u32 shift_clk_div_register;
1437         u32 val;
1438
1439         /* Get the corresponding register value of shift_clk_div. */
1440         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1441
1442 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1443         shift_clk_div_register = 1;
1444 #endif
1445
1446         /* TODO: find out if PCD3 option is required */
1447         val = PIXEL_CLK_DIVIDER_PCD1 |
1448                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1449         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1450 }
1451
1452 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1453                         struct tegra_dc_dsi_data *dsi, u32 clk)
1454 {
1455         u32 rm;
1456
1457         /* Round up to MHz */
1458         rm = clk % 1000;
1459         if (rm != 0)
1460                 clk -= rm;
1461
1462         /* Set up pixel clock */
1463         dc->shift_clk_div = dsi->shift_clk_div;
1464         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1465         /* TODO: Define one shot work delay in board file. */
1466         /* Since for one-shot mode, refresh rate is usually set larger than
1467          * expected refresh rate, it needs at least 3 frame period. Less
1468          * delay one shot work is, more powering saving we have. */
1469         dc->one_shot_delay_ms = 4 *
1470                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1471
1472         /* Enable DSI clock */
1473         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1474         tegra_dsi_clk_enable(dsi);
1475         tegra_periph_reset_deassert(dsi->dsi_clk);
1476
1477         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1478         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1479 }
1480
1481 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1482 {
1483         u32 val;
1484
1485         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1486         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1487
1488         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1489                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1490                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1491         } else {
1492                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1493                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1494         }
1495         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1496
1497         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1498         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1499         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1500         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1501
1502         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1503 }
1504
1505 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1506 {
1507         u32 val;
1508         tegra_dsi_hs_clk_out_enable(dsi);
1509
1510         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1511         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1512         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1513         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1514 }
1515
1516 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1517                                                 struct tegra_dc_dsi_data *dsi)
1518 {
1519         u32 val;
1520
1521         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1522                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1523
1524         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1525         /* stabilization delay */
1526         udelay(300);
1527
1528         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1529         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1530         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1531         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1532
1533         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1534         /* stabilization delay */
1535         udelay(300);
1536
1537         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1538         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1539 }
1540
1541 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1542 {
1543         u32 dsi_control;
1544         u32 host_dsi_control;
1545         u32 max_threshold;
1546
1547         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1548         host_dsi_control = HOST_DSI_CTRL_COMMON |
1549                         HOST_DSI_CTRL_HOST_DRIVEN |
1550                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1551         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1552
1553         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1554         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1555         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1556
1557         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1558         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1559         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1560 }
1561
1562 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1563 {
1564         u32 dsi_control;
1565         u32 host_dsi_control;
1566         u32 max_threshold;
1567         u32 dcs_cmd;
1568
1569         dsi_control = dsi->dsi_control_val;
1570         host_dsi_control = HOST_DSI_CTRL_COMMON;
1571         max_threshold = 0;
1572         dcs_cmd = 0;
1573
1574         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1575                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1576                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1577                 max_threshold =
1578                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1579                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1580         } else {
1581                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1582                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1583                 max_threshold =
1584                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1585                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1586         }
1587
1588         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1589                 dsi_control |= DSI_CTRL_CMD_MODE;
1590                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1591                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1592                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1593
1594         } else {
1595                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1596                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1597         }
1598
1599         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1600         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1601         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1602         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1603 }
1604
1605 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1606 {
1607         u32 val;
1608
1609         val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1610                 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1611                 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1612                 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1613                 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1614         if (!dsi->ulpm) {
1615                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
1616                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1617                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1618         } else {
1619                 val |=  DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1620                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1621                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1622         }
1623         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1624
1625         val = MIPI_CAL_TERMOSA(0x4);
1626         tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1627
1628         val = MIPI_CAL_TERMOSB(0x4);
1629         tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1630
1631         val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1632         tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1633
1634         val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1635         tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1636
1637         val = PAD_CIL_PDVREG(0x0);
1638         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1639 }
1640
1641 static void tegra_dsi_panelB_enable(void)
1642 {
1643         unsigned int val;
1644
1645         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
1646         val |= DSIB_MODE_ENABLE;
1647         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
1648 }
1649
1650 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1651                                                 struct tegra_dc_dsi_data *dsi)
1652 {
1653         u32 i;
1654
1655         tegra_dsi_writel(dsi,
1656                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1657                 DSI_POWER_CONTROL);
1658         /* stabilization delay */
1659         udelay(300);
1660
1661         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1662         if (dsi->info.dsi_instance) {
1663                 tegra_dsi_panelB_enable();
1664         }
1665
1666         /* TODO: only need to change the timing for bta */
1667         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1668
1669         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1670                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1671
1672         /* Initializing DSI registers */
1673         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1674                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1675
1676         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1677
1678         tegra_dsi_pad_calibration(dsi);
1679
1680         tegra_dsi_writel(dsi,
1681                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1682                 DSI_POWER_CONTROL);
1683         /* stabilization delay */
1684         udelay(300);
1685
1686         dsi->status.init = DSI_MODULE_INIT;
1687         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1688         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1689         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1690         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1691         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1692         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1693         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1694         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1695
1696         return 0;
1697 }
1698
1699 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1700                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1701 {
1702         int err;
1703
1704         if (dsi->status.init != DSI_MODULE_INIT) {
1705                 err = -EPERM;
1706                 goto fail;
1707         }
1708
1709         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1710                         dsi->status.lp_op == lp_op)
1711                 goto success;
1712
1713         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1714                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1715
1716         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1717         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1718                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1719                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1720
1721         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1722         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1723                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1724                 tegra_dsi_set_timeout(dsi);
1725         }
1726
1727         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1728
1729         tegra_dsi_set_control_reg_lp(dsi);
1730
1731         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1732                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1733                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1734
1735         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1736         dsi->status.lp_op = lp_op;
1737 success:
1738         err = 0;
1739 fail:
1740         return err;
1741 }
1742
1743 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1744                                         struct tegra_dc_dsi_data *dsi)
1745 {
1746         int err;
1747
1748         if (dsi->status.init != DSI_MODULE_INIT) {
1749                 err = -EPERM;
1750                 goto fail;
1751         }
1752
1753         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1754                 goto success;
1755
1756         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1757                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1758
1759         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1760                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1761                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1762
1763         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1764                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1765                 tegra_dsi_set_timeout(dsi);
1766         }
1767
1768         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1769
1770         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1771                 tegra_dsi_set_pkt_seq(dc, dsi);
1772                 tegra_dsi_set_pkt_length(dc, dsi);
1773                 tegra_dsi_set_sol_delay(dc, dsi);
1774                 tegra_dsi_set_dc_clk(dc, dsi);
1775         }
1776
1777         tegra_dsi_set_control_reg_hs(dsi);
1778
1779         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1780                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1781                 tegra_dsi_hs_clk_out_enable(dsi);
1782
1783         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1784 success:
1785         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1786         err = 0;
1787 fail:
1788         return err;
1789 }
1790
1791 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1792 {
1793         u32 timeout = 0;
1794         bool retVal = true;
1795
1796         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1797                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1798                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1799                         retVal = false;
1800                         break;
1801                 }
1802                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1803                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1804         }
1805
1806         return retVal;
1807 }
1808
1809 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1810 {
1811         u32 timeout = 0;
1812         bool retVal = true;
1813
1814         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
1815                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1816                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1817                         retVal = false;
1818                         break;
1819                 }
1820                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1821                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1822         }
1823
1824         return retVal;
1825 }
1826
1827 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1828 {
1829         int err = 0;
1830
1831         if (tegra_dsi_write_busy(dsi)) {
1832                 err = -EBUSY;
1833                 dev_err(&dsi->dc->ndev->dev,
1834                         "DSI trigger bit already set\n");
1835                 goto fail;
1836         }
1837
1838         if (tegra_dsi_read_busy(dsi)) {
1839                 err = -EBUSY;
1840                 dev_err(&dsi->dc->ndev->dev,
1841                         "DSI immediate bta bit already set\n");
1842                 goto fail;
1843         }
1844 fail:
1845         return (err < 0 ? true : false);
1846 }
1847
1848 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1849 {
1850         u32 trigger;
1851         u32 status;
1852
1853         tegra_dsi_writel(dsi,
1854                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1855                 DSI_POWER_CONTROL);
1856         /* stabilization delay */
1857         udelay(300);
1858
1859         tegra_dsi_writel(dsi,
1860                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1861                 DSI_POWER_CONTROL);
1862         /* stabilization delay */
1863         udelay(300);
1864
1865         /* dsi HW does not clear host trigger bit automatically
1866          * on dsi interface disable if host fifo is empty
1867          */
1868         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1869         status = tegra_dsi_readl(dsi, DSI_STATUS);
1870         if (trigger & DSI_TRIGGER_HOST_TRIGGER(0x1) &&
1871                 status & DSI_STATUS_IDLE(0x1)) {
1872                 trigger &= ~(DSI_TRIGGER_HOST_TRIGGER(0x1));
1873                 tegra_dsi_writel(dsi, trigger, DSI_TRIGGER);
1874         }
1875 }
1876
1877 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1878 {
1879         u32 val;
1880
1881         val = tegra_dsi_readl(dsi, DSI_STATUS);
1882         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1883         if (val) {
1884                 dev_warn(&dsi->dc->ndev->dev,
1885                         "DSI read count not zero, resetting\n");
1886                 tegra_dsi_soft_reset(dsi);
1887         }
1888 }
1889
1890 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1891                                                 struct tegra_dc_dsi_data *dsi,
1892                                                 struct tegra_dc *dc,
1893                                                 u8 lp_op)
1894 {
1895         struct dsi_status *init_status;
1896         int err;
1897
1898         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1899         if (!init_status)
1900                 return ERR_PTR(-ENOMEM);
1901
1902         *init_status = dsi->status;
1903
1904         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1905                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1906                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1907                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1908                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1909                         if (dsi->info.hs_cmd_mode_supported) {
1910                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1911                                 if (err < 0) {
1912                                         dev_err(&dc->ndev->dev,
1913                                         "Switch to HS host mode failed\n");
1914                                         goto fail;
1915                                 }
1916                         }
1917                 }
1918                 if (!dsi->info.hs_cmd_mode_supported) {
1919                         err =
1920                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1921                         if (err < 0) {
1922                                 dev_err(&dc->ndev->dev,
1923                                 "DSI failed to go to LP mode\n");
1924                                 goto fail;
1925                         }
1926                 }
1927         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1928                 if (dsi->status.lp_op != lp_op) {
1929                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1930                         if (err < 0) {
1931                                 dev_err(&dc->ndev->dev,
1932                                 "DSI failed to go to LP mode\n");
1933                                 goto fail;
1934                         }
1935                 }
1936         }
1937
1938         return init_status;
1939 fail:
1940         kfree(init_status);
1941         return ERR_PTR(err);
1942 }
1943
1944 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1945                                 struct tegra_dc *dc,
1946                                 struct tegra_dc_dsi_data *dsi,
1947                                 u8 lp_op)
1948 {
1949         int err = 0;
1950         struct dsi_status *init_status;
1951
1952         if (dsi->status.init != DSI_MODULE_INIT ||
1953                 dsi->ulpm) {
1954                 err = -EPERM;
1955                 goto fail;
1956         }
1957
1958         if (tegra_dsi_host_busy(dsi)) {
1959                 tegra_dsi_soft_reset(dsi);
1960
1961                 /* WAR to stop host write in middle */
1962                 tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_TRIGGER);
1963
1964                 if (tegra_dsi_host_busy(dsi)) {
1965                         err = -EBUSY;
1966                         dev_err(&dc->ndev->dev, "DSI host busy\n");
1967                         goto fail;
1968                 }
1969         }
1970
1971         if (lp_op == DSI_LP_OP_READ)
1972                 tegra_dsi_reset_read_count(dsi);
1973
1974         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1975                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1976                 if (err < 0) {
1977                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1978                         goto fail;
1979                 }
1980         }
1981
1982         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1983                                         (dsi, dc, lp_op);
1984         if (IS_ERR_OR_NULL(init_status)) {
1985                 err = PTR_ERR(init_status);
1986                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1987                 goto fail;
1988         }
1989
1990         return init_status;
1991 fail:
1992         return ERR_PTR(err);
1993 }
1994
1995 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1996                                 struct tegra_dc_dsi_data *dsi,
1997                                 struct dsi_status *init_status)
1998 {
1999         bool switch_back_to_dc_mode = false;
2000         bool switch_back_to_hs_mode = false;
2001         bool restart_dc_stream;
2002         int err = 0;
2003
2004         switch_back_to_dc_mode = (dsi->status.driven ==
2005                                 DSI_DRIVEN_MODE_HOST &&
2006                                 init_status->driven ==
2007                                 DSI_DRIVEN_MODE_DC);
2008         switch_back_to_hs_mode = (dsi->status.lphs ==
2009                                 DSI_LPHS_IN_LP_MODE &&
2010                                 init_status->lphs ==
2011                                 DSI_LPHS_IN_HS_MODE);
2012         restart_dc_stream = (dsi->status.dc_stream ==
2013                                 DSI_DC_STREAM_DISABLE &&
2014                                 init_status->dc_stream ==
2015                                 DSI_DC_STREAM_ENABLE);
2016
2017         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2018                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2019                 if (dsi->status.lp_op != init_status->lp_op) {
2020                         err =
2021                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2022                         if (err < 0) {
2023                                 dev_err(&dc->ndev->dev,
2024                                         "Failed to config LP mode\n");
2025                                 goto fail;
2026                         }
2027                 }
2028                 goto success;
2029         }
2030
2031         if (switch_back_to_dc_mode)
2032                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2033         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
2034                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2035                 if (err < 0) {
2036                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2037                         goto fail;
2038                 }
2039         }
2040         if (restart_dc_stream)
2041                 tegra_dsi_start_dc_stream(dc, dsi);
2042
2043 success:
2044 fail:
2045         kfree(init_status);
2046         return err;
2047 }
2048
2049 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2050 {
2051         int status = 0;
2052
2053         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2054                 status = -EBUSY;
2055                 goto fail;
2056         }
2057
2058         tegra_dsi_writel(dsi,
2059                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2060
2061 #if DSI_USE_SYNC_POINTS
2062         status = tegra_dsi_syncpt(dsi);
2063         if (status < 0) {
2064                 dev_err(&dsi->dc->ndev->dev,
2065                         "DSI syncpt for host trigger failed\n");
2066                 goto fail;
2067         }
2068 #else
2069         if (tegra_dsi_write_busy(dsi)) {
2070                 status = -EBUSY;
2071                 dev_err(&dsi->dc->ndev->dev,
2072                         "Timeout waiting on write completion\n");
2073         }
2074 #endif
2075
2076 fail:
2077         return status;
2078 }
2079
2080 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2081                                         u8 *pdata, u8 data_id, u16 data_len)
2082 {
2083         u8 virtual_channel;
2084         u8 *pval;
2085         u32 val;
2086         int err;
2087
2088         err = 0;
2089
2090         virtual_channel = dsi->info.virtual_channel <<
2091                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2092
2093         /* always use hw for ecc */
2094         val = (virtual_channel | data_id) << 0 |
2095                         data_len << 8;
2096         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2097
2098         /* if pdata != NULL, pkt type is long pkt */
2099         if (pdata != NULL) {
2100                 while (data_len) {
2101                         if (data_len >= 4) {
2102                                 val = ((u32 *) pdata)[0];
2103                                 data_len -= 4;
2104                                 pdata += 4;
2105                         } else {
2106                                 val = 0;
2107                                 pval = (u8 *) &val;
2108                                 do
2109                                         *pval++ = *pdata++;
2110                                 while (--data_len);
2111                         }
2112                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2113                 }
2114         }
2115
2116         err = tegra_dsi_host_trigger(dsi);
2117         if (err < 0)
2118                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2119
2120         return err;
2121 }
2122
2123 int tegra_dsi_write_data(struct tegra_dc *dc,
2124                         struct tegra_dc_dsi_data *dsi,
2125                         u8 *pdata, u8 data_id, u16 data_len)
2126 {
2127         int err = 0;
2128         struct dsi_status *init_status;
2129
2130         tegra_dc_io_start(dc);
2131
2132         init_status = tegra_dsi_prepare_host_transmission(
2133                                 dc, dsi, DSI_LP_OP_WRITE);
2134         if (IS_ERR_OR_NULL(init_status)) {
2135                 err = PTR_ERR(init_status);
2136                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2137                 goto fail;
2138         }
2139
2140         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2141 fail:
2142         err = tegra_dsi_restore_state(dc, dsi, init_status);
2143         if (err < 0)
2144                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2145         tegra_dc_io_end(dc);
2146         return err;
2147 }
2148 EXPORT_SYMBOL(tegra_dsi_write_data);
2149
2150 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2151                                         struct tegra_dc_dsi_data *dsi,
2152                                         struct tegra_dsi_cmd *cmd,
2153                                         u32 n_cmd)
2154 {
2155         u32 i;
2156         int err;
2157
2158         err = 0;
2159         for (i = 0; i < n_cmd; i++) {
2160                 struct tegra_dsi_cmd *cur_cmd;
2161                 cur_cmd = &cmd[i];
2162
2163                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
2164                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2165                 else {
2166                         err = tegra_dsi_write_data(dc, dsi,
2167                                                 cur_cmd->pdata,
2168                                                 cur_cmd->data_id,
2169                                                 cur_cmd->sp_len_dly.data_len);
2170                         if (err < 0)
2171                                 break;
2172                 }
2173         }
2174         return err;
2175 }
2176
2177 static u8 get_8bit_ecc(u32 header)
2178 {
2179         char ecc_parity[24] = {
2180                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2181                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2182                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2183         };
2184         u8 ecc_byte;
2185         int i;
2186
2187         ecc_byte = 0;
2188         for (i = 0; i < 24; i++)
2189                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2190
2191         return ecc_byte;
2192 }
2193
2194 /* This function is written to send DCS short write (1 parameter) only.
2195  * This means the cmd will contain only 1 byte of index and 1 byte of value.
2196  * The data type ID is fixed at 0x15 and the ECC is calculated based on the
2197  * data in pdata.
2198  * The command will be sent by hardware every frame.
2199  * pdata should contain both the index + value for each cmd.
2200  * data_len will be the total number of bytes in pdata.
2201  */
2202 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
2203 {
2204         u8 ecc8bits = 0, data_len_orig = 0;
2205         u32 val = 0, pkthdr = 0;
2206         int err = 0, count = 0;
2207         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2208
2209         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2210                 tegra_dc_host_resume(dc);
2211
2212         data_len_orig = data_len;
2213         if (pdata != NULL) {
2214                 while (data_len) {
2215                         if (data_len >= 2) {
2216                                 pkthdr = (CMD_SHORTW |
2217                                         (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
2218                                 ecc8bits = get_8bit_ecc(pkthdr);
2219                                 val = (pkthdr | (ecc8bits << 24));
2220                                 data_len -= 2;
2221                                 pdata += 2;
2222                                 count++;
2223                         }
2224                         switch (count) {
2225                         case 1:
2226                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
2227                                 break;
2228                         case 2:
2229                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
2230                                 break;
2231                         case 3:
2232                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
2233                                 break;
2234                         case 4:
2235                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
2236                                 break;
2237                         case 5:
2238                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
2239                                 break;
2240                         case 6:
2241                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
2242                                 break;
2243                         case 7:
2244                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
2245                                 break;
2246                         case 8:
2247                                 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
2248                                 break;
2249                         default:
2250                                 err = 1;
2251                                 break;
2252                         }
2253                 }
2254         }
2255
2256         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
2257                 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
2258         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2259
2260         return err;
2261 }
2262 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
2263
2264 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2265 {
2266         u32 val;
2267         u32 poll_time;
2268         int err;
2269
2270         poll_time = 0;
2271         err = 0;
2272
2273         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2274         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2275         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2276
2277 #if DSI_USE_SYNC_POINTS
2278         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev,
2279                         dsi->syncpt_id);
2280
2281         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2282                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2283         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2284
2285         /* TODO: Use interrupt rather than polling */
2286         err = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
2287                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
2288         if (err < 0)
2289                 dev_err(&dsi->dc->ndev->dev,
2290                         "DSI sync point failure\n");
2291         else
2292                 (dsi->syncpt_val)++;
2293 #else
2294         if (tegra_dsi_read_busy(dsi)) {
2295                 err = -EBUSY;
2296                 dev_err(&dsi->dc->ndev->dev,
2297                         "Timeout wating on read completion\n");
2298         }
2299 #endif
2300
2301         return err;
2302 }
2303
2304 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2305                                         u32 rd_fifo_cnt, u8 *read_fifo)
2306 {
2307         int err;
2308         u32 payload_size;
2309
2310         payload_size = 0;
2311         err = 0;
2312
2313         switch (read_fifo[0]) {
2314         case DSI_ESCAPE_CMD:
2315                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2316                 break;
2317         case DSI_ACK_NO_ERR:
2318                 dev_info(&dc->ndev->dev,
2319                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2320                 return err;
2321         default:
2322                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2323                 break;
2324         }
2325
2326         switch (read_fifo[4] & 0xff) {
2327         case GEN_LONG_RD_RES:
2328                 /* Fall through */
2329         case DCS_LONG_RD_RES:
2330                 payload_size = (read_fifo[5] |
2331                                 (read_fifo[6] << 8)) & 0xFFFF;
2332                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2333                                 "payload_size[0x%x]\n", payload_size);
2334                 break;
2335         case GEN_1_BYTE_SHORT_RD_RES:
2336                 /* Fall through */
2337         case DCS_1_BYTE_SHORT_RD_RES:
2338                 payload_size = 1;
2339                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2340                         "payload_size[0x%x]\n", payload_size);
2341                 break;
2342         case GEN_2_BYTE_SHORT_RD_RES:
2343                 /* Fall through */
2344         case DCS_2_BYTE_SHORT_RD_RES:
2345                 payload_size = 2;
2346                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2347                         "payload_size[0x%x]\n", payload_size);
2348                 break;
2349         case ACK_ERR_RES:
2350                 payload_size = 2;
2351                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2352                         "Packet payload_size[0x%x]\n", payload_size);
2353                 break;
2354         default:
2355                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2356                 err = -EINVAL;
2357                 break;
2358         }
2359         return err;
2360 }
2361
2362 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2363                         struct tegra_dc_dsi_data *dsi,
2364                         u8 *read_fifo)
2365 {
2366         u32 val;
2367         u32 i;
2368         u32 poll_time = 0;
2369         u32 rd_fifo_cnt;
2370         int err = 0;
2371         u8 *read_fifo_cp = read_fifo;
2372
2373         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2374                 mdelay(1);
2375                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2376                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2377                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2378                         dev_err(&dc->ndev->dev,
2379                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2380                         break;
2381                 poll_time++;
2382         }
2383
2384         if (rd_fifo_cnt == 0) {
2385                 dev_info(&dc->ndev->dev,
2386                         "DSI RD_FIFO_CNT is zero\n");
2387                 err = -EINVAL;
2388                 goto fail;
2389         }
2390
2391         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2392                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2393                 dev_warn(&dc->ndev->dev,
2394                         "DSI overflow/underflow error\n");
2395         }
2396
2397         /* Read data from FIFO */
2398         for (i = 0; i < rd_fifo_cnt; i++) {
2399                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2400                 if (enable_read_debug)
2401                         dev_info(&dc->ndev->dev,
2402                         "Read data[%d]: 0x%x\n", i, val);
2403                 memcpy(read_fifo, &val, 4);
2404                 read_fifo += 4;
2405         }
2406
2407         /* Make sure all the data is read from the FIFO */
2408         val = tegra_dsi_readl(dsi, DSI_STATUS);
2409         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2410         if (val)
2411                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2412                 " even after reading FIFO_RD_CNT words from read fifo\n");
2413
2414         if (enable_read_debug) {
2415                 err =
2416                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2417                 if (err < 0)
2418                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2419         }
2420 fail:
2421         return err;
2422 }
2423
2424 int tegra_dsi_read_data(struct tegra_dc *dc,
2425                                 struct tegra_dc_dsi_data *dsi,
2426                                 u32 max_ret_payload_size,
2427                                 u32 panel_reg_addr, u8 *read_data)
2428 {
2429         int err = 0;
2430         struct dsi_status *init_status;
2431
2432         tegra_dc_io_start(dc);
2433
2434         init_status = tegra_dsi_prepare_host_transmission(
2435                                 dc, dsi, DSI_LP_OP_WRITE);
2436         if (IS_ERR_OR_NULL(init_status)) {
2437                 err = PTR_ERR(init_status);
2438                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2439                 goto fail;
2440         }
2441
2442         /* Set max return payload size in words */
2443         err = _tegra_dsi_write_data(dsi, NULL,
2444                 dsi_command_max_return_pkt_size,
2445                 max_ret_payload_size);
2446         if (err < 0) {
2447                 dev_err(&dc->ndev->dev,
2448                                 "DSI write failed\n");
2449                 goto fail;
2450         }
2451
2452         /* DCS to read given panel register */
2453         err = _tegra_dsi_write_data(dsi, NULL,
2454                 dsi_command_dcs_read_with_no_params,
2455                 panel_reg_addr);
2456         if (err < 0) {
2457                 dev_err(&dc->ndev->dev,
2458                                 "DSI write failed\n");
2459                 goto fail;
2460         }
2461
2462         tegra_dsi_reset_read_count(dsi);
2463
2464         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2465                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2466                 if (err < 0) {
2467                         dev_err(&dc->ndev->dev,
2468                         "DSI failed to go to LP read mode\n");
2469                         goto fail;
2470                 }
2471         }
2472
2473         err = tegra_dsi_bta(dsi);
2474         if (err < 0) {
2475                 dev_err(&dc->ndev->dev,
2476                         "DSI IMM BTA timeout\n");
2477                 goto fail;
2478         }
2479
2480         err = tegra_dsi_read_fifo(dc, dsi, read_data);
2481         if (err < 0) {
2482                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2483                 goto fail;
2484         }
2485 fail:
2486         err = tegra_dsi_restore_state(dc, dsi, init_status);
2487         if (err < 0)
2488                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2489         tegra_dc_io_end(dc);
2490         return err;
2491 }
2492 EXPORT_SYMBOL(tegra_dsi_read_data);
2493
2494 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2495                                 struct tegra_dc_dsi_data *dsi)
2496 {
2497         int err = 0;
2498         u8 read_fifo[DSI_READ_FIFO_DEPTH];
2499         struct dsi_status *init_status;
2500         static struct tegra_dsi_cmd dsi_nop_cmd =
2501                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
2502
2503         tegra_dc_io_start(dc);
2504
2505         init_status = tegra_dsi_prepare_host_transmission(
2506                                         dc, dsi, DSI_LP_OP_WRITE);
2507         if (IS_ERR_OR_NULL(init_status)) {
2508                 err = PTR_ERR(init_status);
2509                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2510                 goto fail;
2511         }
2512
2513         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2514         if (err < 0) {
2515                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2516                 goto fail;
2517         }
2518
2519         tegra_dsi_reset_read_count(dsi);
2520
2521         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2522                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2523                 if (err < 0) {
2524                         dev_err(&dc->ndev->dev,
2525                         "DSI failed to go to LP read mode\n");
2526                         goto fail;
2527                 }
2528         }
2529
2530         err = tegra_dsi_bta(dsi);
2531         if (err < 0) {
2532                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2533                 goto fail;
2534         }
2535
2536         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2537         if (err < 0) {
2538                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2539                 goto fail;
2540         }
2541
2542         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2543                 dev_warn(&dc->ndev->dev,
2544                         "Ack no error trigger message not received\n");
2545                 err = -EAGAIN;
2546         }
2547 fail:
2548         err = tegra_dsi_restore_state(dc, dsi, init_status);
2549         if (err < 0)
2550                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2551         tegra_dc_io_end(dc);
2552         return err;
2553 }
2554 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2555
2556 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2557 {
2558         u32 val;
2559         int ret;
2560
2561         ret = 0;
2562
2563         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2564         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2565         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2566         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2567
2568 #if DSI_USE_SYNC_POINTS
2569         ret = tegra_dsi_syncpt(dsi);
2570         if (ret < 0) {
2571                 dev_err(&dsi->dc->ndev->dev,
2572                         "DSI syncpt for ulpm enter failed\n");
2573                 goto fail;
2574         }
2575 #else
2576         /* TODO: Find exact delay required */
2577         mdelay(10);
2578 #endif
2579         dsi->ulpm = true;
2580 fail:
2581         return ret;
2582 }
2583
2584 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2585 {
2586         u32 val;
2587         int ret;
2588
2589         ret = 0;
2590
2591         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2592         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2593         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2594         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2595
2596 #if DSI_USE_SYNC_POINTS
2597         ret = tegra_dsi_syncpt(dsi);
2598         if (ret < 0) {
2599                 dev_err(&dsi->dc->ndev->dev,
2600                         "DSI syncpt for ulpm exit failed\n");
2601                 goto fail;
2602         }
2603 #else
2604         /* TODO: Find exact delay required */
2605         mdelay(10);
2606 #endif
2607         dsi->ulpm = false;
2608
2609         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2610         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2611         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2612         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2613 fail:
2614         return ret;
2615
2616 }
2617
2618 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
2619                                      struct tegra_dc_dsi_data *dsi,
2620                                      int no_of_frames)
2621 {
2622         int err;
2623         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
2624         u8 lp_op = dsi->status.lp_op;
2625         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
2626
2627         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
2628                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2629                 if (err < 0) {
2630                         dev_err(&dc->ndev->dev,
2631                                 "Switch to HS host mode failed\n");
2632                         return;
2633                 }
2634         }
2635
2636         /*
2637          * Some panels need DC frames be sent under certain
2638          * conditions. We are working on the right fix for this
2639          * requirement, while using this current fix.
2640          */
2641         tegra_dsi_start_dc_stream(dc, dsi);
2642
2643         /*
2644          * Send frames in Continuous or One-shot mode.
2645          */
2646         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2647                 while (no_of_frames--) {
2648                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
2649                                         DC_CMD_STATE_CONTROL);
2650                         mdelay(frame_period);
2651                 }
2652         } else
2653                 mdelay(no_of_frames * frame_period);
2654
2655         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2656
2657         if (switch_to_lp) {
2658                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2659                 if (err < 0)
2660                         dev_err(&dc->ndev->dev,
2661                                 "DSI failed to go to LP mode\n");
2662         }
2663 }
2664
2665 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2666 {
2667         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2668         int err;
2669         u32 val;
2670
2671         tegra_dc_io_start(dc);
2672         mutex_lock(&dsi->lock);
2673
2674         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2675                 tegra_dc_host_resume(dc);
2676         /* Stop DC stream before configuring DSI registers
2677          * to avoid visible glitches on panel during transition
2678          * from bootloader to kernel driver
2679          */
2680         tegra_dsi_stop_dc_stream(dc, dsi);
2681
2682         if (dsi->enabled) {
2683                 if (dsi->ulpm) {
2684                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2685                                 dev_err(&dc->ndev->dev,
2686                                         "DSI failed to exit ulpm\n");
2687                                 goto fail;
2688                         }
2689                 }
2690
2691                 if (dsi->info.panel_reset) {
2692                         /*
2693                          * Certain panels need dc frames be sent before
2694                          * waking panel.
2695                          */
2696                         if (dsi->info.panel_send_dc_frames)
2697                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
2698
2699                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2700                                                         dsi->info.dsi_init_cmd,
2701                                                         dsi->info.n_init_cmd);
2702                         if (err < 0) {
2703                                 dev_err(&dc->ndev->dev,
2704                                 "dsi: error sending dsi init cmd\n");
2705                                 goto fail;
2706                         }
2707                 } else if (dsi->info.dsi_late_resume_cmd) {
2708                         err = tegra_dsi_send_panel_cmd(dc, dsi,
2709                                                 dsi->info.dsi_late_resume_cmd,
2710                                                 dsi->info.n_late_resume_cmd);
2711                         if (err < 0) {
2712                                 dev_err(&dc->ndev->dev,
2713                                 "dsi: error sending late resume cmd\n");
2714                                 goto fail;
2715                         }
2716                 }
2717         } else {
2718                 err = tegra_dsi_init_hw(dc, dsi);
2719                 if (err < 0) {
2720                         dev_err(&dc->ndev->dev,
2721                                 "dsi: not able to init dsi hardware\n");
2722                         goto fail;
2723                 }
2724
2725                 if (dsi->ulpm) {
2726                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
2727                                 dev_err(&dc->ndev->dev,
2728                                         "DSI failed to enter ulpm\n");
2729                                 goto fail;
2730                         }
2731
2732                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2733
2734                         /* erase bits we're about to set */
2735                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2736                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2737                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2738
2739                         val |= (DSI_PAD_CONTROL_PAD_PDIO(0) |
2740                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2741                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2742                                                 (TEGRA_DSI_DISABLE));
2743
2744                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2745                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
2746                                 dev_err(&dc->ndev->dev,
2747                                         "DSI failed to exit ulpm\n");
2748                                 goto fail;
2749                         }
2750                 }
2751
2752                 /*
2753                  * Certain panels need dc frames be sent before
2754                  * waking panel.
2755                  */
2756                 if (dsi->info.panel_send_dc_frames)
2757                         tegra_dsi_send_dc_frames(dc, dsi, 2);
2758
2759                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2760                 if (err < 0) {
2761                         dev_err(&dc->ndev->dev,
2762                                 "dsi: not able to set to lp mode\n");
2763                         goto fail;
2764                 }
2765
2766                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2767                                                 dsi->info.n_init_cmd);
2768                 if (err < 0) {
2769                         dev_err(&dc->ndev->dev,
2770                                 "dsi: error while sending dsi init cmd\n");
2771                         goto fail;
2772                 }
2773
2774                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2775                 if (err < 0) {
2776                         dev_err(&dc->ndev->dev,
2777                                 "dsi: not able to set to hs mode\n");
2778                         goto fail;
2779                 }
2780
2781                 dsi->enabled = true;
2782         }
2783
2784         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2785                 tegra_dsi_start_dc_stream(dc, dsi);
2786 fail:
2787         mutex_unlock(&dsi->lock);
2788         tegra_dc_io_end(dc);
2789 }
2790
2791 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2792 {
2793         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2794
2795         tegra_dc_dsi_debug_create(dsi);
2796         tegra_dsi_init_sw(dc, dsi);
2797         /* TODO: Configure the CSI pad configuration */
2798 }
2799
2800 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2801                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
2802 {
2803         u16 i;
2804         u16 len;
2805
2806         memcpy(dst, src, sizeof(*dst) * n_cmd);
2807
2808         for (i = 0; i < n_cmd; i++)
2809                 if (src[i].pdata) {
2810                         len = sizeof(*src[i].pdata) *
2811                                         src[i].sp_len_dly.data_len;
2812                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
2813                         if (!dst[i].pdata)
2814                                 goto free_cmd_pdata;
2815                         memcpy(dst[i].pdata, src[i].pdata, len);
2816                 }
2817
2818         return 0;
2819
2820 free_cmd_pdata:
2821         for (--i; i >= 0; i--)
2822                 if (dst[i].pdata)
2823                         kfree(dst[i].pdata);
2824         return -ENOMEM;
2825 }
2826
2827 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2828                                         struct tegra_dsi_out *p_dsi)
2829 {
2830         struct tegra_dsi_cmd *p_init_cmd;
2831         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
2832         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
2833         struct tegra_dsi_cmd *p_suspend_cmd;
2834         int err;
2835
2836         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2837                 return -EINVAL;
2838
2839         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2840                                 p_dsi->n_init_cmd, GFP_KERNEL);
2841         if (!p_init_cmd)
2842                 return -ENOMEM;
2843
2844         if (p_dsi->dsi_early_suspend_cmd) {
2845                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2846                                         p_dsi->n_early_suspend_cmd,
2847                                         GFP_KERNEL);
2848                 if (!p_early_suspend_cmd) {
2849                         err = -ENOMEM;
2850                         goto err_free_init_cmd;
2851                 }
2852         }
2853
2854         if (p_dsi->dsi_late_resume_cmd) {
2855                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2856                                         p_dsi->n_late_resume_cmd,
2857                                         GFP_KERNEL);
2858                 if (!p_late_resume_cmd) {
2859                         err = -ENOMEM;
2860                         goto err_free_p_early_suspend_cmd;
2861                 }
2862         }
2863
2864         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2865                                 GFP_KERNEL);
2866         if (!p_suspend_cmd) {
2867                 err = -ENOMEM;
2868                 goto err_free_p_late_resume_cmd;
2869         }
2870
2871         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2872
2873         /* Copy panel init cmd */
2874         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2875                                                 p_init_cmd, p_dsi->n_init_cmd);
2876         if (err < 0)
2877                 goto err_free;
2878         dsi->info.dsi_init_cmd = p_init_cmd;
2879
2880         /* Copy panel early suspend cmd */
2881         if (p_dsi->dsi_early_suspend_cmd) {
2882                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2883                                         p_early_suspend_cmd,
2884                                         p_dsi->n_early_suspend_cmd);
2885                 if (err < 0)
2886                         goto err_free;
2887                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2888         }
2889
2890         /* Copy panel late resume cmd */
2891         if (p_dsi->dsi_late_resume_cmd) {
2892                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2893                                                 p_late_resume_cmd,
2894                                                 p_dsi->n_late_resume_cmd);
2895                 if (err < 0)
2896                         goto err_free;
2897                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2898         }
2899
2900         /* Copy panel suspend cmd */
2901         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2902                                         p_dsi->n_suspend_cmd);
2903         if (err < 0)
2904                 goto err_free;
2905         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2906
2907         if (!dsi->info.panel_reset_timeout_msec)
2908                 dsi->info.panel_reset_timeout_msec =
2909                                                 DEFAULT_PANEL_RESET_TIMEOUT;
2910
2911         if (!dsi->info.panel_buffer_size_byte)
2912                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2913
2914         if (!dsi->info.max_panel_freq_khz) {
2915                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2916
2917                 if (dsi->info.video_burst_mode >
2918                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2919                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2920                                         "is not set for DSI burst mode.\n");
2921                         dsi->info.video_burst_mode =
2922                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2923                 }
2924         }
2925
2926         if (!dsi->info.lp_cmd_mode_freq_khz)
2927                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2928
2929         if (!dsi->info.chip_id || !dsi->info.chip_rev)
2930                 dev_warn(&dsi->dc->ndev->dev,
2931                         "DSI: Failed to get chip info\n");
2932
2933         if (!dsi->info.lp_read_cmd_mode_freq_khz)
2934                 dsi->info.lp_read_cmd_mode_freq_khz =
2935                         dsi->info.lp_cmd_mode_freq_khz;
2936
2937         /* host mode is for testing only */
2938         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2939         return 0;
2940
2941 err_free:
2942         kfree(p_suspend_cmd);
2943 err_free_p_late_resume_cmd:
2944         kfree(p_late_resume_cmd);
2945 err_free_p_early_suspend_cmd:
2946         kfree(p_early_suspend_cmd);
2947 err_free_init_cmd:
2948         kfree(p_init_cmd);
2949         return err;
2950 }
2951
2952 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2953 {
2954         struct tegra_dc_dsi_data *dsi;
2955         struct resource *res;
2956         struct resource *base_res;
2957         void __iomem *base;
2958         struct clk *dc_clk = NULL;
2959         struct clk *dsi_clk = NULL;
2960         struct clk *dsi_fixed_clk = NULL;
2961         struct tegra_dsi_out *dsi_pdata;
2962         int err;
2963
2964         err = 0;
2965
2966         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2967         if (!dsi)
2968                 return -ENOMEM;
2969
2970         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2971                                         "dsi_regs");
2972         if (!res) {
2973                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2974                 err = -ENOENT;
2975                 goto err_free_dsi;
2976         }
2977
2978         base_res = request_mem_region(res->start, resource_size(res),
2979                                 dc->ndev->name);
2980         if (!base_res) {
2981                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2982                 err = -EBUSY;
2983                 goto err_free_dsi;
2984         }
2985
2986         base = ioremap(res->start, resource_size(res));
2987         if (!base) {
2988                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2989                 err = -EBUSY;
2990                 goto err_release_regs;
2991         }
2992
2993         dsi_pdata = dc->pdata->default_out->dsi;
2994         if (!dsi_pdata) {
2995                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2996                 goto err_release_regs;
2997         }
2998
2999         if (dsi_pdata->dsi_instance)
3000                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3001         else
3002                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3003         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3004
3005         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3006                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3007                 err = -EBUSY;
3008                 goto err_release_regs;
3009         }
3010
3011         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3012         if (IS_ERR_OR_NULL(dc_clk)) {
3013                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3014                         dev_name(&dc->ndev->dev));
3015                 err = -EBUSY;
3016                 goto err_clk_put;
3017         }
3018
3019         mutex_init(&dsi->lock);
3020         dsi->dc = dc;
3021         dsi->base = base;
3022         dsi->base_res = base_res;
3023         dsi->dc_clk = dc_clk;
3024         dsi->dsi_clk = dsi_clk;
3025         dsi->dsi_fixed_clk = dsi_fixed_clk;
3026
3027         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3028         if (err < 0)
3029                 goto err_dsi_data;
3030
3031         tegra_dc_set_outdata(dc, dsi);
3032         _tegra_dc_dsi_init(dc);
3033
3034         return 0;
3035
3036 err_dsi_data:
3037 err_clk_put:
3038         clk_put(dsi_clk);
3039         clk_put(dsi_fixed_clk);
3040 err_release_regs:
3041         release_resource(base_res);
3042 err_free_dsi:
3043         kfree(dsi);
3044
3045         return err;
3046 }
3047
3048 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
3049 {
3050         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3051         u16 i;
3052         u32 val;
3053
3054         mutex_lock(&dsi->lock);
3055
3056         /* free up the pdata */
3057         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3058                 if (dsi->info.dsi_init_cmd[i].pdata)
3059                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3060         }
3061         kfree(dsi->info.dsi_init_cmd);
3062
3063         /* Disable dc stream */
3064         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3065                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3066
3067         /* Disable dsi phy clock */
3068         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3069                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3070
3071         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3072         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3073
3074         iounmap(dsi->base);
3075         release_resource(dsi->base_res);
3076
3077         clk_put(dsi->dc_clk);
3078         clk_put(dsi->dsi_clk);
3079
3080         mutex_unlock(&dsi->lock);
3081
3082         mutex_destroy(&dsi->lock);
3083         kfree(dsi);
3084 }
3085
3086 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3087                                                         u32 settings)
3088 {
3089         struct clk *parent_clk = NULL;
3090         struct clk *base_clk = NULL;
3091
3092         /* Disable dsi fast and slow clock */
3093         parent_clk = clk_get_parent(dsi->dsi_clk);
3094         base_clk = clk_get_parent(parent_clk);
3095         if (dsi->info.dsi_instance)
3096                 tegra_clk_cfg_ex(base_clk,
3097                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3098                                 settings);
3099         else
3100                 tegra_clk_cfg_ex(base_clk,
3101                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3102                                 settings);
3103 }
3104
3105 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
3106                                 struct tegra_dc_dsi_data *dsi, u32 suspend_aggr)
3107 {
3108         int val = 0;
3109         int err = 0;
3110
3111         if (!dsi->enabled) {
3112                 err = -EPERM;
3113                 goto fail;
3114         }
3115
3116         switch (suspend_aggr) {
3117         case DSI_SUSPEND_FULL:
3118                 /* Suspend DSI panel */
3119                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3120                 if (err < 0) {
3121                         dev_err(&dc->ndev->dev,
3122                         "DSI failed to go to LP mode\n");
3123                         goto fail;
3124                 }
3125
3126                 err = tegra_dsi_send_panel_cmd(dc, dsi,
3127                                 dsi->info.dsi_suspend_cmd,
3128                                 dsi->info.n_suspend_cmd);
3129                 /*
3130                  * Certain panels need dc frames be sent after
3131                  * putting panel to sleep.
3132                  */
3133                 if (dsi->info.panel_send_dc_frames)
3134                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3135
3136                 if (err < 0) {
3137                         dev_err(&dc->ndev->dev,
3138                                 "dsi: Error sending suspend cmd\n");
3139                         goto fail;
3140                 }
3141         case DSI_HOST_SUSPEND_LV2:
3142                 /* Set DSI to ULPM and suspend pads. DSI will be set to the
3143                  * lowest power state in this level. */
3144                 if (!dsi->ulpm) {
3145                         err = tegra_dsi_enter_ulpm(dsi);
3146                         if (err < 0) {
3147                                 dev_err(&dc->ndev->dev,
3148                                         "DSI failed to enter ulpm\n");
3149                                 goto fail;
3150                         }
3151                 }
3152
3153                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3154                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3155                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
3156                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3157
3158                 /* Suspend core-logic */
3159                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3160                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3161         case DSI_HOST_SUSPEND_LV1:
3162                 /* Disable dsi fast and slow clock */
3163                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3164         case DSI_HOST_SUSPEND_LV0:
3165                 /* Disable dsi source clock */
3166                 tegra_dsi_clk_disable(dsi);
3167                 break;
3168         case DSI_NO_SUSPEND:
3169                 break;
3170         default:
3171                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3172                                                 "is not supported.\n");
3173         }
3174
3175         dsi->enabled = false;
3176
3177         return 0;
3178 fail:
3179         return err;
3180 }
3181
3182
3183 int tegra_dsi_host_suspend(struct tegra_dc *dc)
3184 {
3185         int err = 0;
3186         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3187
3188         if (dsi->host_suspended)
3189                 return 0;
3190
3191         tegra_dsi_stop_dc_stream(dc, dsi);
3192
3193         err = tegra_dsi_deep_sleep(dc, dsi, dsi->info.suspend_aggr);
3194         if (err < 0)
3195                 dev_err(&dc->ndev->dev,
3196                         "DSI failed to enter deep sleep\n");
3197
3198         dsi->host_suspended = true;
3199
3200         return err;
3201 }
3202
3203
3204 int tegra_dsi_host_resume(struct tegra_dc *dc)
3205 {
3206         int val = 0;
3207         int err = 0;
3208         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3209
3210         if (!dsi->host_suspended)
3211                 return 0;
3212
3213         switch (dsi->info.suspend_aggr) {
3214         case DSI_HOST_SUSPEND_LV0:
3215                 tegra_dsi_clk_enable(dsi);
3216                 break;
3217         case DSI_HOST_SUSPEND_LV1:
3218                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3219                 tegra_dsi_clk_enable(dsi);
3220                 break;
3221         case DSI_HOST_SUSPEND_LV2:
3222                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3223                 tegra_dsi_clk_enable(dsi);
3224
3225                 tegra_dsi_writel(dsi,
3226                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3227                         DSI_POWER_CONTROL);
3228
3229                 if (dsi->ulpm) {
3230                         err = tegra_dsi_enter_ulpm(dsi);
3231                         if (err < 0) {
3232                                 dev_err(&dc->ndev->dev,
3233                                         "DSI failed to enter ulpm\n");
3234                                 goto fail;
3235                         }
3236
3237                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3238                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3239                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3240                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3241                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3242
3243                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3244                                 dev_err(&dc->ndev->dev,
3245                                         "DSI failed to exit ulpm\n");
3246                                 goto fail;
3247                         }
3248                 }
3249                 break;
3250         case DSI_NO_SUSPEND:
3251                 break;
3252         default:
3253                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3254                                                 "is not supported.\n");
3255         }
3256
3257         dsi->enabled = true;
3258         dsi->host_suspended = false;
3259         tegra_dsi_start_dc_stream(dc, dsi);
3260 fail:
3261         return err;
3262 }
3263
3264 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
3265 {
3266         int err;
3267         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3268
3269         tegra_dc_io_start(dc);
3270         mutex_lock(&dsi->lock);
3271
3272         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3273                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3274
3275         if (dsi->info.power_saving_suspend) {
3276                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3277                         dev_err(&dc->ndev->dev,
3278                                 "DSI failed to enter deep sleep\n");
3279                         goto fail;
3280                 }
3281         } else {
3282                 if (dsi->info.dsi_early_suspend_cmd) {
3283                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3284                                 dsi->info.dsi_early_suspend_cmd,
3285                                 dsi->info.n_early_suspend_cmd);
3286                         if (err < 0) {
3287                                 dev_err(&dc->ndev->dev,
3288                                 "dsi: Error sending early suspend cmd\n");
3289                                 goto fail;
3290                         }
3291                 }
3292
3293                 if (!dsi->ulpm) {
3294                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3295                                 dev_err(&dc->ndev->dev,
3296                                         "DSI failed to enter ulpm\n");
3297                                 goto fail;
3298                         }
3299                 }
3300         }
3301
3302 fail:
3303         mutex_unlock(&dsi->lock);
3304         tegra_dc_io_end(dc);
3305 }
3306
3307 #ifdef CONFIG_PM
3308 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
3309 {
3310         struct tegra_dc_dsi_data *dsi;
3311
3312         dsi = tegra_dc_get_outdata(dc);
3313
3314         if (!dsi->enabled)
3315                 return;
3316
3317         tegra_dc_io_start(dc);
3318         mutex_lock(&dsi->lock);
3319
3320         if (!dsi->info.power_saving_suspend) {
3321                 if (dsi->ulpm) {
3322                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3323                                 dev_err(&dc->ndev->dev,
3324                                         "DSI failed to exit ulpm");
3325                                 goto fail;
3326                         }
3327                 }
3328
3329                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3330                         dev_err(&dc->ndev->dev,
3331                                 "DSI failed to enter deep sleep\n");
3332                         goto fail;
3333                 }
3334         }
3335 fail:
3336         mutex_unlock(&dsi->lock);
3337         tegra_dc_io_end(dc);
3338 }
3339
3340 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3341 {
3342         /* Not required since tegra_dc_dsi_enable
3343          * will reconfigure the controller from scratch
3344          */
3345 }
3346 #endif
3347
3348 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
3349         .init = tegra_dc_dsi_init,
3350         .destroy = tegra_dc_dsi_destroy,
3351         .enable = tegra_dc_dsi_enable,
3352         .disable = tegra_dc_dsi_disable,
3353 #ifdef CONFIG_PM
3354         .suspend = tegra_dc_dsi_suspend,
3355         .resume = tegra_dc_dsi_resume,
3356 #endif
3357 };