2 * drivers/video/tegra/dc/dsi.c
4 * Copyright (c) 2011, NVIDIA Corporation.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
32 #include <linux/nvhost.h>
39 #define DSI_USE_SYNC_POINTS 1
40 #define S_TO_MS(x) (1000 * (x))
42 #define DSI_MODULE_NOT_INIT 0x0
43 #define DSI_MODULE_INIT 0x1
45 #define DSI_LPHS_NOT_INIT 0x0
46 #define DSI_LPHS_IN_LP_MODE 0x1
47 #define DSI_LPHS_IN_HS_MODE 0x2
49 #define DSI_VIDEO_TYPE_NOT_INIT 0x0
50 #define DSI_VIDEO_TYPE_VIDEO_MODE 0x1
51 #define DSI_VIDEO_TYPE_CMD_MODE 0x2
53 #define DSI_DRIVEN_MODE_NOT_INIT 0x0
54 #define DSI_DRIVEN_MODE_DC 0x1
55 #define DSI_DRIVEN_MODE_HOST 0x2
57 #define DSI_PHYCLK_OUT_DIS 0x0
58 #define DSI_PHYCLK_OUT_EN 0x1
60 #define DSI_PHYCLK_NOT_INIT 0x0
61 #define DSI_PHYCLK_CONTINUOUS 0x1
62 #define DSI_PHYCLK_TX_ONLY 0x2
64 #define DSI_CLK_BURST_NOT_INIT 0x0
65 #define DSI_CLK_BURST_NONE_BURST 0x1
66 #define DSI_CLK_BURST_BURST_MODE 0x2
68 #define DSI_DC_STREAM_DISABLE 0x0
69 #define DSI_DC_STREAM_ENABLE 0x1
71 #define DSI_LP_OP_NOT_INIT 0x0
72 #define DSI_LP_OP_WRITE 0x1
73 #define DSI_LP_OP_READ 0x2
75 static bool enable_read_debug;
76 module_param(enable_read_debug, bool, 0644);
77 MODULE_PARM_DESC(enable_read_debug,
78 "Enable to print read fifo and return packet type");
97 /* source of video data */
99 TEGRA_DSI_DRIVEN_BY_DC,
100 TEGRA_DSI_DRIVEN_BY_HOST,
103 struct tegra_dc_dsi_data {
106 struct resource *base_res;
114 /* data from board info */
115 struct tegra_dsi_out info;
117 struct dsi_status status;
119 struct dsi_phy_timing_inclk phy_timing;
127 u32 default_shift_clk_div;
128 u32 default_pixel_clk_khz;
129 u32 default_hs_clk_khz;
132 u32 target_hs_clk_khz;
133 u32 target_lp_clk_khz;
138 u16 current_bit_clk_ns;
139 u32 current_dsi_clk_khz;
147 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
162 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
163 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
165 PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
167 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
169 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
170 PKT_ID2(CMD_HE) | PKT_LEN2(0),
171 PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
172 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
173 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
175 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
176 PKT_ID2(CMD_HE) | PKT_LEN2(0),
177 PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
178 PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
181 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
182 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
184 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
186 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
188 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
189 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
190 PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
191 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
193 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
194 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
195 PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
198 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
199 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
201 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
203 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
205 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
206 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
207 PKT_ID0(CMD_EOT) | PKT_LEN0(7),
208 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
210 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
211 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
212 PKT_ID0(CMD_EOT) | PKT_LEN0(7),
215 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
216 PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
218 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
220 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
222 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
223 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
224 PKT_ID0(CMD_EOT) | PKT_LEN0(0),
225 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
227 PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
228 PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
229 PKT_ID0(CMD_EOT) | PKT_LEN0(0),
232 /* TODO: verify with hw about this format */
233 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
240 PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
244 PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
248 const u32 init_reg[] = {
274 DSI_HOST_DSI_CONTROL,
281 DSI_INIT_SEQ_CONTROL,
288 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
290 return readl(dsi->base + reg * 4);
292 EXPORT_SYMBOL(tegra_dsi_readl);
294 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
296 writel(val, dsi->base + reg * 4);
298 EXPORT_SYMBOL(tegra_dsi_writel);
300 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
307 dsi->syncpt_val = nvhost_syncpt_read(
308 &nvhost_get_host(dsi->dc->ndev)->syncpt,
311 val = DSI_INCR_SYNCPT_COND(OP_DONE) |
312 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
313 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
315 /* TODO: Use interrupt rather than polling */
316 ret = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
317 dsi->syncpt_id, dsi->syncpt_val + 1);
319 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
329 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
331 u32 dsi_clock_rate_khz;
333 switch (dsi->info.video_burst_mode) {
334 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
335 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
336 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
337 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
338 /* Calculate DSI HS clock rate for DSI burst mode */
339 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
342 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
343 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
344 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
346 /* Clock rate is default DSI clock rate for non-burst mode */
347 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
351 return dsi_clock_rate_khz;
354 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
356 u32 dsi_clock_rate_khz;
358 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
359 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
361 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
363 dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
365 if (lp_op == DSI_LP_OP_READ)
367 dsi->info.lp_read_cmd_mode_freq_khz;
370 dsi->info.lp_cmd_mode_freq_khz;
372 return dsi_clock_rate_khz;
375 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
378 u32 max_shift_clk_div;
382 /* Get the real value of default shift_clk_div. default_shift_clk_div
383 * holds the real value of shift_clk_div.
385 shift_clk_div = dsi->default_shift_clk_div;
387 /* Calculate shift_clk_div which can matche the video_burst_mode. */
388 if (dsi->info.video_burst_mode >=
389 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
390 /* The max_shift_clk_div is multiplied by 10 to save the
393 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
394 max_shift_clk_div = dsi->info.max_panel_freq_khz
395 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
397 max_shift_clk_div = shift_clk_div * 10;
399 burst_width = dsi->info.video_burst_mode
400 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
401 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
402 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
404 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
405 burst_width / (burst_width_max * 10) + shift_clk_div;
408 return shift_clk_div;
411 static void tegra_dsi_init_sw(struct tegra_dc *dc,
412 struct tegra_dc_dsi_data *dsi)
420 switch (dsi->info.pixel_format) {
421 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
422 /* 2 bytes per pixel */
423 dsi->pixel_scaler_mul = 2;
424 dsi->pixel_scaler_div = 1;
426 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
427 /* 2.25 bytes per pixel */
428 dsi->pixel_scaler_mul = 9;
429 dsi->pixel_scaler_div = 4;
431 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
432 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
433 /* 3 bytes per pixel */
434 dsi->pixel_scaler_mul = 3;
435 dsi->pixel_scaler_div = 1;
441 dsi->controller_index = dc->ndev->id;
443 dsi->enabled = false;
444 dsi->clk_ref = false;
446 dsi->dsi_control_val =
447 DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
448 DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
449 DSI_CONTROL_VID_SOURCE(dsi->controller_index) |
450 DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
452 /* Below we are going to calculate dsi and dc clock rate.
453 * Calcuate the horizontal and vertical width.
455 h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
456 dc->mode.h_sync_width + dc->mode.h_active;
457 v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
458 dc->mode.v_sync_width + dc->mode.v_active;
460 /* Calculate minimum required pixel rate. */
461 pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
463 /* Calculate minimum byte rate on DSI interface. */
464 byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
465 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
467 /* Round up to multiple of mega hz. */
468 plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
471 /* Calculate default real shift_clk_div. */
472 dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
473 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
474 dsi->info.n_data_lanes);
475 /* Calculate default DSI hs clock. DSI interface is double data rate.
476 * Data is transferred on both rising and falling edge of clk, div by 2
477 * to get the actual clock rate.
479 dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
480 dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
481 / dsi->default_shift_clk_div;
483 /* Get the actual shift_clk_div and clock rates. */
484 dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
485 dsi->target_lp_clk_khz =
486 tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
487 dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
489 dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
490 dsi->target_hs_clk_khz);
492 dsi->controller_index = dc->ndev->id;
494 #if DSI_USE_SYNC_POINTS
495 dsi->syncpt_id = NVSYNCPT_DSI;
499 * Force video clock to be continuous mode if
500 * enable_hs_clock_on_lp_cmd_mode is set
502 if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
503 if (dsi->info.video_clock_mode !=
504 TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
505 dev_warn(&dc->ndev->dev,
506 "Force clock continuous mode\n");
508 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
513 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns) ( \
514 (platform_t_phy_ns) ? ( \
515 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns)) < 0 ? 0 : \
516 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns)))) : \
517 ((default_phy) < 0 ? 0 : (default_phy)))
519 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
520 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
522 phy_timing_clk->t_tlpx = SELECT_T_PHY(
523 dsi->info.phy_timing.t_tlpx_ns,
524 T_TLPX_DEFAULT(clk_ns), clk_ns);
526 phy_timing_clk->t_clktrail = SELECT_T_PHY(
527 dsi->info.phy_timing.t_clktrail_ns,
528 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns);
530 phy_timing_clk->t_clkpost = SELECT_T_PHY(
531 dsi->info.phy_timing.t_clkpost_ns,
532 T_CLKPOST_DEFAULT(clk_ns), clk_ns);
534 phy_timing_clk->t_clkzero = SELECT_T_PHY(
535 dsi->info.phy_timing.t_clkzero_ns,
536 T_CLKZERO_DEFAULT(clk_ns), clk_ns);
538 phy_timing_clk->t_clkprepare = SELECT_T_PHY(
539 dsi->info.phy_timing.t_clkprepare_ns,
540 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns);
542 phy_timing_clk->t_clkpre = SELECT_T_PHY(
543 dsi->info.phy_timing.t_clkpre_ns,
544 T_CLKPRE_DEFAULT, clk_ns);
547 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
548 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
550 phy_timing_clk->t_tlpx = SELECT_T_PHY(
551 dsi->info.phy_timing.t_tlpx_ns,
552 T_TLPX_DEFAULT(clk_ns), clk_ns);
554 phy_timing_clk->t_hsdexit = SELECT_T_PHY(
555 dsi->info.phy_timing.t_hsdexit_ns,
556 T_HSEXIT_DEFAULT(clk_ns), clk_ns);
558 phy_timing_clk->t_hstrail = SELECT_T_PHY(
559 dsi->info.phy_timing.t_hstrail_ns,
560 T_HSTRAIL_DEFAULT(clk_ns), clk_ns);
562 phy_timing_clk->t_datzero = SELECT_T_PHY(
563 dsi->info.phy_timing.t_datzero_ns,
564 T_DATZERO_DEFAULT(clk_ns), clk_ns);
566 phy_timing_clk->t_hsprepare = SELECT_T_PHY(
567 dsi->info.phy_timing.t_hsprepare_ns,
568 T_HSPREPARE_DEFAULT(clk_ns), clk_ns);
571 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
572 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
574 phy_timing_clk->t_tlpx = SELECT_T_PHY(
575 dsi->info.phy_timing.t_tlpx_ns,
576 T_TLPX_DEFAULT(clk_ns), clk_ns);
579 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
580 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
582 phy_timing_clk->t_tlpx = SELECT_T_PHY(
583 dsi->info.phy_timing.t_tlpx_ns,
584 T_TLPX_DEFAULT(clk_ns), clk_ns);
586 phy_timing_clk->t_taget = SELECT_T_PHY(
587 dsi->info.phy_timing.t_taget_ns,
588 T_TAGET_DEFAULT(clk_ns), clk_ns);
590 phy_timing_clk->t_tasure = SELECT_T_PHY(
591 dsi->info.phy_timing.t_tasure_ns,
592 T_TASURE_DEFAULT(clk_ns), clk_ns);
594 phy_timing_clk->t_tago = SELECT_T_PHY(
595 dsi->info.phy_timing.t_tago_ns,
596 T_TAGO_DEFAULT(clk_ns), clk_ns);
599 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
600 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
602 phy_timing_clk->t_tlpx = SELECT_T_PHY(
603 dsi->info.phy_timing.t_tlpx_ns,
604 T_TLPX_DEFAULT(clk_ns), clk_ns);
606 phy_timing_clk->t_wakeup = SELECT_T_PHY(
607 dsi->info.phy_timing.t_wakeup_ns,
608 T_WAKEUP_DEFAULT, clk_ns);
613 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
614 struct dsi_phy_timing_inclk *phy_timing_clk,
617 if (lphs == DSI_LPHS_IN_HS_MODE) {
618 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
619 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
621 /* default is LP mode */
622 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
623 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
624 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
625 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
626 tegra_dsi_get_clk_phy_timing
627 (dsi, phy_timing_clk, clk_ns);
631 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
632 struct dsi_phy_timing_inclk *phy_timing,
635 #define CHECK_RANGE(val, min, max) ( \
636 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
637 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
642 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_tlpx, clk_ns),
643 MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
645 dev_warn(&dsi->dc->ndev->dev,
646 "dsi: Tlpx mipi range violated\n");
650 if (lphs == DSI_LPHS_IN_HS_MODE) {
652 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hsdexit, clk_ns),
653 MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
655 dev_warn(&dsi->dc->ndev->dev,
656 "dsi: HsExit mipi range violated\n");
661 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hstrail, clk_ns),
662 MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
664 dev_warn(&dsi->dc->ndev->dev,
665 "dsi: HsTrail mipi range violated\n");
670 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_datzero, clk_ns),
671 MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
673 dev_warn(&dsi->dc->ndev->dev,
674 "dsi: HsZero mipi range violated\n");
679 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hsprepare, clk_ns),
680 MIPI_T_HSPREPARE_NS_MIN(clk_ns),
681 MIPI_T_HSPREPARE_NS_MAX(clk_ns));
683 dev_warn(&dsi->dc->ndev->dev,
684 "dsi: HsPrepare mipi range violated\n");
689 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
690 phy_timing->t_hsprepare, clk_ns) +
691 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_datzero, clk_ns),
692 MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
693 MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
695 dev_warn(&dsi->dc->ndev->dev,
696 "dsi: HsPrepare + HsZero mipi range violated\n");
700 /* default is LP mode */
702 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_wakeup, clk_ns),
703 MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
705 dev_warn(&dsi->dc->ndev->dev,
706 "dsi: WakeUp mipi range violated\n");
711 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_tasure, clk_ns),
712 MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
713 phy_timing->t_tlpx, clk_ns)),
714 MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
715 phy_timing->t_tlpx, clk_ns)));
717 dev_warn(&dsi->dc->ndev->dev,
718 "dsi: TaSure mipi range violated\n");
723 if (lphs == DSI_LPHS_IN_HS_MODE ||
724 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
726 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clktrail, clk_ns),
727 MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
729 dev_warn(&dsi->dc->ndev->dev,
730 "dsi: ClkTrail mipi range violated\n");
735 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkpost, clk_ns),
736 MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
738 dev_warn(&dsi->dc->ndev->dev,
739 "dsi: ClkPost mipi range violated\n");
744 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkzero, clk_ns),
745 MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
747 dev_warn(&dsi->dc->ndev->dev,
748 "dsi: ClkZero mipi range violated\n");
753 DSI_CONVERT_T_PHY_TO_T_PHY_NS
754 (phy_timing->t_clkprepare, clk_ns),
755 MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
757 dev_warn(&dsi->dc->ndev->dev,
758 "dsi: ClkPrepare mipi range violated\n");
763 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkpre, clk_ns),
764 MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
766 dev_warn(&dsi->dc->ndev->dev,
767 "dsi: ClkPre mipi range violated\n");
772 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
773 phy_timing->t_clkprepare, clk_ns) +
774 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkzero, clk_ns),
775 MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
776 MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
778 dev_warn(&dsi->dc->ndev->dev,
779 "dsi: ClkPrepare + ClkZero mipi range violated\n");
788 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
789 struct dsi_phy_timing_inclk *phy_timing,
794 err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
796 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
800 /* TODO: add more contraints */
805 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
808 struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
810 tegra_dsi_get_phy_timing
811 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
813 tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
814 dsi->current_bit_clk_ns, lphs);
816 val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
817 DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
818 DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
819 DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
820 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
822 val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
823 DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
824 DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
825 DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
826 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
828 val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
829 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
830 DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
831 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
833 val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
834 DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
835 DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
836 tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
838 dsi->phy_timing = phy_timing;
841 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
842 struct tegra_dc_dsi_data *dsi)
844 u32 dsi_to_pixel_clk_ratio;
847 u32 mipi_clk_adj_kHz;
849 struct tegra_dc_mode *dc_modes = &dc->mode;
851 /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
852 dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
853 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
855 /* Convert Fdsi to byte format */
856 dsi_to_pixel_clk_ratio *= 1000/8;
858 /* Multiplying by 1000 so that we don't loose the fraction part */
859 temp = dc_modes->h_active * 1000;
860 temp1 = dc_modes->h_active + dc_modes->h_back_porch +
861 dc_modes->h_sync_width;
863 sol_delay = temp1 * dsi_to_pixel_clk_ratio -
864 temp * dsi->pixel_scaler_mul /
865 (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
867 /* Do rounding on sol delay */
868 sol_delay = (sol_delay + 1000 - 1)/1000;
871 * 1. find out the correct sol fifo depth to use
872 * 2. verify with hw about the clamping function
874 if (sol_delay > (480 * 4)) {
875 sol_delay = (480 * 4);
876 mipi_clk_adj_kHz = sol_delay +
877 (dc_modes->h_active * dsi->pixel_scaler_mul) /
878 (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
880 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
882 mipi_clk_adj_kHz *= 4;
885 dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
890 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
891 struct tegra_dc_dsi_data *dsi)
895 if (dsi->info.video_burst_mode == TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
896 dsi->info.video_burst_mode ==
897 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
898 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
899 sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
900 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
901 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
902 dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
904 sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
905 dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
908 tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
912 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
918 /* TODO: verify the following equation */
919 bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
920 (dsi->info.refresh_rate * 8);
921 timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
922 timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
924 val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
925 DSI_TIMEOUT_0_HTX_TO(timeout);
926 tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
928 if (dsi->info.panel_reset_timeout_msec)
929 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
930 / dsi->current_bit_clk_ns;
932 timeout = DSI_PR_TO_VALUE;
934 val = DSI_TIMEOUT_1_PR_TO(timeout) |
935 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
936 tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
938 val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
939 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
940 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
941 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
942 tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
945 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
946 struct tegra_dc_dsi_data *dsi)
954 hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
955 dsi->pixel_scaler_div;
956 hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
957 dsi->pixel_scaler_div;
958 hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
959 dsi->pixel_scaler_div;
960 hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
961 dsi->pixel_scaler_div;
963 if (dsi->info.video_burst_mode !=
964 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
965 hbp_pkt_len += hsa_pkt_len;
967 hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
968 hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
969 hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
971 val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
972 DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
973 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
975 val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
976 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
977 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
979 val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
980 DSI_PKT_LEN_4_5_LENGTH_5(0);
981 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
983 val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
984 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
987 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
988 struct tegra_dc_dsi_data *dsi)
991 unsigned long act_bytes;
993 act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
994 dsi->pixel_scaler_div + 1;
996 val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
997 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
999 val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1000 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1002 val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1003 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1005 val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1006 tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1009 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1010 struct tegra_dc_dsi_data *dsi)
1012 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1015 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
1016 tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1018 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1021 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1022 struct tegra_dc_dsi_data *dsi)
1026 u32 pkt_seq_3_5_rgb_lo;
1027 u32 pkt_seq_3_5_rgb_hi;
1032 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1035 switch (dsi->info.pixel_format) {
1036 case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1037 rgb_info = CMD_RGB_16BPP;
1039 case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1040 rgb_info = CMD_RGB_18BPP;
1042 case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1043 rgb_info = CMD_RGB_18BPPNP;
1045 case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1047 rgb_info = CMD_RGB_24BPP;
1051 pkt_seq_3_5_rgb_lo = 0;
1052 pkt_seq_3_5_rgb_hi = 0;
1053 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1054 pkt_seq = dsi_pkt_seq_cmd_mode;
1056 switch (dsi->info.video_burst_mode) {
1057 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1058 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1059 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1060 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1061 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1062 pkt_seq_3_5_rgb_lo =
1063 DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1064 if (!dsi->info.no_pkt_seq_eot)
1065 pkt_seq = dsi_pkt_seq_video_burst;
1067 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1069 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1070 pkt_seq_3_5_rgb_hi =
1071 DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1072 pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1074 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1076 pkt_seq_3_5_rgb_lo =
1077 DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1078 pkt_seq = dsi_pkt_seq_video_non_burst;
1083 for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1085 reg = dsi_pkt_seq_reg[i];
1086 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1087 val |= pkt_seq_3_5_rgb_lo;
1088 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1089 val |= pkt_seq_3_5_rgb_hi;
1090 tegra_dsi_writel(dsi, val, reg);
1094 static void tegra_dsi_reset_underflow_overflow
1095 (struct tegra_dc_dsi_data *dsi)
1099 val = tegra_dsi_readl(dsi, DSI_STATUS);
1100 val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1102 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1103 dev_warn(&dsi->dc->ndev->dev,
1104 "dsi: video fifo overflow. Resetting flag\n");
1105 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1106 dev_warn(&dsi->dc->ndev->dev,
1107 "dsi: video fifo underflow. Resetting flag\n");
1108 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1109 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1110 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1115 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1116 struct tegra_dc_dsi_data *dsi)
1118 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1119 tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1120 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1121 tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1123 dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1126 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1127 struct tegra_dc_dsi_data *dsi)
1131 u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1134 tegra_dsi_stop_dc_stream(dc, dsi);
1136 /* enable frame end interrupt */
1137 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1138 val |= FRAME_END_INT;
1139 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1141 /* wait for frame_end completion.
1142 * timeout is 2 frame duration to accomodate for
1145 timeout = wait_for_completion_interruptible_timeout(
1146 &dc->frame_end_complete,
1147 msecs_to_jiffies(2 * frame_period));
1149 /* disable frame end interrupt */
1150 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1151 val &= ~FRAME_END_INT;
1152 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1155 dev_warn(&dc->ndev->dev,
1156 "DC doesn't stop at end of frame.\n");
1158 tegra_dsi_reset_underflow_overflow(dsi);
1161 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1162 struct tegra_dc_dsi_data *dsi)
1166 tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1168 /* TODO: clean up */
1169 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1170 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1171 DC_CMD_DISPLAY_POWER_CONTROL);
1173 /* Configure one-shot mode or continuous mode */
1174 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1175 /* disable LSPI/LCD_DE output */
1176 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1177 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1179 /* enable MSF & set MSF polarity */
1180 val = MSF_ENABLE | MSF_LSPI;
1181 if (!dsi->info.te_polarity_low)
1182 val |= MSF_POLARITY_HIGH;
1184 val |= MSF_POLARITY_LOW;
1185 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1187 /* set non-continuous mode */
1188 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1189 DC_CMD_DISPLAY_COMMAND);
1190 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1191 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1192 DC_CMD_STATE_CONTROL);
1194 /* set continuous mode */
1195 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1196 DC_CMD_DISPLAY_COMMAND);
1197 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1198 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1201 dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1204 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1205 struct tegra_dc_dsi_data *dsi)
1207 u32 shift_clk_div_register;
1210 /* Get the corresponding register value of shift_clk_div. */
1211 shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1213 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1214 shift_clk_div_register = 1;
1217 /* TODO: find out if PCD3 option is required */
1218 val = PIXEL_CLK_DIVIDER_PCD1 |
1219 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1220 tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1223 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1224 struct tegra_dc_dsi_data *dsi, u32 clk)
1228 /* Round up to MHz */
1233 /* Set up pixel clock */
1234 dc->shift_clk_div = dsi->shift_clk_div;
1235 dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1236 /* TODO: Define one shot work delay in board file. */
1237 /* Since for one-shot mode, refresh rate is usually set larger than
1238 * expected refresh rate, it needs at least 3 frame period. Less
1239 * delay one shot work is, more powering saving we have. */
1240 dc->one_shot_delay_ms = 4 *
1241 DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1243 /* Enable DSI clock */
1244 tegra_dc_setup_clk(dc, dsi->dsi_clk);
1245 if (!dsi->clk_ref) {
1246 dsi->clk_ref = true;
1247 clk_enable(dsi->dsi_clk);
1248 tegra_periph_reset_deassert(dsi->dsi_clk);
1250 dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1251 dsi->current_bit_clk_ns = 1000*1000 / (dsi->current_dsi_clk_khz * 2);
1254 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1258 val = tegra_dsi_readl(dsi, DSI_CONTROL);
1259 val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1261 if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1262 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1263 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1265 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1266 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1268 tegra_dsi_writel(dsi, val, DSI_CONTROL);
1270 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1271 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1272 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1273 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1275 dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1278 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1281 tegra_dsi_hs_clk_out_enable(dsi);
1283 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1284 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1285 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1286 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1289 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1290 struct tegra_dc_dsi_data *dsi)
1294 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1295 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1297 tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1298 /* stabilization delay */
1301 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1302 val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1303 val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1304 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1306 tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1307 /* stabilization delay */
1310 dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1311 dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1314 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1317 u32 host_dsi_control;
1320 dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1321 host_dsi_control = HOST_DSI_CTRL_COMMON |
1322 HOST_DSI_CTRL_HOST_DRIVEN |
1323 DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1324 max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1326 tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1327 tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1328 tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1330 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1331 dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1332 dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1335 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1338 u32 host_dsi_control;
1342 dsi_control = dsi->dsi_control_val;
1343 host_dsi_control = HOST_DSI_CTRL_COMMON;
1347 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1348 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1349 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1351 DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1352 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1354 dsi_control |= DSI_CTRL_DC_DRIVEN;
1355 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1357 DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1358 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1361 if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1362 dsi_control |= DSI_CTRL_CMD_MODE;
1363 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1364 DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1365 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1368 dsi_control |= DSI_CTRL_VIDEO_MODE;
1369 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1372 tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1373 tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1374 tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1375 tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1378 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1382 val = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1383 DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1384 DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1385 DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1386 DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1388 val |= DSI_PAD_CONTROL_PAD_PDIO(0) |
1389 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
1390 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE);
1392 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1393 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1394 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
1396 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1398 val = MIPI_CAL_TERMOSA(0x4);
1399 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1401 val = MIPI_CAL_TERMOSB(0x4);
1402 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1404 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1405 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1407 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1408 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1410 val = PAD_CIL_PDVREG(0x0);
1411 tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1414 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1415 struct tegra_dc_dsi_data *dsi)
1419 tegra_dsi_writel(dsi,
1420 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1422 /* stabilization delay */
1425 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1426 if (dsi->info.dsi_instance) {
1427 /* TODO:Set the misc register*/
1430 /* TODO: only need to change the timing for bta */
1431 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1433 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1434 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1436 /* Initializing DSI registers */
1437 for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1438 tegra_dsi_writel(dsi, 0, init_reg[i]);
1440 tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1442 tegra_dsi_pad_calibration(dsi);
1444 tegra_dsi_writel(dsi,
1445 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1447 /* stabilization delay */
1450 dsi->status.init = DSI_MODULE_INIT;
1451 dsi->status.lphs = DSI_LPHS_NOT_INIT;
1452 dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1453 dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1454 dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1455 dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1456 dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1457 dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1458 dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1463 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1464 struct tegra_dc_dsi_data *dsi, u8 lp_op)
1468 if (dsi->status.init != DSI_MODULE_INIT) {
1473 if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1474 dsi->status.lp_op == lp_op)
1477 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1478 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1480 /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1481 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1482 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1483 tegra_dsi_hs_clk_out_disable(dc, dsi);
1485 dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1486 if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1487 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1488 tegra_dsi_set_timeout(dsi);
1491 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1493 tegra_dsi_set_control_reg_lp(dsi);
1495 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1496 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1497 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1499 dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1500 dsi->status.lp_op = lp_op;
1507 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1508 struct tegra_dc_dsi_data *dsi)
1512 if (dsi->status.init != DSI_MODULE_INIT) {
1517 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
1520 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1521 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1523 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1524 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1525 tegra_dsi_hs_clk_out_disable(dc, dsi);
1527 if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
1528 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
1529 tegra_dsi_set_timeout(dsi);
1532 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1534 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1535 tegra_dsi_set_pkt_seq(dc, dsi);
1536 tegra_dsi_set_pkt_length(dc, dsi);
1537 tegra_dsi_set_sol_delay(dc, dsi);
1538 tegra_dsi_set_dc_clk(dc, dsi);
1541 tegra_dsi_set_control_reg_hs(dsi);
1543 if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
1544 dsi->info.enable_hs_clock_on_lp_cmd_mode)
1545 tegra_dsi_hs_clk_out_enable(dsi);
1547 dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
1549 dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1555 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1560 while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1561 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1562 tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1566 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
1567 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
1573 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1578 while (timeout < DSI_STATUS_POLLING_DURATION_USEC) {
1579 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1580 tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1584 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1585 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1591 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1595 if (tegra_dsi_write_busy(dsi)) {
1597 dev_err(&dsi->dc->ndev->dev,
1598 "DSI trigger bit already set\n");
1602 if (tegra_dsi_read_busy(dsi)) {
1604 dev_err(&dsi->dc->ndev->dev,
1605 "DSI immediate bta bit already set\n");
1609 return (err < 0 ? true : false);
1612 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1614 tegra_dsi_writel(dsi,
1615 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1617 /* stabilization delay */
1620 tegra_dsi_writel(dsi,
1621 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1623 /* stabilization delay */
1627 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1631 val = tegra_dsi_readl(dsi, DSI_STATUS);
1632 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1634 dev_warn(&dsi->dc->ndev->dev,
1635 "DSI read count not zero, resetting\n");
1636 tegra_dsi_soft_reset(dsi);
1640 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1641 struct tegra_dc_dsi_data *dsi,
1642 struct tegra_dc *dc,
1645 struct dsi_status *init_status;
1648 init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1650 return ERR_PTR(-ENOMEM);
1652 *init_status = dsi->status;
1654 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1655 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1656 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1657 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1658 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1659 if (dsi->info.hs_cmd_mode_supported) {
1660 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1662 dev_err(&dc->ndev->dev,
1663 "Switch to HS host mode failed\n");
1668 if (!dsi->info.hs_cmd_mode_supported) {
1670 tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1672 dev_err(&dc->ndev->dev,
1673 "DSI failed to go to LP mode\n");
1677 } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1678 if (dsi->status.lp_op != lp_op) {
1679 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1681 dev_err(&dc->ndev->dev,
1682 "DSI failed to go to LP mode\n");
1691 return ERR_PTR(err);
1694 static struct dsi_status *tegra_dsi_prepare_host_transmission(
1695 struct tegra_dc *dc,
1696 struct tegra_dc_dsi_data *dsi,
1700 struct dsi_status *init_status;
1702 if (dsi->status.init != DSI_MODULE_INIT ||
1708 if (tegra_dsi_host_busy(dsi)) {
1709 tegra_dsi_soft_reset(dsi);
1710 if (tegra_dsi_host_busy(dsi)) {
1712 dev_err(&dc->ndev->dev, "DSI host busy\n");
1717 if (lp_op == DSI_LP_OP_READ)
1718 tegra_dsi_reset_read_count(dsi);
1720 if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1721 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1723 dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1728 init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1730 if (IS_ERR_OR_NULL(init_status)) {
1731 err = PTR_ERR(init_status);
1732 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1738 return ERR_PTR(err);
1741 static int tegra_dsi_restore_state(struct tegra_dc *dc,
1742 struct tegra_dc_dsi_data *dsi,
1743 struct dsi_status *init_status)
1745 bool switch_back_to_dc_mode = false;
1746 bool switch_back_to_hs_mode = false;
1747 bool restart_dc_stream;
1750 switch_back_to_dc_mode = (dsi->status.driven ==
1751 DSI_DRIVEN_MODE_HOST &&
1752 init_status->driven ==
1753 DSI_DRIVEN_MODE_DC);
1754 switch_back_to_hs_mode = (dsi->status.lphs ==
1755 DSI_LPHS_IN_LP_MODE &&
1756 init_status->lphs ==
1757 DSI_LPHS_IN_HS_MODE);
1758 restart_dc_stream = (dsi->status.dc_stream ==
1759 DSI_DC_STREAM_DISABLE &&
1760 init_status->dc_stream ==
1761 DSI_DC_STREAM_ENABLE);
1763 if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1764 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1765 if (dsi->status.lp_op != init_status->lp_op) {
1767 tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1769 dev_err(&dc->ndev->dev,
1770 "Failed to config LP mode\n");
1777 if (switch_back_to_dc_mode)
1778 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1779 if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1780 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1782 dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1786 if (restart_dc_stream)
1787 tegra_dsi_start_dc_stream(dc, dsi);
1795 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1799 if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
1804 tegra_dsi_writel(dsi,
1805 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
1807 #if DSI_USE_SYNC_POINTS
1808 status = tegra_dsi_syncpt(dsi);
1810 dev_err(&dsi->dc->ndev->dev,
1811 "DSI syncpt for host trigger failed\n");
1815 if (tegra_dsi_write_busy(dsi)) {
1817 dev_err(&dsi->dc->ndev->dev,
1818 "Timeout waiting on write completion\n");
1826 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1827 u8 *pdata, u8 data_id, u16 data_len)
1836 virtual_channel = dsi->info.virtual_channel <<
1837 DSI_VIR_CHANNEL_BIT_POSITION;
1839 /* always use hw for ecc */
1840 val = (virtual_channel | data_id) << 0 |
1842 tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1844 /* if pdata != NULL, pkt type is long pkt */
1845 if (pdata != NULL) {
1847 if (data_len >= 4) {
1848 val = ((u32 *) pdata)[0];
1858 tegra_dsi_writel(dsi, val, DSI_WR_DATA);
1862 err = tegra_dsi_host_trigger(dsi);
1864 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1869 int tegra_dsi_write_data(struct tegra_dc *dc,
1870 struct tegra_dc_dsi_data *dsi,
1871 u8 *pdata, u8 data_id, u16 data_len)
1874 struct dsi_status *init_status;
1876 tegra_dc_io_start(dc);
1878 init_status = tegra_dsi_prepare_host_transmission(
1879 dc, dsi, DSI_LP_OP_WRITE);
1880 if (IS_ERR_OR_NULL(init_status)) {
1881 err = PTR_ERR(init_status);
1882 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1886 err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1888 err = tegra_dsi_restore_state(dc, dsi, init_status);
1890 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1891 tegra_dc_io_end(dc);
1894 EXPORT_SYMBOL(tegra_dsi_write_data);
1896 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
1897 struct tegra_dc_dsi_data *dsi,
1898 struct tegra_dsi_cmd *cmd,
1905 for (i = 0; i < n_cmd; i++) {
1906 struct tegra_dsi_cmd *cur_cmd;
1909 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
1910 mdelay(cur_cmd->sp_len_dly.delay_ms);
1912 err = tegra_dsi_write_data(dc, dsi,
1915 cur_cmd->sp_len_dly.data_len);
1923 static u8 get_8bit_ecc(u32 header)
1925 char ecc_parity[24] = {
1926 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
1927 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
1928 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
1934 for (i = 0; i < 24; i++)
1935 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
1940 /* This function is written to send DCS short write (1 parameter) only.
1941 * This means the cmd will contain only 1 byte of index and 1 byte of value.
1942 * The data type ID is fixed at 0x15 and the ECC is calculated based on the
1944 * The command will be sent by hardware every frame.
1945 * pdata should contain both the index + value for each cmd.
1946 * data_len will be the total number of bytes in pdata.
1948 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len)
1950 u8 ecc8bits = 0, data_len_orig = 0;
1951 u32 val = 0, pkthdr = 0;
1952 int err = 0, count = 0;
1953 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
1955 data_len_orig = data_len;
1956 if (pdata != NULL) {
1958 if (data_len >= 2) {
1959 pkthdr = (CMD_SHORTW |
1960 (((u16 *)pdata)[0]) << 8 | 0x00 << 24);
1961 ecc8bits = get_8bit_ecc(pkthdr);
1962 val = (pkthdr | (ecc8bits << 24));
1969 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0);
1972 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_1);
1975 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_2);
1978 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_3);
1981 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_4);
1984 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_5);
1987 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_6);
1990 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_7);
1999 val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(data_len_orig * 2)
2000 | DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(1);
2001 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2005 EXPORT_SYMBOL(tegra_dsi_send_panel_short_cmd);
2007 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2016 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2017 val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2018 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2020 #if DSI_USE_SYNC_POINTS
2021 /* FIXME: Workaround for nvhost_syncpt_read */
2022 dsi->syncpt_val = nvhost_syncpt_update_min(
2023 &nvhost_get_host(dsi->dc->ndev)->syncpt,
2026 val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2027 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2028 tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2030 /* TODO: Use interrupt rather than polling */
2031 err = nvhost_syncpt_wait(&nvhost_get_host(dsi->dc->ndev)->syncpt,
2032 dsi->syncpt_id, dsi->syncpt_val + 1);
2034 dev_err(&dsi->dc->ndev->dev,
2035 "DSI sync point failure\n");
2037 (dsi->syncpt_val)++;
2039 if (tegra_dsi_read_busy(dsi)) {
2041 dev_err(&dsi->dc->ndev->dev,
2042 "Timeout wating on read completion\n");
2049 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2050 u32 rd_fifo_cnt, u8 *read_fifo)
2058 switch (read_fifo[0]) {
2059 case DSI_ESCAPE_CMD:
2060 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2062 case DSI_ACK_NO_ERR:
2063 dev_info(&dc->ndev->dev,
2064 "Panel ack, no err[0x%x]\n", read_fifo[0]);
2067 dev_info(&dc->ndev->dev, "Invalid read response\n");
2071 switch (read_fifo[4] & 0xff) {
2072 case GEN_LONG_RD_RES:
2074 case DCS_LONG_RD_RES:
2075 payload_size = (read_fifo[5] |
2076 (read_fifo[6] << 8)) & 0xFFFF;
2077 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2078 "payload_size[0x%x]\n", payload_size);
2080 case GEN_1_BYTE_SHORT_RD_RES:
2082 case DCS_1_BYTE_SHORT_RD_RES:
2084 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2085 "payload_size[0x%x]\n", payload_size);
2087 case GEN_2_BYTE_SHORT_RD_RES:
2089 case DCS_2_BYTE_SHORT_RD_RES:
2091 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2092 "payload_size[0x%x]\n", payload_size);
2096 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2097 "Packet payload_size[0x%x]\n", payload_size);
2100 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2107 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2108 struct tegra_dc_dsi_data *dsi,
2116 u8 *read_fifo_cp = read_fifo;
2118 while (poll_time < DSI_DELAY_FOR_READ_FIFO) {
2120 val = tegra_dsi_readl(dsi, DSI_STATUS);
2121 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2122 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2123 dev_err(&dc->ndev->dev,
2124 "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2129 if (rd_fifo_cnt == 0) {
2130 dev_info(&dc->ndev->dev,
2131 "DSI RD_FIFO_CNT is zero\n");
2136 if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2137 DSI_STATUS_LB_OVERFLOW(0x1))) {
2138 dev_warn(&dc->ndev->dev,
2139 "DSI overflow/underflow error\n");
2142 /* Read data from FIFO */
2143 for (i = 0; i < rd_fifo_cnt; i++) {
2144 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2145 if (enable_read_debug)
2146 dev_info(&dc->ndev->dev,
2147 "Read data[%d]: 0x%x\n", i, val);
2148 memcpy(read_fifo, &val, 4);
2152 /* Make sure all the data is read from the FIFO */
2153 val = tegra_dsi_readl(dsi, DSI_STATUS);
2154 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2156 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2157 " even after reading FIFO_RD_CNT words from read fifo\n");
2159 if (enable_read_debug) {
2161 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2163 dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2169 int tegra_dsi_read_data(struct tegra_dc *dc,
2170 struct tegra_dc_dsi_data *dsi,
2171 u32 max_ret_payload_size,
2172 u32 panel_reg_addr, u8 *read_data)
2175 struct dsi_status *init_status;
2177 tegra_dc_io_start(dc);
2179 init_status = tegra_dsi_prepare_host_transmission(
2180 dc, dsi, DSI_LP_OP_WRITE);
2181 if (IS_ERR_OR_NULL(init_status)) {
2182 err = PTR_ERR(init_status);
2183 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2187 /* Set max return payload size in words */
2188 err = _tegra_dsi_write_data(dsi, NULL,
2189 dsi_command_max_return_pkt_size,
2190 max_ret_payload_size);
2192 dev_err(&dc->ndev->dev,
2193 "DSI write failed\n");
2197 /* DCS to read given panel register */
2198 err = _tegra_dsi_write_data(dsi, NULL,
2199 dsi_command_dcs_read_with_no_params,
2202 dev_err(&dc->ndev->dev,
2203 "DSI write failed\n");
2207 tegra_dsi_reset_read_count(dsi);
2209 if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2210 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2212 dev_err(&dc->ndev->dev,
2213 "DSI failed to go to LP read mode\n");
2218 err = tegra_dsi_bta(dsi);
2220 dev_err(&dc->ndev->dev,
2221 "DSI IMM BTA timeout\n");
2225 err = tegra_dsi_read_fifo(dc, dsi, read_data);
2227 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2231 err = tegra_dsi_restore_state(dc, dsi, init_status);
2233 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2234 tegra_dc_io_end(dc);
2237 EXPORT_SYMBOL(tegra_dsi_read_data);
2239 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2240 struct tegra_dc_dsi_data *dsi)
2243 u8 read_fifo[DSI_READ_FIFO_DEPTH];
2244 struct dsi_status *init_status;
2245 static struct tegra_dsi_cmd dsi_nop_cmd =
2246 DSI_CMD_SHORT(0x05, 0x0, 0x0);
2248 tegra_dc_io_start(dc);
2250 init_status = tegra_dsi_prepare_host_transmission(
2251 dc, dsi, DSI_LP_OP_WRITE);
2252 if (IS_ERR_OR_NULL(init_status)) {
2253 err = PTR_ERR(init_status);
2254 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2258 err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2260 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2264 tegra_dsi_reset_read_count(dsi);
2266 if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2267 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2269 dev_err(&dc->ndev->dev,
2270 "DSI failed to go to LP read mode\n");
2275 err = tegra_dsi_bta(dsi);
2277 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2281 err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2283 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2287 if (read_fifo[0] != DSI_ACK_NO_ERR) {
2288 dev_warn(&dc->ndev->dev,
2289 "Ack no error trigger message not received\n");
2293 err = tegra_dsi_restore_state(dc, dsi, init_status);
2295 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2296 tegra_dc_io_end(dc);
2299 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2301 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2308 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2309 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2310 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2311 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2313 #if DSI_USE_SYNC_POINTS
2314 ret = tegra_dsi_syncpt(dsi);
2316 dev_err(&dsi->dc->ndev->dev,
2317 "DSI syncpt for ulpm enter failed\n");
2321 /* TODO: Find exact delay required */
2329 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
2336 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2337 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2338 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
2339 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2341 #if DSI_USE_SYNC_POINTS
2342 ret = tegra_dsi_syncpt(dsi);
2344 dev_err(&dsi->dc->ndev->dev,
2345 "DSI syncpt for ulpm exit failed\n");
2349 /* TODO: Find exact delay required */
2354 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2355 val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
2356 val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
2357 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2363 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
2365 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2369 tegra_dc_io_start(dc);
2370 mutex_lock(&dsi->lock);
2372 /* Stop DC stream before configuring DSI registers
2373 * to avoid visible glitches on panel during transition
2374 * from bootloader to kernel driver
2376 tegra_dsi_stop_dc_stream(dc, dsi);
2380 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2381 dev_err(&dc->ndev->dev,
2382 "DSI failed to exit ulpm\n");
2387 if (dsi->info.panel_reset) {
2388 err = tegra_dsi_send_panel_cmd(dc, dsi,
2389 dsi->info.dsi_init_cmd,
2390 dsi->info.n_init_cmd);
2392 dev_err(&dc->ndev->dev,
2393 "dsi: error sending dsi init cmd\n");
2396 } else if (dsi->info.dsi_late_resume_cmd) {
2397 err = tegra_dsi_send_panel_cmd(dc, dsi,
2398 dsi->info.dsi_late_resume_cmd,
2399 dsi->info.n_late_resume_cmd);
2401 dev_err(&dc->ndev->dev,
2402 "dsi: error sending late resume cmd\n");
2407 err = tegra_dsi_init_hw(dc, dsi);
2409 dev_err(&dc->ndev->dev,
2410 "dsi: not able to init dsi hardware\n");
2415 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2416 dev_err(&dc->ndev->dev,
2417 "DSI failed to enter ulpm\n");
2420 val = DSI_PAD_CONTROL_PAD_PDIO(0) |
2421 DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
2422 DSI_PAD_CONTROL_PAD_PULLDN_ENAB
2423 (TEGRA_DSI_DISABLE);
2424 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2425 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2426 dev_err(&dc->ndev->dev,
2427 "DSI failed to exit ulpm\n");
2432 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2434 dev_err(&dc->ndev->dev,
2435 "dsi: not able to set to lp mode\n");
2439 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
2440 dsi->info.n_init_cmd);
2442 dev_err(&dc->ndev->dev,
2443 "dsi: error while sending dsi init cmd\n");
2447 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2449 dev_err(&dc->ndev->dev,
2450 "dsi: not able to set to hs mode\n");
2454 dsi->enabled = true;
2457 if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
2458 tegra_dsi_start_dc_stream(dc, dsi);
2460 mutex_unlock(&dsi->lock);
2461 tegra_dc_io_end(dc);
2464 static void _tegra_dc_dsi_init(struct tegra_dc *dc)
2466 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2468 tegra_dsi_init_sw(dc, dsi);
2469 /* TODO: Configure the CSI pad configuration */
2472 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
2473 struct tegra_dsi_cmd *dst, u16 n_cmd)
2478 memcpy(dst, src, sizeof(*dst) * n_cmd);
2480 for (i = 0; i < n_cmd; i++)
2482 len = sizeof(*src[i].pdata) *
2483 src[i].sp_len_dly.data_len;
2484 dst[i].pdata = kzalloc(len, GFP_KERNEL);
2486 goto free_cmd_pdata;
2487 memcpy(dst[i].pdata, src[i].pdata, len);
2493 for (--i; i >= 0; i--)
2495 kfree(dst[i].pdata);
2499 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2500 struct tegra_dsi_out *p_dsi)
2502 struct tegra_dsi_cmd *p_init_cmd;
2503 struct tegra_dsi_cmd *p_early_suspend_cmd;
2504 struct tegra_dsi_cmd *p_late_resume_cmd;
2505 struct tegra_dsi_cmd *p_suspend_cmd;
2508 if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
2511 p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
2512 p_dsi->n_init_cmd, GFP_KERNEL);
2516 if (p_dsi->dsi_early_suspend_cmd) {
2517 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
2518 p_dsi->n_early_suspend_cmd,
2520 if (!p_early_suspend_cmd) {
2522 goto err_free_init_cmd;
2526 if (p_dsi->dsi_late_resume_cmd) {
2527 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
2528 p_dsi->n_late_resume_cmd,
2530 if (!p_late_resume_cmd) {
2532 goto err_free_p_early_suspend_cmd;
2536 p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
2538 if (!p_suspend_cmd) {
2540 goto err_free_p_late_resume_cmd;
2543 memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
2545 /* Copy panel init cmd */
2546 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
2547 p_init_cmd, p_dsi->n_init_cmd);
2550 dsi->info.dsi_init_cmd = p_init_cmd;
2552 /* Copy panel early suspend cmd */
2553 if (p_dsi->dsi_early_suspend_cmd) {
2554 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
2555 p_early_suspend_cmd,
2556 p_dsi->n_early_suspend_cmd);
2559 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
2562 /* Copy panel late resume cmd */
2563 if (p_dsi->dsi_late_resume_cmd) {
2564 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
2566 p_dsi->n_late_resume_cmd);
2569 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
2572 /* Copy panel suspend cmd */
2573 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
2574 p_dsi->n_suspend_cmd);
2577 dsi->info.dsi_suspend_cmd = p_suspend_cmd;
2579 if (!dsi->info.panel_reset_timeout_msec)
2580 dsi->info.panel_reset_timeout_msec =
2581 DEFAULT_PANEL_RESET_TIMEOUT;
2583 if (!dsi->info.panel_buffer_size_byte)
2584 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
2586 if (!dsi->info.max_panel_freq_khz) {
2587 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
2589 if (dsi->info.video_burst_mode >
2590 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
2591 dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
2592 "is not set for DSI burst mode.\n");
2593 dsi->info.video_burst_mode =
2594 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
2598 if (!dsi->info.lp_cmd_mode_freq_khz)
2599 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2601 if (!dsi->info.chip_id || !dsi->info.chip_rev)
2602 dev_warn(&dsi->dc->ndev->dev,
2603 "DSI: Failed to get chip info\n");
2605 if (!dsi->info.lp_read_cmd_mode_freq_khz)
2606 dsi->info.lp_read_cmd_mode_freq_khz =
2607 dsi->info.lp_cmd_mode_freq_khz;
2609 /* host mode is for testing only */
2610 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2614 kfree(p_suspend_cmd);
2615 err_free_p_late_resume_cmd:
2616 kfree(p_late_resume_cmd);
2617 err_free_p_early_suspend_cmd:
2618 kfree(p_early_suspend_cmd);
2624 static int tegra_dc_dsi_init(struct tegra_dc *dc)
2626 struct tegra_dc_dsi_data *dsi;
2627 struct resource *res;
2628 struct resource *base_res;
2630 struct clk *dc_clk = NULL;
2631 struct clk *dsi_clk = NULL;
2632 struct tegra_dsi_out *dsi_pdata;
2637 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
2641 res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM,
2644 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
2649 base_res = request_mem_region(res->start, resource_size(res),
2652 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
2657 base = ioremap(res->start, resource_size(res));
2659 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
2661 goto err_release_regs;
2664 dsi_pdata = dc->pdata->default_out->dsi;
2666 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
2667 goto err_release_regs;
2670 if (dsi_pdata->dsi_instance)
2671 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
2673 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
2675 if (IS_ERR_OR_NULL(dsi_clk)) {
2676 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
2678 goto err_release_regs;
2681 dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
2682 if (IS_ERR_OR_NULL(dc_clk)) {
2683 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
2684 dev_name(&dc->ndev->dev));
2689 mutex_init(&dsi->lock);
2692 dsi->base_res = base_res;
2693 dsi->dc_clk = dc_clk;
2694 dsi->dsi_clk = dsi_clk;
2696 err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
2700 tegra_dc_set_outdata(dc, dsi);
2701 _tegra_dc_dsi_init(dc);
2709 release_resource(base_res);
2716 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
2718 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2722 mutex_lock(&dsi->lock);
2724 /* free up the pdata */
2725 for (i = 0; i < dsi->info.n_init_cmd; i++) {
2726 if (dsi->info.dsi_init_cmd[i].pdata)
2727 kfree(dsi->info.dsi_init_cmd[i].pdata);
2729 kfree(dsi->info.dsi_init_cmd);
2731 /* Disable dc stream */
2732 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2733 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2735 /* Disable dsi phy clock */
2736 if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
2737 tegra_dsi_hs_clk_out_disable(dc, dsi);
2739 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2740 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2743 release_resource(dsi->base_res);
2745 clk_put(dsi->dc_clk);
2746 clk_put(dsi->dsi_clk);
2748 mutex_unlock(&dsi->lock);
2750 mutex_destroy(&dsi->lock);
2754 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
2755 struct tegra_dc_dsi_data *dsi)
2759 struct clk *parent_clk = NULL;
2760 struct clk *base_clk = NULL;
2762 if (!dsi->enabled) {
2767 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
2769 dev_err(&dc->ndev->dev,
2770 "DSI failed to go to LP mode\n");
2775 err = tegra_dsi_send_panel_cmd(dc, dsi,
2776 dsi->info.dsi_suspend_cmd,
2777 dsi->info.n_suspend_cmd);
2779 dev_err(&dc->ndev->dev,
2780 "dsi: Error sending suspend cmd\n");
2785 err = tegra_dsi_enter_ulpm(dsi);
2787 dev_err(&dc->ndev->dev,
2788 "DSI failed to enter ulpm\n");
2794 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2795 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2796 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2797 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
2798 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2800 /* Suspend core-logic */
2801 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
2802 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
2804 /* Disable dsi fast and slow clock */
2805 parent_clk = clk_get_parent(dsi->dsi_clk);
2806 base_clk = clk_get_parent(parent_clk);
2807 if (dsi->info.dsi_instance)
2808 tegra_clk_cfg_ex(base_clk,
2809 TEGRA_CLK_PLLD_CSI_OUT_ENB,
2812 tegra_clk_cfg_ex(base_clk,
2813 TEGRA_CLK_PLLD_DSI_OUT_ENB,
2816 /* Disable dsi source clock */
2817 clk_disable(dsi->dsi_clk);
2819 dsi->clk_ref = false;
2820 dsi->enabled = false;
2827 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2830 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2832 tegra_dc_io_start(dc);
2833 mutex_lock(&dsi->lock);
2835 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2836 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2838 if (dsi->info.power_saving_suspend) {
2839 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2840 dev_err(&dc->ndev->dev,
2841 "DSI failed to enter deep sleep\n");
2845 if (dsi->info.dsi_early_suspend_cmd) {
2846 err = tegra_dsi_send_panel_cmd(dc, dsi,
2847 dsi->info.dsi_early_suspend_cmd,
2848 dsi->info.n_early_suspend_cmd);
2850 dev_err(&dc->ndev->dev,
2851 "dsi: Error sending early suspend cmd\n");
2857 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2858 dev_err(&dc->ndev->dev,
2859 "DSI failed to enter ulpm\n");
2866 mutex_unlock(&dsi->lock);
2867 tegra_dc_io_end(dc);
2871 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2873 struct tegra_dc_dsi_data *dsi;
2875 dsi = tegra_dc_get_outdata(dc);
2880 tegra_dc_io_start(dc);
2881 mutex_lock(&dsi->lock);
2883 if (!dsi->info.power_saving_suspend) {
2885 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2886 dev_err(&dc->ndev->dev,
2887 "DSI failed to exit ulpm");
2892 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2893 dev_err(&dc->ndev->dev,
2894 "DSI failed to enter deep sleep\n");
2899 mutex_unlock(&dsi->lock);
2900 tegra_dc_io_end(dc);
2903 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
2905 /* Not required since tegra_dc_dsi_enable
2906 * will reconfigure the controller from scratch
2911 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
2912 .init = tegra_dc_dsi_init,
2913 .destroy = tegra_dc_dsi_destroy,
2914 .enable = tegra_dc_dsi_enable,
2915 .disable = tegra_dc_dsi_disable,
2917 .suspend = tegra_dc_dsi_suspend,
2918 .resume = tegra_dc_dsi_resume,