Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/moduleparam.h>
28 #include <linux/export.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/nvhost.h>
32
33 #include <mach/clk.h>
34 #include <mach/dc.h>
35 #include <mach/fb.h>
36 #include <mach/csi.h>
37 #include <mach/iomap.h>
38 #include <linux/nvhost.h>
39
40 #include "dc_reg.h"
41 #include "dc_priv.h"
42 #include "dev.h"
43 #include "dsi_regs.h"
44 #include "dsi.h"
45
46 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
47 #define DSIB_MODE_ENABLE                0x2
48
49 #define DSI_USE_SYNC_POINTS             1
50 #define S_TO_MS(x)                      (1000 * (x))
51
52 #define DSI_MODULE_NOT_INIT             0x0
53 #define DSI_MODULE_INIT                 0x1
54
55 #define DSI_LPHS_NOT_INIT               0x0
56 #define DSI_LPHS_IN_LP_MODE             0x1
57 #define DSI_LPHS_IN_HS_MODE             0x2
58
59 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
60 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
61 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
62
63 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
64 #define DSI_DRIVEN_MODE_DC              0x1
65 #define DSI_DRIVEN_MODE_HOST            0x2
66
67 #define DSI_PHYCLK_OUT_DIS              0x0
68 #define DSI_PHYCLK_OUT_EN               0x1
69
70 #define DSI_PHYCLK_NOT_INIT             0x0
71 #define DSI_PHYCLK_CONTINUOUS           0x1
72 #define DSI_PHYCLK_TX_ONLY              0x2
73
74 #define DSI_CLK_BURST_NOT_INIT          0x0
75 #define DSI_CLK_BURST_NONE_BURST        0x1
76 #define DSI_CLK_BURST_BURST_MODE        0x2
77
78 #define DSI_DC_STREAM_DISABLE           0x0
79 #define DSI_DC_STREAM_ENABLE            0x1
80
81 #define DSI_LP_OP_NOT_INIT              0x0
82 #define DSI_LP_OP_WRITE                 0x1
83 #define DSI_LP_OP_READ                  0x2
84
85 static bool enable_read_debug;
86 module_param(enable_read_debug, bool, 0644);
87 MODULE_PARM_DESC(enable_read_debug,
88                 "Enable to print read fifo and return packet type");
89
90 /* source of video data */
91 enum {
92         TEGRA_DSI_DRIVEN_BY_DC,
93         TEGRA_DSI_DRIVEN_BY_HOST,
94 };
95
96 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
97
98 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
99         DSI_PKT_SEQ_0_LO,
100         DSI_PKT_SEQ_0_HI,
101         DSI_PKT_SEQ_1_LO,
102         DSI_PKT_SEQ_1_HI,
103         DSI_PKT_SEQ_2_LO,
104         DSI_PKT_SEQ_2_HI,
105         DSI_PKT_SEQ_3_LO,
106         DSI_PKT_SEQ_3_HI,
107         DSI_PKT_SEQ_4_LO,
108         DSI_PKT_SEQ_4_HI,
109         DSI_PKT_SEQ_5_LO,
110         DSI_PKT_SEQ_5_HI,
111 };
112
113 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
114         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
115         0,
116         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
117         0,
118         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
119         0,
120         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
121         PKT_ID2(CMD_HE) | PKT_LEN2(0),
122         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
123         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
124         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
125         0,
126         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
127         PKT_ID2(CMD_HE) | PKT_LEN2(0),
128         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
129         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
130 };
131
132 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
133         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
134         0,
135         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
136         0,
137         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
138         0,
139         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
140         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
141         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
142         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
143         0,
144         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
145         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
146         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
147 };
148
149 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
150         PKT_ID0(CMD_VS) | PKT_LEN0(0),
151         0,
152         PKT_ID0(CMD_HS) | PKT_LEN0(0),
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0),
155         0,
156         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
157         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
158         0,
159         PKT_ID0(CMD_HS) | PKT_LEN0(0),
160         0,
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
162         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
163         0,
164 };
165
166 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
167         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
168         0,
169         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
170         0,
171         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
174         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
175         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
177         0,
178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
179         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
180         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
181 };
182
183 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
184         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
185         0,
186         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
189         0,
190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
191         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
192         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(0) | PKT_LP,
194         0,
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
196         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
197         PKT_ID0(CMD_EOT) | PKT_LEN0(0),
198 };
199
200 /* TODO: verify with hw about this format */
201 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
202         0,
203         0,
204         0,
205         0,
206         0,
207         0,
208         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
209         0,
210         0,
211         0,
212         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
213         0,
214 };
215
216 const u32 init_reg[] = {
217         DSI_INT_ENABLE,
218         DSI_INT_STATUS,
219         DSI_INT_MASK,
220         DSI_INIT_SEQ_DATA_0,
221         DSI_INIT_SEQ_DATA_1,
222         DSI_INIT_SEQ_DATA_2,
223         DSI_INIT_SEQ_DATA_3,
224         DSI_INIT_SEQ_DATA_4,
225         DSI_INIT_SEQ_DATA_5,
226         DSI_INIT_SEQ_DATA_6,
227         DSI_INIT_SEQ_DATA_7,
228         DSI_DCS_CMDS,
229         DSI_PKT_SEQ_0_LO,
230         DSI_PKT_SEQ_1_LO,
231         DSI_PKT_SEQ_2_LO,
232         DSI_PKT_SEQ_3_LO,
233         DSI_PKT_SEQ_4_LO,
234         DSI_PKT_SEQ_5_LO,
235         DSI_PKT_SEQ_0_HI,
236         DSI_PKT_SEQ_1_HI,
237         DSI_PKT_SEQ_2_HI,
238         DSI_PKT_SEQ_3_HI,
239         DSI_PKT_SEQ_4_HI,
240         DSI_PKT_SEQ_5_HI,
241         DSI_CONTROL,
242         DSI_HOST_DSI_CONTROL,
243         DSI_PAD_CONTROL,
244         DSI_PAD_CONTROL_CD,
245         DSI_SOL_DELAY,
246         DSI_MAX_THRESHOLD,
247         DSI_TRIGGER,
248         DSI_TX_CRC,
249         DSI_INIT_SEQ_CONTROL,
250         DSI_PKT_LEN_0_1,
251         DSI_PKT_LEN_2_3,
252         DSI_PKT_LEN_4_5,
253         DSI_PKT_LEN_6_7,
254 };
255
256 const u32 init_reg_vs1_ext[] = {
257         DSI_PAD_CONTROL_0_VS1,
258         DSI_PAD_CONTROL_CD_VS1,
259         DSI_PAD_CD_STATUS_VS1,
260         DSI_PAD_CONTROL_1_VS1,
261         DSI_PAD_CONTROL_2_VS1,
262         DSI_PAD_CONTROL_3_VS1,
263         DSI_PAD_CONTROL_4_VS1,
264         DSI_GANGED_MODE_CONTROL,
265         DSI_GANGED_MODE_START,
266         DSI_GANGED_MODE_SIZE,
267 };
268
269 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
270 static int tegra_dsi_host_resume(struct tegra_dc *dc);
271
272 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
273 {
274         unsigned long ret;
275
276         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
277         ret = readl(dsi->base + reg * 4);
278         trace_printk("readl %p=%#08lx\n", dsi->base + reg * 4, ret);
279         return ret;
280 }
281 EXPORT_SYMBOL(tegra_dsi_readl);
282
283 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
284 {
285         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
286         trace_printk("writel %p=%#08x\n", dsi->base + reg * 4, val);
287         writel(val, dsi->base + reg * 4);
288 }
289 EXPORT_SYMBOL(tegra_dsi_writel);
290
291 #ifdef CONFIG_DEBUG_FS
292 static int dbg_dsi_show(struct seq_file *s, void *unused)
293 {
294         struct tegra_dc_dsi_data *dsi = s->private;
295
296 #define DUMP_REG(a) do {                                                \
297                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
298                        #a, a, tegra_dsi_readl(dsi, a));         \
299         } while (0)
300
301         tegra_dc_io_start(dsi->dc);
302         clk_enable(dsi->dsi_clk);
303
304         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
305         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
306         DUMP_REG(DSI_CTXSW);
307         DUMP_REG(DSI_POWER_CONTROL);
308         DUMP_REG(DSI_INT_ENABLE);
309         DUMP_REG(DSI_CONTROL);
310         DUMP_REG(DSI_SOL_DELAY);
311         DUMP_REG(DSI_MAX_THRESHOLD);
312         DUMP_REG(DSI_TRIGGER);
313         DUMP_REG(DSI_TX_CRC);
314         DUMP_REG(DSI_STATUS);
315         DUMP_REG(DSI_INIT_SEQ_CONTROL);
316         DUMP_REG(DSI_INIT_SEQ_DATA_0);
317         DUMP_REG(DSI_INIT_SEQ_DATA_1);
318         DUMP_REG(DSI_INIT_SEQ_DATA_2);
319         DUMP_REG(DSI_INIT_SEQ_DATA_3);
320         DUMP_REG(DSI_INIT_SEQ_DATA_4);
321         DUMP_REG(DSI_INIT_SEQ_DATA_5);
322         DUMP_REG(DSI_INIT_SEQ_DATA_6);
323         DUMP_REG(DSI_INIT_SEQ_DATA_7);
324         DUMP_REG(DSI_PKT_SEQ_0_LO);
325         DUMP_REG(DSI_PKT_SEQ_0_HI);
326         DUMP_REG(DSI_PKT_SEQ_1_LO);
327         DUMP_REG(DSI_PKT_SEQ_1_HI);
328         DUMP_REG(DSI_PKT_SEQ_2_LO);
329         DUMP_REG(DSI_PKT_SEQ_2_HI);
330         DUMP_REG(DSI_PKT_SEQ_3_LO);
331         DUMP_REG(DSI_PKT_SEQ_3_HI);
332         DUMP_REG(DSI_PKT_SEQ_4_LO);
333         DUMP_REG(DSI_PKT_SEQ_4_HI);
334         DUMP_REG(DSI_PKT_SEQ_5_LO);
335         DUMP_REG(DSI_PKT_SEQ_5_HI);
336         DUMP_REG(DSI_DCS_CMDS);
337         DUMP_REG(DSI_PKT_LEN_0_1);
338         DUMP_REG(DSI_PKT_LEN_2_3);
339         DUMP_REG(DSI_PKT_LEN_4_5);
340         DUMP_REG(DSI_PKT_LEN_6_7);
341         DUMP_REG(DSI_PHY_TIMING_0);
342         DUMP_REG(DSI_PHY_TIMING_1);
343         DUMP_REG(DSI_PHY_TIMING_2);
344         DUMP_REG(DSI_BTA_TIMING);
345         DUMP_REG(DSI_TIMEOUT_0);
346         DUMP_REG(DSI_TIMEOUT_1);
347         DUMP_REG(DSI_TO_TALLY);
348         DUMP_REG(DSI_PAD_CONTROL);
349         DUMP_REG(DSI_PAD_CONTROL_CD);
350         DUMP_REG(DSI_PAD_CD_STATUS);
351         DUMP_REG(DSI_VID_MODE_CONTROL);
352 #undef DUMP_REG
353
354         clk_disable(dsi->dsi_clk);
355         tegra_dc_io_end(dsi->dc);
356
357         return 0;
358 }
359
360 static int dbg_dsi_open(struct inode *inode, struct file *file)
361 {
362         return single_open(file, dbg_dsi_show, inode->i_private);
363 }
364
365 static const struct file_operations dbg_fops = {
366         .open           = dbg_dsi_open,
367         .read           = seq_read,
368         .llseek         = seq_lseek,
369         .release        = single_release,
370 };
371
372 static struct dentry *dsidir;
373
374 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
375 {
376         struct dentry *retval;
377
378         dsidir = debugfs_create_dir("tegra_dsi", NULL);
379         if (!dsidir)
380                 return;
381         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
382                 &dbg_fops);
383         if (!retval)
384                 goto free_out;
385         return;
386 free_out:
387         debugfs_remove_recursive(dsidir);
388         dsidir = NULL;
389         return;
390 }
391 #else
392 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
393 { }
394 #endif
395
396 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
397 {
398         if (!tegra_is_clk_enabled(dsi->dsi_clk)) {
399                 clk_enable(dsi->dsi_clk);
400                 clk_enable(dsi->dsi_fixed_clk);
401         }
402 }
403
404 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
405 {
406         if (tegra_is_clk_enabled(dsi->dsi_clk)) {
407                 clk_disable(dsi->dsi_clk);
408                 clk_disable(dsi->dsi_fixed_clk);
409         }
410 }
411
412 static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
413 {
414         u32 val;
415         int ret;
416
417         ret = 0;
418
419         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
420
421         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
422                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
423         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
424
425         /* TODO: Use interrupt rather than polling */
426         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
427                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
428         if (ret < 0) {
429                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
430                 goto fail;
431         }
432
433         (dsi->syncpt_val)++;
434         return 0;
435 fail:
436         return ret;
437 }
438
439 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
440 {
441         u32 dsi_clock_rate_khz;
442
443         switch (dsi->info.video_burst_mode) {
444         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
445         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
446         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
447         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
448                 /* Calculate DSI HS clock rate for DSI burst mode */
449                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
450                                                         dsi->shift_clk_div;
451                 break;
452         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
453         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
454         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
455         default:
456                 /* Clock rate is default DSI clock rate for non-burst mode */
457                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
458                 break;
459         }
460
461         return dsi_clock_rate_khz;
462 }
463
464 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
465 {
466         u32 dsi_clock_rate_khz;
467
468         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
469                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
470                         dsi_clock_rate_khz =
471                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
472                 else
473                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
474         else
475                 if (lp_op == DSI_LP_OP_READ)
476                         dsi_clock_rate_khz =
477                                 dsi->info.lp_read_cmd_mode_freq_khz;
478                 else
479                         dsi_clock_rate_khz =
480                                 dsi->info.lp_cmd_mode_freq_khz;
481
482         return dsi_clock_rate_khz;
483 }
484
485 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
486 {
487         u32 shift_clk_div;
488         u32 max_shift_clk_div;
489         u32 burst_width;
490         u32 burst_width_max;
491
492         /* Get the real value of default shift_clk_div. default_shift_clk_div
493          * holds the real value of shift_clk_div.
494          */
495         shift_clk_div = dsi->default_shift_clk_div;
496
497         /* Calculate shift_clk_div which can matche the video_burst_mode. */
498         if (dsi->info.video_burst_mode >=
499                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
500                 /* The max_shift_clk_div is multiplied by 10 to save the
501                  * fraction
502                  */
503                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
504                         max_shift_clk_div = dsi->info.max_panel_freq_khz
505                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
506                 else
507                         max_shift_clk_div = shift_clk_div * 10;
508
509                 burst_width = dsi->info.video_burst_mode
510                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
511                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
512                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
513
514                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
515                         burst_width / (burst_width_max * 10) + shift_clk_div;
516         }
517
518         return shift_clk_div;
519 }
520
521 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
522                                         struct tegra_dc_dsi_data *dsi)
523 {
524         u32 h_width_pixels;
525         u32 h_act_corr = 0;
526         u32 hfp_corr = 0;
527         u32 temp = 0;
528
529         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
530                         dc->mode.h_sync_width + dc->mode.h_active;
531
532         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
533                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
534                 if (temp) {
535                         h_act_corr = dsi->info.n_data_lanes - temp;
536                         h_width_pixels += h_act_corr;
537                 }
538         }
539
540         temp = h_width_pixels % dsi->info.n_data_lanes;
541         if (temp) {
542                 hfp_corr = dsi->info.n_data_lanes - temp;
543                 h_width_pixels += hfp_corr;
544         }
545
546         while (1) {
547                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
548                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
549                 if (temp) {
550                         hfp_corr += dsi->info.n_data_lanes;
551                         h_width_pixels += dsi->info.n_data_lanes;
552                 }
553                 else
554                         break;
555         }
556
557         dc->mode.h_front_porch += hfp_corr;
558         dc->mode.h_active += h_act_corr;
559 }
560
561 static void tegra_dsi_init_sw(struct tegra_dc *dc,
562                         struct tegra_dc_dsi_data *dsi)
563 {
564         u32 h_width_pixels;
565         u32 v_width_lines;
566         u32 pixel_clk_hz;
567         u32 byte_clk_hz;
568         u32 plld_clk_mhz;
569         u8 n_data_lanes;
570
571         switch (dsi->info.pixel_format) {
572         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
573                 /* 2 bytes per pixel */
574                 dsi->pixel_scaler_mul = 2;
575                 dsi->pixel_scaler_div = 1;
576                 break;
577         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
578                 /* 2.25 bytes per pixel */
579                 dsi->pixel_scaler_mul = 9;
580                 dsi->pixel_scaler_div = 4;
581                 break;
582         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
583         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
584                 /* 3 bytes per pixel */
585                 dsi->pixel_scaler_mul = 3;
586                 dsi->pixel_scaler_div = 1;
587                 break;
588         default:
589                 break;
590         }
591
592         dsi->ulpm = false;
593         dsi->enabled = false;
594         dsi->clk_ref = false;
595
596         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
597                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
598                 n_data_lanes = dsi->info.n_data_lanes / 2;
599
600         dsi->dsi_control_val =
601                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
602                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
603                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
604                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
605
606         if (dsi->info.ganged_type)
607                 tegra_dsi_pix_correction(dc, dsi);
608
609         /* Below we are going to calculate dsi and dc clock rate.
610          * Calcuate the horizontal and vertical width.
611          */
612         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
613                         dc->mode.h_sync_width + dc->mode.h_active;
614
615         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
616                         dc->mode.v_sync_width + dc->mode.v_active;
617
618         /* Calculate minimum required pixel rate. */
619         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
620         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
621                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
622                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
623                                 "should be larger than rated refresh rate.\n");
624                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
625                                                 dsi->info.rated_refresh_rate;
626         }
627
628         /* Calculate minimum byte rate on DSI interface. */
629         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
630                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
631
632         /* Round up to multiple of mega hz. */
633         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
634                                                                 1000000);
635
636         /* Calculate default real shift_clk_div. */
637         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
638                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
639                 dsi->info.n_data_lanes);
640         /* Calculate default DSI hs clock. DSI interface is double data rate.
641          * Data is transferred on both rising and falling edge of clk, div by 2
642          * to get the actual clock rate.
643          */
644         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
645         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
646                                                 / dsi->default_shift_clk_div;
647
648         /* Get the actual shift_clk_div and clock rates. */
649         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
650         dsi->target_lp_clk_khz =
651                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
652         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
653
654         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
655                                                         dsi->target_hs_clk_khz);
656
657 #if DSI_USE_SYNC_POINTS
658         dsi->syncpt_id = NVSYNCPT_DSI;
659 #endif
660
661         /*
662          * Force video clock to be continuous mode if
663          * enable_hs_clock_on_lp_cmd_mode is set
664          */
665         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
666                 if (dsi->info.video_clock_mode !=
667                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
668                         dev_warn(&dc->ndev->dev,
669                                 "Force clock continuous mode\n");
670
671                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
672         }
673
674 }
675
676 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
677 (platform_t_phy_ns) ? ( \
678 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
679 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
680 ((default_phy) < 0 ? 0 : (default_phy)))
681
682 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
683                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
684 {
685         phy_timing_clk->t_tlpx = SELECT_T_PHY(
686                 dsi->info.phy_timing.t_tlpx_ns,
687                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
688
689         phy_timing_clk->t_clktrail = SELECT_T_PHY(
690                 dsi->info.phy_timing.t_clktrail_ns,
691                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
692
693         phy_timing_clk->t_clkpost = SELECT_T_PHY(
694                 dsi->info.phy_timing.t_clkpost_ns,
695                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
696
697         phy_timing_clk->t_clkzero = SELECT_T_PHY(
698                 dsi->info.phy_timing.t_clkzero_ns,
699                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
700
701         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
702                 dsi->info.phy_timing.t_clkprepare_ns,
703                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
704
705         phy_timing_clk->t_clkpre = SELECT_T_PHY(
706                 dsi->info.phy_timing.t_clkpre_ns,
707                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
708 }
709
710 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
711                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
712 {
713         phy_timing_clk->t_tlpx = SELECT_T_PHY(
714                 dsi->info.phy_timing.t_tlpx_ns,
715                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
716
717         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
718                 dsi->info.phy_timing.t_hsdexit_ns,
719                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
720
721         phy_timing_clk->t_hstrail = SELECT_T_PHY(
722                 dsi->info.phy_timing.t_hstrail_ns,
723                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
724
725         phy_timing_clk->t_datzero = SELECT_T_PHY(
726                 dsi->info.phy_timing.t_datzero_ns,
727                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
728
729         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
730                 dsi->info.phy_timing.t_hsprepare_ns,
731                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
732 }
733
734 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
735                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
736 {
737         phy_timing_clk->t_tlpx = SELECT_T_PHY(
738                 dsi->info.phy_timing.t_tlpx_ns,
739                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
740 }
741
742 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
743                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
744 {
745         phy_timing_clk->t_tlpx = SELECT_T_PHY(
746                 dsi->info.phy_timing.t_tlpx_ns,
747                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
748
749         phy_timing_clk->t_taget = SELECT_T_PHY(
750                 dsi->info.phy_timing.t_taget_ns,
751                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
752
753         phy_timing_clk->t_tasure = SELECT_T_PHY(
754                 dsi->info.phy_timing.t_tasure_ns,
755                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
756
757         phy_timing_clk->t_tago = SELECT_T_PHY(
758                 dsi->info.phy_timing.t_tago_ns,
759                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
760 }
761
762 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
763                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
764 {
765         phy_timing_clk->t_tlpx = SELECT_T_PHY(
766                 dsi->info.phy_timing.t_tlpx_ns,
767                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
768
769         phy_timing_clk->t_wakeup = SELECT_T_PHY(
770                 dsi->info.phy_timing.t_wakeup_ns,
771                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
772 }
773
774 #undef SELECT_T_PHY
775
776 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
777                                 struct dsi_phy_timing_inclk *phy_timing_clk,
778                                 u32 clk_ns, u8 lphs)
779 {
780         if (!(dsi->info.ganged_type)) {
781 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
782                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
783                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
784 #endif
785         }
786
787         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
788                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
789                         (T_HSEXIT_DEFAULT(clk_ns));
790
791         if (lphs == DSI_LPHS_IN_HS_MODE) {
792                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
793                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
794         } else {
795                 /* default is LP mode */
796                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
797                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
798                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
799                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
800                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
801         }
802 }
803
804 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
805                                 struct dsi_phy_timing_inclk *phy_timing,
806                                 u32 clk_ns, u8 lphs)
807 {
808         int err = 0;
809
810 #define CHECK_RANGE(val, min, max) ( \
811                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
812                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
813
814 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
815         clk_ns = dsi->info.fpga_freq_khz ?
816                 ((1000 * 1000) / dsi->info.fpga_freq_khz) :
817                 DEFAULT_FPGA_FREQ_KHZ;
818 #endif
819
820         err = CHECK_RANGE(
821         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
822                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
823                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
824         if (err < 0) {
825                 dev_warn(&dsi->dc->ndev->dev,
826                         "dsi: Tlpx mipi range violated\n");
827                 goto fail;
828         }
829
830         if (lphs == DSI_LPHS_IN_HS_MODE) {
831                 err = CHECK_RANGE(
832                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
833                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
834                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
835                 if (err < 0) {
836                         dev_warn(&dsi->dc->ndev->dev,
837                                 "dsi: HsExit mipi range violated\n");
838                         goto fail;
839                 }
840
841                 err = CHECK_RANGE(
842                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
843                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
844                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
845                 if (err < 0) {
846                         dev_warn(&dsi->dc->ndev->dev,
847                                 "dsi: HsTrail mipi range violated\n");
848                         goto fail;
849                 }
850
851                 err = CHECK_RANGE(
852                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
853                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
854                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
855                 if (err < 0) {
856                         dev_warn(&dsi->dc->ndev->dev,
857                                 "dsi: HsZero mipi range violated\n");
858                         goto fail;
859                 }
860
861                 err = CHECK_RANGE(
862                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
863                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
864                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
865                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
866                 if (err < 0) {
867                         dev_warn(&dsi->dc->ndev->dev,
868                                 "dsi: HsPrepare mipi range violated\n");
869                         goto fail;
870                 }
871
872                 err = CHECK_RANGE(
873                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
874                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
875                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
876                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
877                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
878                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
879                 if (err < 0) {
880                         dev_warn(&dsi->dc->ndev->dev,
881                         "dsi: HsPrepare + HsZero mipi range violated\n");
882                         goto fail;
883                 }
884         } else {
885                 /* default is LP mode */
886                 err = CHECK_RANGE(
887                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
888                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
889                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
890                 if (err < 0) {
891                         dev_warn(&dsi->dc->ndev->dev,
892                                 "dsi: WakeUp mipi range violated\n");
893                         goto fail;
894                 }
895
896                 err = CHECK_RANGE(
897                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
898                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
899                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
900                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
901                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
902                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
903                 if (err < 0) {
904                         dev_warn(&dsi->dc->ndev->dev,
905                                 "dsi: TaSure mipi range violated\n");
906                         goto fail;
907                 }
908         }
909
910         if (lphs == DSI_LPHS_IN_HS_MODE ||
911                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
912                 err = CHECK_RANGE(
913                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
914                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
915                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
916                 if (err < 0) {
917                         dev_warn(&dsi->dc->ndev->dev,
918                                 "dsi: ClkTrail mipi range violated\n");
919                         goto fail;
920                 }
921
922                 err = CHECK_RANGE(
923                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
924                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
925                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
926                 if (err < 0) {
927                         dev_warn(&dsi->dc->ndev->dev,
928                                 "dsi: ClkPost mipi range violated\n");
929                         goto fail;
930                 }
931
932                 err = CHECK_RANGE(
933                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
934                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
935                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
936                 if (err < 0) {
937                         dev_warn(&dsi->dc->ndev->dev,
938                                 "dsi: ClkZero mipi range violated\n");
939                         goto fail;
940                 }
941
942                 err = CHECK_RANGE(
943                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
944                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
945                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
946                 if (err < 0) {
947                         dev_warn(&dsi->dc->ndev->dev,
948                                 "dsi: ClkPrepare mipi range violated\n");
949                         goto fail;
950                 }
951
952                 err = CHECK_RANGE(
953                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
954                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
955                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
956                 if (err < 0) {
957                         dev_warn(&dsi->dc->ndev->dev,
958                                 "dsi: ClkPre mipi range violated\n");
959                         goto fail;
960                 }
961
962                 err = CHECK_RANGE(
963                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
964                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
965                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
966                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
967                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
968                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
969                 if (err < 0) {
970                         dev_warn(&dsi->dc->ndev->dev,
971                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
972                         goto fail;
973                 }
974         }
975 fail:
976 #undef CHECK_RANGE
977         return err;
978 }
979
980 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
981                                 struct dsi_phy_timing_inclk *phy_timing,
982                                 u32 clk_ns, u8 lphs)
983 {
984         u32 hs_t_phy_ns;
985         u32 clk_t_phy_ns;
986         u32 t_phy_ns;
987         u32 h_blank_ns;
988         struct tegra_dc_mode *modes;
989         u32 t_pix_ns;
990         int err = 0;
991
992         if (!(lphs == DSI_LPHS_IN_HS_MODE))
993                 goto fail;
994
995         modes = dsi->dc->out->modes;
996         t_pix_ns = clk_ns * BITS_PER_BYTE *
997                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
998
999         hs_t_phy_ns =
1000                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1001                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1002                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1003                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1004                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1005                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1006                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1007                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1008                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1009                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1010
1011         clk_t_phy_ns =
1012                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1013                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1014                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1015                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1016                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1017                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1018                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1019                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1020                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1021                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1022                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1023                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1024                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1025                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1026
1027         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1028                                                 modes->h_front_porch);
1029
1030         /* Extra tlpx and byte cycle required by dsi HW */
1031         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1032                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1033                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1034                 clk_ns * BITS_PER_BYTE);
1035
1036         if (h_blank_ns < t_phy_ns) {
1037                 err = -EINVAL;
1038                 dev_err(&dsi->dc->ndev->dev,
1039                         "dsi: Hblank is smaller than HS trans phy timing\n");
1040                 goto fail;
1041         }
1042
1043         return 0;
1044 fail:
1045         return err;
1046 }
1047
1048 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1049                                 struct dsi_phy_timing_inclk *phy_timing,
1050                                 u32 clk_ns, u8 lphs)
1051 {
1052         int err = 0;
1053
1054         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1055         if (err < 0) {
1056                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1057                 goto fail;
1058         }
1059
1060         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1061         if (err < 0) {
1062                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1063                 goto fail;
1064         }
1065
1066         /* TODO: add more contraints */
1067 fail:
1068         return err;
1069 }
1070
1071 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1072 {
1073         u32 val;
1074         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1075
1076         tegra_dsi_get_phy_timing
1077                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1078
1079         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1080                                         dsi->current_bit_clk_ns, lphs);
1081
1082         if (dsi->info.ganged_type) {
1083 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1084                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1085                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1086                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1087                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1088
1089                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1090                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1091                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1092                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1093
1094                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1095                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1096                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1097
1098                 phy_timing.t_taget += T_TAGET_HW_INC;
1099                 phy_timing.t_tasure += T_TASURE_HW_INC;
1100                 phy_timing.t_tago += T_TAGO_HW_INC;
1101 #endif
1102         }
1103
1104         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1105                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1106                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1107                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1108         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1109
1110         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1111                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1112                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1113                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1114         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1115
1116         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1117                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1118                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1119         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1120
1121         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1122                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1123                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1124         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1125
1126         dsi->phy_timing = phy_timing;
1127 }
1128
1129 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1130                                 struct tegra_dc_dsi_data *dsi)
1131 {
1132         u32 dsi_to_pixel_clk_ratio;
1133         u32 temp;
1134         u32 temp1;
1135         u32 mipi_clk_adj_kHz = 0;
1136         u32 sol_delay;
1137         struct tegra_dc_mode *dc_modes = &dc->mode;
1138
1139         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1140         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1141                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1142
1143         /* Convert Fdsi to byte format */
1144         dsi_to_pixel_clk_ratio *= 1000/8;
1145
1146         /* Multiplying by 1000 so that we don't loose the fraction part */
1147         temp = dc_modes->h_active * 1000;
1148         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1149                         dc_modes->h_sync_width;
1150
1151         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1152                         temp * dsi->pixel_scaler_mul /
1153                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1154
1155         /* Do rounding on sol delay */
1156         sol_delay = (sol_delay + 1000 - 1)/1000;
1157
1158         /* TODO:
1159          * 1. find out the correct sol fifo depth to use
1160          * 2. verify with hw about the clamping function
1161          */
1162         if (sol_delay > (480 * 4)) {
1163                 sol_delay = (480 * 4);
1164                 mipi_clk_adj_kHz = sol_delay +
1165                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1166                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1167
1168                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1169
1170                 mipi_clk_adj_kHz *= 4;
1171         }
1172
1173         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1174
1175         return sol_delay;
1176 }
1177
1178 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1179                                 struct tegra_dc_dsi_data *dsi)
1180 {
1181         u32 sol_delay;
1182         u32 internal_delay;
1183         u32 h_width_byte_clk;
1184         u32 h_width_pixels;
1185         u32 h_width_ganged_byte_clk;
1186         u8 n_data_lanes_this_cont = 0;
1187         u8 n_data_lanes_ganged = 0;
1188
1189         if (!(dsi->info.ganged_type)) {
1190                 if (dsi->info.video_burst_mode ==
1191                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1192                         dsi->info.video_burst_mode ==
1193                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1194 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1195                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1196                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1197 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1198                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1199                 } else {
1200                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1201                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1202                 }
1203         } else {
1204 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1205 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1206 #define FIFO_WR_PIX_CLK_DELAY 2
1207 #define FIFO_RD_BYTE_CLK_DELAY 6
1208 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1209                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1210                                 FIFO_WR_PIX_CLK_DELAY)
1211
1212                 internal_delay = DIV_ROUND_UP(
1213                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1214                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1215                                 + FIFO_RD_BYTE_CLK_DELAY;
1216
1217                 h_width_pixels = dc->mode.h_sync_width +
1218                                         dc->mode.h_back_porch +
1219                                         dc->mode.h_active +
1220                                         dc->mode.h_front_porch;
1221
1222                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1223                                         dsi->pixel_scaler_mul,
1224                                         dsi->pixel_scaler_div *
1225                                         dsi->info.n_data_lanes);
1226
1227                 if (dsi->info.ganged_type ==
1228                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1229                         dsi->info.ganged_type ==
1230                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1231                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1232                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1233                 }
1234
1235                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1236                                         n_data_lanes_this_cont *
1237                                         h_width_byte_clk,
1238                                         n_data_lanes_ganged);
1239
1240                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1241                                                         internal_delay;
1242                 sol_delay = (dsi->info.video_data_type ==
1243                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1244                                 sol_delay + 20: sol_delay;
1245
1246 #undef SOL_TO_VALID_PIX_CLK_DELAY
1247 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1248 #undef FIFO_WR_PIX_CLK_DELAY
1249 #undef FIFO_RD_BYTE_CLK_DELAY
1250 #undef TOT_INTERNAL_PIX_DELAY
1251         }
1252
1253         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1254                                                 DSI_SOL_DELAY);
1255 }
1256
1257 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1258 {
1259         u32 val;
1260         u32 bytes_per_frame;
1261         u32 timeout = 0;
1262
1263         /* TODO: verify the following equation */
1264         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1265                                                 (dsi->info.refresh_rate * 8);
1266         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1267         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1268
1269         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1270                         DSI_TIMEOUT_0_HTX_TO(timeout);
1271         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1272
1273         if (dsi->info.panel_reset_timeout_msec)
1274                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1275                                         / dsi->current_bit_clk_ns;
1276         else
1277                 timeout = DSI_PR_TO_VALUE;
1278
1279         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1280                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1281         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1282
1283         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1284                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1285                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1286                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1287         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1288 }
1289
1290 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1291                                                 struct tegra_dc_dsi_data *dsi)
1292 {
1293         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1294         u32 hact_pkt_len_pix = 0;
1295         u32 hact_pkt_len_bytes = 0;
1296         u32 hfp_pkt_len_bytes = 0;
1297         u32 pix_per_line_orig = 0;
1298         u32 pix_per_line = 0;
1299         u32 val = 0;
1300
1301 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1302 #define HEADER_OVERHEAD 16
1303
1304         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1305                         dc->mode.h_active + dc->mode.h_front_porch;
1306
1307         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1308                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1309                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1310                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1311                 if (dsi->controller_index) {
1312                         hact_pkt_len_pix =
1313                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1314                         pix_per_line = pix_per_line_orig - pix_per_line;
1315                 }
1316                 hact_pkt_len_bytes = hact_pkt_len_pix *
1317                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1318                 hfp_pkt_len_bytes = pix_per_line *
1319                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1320                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1321         }
1322
1323         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1324                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1325         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1326
1327         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1328                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1329         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1330
1331         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1332                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1333         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1334
1335         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1336                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1337         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1338
1339 #undef HEADER_OVERHEAD
1340 }
1341
1342 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1343                                                 struct tegra_dc_dsi_data *dsi)
1344 {
1345         u32 val;
1346         u32 hact_pkt_len;
1347         u32 hsa_pkt_len;
1348         u32 hbp_pkt_len;
1349         u32 hfp_pkt_len;
1350
1351         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1352                                                         dsi->pixel_scaler_div;
1353         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1354                                                         dsi->pixel_scaler_div;
1355         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1356                                                         dsi->pixel_scaler_div;
1357         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1358                                                         dsi->pixel_scaler_div;
1359
1360         if (dsi->info.video_burst_mode !=
1361                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1362                 hbp_pkt_len += hsa_pkt_len;
1363
1364         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1365         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1366         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1367
1368         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1369                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1370         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1371
1372         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1373                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1374         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1375
1376         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1377                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1378         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1379
1380         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0);
1381         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1382 }
1383
1384 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1385                                                 struct tegra_dc_dsi_data *dsi)
1386 {
1387         unsigned long   val;
1388         unsigned long   act_bytes;
1389
1390         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1391                         dsi->pixel_scaler_div + 1;
1392
1393         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1394         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1395
1396         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1397         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1398
1399         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1400         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1401
1402         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1403         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1404 }
1405
1406 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1407                                 struct tegra_dc_dsi_data *dsi)
1408 {
1409         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1410                 return;
1411
1412         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1413                 if (dsi->info.ganged_type)
1414                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1415                 else
1416                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1417         } else {
1418                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1419         }
1420 }
1421
1422 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1423                                 struct tegra_dc_dsi_data *dsi)
1424 {
1425         const u32 *pkt_seq;
1426         u32 rgb_info;
1427         u32 pkt_seq_3_5_rgb_lo;
1428         u32 pkt_seq_3_5_rgb_hi;
1429         u32     val;
1430         u32 reg;
1431         u8  i;
1432
1433         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1434                 return;
1435
1436         switch (dsi->info.pixel_format) {
1437         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1438                 rgb_info = CMD_RGB_16BPP;
1439                 break;
1440         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1441                 rgb_info = CMD_RGB_18BPP;
1442                 break;
1443         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1444                 rgb_info = CMD_RGB_18BPPNP;
1445                 break;
1446         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1447         default:
1448                 rgb_info = CMD_RGB_24BPP;
1449                 break;
1450         }
1451
1452         pkt_seq_3_5_rgb_lo = 0;
1453         pkt_seq_3_5_rgb_hi = 0;
1454         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1455                 pkt_seq = dsi_pkt_seq_cmd_mode;
1456         else {
1457                 switch (dsi->info.video_burst_mode) {
1458                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1459                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1460                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1461                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1462                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1463                         pkt_seq_3_5_rgb_lo =
1464                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1465                         if (!dsi->info.no_pkt_seq_eot)
1466                                 pkt_seq = dsi_pkt_seq_video_burst;
1467                         else
1468                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1469                         break;
1470                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1471                         pkt_seq_3_5_rgb_hi =
1472                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1473                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1474                         break;
1475                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1476                 default:
1477                         if (dsi->info.ganged_type) {
1478                                 pkt_seq_3_5_rgb_lo =
1479                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1480                                 pkt_seq =
1481                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1482                         } else {
1483                                 pkt_seq_3_5_rgb_lo =
1484                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1485                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1486                         }
1487                         break;
1488                 }
1489         }
1490
1491         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1492                 val = pkt_seq[i];
1493                 reg = dsi_pkt_seq_reg[i];
1494                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1495                         val |= pkt_seq_3_5_rgb_lo;
1496                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1497                         val |= pkt_seq_3_5_rgb_hi;
1498                 tegra_dsi_writel(dsi, val, reg);
1499         }
1500 }
1501
1502 static void tegra_dsi_reset_underflow_overflow
1503                                 (struct tegra_dc_dsi_data *dsi)
1504 {
1505         u32 val;
1506
1507         val = tegra_dsi_readl(dsi, DSI_STATUS);
1508         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1509         if (val) {
1510                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1511                         dev_warn(&dsi->dc->ndev->dev,
1512                                 "dsi: video fifo overflow. Resetting flag\n");
1513                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1514                         dev_warn(&dsi->dc->ndev->dev,
1515                                 "dsi: video fifo underflow. Resetting flag\n");
1516                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1517                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1518                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1519                 udelay(5);
1520         }
1521 }
1522
1523 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1524                                         struct tegra_dc_dsi_data *dsi)
1525 {
1526         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1527         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1528         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1529         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1530
1531         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1532 }
1533
1534 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1535                                                 struct tegra_dc_dsi_data *dsi)
1536 {
1537         int val;
1538         long timeout;
1539         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1540
1541         /* stop dc */
1542         tegra_dsi_stop_dc_stream(dc, dsi);
1543
1544         /* enable frame end interrupt */
1545         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1546         val |= FRAME_END_INT;
1547         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1548
1549         /* wait for frame_end completion.
1550          * timeout is 2 frame duration to accomodate for
1551          * internal delay.
1552          */
1553         timeout = wait_for_completion_interruptible_timeout(
1554                         &dc->frame_end_complete,
1555                         msecs_to_jiffies(2 * frame_period));
1556
1557         /* disable frame end interrupt */
1558         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1559         val &= ~FRAME_END_INT;
1560         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1561
1562         if (timeout == 0)
1563                 dev_warn(&dc->ndev->dev,
1564                         "DC doesn't stop at end of frame.\n");
1565
1566         tegra_dsi_reset_underflow_overflow(dsi);
1567 }
1568
1569 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1570                                         struct tegra_dc_dsi_data *dsi)
1571 {
1572         u32 val;
1573
1574         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1575
1576         /* TODO: clean up */
1577         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1578                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1579                         DC_CMD_DISPLAY_POWER_CONTROL);
1580
1581         /* Configure one-shot mode or continuous mode */
1582         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1583                 /* disable LSPI/LCD_DE output */
1584                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1585                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1586
1587                 /* enable MSF & set MSF polarity */
1588                 val = MSF_ENABLE | MSF_LSPI;
1589                 if (!dsi->info.te_polarity_low)
1590                         val |= MSF_POLARITY_HIGH;
1591                 else
1592                         val |= MSF_POLARITY_LOW;
1593                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1594
1595                 /* set non-continuous mode */
1596                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1597                                                 DC_CMD_DISPLAY_COMMAND);
1598                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1599                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1600                                                 DC_CMD_STATE_CONTROL);
1601         } else {
1602                 /* set continuous mode */
1603                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1604                                                 DC_CMD_DISPLAY_COMMAND);
1605                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1606                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1607         }
1608
1609         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1610 }
1611
1612 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1613                                 struct tegra_dc_dsi_data *dsi)
1614 {
1615         u32 shift_clk_div_register;
1616         u32 val;
1617
1618         /* Get the corresponding register value of shift_clk_div. */
1619         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1620
1621 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1622         shift_clk_div_register = 1;
1623         if (dsi->info.ganged_type)
1624                 shift_clk_div_register = 0;
1625 #endif
1626
1627         /* TODO: find out if PCD3 option is required */
1628         val = PIXEL_CLK_DIVIDER_PCD1 |
1629                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1630         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1631 }
1632
1633 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1634                         struct tegra_dc_dsi_data *dsi, u32 clk)
1635 {
1636         u32 rm;
1637
1638         /* Round up to MHz */
1639         rm = clk % 1000;
1640         if (rm != 0)
1641                 clk -= rm;
1642
1643         /* Set up pixel clock */
1644         dc->shift_clk_div = dsi->shift_clk_div;
1645         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1646         /* TODO: Define one shot work delay in board file. */
1647         /* Since for one-shot mode, refresh rate is usually set larger than
1648          * expected refresh rate, it needs at least 3 frame period. Less
1649          * delay one shot work is, more powering saving we have. */
1650         dc->one_shot_delay_ms = 4 *
1651                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1652
1653         /* Enable DSI clock */
1654         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1655         tegra_dsi_clk_enable(dsi);
1656         tegra_periph_reset_deassert(dsi->dsi_clk);
1657
1658         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1659         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1660 }
1661
1662 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1663 {
1664         u32 val;
1665
1666         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1667         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1668
1669         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1670                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1671                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1672         } else {
1673                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1674                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1675         }
1676         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1677
1678         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1679         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1680         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1681         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1682
1683         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1684 }
1685
1686 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1687 {
1688         u32 val;
1689         tegra_dsi_hs_clk_out_enable(dsi);
1690
1691         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1692         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1693         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1694         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1695 }
1696
1697 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1698                                                 struct tegra_dc_dsi_data *dsi)
1699 {
1700         u32 val;
1701
1702         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1703                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1704
1705         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1706         /* stabilization delay */
1707         udelay(300);
1708
1709         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1710         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1711         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1712         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1713
1714         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1715         /* stabilization delay */
1716         udelay(300);
1717
1718         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1719         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1720 }
1721
1722 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1723 {
1724         u32 dsi_control;
1725         u32 host_dsi_control;
1726         u32 max_threshold;
1727
1728         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1729         host_dsi_control = HOST_DSI_CTRL_COMMON |
1730                         HOST_DSI_CTRL_HOST_DRIVEN |
1731                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1732         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1733
1734         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1735         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1736         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1737
1738         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1739         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1740         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1741 }
1742
1743 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
1744 {
1745         u32 dsi_control;
1746         u32 host_dsi_control;
1747         u32 max_threshold;
1748         u32 dcs_cmd;
1749
1750         dsi_control = dsi->dsi_control_val;
1751         host_dsi_control = HOST_DSI_CTRL_COMMON;
1752         max_threshold = 0;
1753         dcs_cmd = 0;
1754
1755         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1756                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1757                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1758                 max_threshold =
1759                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1760                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1761         } else {
1762                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1763                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1764                 max_threshold =
1765                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1766                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1767         }
1768
1769         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1770                 dsi_control |= DSI_CTRL_CMD_MODE;
1771                 dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)|
1772                         DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE);
1773                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1774
1775         } else {
1776                 dsi_control |= DSI_CTRL_VIDEO_MODE;
1777                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1778         }
1779
1780         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1781         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1782         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1783         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1784 }
1785
1786 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1787 {
1788         u32 val;
1789
1790         if (dsi->info.controller_vs == DSI_VS_1) {
1791                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1792                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1793                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1794                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1795                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1796                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1797                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
1798                                                 (TEGRA_DSI_PAD_DISABLE) |
1799                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1800                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
1801                                                 (TEGRA_DSI_PAD_DISABLE);
1802                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1803         } else {
1804                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1805                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1806                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1807                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1808                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1809                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
1810                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
1811                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1812         }
1813 }
1814
1815 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
1816 {
1817         u32 val;
1818
1819         if (dsi->info.controller_vs == DSI_VS_1) {
1820                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1821                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1822                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1823                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1824                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1825                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1826                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
1827                                                 TEGRA_DSI_PAD_ENABLE) |
1828                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
1829                                                 TEGRA_DSI_PAD_ENABLE) |
1830                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
1831                                                 TEGRA_DSI_PAD_ENABLE);
1832                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1833         } else {
1834                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1835                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1836                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1837                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1838                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1839                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
1840                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
1841                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1842         }
1843 }
1844
1845 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1846 {
1847         u32 val;
1848
1849         if (!dsi->ulpm)
1850                 tegra_dsi_pad_enable(dsi);
1851         else
1852                 tegra_dsi_pad_disable(dsi);
1853
1854         if (dsi->info.controller_vs == DSI_VS_1) {
1855                 /* TODO: characterization parameters */
1856         } else {
1857                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1858                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
1859                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
1860                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1861                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
1862                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
1863
1864                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1865                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1866                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1867                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1868                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1869
1870                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1871
1872                 val = MIPI_CAL_TERMOSA(0x4);
1873                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1874
1875                 val = MIPI_CAL_TERMOSB(0x4);
1876                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1877
1878                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1879                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1880
1881                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1882                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1883         }
1884
1885         val = PAD_CIL_PDVREG(0x0);
1886         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1887 }
1888
1889 static void tegra_dsi_panelB_enable(void)
1890 {
1891         unsigned int val;
1892
1893         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
1894         val |= DSIB_MODE_ENABLE;
1895         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
1896 }
1897
1898 static int tegra_dsi_init_hw(struct tegra_dc *dc,
1899                                 struct tegra_dc_dsi_data *dsi)
1900 {
1901         u32 i;
1902
1903         tegra_dsi_writel(dsi,
1904                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1905                 DSI_POWER_CONTROL);
1906         /* stabilization delay */
1907         udelay(300);
1908
1909         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1910         if (dsi->info.dsi_instance) {
1911                 tegra_dsi_panelB_enable();
1912                 /* TODO:Set the misc register */
1913         }
1914
1915         /* TODO: only need to change the timing for bta */
1916         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1917
1918         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1919                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1920
1921         /* Initialize DSI registers */
1922         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
1923                 tegra_dsi_writel(dsi, 0, init_reg[i]);
1924         if (dsi->info.controller_vs == DSI_VS_1) {
1925                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
1926                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
1927         }
1928
1929         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
1930
1931         tegra_dsi_pad_calibration(dsi);
1932
1933         tegra_dsi_writel(dsi,
1934                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1935                 DSI_POWER_CONTROL);
1936         /* stabilization delay */
1937         udelay(300);
1938
1939         dsi->status.init = DSI_MODULE_INIT;
1940         dsi->status.lphs = DSI_LPHS_NOT_INIT;
1941         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1942         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
1943         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1944         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1945         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1946         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1947         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
1948
1949         return 0;
1950 }
1951
1952 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1953                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
1954 {
1955         int err;
1956
1957         if (dsi->status.init != DSI_MODULE_INIT) {
1958                 err = -EPERM;
1959                 goto fail;
1960         }
1961
1962         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1963                         dsi->status.lp_op == lp_op)
1964                 goto success;
1965
1966         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1967                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1968
1969         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
1970         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
1971                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
1972                 tegra_dsi_hs_clk_out_disable(dc, dsi);
1973
1974         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
1975         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
1976                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
1977                 tegra_dsi_set_timeout(dsi);
1978         }
1979
1980         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1981
1982         tegra_dsi_set_control_reg_lp(dsi);
1983
1984         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
1985                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
1986                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
1987
1988         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
1989         dsi->status.lp_op = lp_op;
1990 success:
1991         err = 0;
1992 fail:
1993         return err;
1994 }
1995
1996 static void tegra_dsi_ganged(struct tegra_dc *dc,
1997                                 struct tegra_dc_dsi_data *dsi)
1998 {
1999         u32 start = 0;
2000         u32 low_width = 0;
2001         u32 high_width = 0;
2002         u32 h_active = dc->out->modes->h_active;
2003         u32 val = 0;
2004
2005         if (dsi->info.controller_vs < DSI_VS_1) {
2006                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2007                 "supported with current controller version\n");
2008                 return;
2009         }
2010
2011         if (dsi->info.ganged_type ==
2012                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2013                 low_width = DIV_ROUND_UP(h_active, 2);
2014                 high_width = h_active - low_width;
2015                 if (dsi->controller_index)
2016                         start = h_active / 2;
2017                 else
2018                         start = 0;
2019         } else if (dsi->info.ganged_type ==
2020                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2021                 low_width = 0x1;
2022                 high_width = 0x1;
2023                 if (dsi->controller_index)
2024                         start = 1;
2025                 else
2026                         start = 0;
2027         }
2028
2029         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2030                                                 DSI_GANGED_MODE_START);
2031
2032         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2033                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2034         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2035
2036         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2037                                                 DSI_GANGED_MODE_CONTROL);
2038 }
2039
2040 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2041                                         struct tegra_dc_dsi_data *dsi)
2042 {
2043         int err;
2044
2045         if (dsi->status.init != DSI_MODULE_INIT) {
2046                 err = -EPERM;
2047                 goto fail;
2048         }
2049
2050         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE)
2051                 goto success;
2052
2053         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2054                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2055
2056         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2057                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2058                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2059
2060         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2061                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2062                 tegra_dsi_set_timeout(dsi);
2063         }
2064
2065         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2066
2067         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2068                 tegra_dsi_set_pkt_seq(dc, dsi);
2069                 tegra_dsi_set_pkt_length(dc, dsi);
2070                 tegra_dsi_set_sol_delay(dc, dsi);
2071                 tegra_dsi_set_dc_clk(dc, dsi);
2072         }
2073
2074         tegra_dsi_set_control_reg_hs(dsi);
2075
2076         if (dsi->info.ganged_type)
2077                 tegra_dsi_ganged(dc, dsi);
2078
2079         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2080                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2081                 tegra_dsi_hs_clk_out_enable(dsi);
2082
2083         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2084 success:
2085         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2086         err = 0;
2087 fail:
2088         return err;
2089 }
2090
2091 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2092 {
2093         u32 timeout = 0;
2094         bool retVal = true;
2095
2096         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2097                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2098                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2099                         retVal = false;
2100                         break;
2101                 }
2102                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2103                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2104         }
2105
2106         return retVal;
2107 }
2108
2109 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2110 {
2111         u32 timeout = 0;
2112         bool retVal = true;
2113
2114         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2115                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2116                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2117                         retVal = false;
2118                         break;
2119                 }
2120                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2121                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2122         }
2123
2124         return retVal;
2125 }
2126
2127 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2128 {
2129         int err = 0;
2130
2131         if (tegra_dsi_write_busy(dsi)) {
2132                 err = -EBUSY;
2133                 dev_err(&dsi->dc->ndev->dev,
2134                         "DSI trigger bit already set\n");
2135                 goto fail;
2136         }
2137
2138         if (tegra_dsi_read_busy(dsi)) {
2139                 err = -EBUSY;
2140                 dev_err(&dsi->dc->ndev->dev,
2141                         "DSI immediate bta bit already set\n");
2142                 goto fail;
2143         }
2144 fail:
2145         return (err < 0 ? true : false);
2146 }
2147
2148 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
2149 {
2150         u32 trigger;
2151         u32 status;
2152
2153         tegra_dsi_writel(dsi,
2154                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2155                 DSI_POWER_CONTROL);
2156         /* stabilization delay */
2157         udelay(300);
2158
2159         tegra_dsi_writel(dsi,
2160                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2161                 DSI_POWER_CONTROL);
2162         /* stabilization delay */
2163         udelay(300);
2164
2165         /* dsi HW does not clear host trigger bit automatically
2166          * on dsi interface disable if host fifo is empty
2167          */
2168         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
2169         status = tegra_dsi_readl(dsi, DSI_STATUS);
2170         if (trigger & DSI_TRIGGER_HOST_TRIGGER(0x1) &&
2171                 status & DSI_STATUS_IDLE(0x1)) {
2172                 trigger &= ~(DSI_TRIGGER_HOST_TRIGGER(0x1));
2173                 tegra_dsi_writel(dsi, trigger, DSI_TRIGGER);
2174         }
2175 }
2176
2177 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2178 {
2179         u32 val;
2180
2181         val = tegra_dsi_readl(dsi, DSI_STATUS);
2182         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2183         if (val) {
2184                 dev_warn(&dsi->dc->ndev->dev,
2185                         "DSI read count not zero, resetting\n");
2186                 tegra_dsi_soft_reset(dsi);
2187         }
2188 }
2189
2190 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2191                                                 struct tegra_dc_dsi_data *dsi,
2192                                                 struct tegra_dc *dc,
2193                                                 u8 lp_op)
2194 {
2195         struct dsi_status *init_status;
2196         int err;
2197
2198         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2199         if (!init_status)
2200                 return ERR_PTR(-ENOMEM);
2201
2202         *init_status = dsi->status;
2203
2204         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
2205                 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
2206                         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2207                                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
2208                         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2209                         if (dsi->info.hs_cmd_mode_supported) {
2210                                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2211                                 if (err < 0) {
2212                                         dev_err(&dc->ndev->dev,
2213                                         "Switch to HS host mode failed\n");
2214                                         goto fail;
2215                                 }
2216                         }
2217                 }
2218                 if (!dsi->info.hs_cmd_mode_supported) {
2219                         err =
2220                         tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2221                         if (err < 0) {
2222                                 dev_err(&dc->ndev->dev,
2223                                 "DSI failed to go to LP mode\n");
2224                                 goto fail;
2225                         }
2226                 }
2227         } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
2228                 if (dsi->status.lp_op != lp_op) {
2229                         err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2230                         if (err < 0) {
2231                                 dev_err(&dc->ndev->dev,
2232                                 "DSI failed to go to LP mode\n");
2233                                 goto fail;
2234                         }
2235                 }
2236         }
2237
2238         return init_status;
2239 fail:
2240         kfree(init_status);
2241         return ERR_PTR(err);
2242 }
2243
2244 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2245                                 struct tegra_dc *dc,
2246                                 struct tegra_dc_dsi_data *dsi,
2247                                 u8 lp_op)
2248 {
2249         int err = 0;
2250         struct dsi_status *init_status;
2251
2252         if (dsi->status.init != DSI_MODULE_INIT ||
2253                 dsi->ulpm) {
2254                 err = -EPERM;
2255                 goto fail;
2256         }
2257
2258         if (tegra_dsi_host_busy(dsi)) {
2259                 tegra_dsi_soft_reset(dsi);
2260
2261                 /* WAR to stop host write in middle */
2262                 tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_TRIGGER);
2263
2264                 if (tegra_dsi_host_busy(dsi)) {
2265                         err = -EBUSY;
2266                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2267                         goto fail;
2268                 }
2269         }
2270
2271         if (lp_op == DSI_LP_OP_READ)
2272                 tegra_dsi_reset_read_count(dsi);
2273
2274         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2275                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2276                 if (err < 0) {
2277                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2278                         goto fail;
2279                 }
2280         }
2281
2282         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2283                                         (dsi, dc, lp_op);
2284         if (IS_ERR_OR_NULL(init_status)) {
2285                 err = PTR_ERR(init_status);
2286                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2287                 goto fail;
2288         }
2289
2290         return init_status;
2291 fail:
2292         return ERR_PTR(err);
2293 }
2294
2295 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2296                                 struct tegra_dc_dsi_data *dsi,
2297                                 struct dsi_status *init_status)
2298 {
2299         bool switch_back_to_dc_mode = false;
2300         bool switch_back_to_hs_mode = false;
2301         bool restart_dc_stream;
2302         int err = 0;
2303
2304         switch_back_to_dc_mode = (dsi->status.driven ==
2305                                 DSI_DRIVEN_MODE_HOST &&
2306                                 init_status->driven ==
2307                                 DSI_DRIVEN_MODE_DC);
2308         switch_back_to_hs_mode = (dsi->status.lphs ==
2309                                 DSI_LPHS_IN_LP_MODE &&
2310                                 init_status->lphs ==
2311                                 DSI_LPHS_IN_HS_MODE);
2312         restart_dc_stream = (dsi->status.dc_stream ==
2313                                 DSI_DC_STREAM_DISABLE &&
2314                                 init_status->dc_stream ==
2315                                 DSI_DC_STREAM_ENABLE);
2316
2317         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2318                 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2319                 if (dsi->status.lp_op != init_status->lp_op) {
2320                         err =
2321                         tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2322                         if (err < 0) {
2323                                 dev_err(&dc->ndev->dev,
2324                                         "Failed to config LP mode\n");
2325                                 goto fail;
2326                         }
2327                 }
2328                 goto success;
2329         }
2330
2331         if (switch_back_to_dc_mode)
2332                 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
2333         if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
2334                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
2335                 if (err < 0) {
2336                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2337                         goto fail;
2338                 }
2339         }
2340         if (restart_dc_stream)
2341                 tegra_dsi_start_dc_stream(dc, dsi);
2342
2343 success:
2344 fail:
2345         kfree(init_status);
2346         return err;
2347 }
2348
2349 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2350 {
2351         int status = 0;
2352
2353         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2354                 status = -EBUSY;
2355                 goto fail;
2356         }
2357
2358         tegra_dsi_writel(dsi,
2359                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2360
2361 #if DSI_USE_SYNC_POINTS
2362         status = tegra_dsi_syncpt(dsi);
2363         if (status < 0) {
2364                 dev_err(&dsi->dc->ndev->dev,
2365                         "DSI syncpt for host trigger failed\n");
2366                 goto fail;
2367         }
2368 #else
2369         if (tegra_dsi_write_busy(dsi)) {
2370                 status = -EBUSY;
2371                 dev_err(&dsi->dc->ndev->dev,
2372                         "Timeout waiting on write completion\n");
2373         }
2374 #endif
2375
2376 fail:
2377         return status;
2378 }
2379
2380 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2381                                         u8 *pdata, u8 data_id, u16 data_len)
2382 {
2383         u8 virtual_channel;
2384         u32 val;
2385         int err;
2386
2387         err = 0;
2388
2389         virtual_channel = dsi->info.virtual_channel <<
2390                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2391
2392         /* always use hw for ecc */
2393         val = (virtual_channel | data_id) << 0 |
2394                         data_len << 8;
2395         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2396
2397         /* if pdata != NULL, pkt type is long pkt */
2398         if (pdata != NULL) {
2399                 while (data_len) {
2400                         if (data_len >= 4) {
2401                                 val = ((u32 *) pdata)[0];
2402                                 data_len -= 4;
2403                                 pdata += 4;
2404                         } else {
2405                                 val = 0;
2406                                 memcpy(&val, pdata, data_len);
2407                                 pdata += data_len;
2408                                 data_len = 0;
2409                         }
2410                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2411                 }
2412         }
2413
2414         err = tegra_dsi_host_trigger(dsi);
2415         if (err < 0)
2416                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2417
2418         return err;
2419 }
2420
2421 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2422 {
2423         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2424
2425         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2426                 /*
2427                  * The reference count should never be more than 1.
2428                  */
2429                 BUG_ON(tegra_is_clk_enabled(dc->clk) > 1);
2430
2431                 if (dsi->host_suspended)
2432                         tegra_dsi_host_resume(dc);
2433
2434                 /*
2435                  * Take an extra refrence to count for the clk_disable in
2436                  * tegra_dc_release_host.
2437                  */
2438                 clk_enable(dc->clk);
2439         }
2440 }
2441
2442 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2443 {
2444         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2445                 clk_disable(dc->clk);
2446 }
2447
2448 static void tegra_dc_dsi_idle(struct tegra_dc *dc)
2449 {
2450         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2451                 tegra_dsi_host_suspend(dc);
2452 }
2453
2454 int tegra_dsi_write_data(struct tegra_dc *dc,
2455                         struct tegra_dc_dsi_data *dsi,
2456                         u8 *pdata, u8 data_id, u16 data_len)
2457 {
2458         int err = 0;
2459         struct dsi_status *init_status;
2460
2461         tegra_dc_io_start(dc);
2462
2463         init_status = tegra_dsi_prepare_host_transmission(
2464                                 dc, dsi, DSI_LP_OP_WRITE);
2465         if (IS_ERR_OR_NULL(init_status)) {
2466                 err = PTR_ERR(init_status);
2467                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2468                 goto fail;
2469         }
2470
2471         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2472 fail:
2473         err = tegra_dsi_restore_state(dc, dsi, init_status);
2474         if (err < 0)
2475                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2476         tegra_dc_io_end(dc);
2477
2478         return err;
2479 }
2480 EXPORT_SYMBOL(tegra_dsi_write_data);
2481
2482 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2483                                         struct tegra_dc_dsi_data *dsi,
2484                                         struct tegra_dsi_cmd *cmd,
2485                                         u32 n_cmd)
2486 {
2487         u32 i;
2488         int err;
2489
2490         err = 0;
2491         for (i = 0; i < n_cmd; i++) {
2492                 struct tegra_dsi_cmd *cur_cmd;
2493                 cur_cmd = &cmd[i];
2494
2495                 if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS)
2496                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2497                 else {
2498                         err = tegra_dsi_write_data(dc, dsi,
2499                                                 cur_cmd->pdata,
2500                                                 cur_cmd->data_id,
2501                                                 cur_cmd->sp_len_dly.data_len);
2502                         if (err < 0)
2503                                 break;
2504                 }
2505         }
2506         return err;
2507 }
2508
2509 static u8 tegra_dsi_ecc(u32 header)
2510 {
2511         char ecc_parity[24] = {
2512                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2513                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2514                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2515         };
2516         u8 ecc_byte;
2517         int i;
2518
2519         ecc_byte = 0;
2520         for (i = 0; i < 24; i++)
2521                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2522
2523         return ecc_byte;
2524 }
2525
2526 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2527 {
2528         u16 byte_cnt;
2529         u8 bit_cnt;
2530         char curr_byte;
2531         u16 crc = 0xFFFF;
2532         u16 poly = 0x8408;
2533
2534         if (data_len > 0) {
2535                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2536                         curr_byte = pdata[byte_cnt];
2537                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2538                                 if (((crc & 0x0001 ) ^
2539                                         (curr_byte & 0x0001)) > 0)
2540                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2541                                 else
2542                                         crc = (crc >> 1) & 0x7FFF;
2543
2544                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2545                         }
2546                 }
2547         }
2548         return crc;
2549 }
2550
2551 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2552                                                 struct tegra_dsi_cmd *cmd)
2553 {
2554         u8 virtual_channel;
2555         u32 val;
2556         u16 data_len = cmd->sp_len_dly.data_len;
2557         u8 seq_ctrl_reg = 0;
2558
2559         virtual_channel = dsi->info.virtual_channel <<
2560                                 DSI_VIR_CHANNEL_BIT_POSITION;
2561
2562         val = (virtual_channel | cmd->data_id) << 0 |
2563                 data_len << 8;
2564
2565         val |= tegra_dsi_ecc(val) << 24;
2566
2567         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2568
2569         /* if pdata != NULL, pkt type is long pkt */
2570         if (cmd->pdata != NULL) {
2571                 u8 *pdata;
2572                 u8 *pdata_mem;
2573                 /*  allocate memory for pdata + 2 bytes checksum */
2574                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2575                 if (!pdata_mem) {
2576                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2577                         tegra_dsi_soft_reset(dsi);
2578                         return -ENOMEM;
2579                 }
2580
2581                 memcpy(pdata_mem, cmd->pdata, data_len);
2582                 pdata = pdata_mem;
2583                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2584
2585                 /* data_len = length of pdata + 2 byte checksum */
2586                 data_len += 2;
2587
2588                 while (data_len) {
2589                         if (data_len >= 4) {
2590                                 val = ((u32 *) pdata)[0];
2591                                 data_len -= 4;
2592                                 pdata += 4;
2593                         } else {
2594                                 val = 0;
2595                                 memcpy(&val, pdata, data_len);
2596                                 pdata += data_len;
2597                                 data_len = 0;
2598                         }
2599                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2600                                                         seq_ctrl_reg++);
2601                 }
2602                 kfree(pdata_mem);
2603         }
2604
2605         return 0;
2606 }
2607
2608 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2609                                                 struct tegra_dsi_cmd *cmd)
2610 {
2611 #define PKT_HEADER_LEN_BYTE     4
2612 #define CHECKSUM_LEN_BYTE       2
2613
2614         int err = 0;
2615         u32 val;
2616         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2617         struct tegra_dc *dc = dsi->dc;
2618
2619         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2620                 return -EINVAL;
2621
2622         mutex_lock(&dsi->lock);
2623         tegra_dc_dsi_hold_host(dc);
2624
2625         tegra_dc_io_start(dc);
2626
2627
2628         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2629         if (err < 0) {
2630                 dev_err(&dsi->dc->ndev->dev,
2631                         "dsi: dcs pkt seq ctrl init failed\n");
2632                 goto fail;
2633         }
2634
2635         if (cmd->pdata) {
2636                 u16 data_len = cmd->sp_len_dly.data_len;
2637                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2638         }
2639
2640         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2641                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2642                                                 TEGRA_DSI_ENABLE);
2643         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2644
2645 fail:
2646         tegra_dc_io_end(dc);
2647         tegra_dc_dsi_release_host(dc);
2648         mutex_unlock(&dsi->lock);
2649         return err;
2650
2651 #undef PKT_HEADER_LEN_BYTE
2652 #undef CHECKSUM_LEN_BYTE
2653 }
2654 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2655
2656 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2657 {
2658         struct tegra_dc *dc = dsi->dc;
2659         u32 cnt;
2660
2661         mutex_lock(&dsi->lock);
2662         tegra_dc_dsi_hold_host(dc);
2663
2664         tegra_dc_io_start(dc);
2665
2666         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2667
2668         /* clear seq data registers */
2669         for (cnt = 0; cnt < 8; cnt++)
2670                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2671
2672         tegra_dc_io_end(dc);
2673
2674         tegra_dc_dsi_release_host(dc);
2675         mutex_unlock(&dsi->lock);
2676 }
2677 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2678
2679 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2680 {
2681         u32 val;
2682         u32 poll_time;
2683         int err;
2684
2685         poll_time = 0;
2686         err = 0;
2687
2688         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2689         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2690         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2691
2692 #if DSI_USE_SYNC_POINTS
2693         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev,
2694                         dsi->syncpt_id);
2695
2696         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
2697                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
2698         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
2699
2700         /* TODO: Use interrupt rather than polling */
2701         err = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
2702                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
2703         if (err < 0)
2704                 dev_err(&dsi->dc->ndev->dev,
2705                         "DSI sync point failure\n");
2706         else
2707                 (dsi->syncpt_val)++;
2708 #else
2709         if (tegra_dsi_read_busy(dsi)) {
2710                 err = -EBUSY;
2711                 dev_err(&dsi->dc->ndev->dev,
2712                         "Timeout wating on read completion\n");
2713         }
2714 #endif
2715
2716         return err;
2717 }
2718
2719 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2720                                         u32 rd_fifo_cnt, u8 *read_fifo)
2721 {
2722         int err;
2723         u32 payload_size;
2724
2725         payload_size = 0;
2726         err = 0;
2727
2728         switch (read_fifo[0]) {
2729         case DSI_ESCAPE_CMD:
2730                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2731                 break;
2732         case DSI_ACK_NO_ERR:
2733                 dev_info(&dc->ndev->dev,
2734                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2735                 return err;
2736         default:
2737                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2738                 break;
2739         }
2740
2741         switch (read_fifo[4] & 0xff) {
2742         case GEN_LONG_RD_RES:
2743                 /* Fall through */
2744         case DCS_LONG_RD_RES:
2745                 payload_size = (read_fifo[5] |
2746                                 (read_fifo[6] << 8)) & 0xFFFF;
2747                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2748                                 "payload_size[0x%x]\n", payload_size);
2749                 break;
2750         case GEN_1_BYTE_SHORT_RD_RES:
2751                 /* Fall through */
2752         case DCS_1_BYTE_SHORT_RD_RES:
2753                 payload_size = 1;
2754                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2755                         "payload_size[0x%x]\n", payload_size);
2756                 break;
2757         case GEN_2_BYTE_SHORT_RD_RES:
2758                 /* Fall through */
2759         case DCS_2_BYTE_SHORT_RD_RES:
2760                 payload_size = 2;
2761                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2762                         "payload_size[0x%x]\n", payload_size);
2763                 break;
2764         case ACK_ERR_RES:
2765                 payload_size = 2;
2766                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2767                         "Packet payload_size[0x%x]\n", payload_size);
2768                 break;
2769         default:
2770                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2771                 err = -EINVAL;
2772                 break;
2773         }
2774         return err;
2775 }
2776
2777 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2778                         struct tegra_dc_dsi_data *dsi,
2779                         u8 *read_fifo)
2780 {
2781         u32 val;
2782         u32 i;
2783         u32 poll_time = 0;
2784         u32 rd_fifo_cnt;
2785         int err = 0;
2786         u8 *read_fifo_cp = read_fifo;
2787
2788         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2789                 mdelay(1);
2790                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2791                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2792                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
2793                         dev_err(&dc->ndev->dev,
2794                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2795                         break;
2796                 poll_time++;
2797         }
2798
2799         if (rd_fifo_cnt == 0) {
2800                 dev_info(&dc->ndev->dev,
2801                         "DSI RD_FIFO_CNT is zero\n");
2802                 err = -EINVAL;
2803                 goto fail;
2804         }
2805
2806         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2807                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2808                 dev_warn(&dc->ndev->dev,
2809                         "DSI overflow/underflow error\n");
2810         }
2811
2812         /* Read data from FIFO */
2813         for (i = 0; i < rd_fifo_cnt; i++) {
2814                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2815                 if (enable_read_debug)
2816                         dev_info(&dc->ndev->dev,
2817                         "Read data[%d]: 0x%x\n", i, val);
2818                 memcpy(read_fifo, &val, 4);
2819                 read_fifo += 4;
2820         }
2821
2822         /* Make sure all the data is read from the FIFO */
2823         val = tegra_dsi_readl(dsi, DSI_STATUS);
2824         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2825         if (val)
2826                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2827                 " even after reading FIFO_RD_CNT words from read fifo\n");
2828
2829         if (enable_read_debug) {
2830                 err =
2831                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2832                 if (err < 0)
2833                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2834         }
2835 fail:
2836         return err;
2837 }
2838
2839 int tegra_dsi_read_data(struct tegra_dc *dc,
2840                                 struct tegra_dc_dsi_data *dsi,
2841                                 u32 max_ret_payload_size,
2842                                 u32 panel_reg_addr, u8 *read_data)
2843 {
2844         int err = 0;
2845         struct dsi_status *init_status;
2846
2847         tegra_dc_io_start(dc);
2848
2849         init_status = tegra_dsi_prepare_host_transmission(
2850                                 dc, dsi, DSI_LP_OP_WRITE);
2851         if (IS_ERR_OR_NULL(init_status)) {
2852                 err = PTR_ERR(init_status);
2853                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2854                 goto fail;
2855         }
2856
2857         /* Set max return payload size in words */
2858         err = _tegra_dsi_write_data(dsi, NULL,
2859                 dsi_command_max_return_pkt_size,
2860                 max_ret_payload_size);
2861         if (err < 0) {
2862                 dev_err(&dc->ndev->dev,
2863                                 "DSI write failed\n");
2864                 goto fail;
2865         }
2866
2867         /* DCS to read given panel register */
2868         err = _tegra_dsi_write_data(dsi, NULL,
2869                 dsi_command_dcs_read_with_no_params,
2870                 panel_reg_addr);
2871         if (err < 0) {
2872                 dev_err(&dc->ndev->dev,
2873                                 "DSI write failed\n");
2874                 goto fail;
2875         }
2876
2877         tegra_dsi_reset_read_count(dsi);
2878
2879         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2880                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2881                 if (err < 0) {
2882                         dev_err(&dc->ndev->dev,
2883                         "DSI failed to go to LP read mode\n");
2884                         goto fail;
2885                 }
2886         }
2887
2888         err = tegra_dsi_bta(dsi);
2889         if (err < 0) {
2890                 dev_err(&dc->ndev->dev,
2891                         "DSI IMM BTA timeout\n");
2892                 goto fail;
2893         }
2894
2895         err = tegra_dsi_read_fifo(dc, dsi, read_data);
2896         if (err < 0) {
2897                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2898                 goto fail;
2899         }
2900 fail:
2901         err = tegra_dsi_restore_state(dc, dsi, init_status);
2902         if (err < 0)
2903                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2904         tegra_dc_io_end(dc);
2905         return err;
2906 }
2907 EXPORT_SYMBOL(tegra_dsi_read_data);
2908
2909 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
2910                                 struct tegra_dc_dsi_data *dsi)
2911 {
2912         int err = 0;
2913         u8 read_fifo[DSI_READ_FIFO_DEPTH];
2914         struct dsi_status *init_status;
2915         static struct tegra_dsi_cmd dsi_nop_cmd =
2916                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
2917
2918         tegra_dc_io_start(dc);
2919
2920         init_status = tegra_dsi_prepare_host_transmission(
2921                                         dc, dsi, DSI_LP_OP_WRITE);
2922         if (IS_ERR_OR_NULL(init_status)) {
2923                 err = PTR_ERR(init_status);
2924                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2925                 goto fail;
2926         }
2927
2928         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
2929         if (err < 0) {
2930                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
2931                 goto fail;
2932         }
2933
2934         tegra_dsi_reset_read_count(dsi);
2935
2936         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2937                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2938                 if (err < 0) {
2939                         dev_err(&dc->ndev->dev,
2940                         "DSI failed to go to LP read mode\n");
2941                         goto fail;
2942                 }
2943         }
2944
2945         err = tegra_dsi_bta(dsi);
2946         if (err < 0) {
2947                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2948                 goto fail;
2949         }
2950
2951         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2952         if (err < 0) {
2953                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2954                 goto fail;
2955         }
2956
2957         if (read_fifo[0] != DSI_ACK_NO_ERR) {
2958                 dev_warn(&dc->ndev->dev,
2959                         "Ack no error trigger message not received\n");
2960                 err = -EAGAIN;
2961         }
2962 fail:
2963         err = tegra_dsi_restore_state(dc, dsi, init_status);
2964         if (err < 0)
2965                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2966         tegra_dc_io_end(dc);
2967         return err;
2968 }
2969 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
2970
2971 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
2972 {
2973         u32 val;
2974         int ret;
2975
2976         ret = 0;
2977
2978         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2979         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
2980         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
2981         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2982
2983 #if DSI_USE_SYNC_POINTS
2984         ret = tegra_dsi_syncpt(dsi);
2985         if (ret < 0) {
2986                 dev_err(&dsi->dc->ndev->dev,
2987                         "DSI syncpt for ulpm enter failed\n");
2988                 goto fail;
2989         }
2990 #else
2991         /* TODO: Find exact delay required */
2992         mdelay(10);
2993 #endif
2994         dsi->ulpm = true;
2995 fail:
2996         return ret;
2997 }
2998
2999 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3000 {
3001         u32 val;
3002         int ret;
3003
3004         ret = 0;
3005
3006         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3007         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3008         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3009         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3010
3011 #if DSI_USE_SYNC_POINTS
3012         ret = tegra_dsi_syncpt(dsi);
3013         if (ret < 0) {
3014                 dev_err(&dsi->dc->ndev->dev,
3015                         "DSI syncpt for ulpm exit failed\n");
3016                 goto fail;
3017         }
3018 #else
3019         /* TODO: Find exact delay required */
3020         mdelay(10);
3021 #endif
3022         dsi->ulpm = false;
3023
3024         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3025         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3026         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3027         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3028 fail:
3029         return ret;
3030
3031 }
3032
3033 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3034                                      struct tegra_dc_dsi_data *dsi,
3035                                      int no_of_frames)
3036 {
3037         int err;
3038         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3039         u8 lp_op = dsi->status.lp_op;
3040         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3041
3042         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3043                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
3044                 if (err < 0) {
3045                         dev_err(&dc->ndev->dev,
3046                                 "Switch to HS host mode failed\n");
3047                         return;
3048                 }
3049         }
3050
3051         /*
3052          * Some panels need DC frames be sent under certain
3053          * conditions. We are working on the right fix for this
3054          * requirement, while using this current fix.
3055          */
3056         tegra_dsi_start_dc_stream(dc, dsi);
3057
3058         /*
3059          * Send frames in Continuous or One-shot mode.
3060          */
3061         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3062                 while (no_of_frames--) {
3063                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3064                                         DC_CMD_STATE_CONTROL);
3065                         mdelay(frame_period);
3066                 }
3067         } else
3068                 mdelay(no_of_frames * frame_period);
3069
3070         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3071
3072         if (switch_to_lp) {
3073                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3074                 if (err < 0)
3075                         dev_err(&dc->ndev->dev,
3076                                 "DSI failed to go to LP mode\n");
3077         }
3078 }
3079
3080 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3081 {
3082         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3083         int err = 0;
3084
3085         mutex_lock(&dsi->lock);
3086         tegra_dc_dsi_hold_host(dc);
3087
3088         tegra_dc_io_start(dc);
3089         /* Stop DC stream before configuring DSI registers
3090          * to avoid visible glitches on panel during transition
3091          * from bootloader to kernel driver
3092          */
3093         tegra_dsi_stop_dc_stream(dc, dsi);
3094
3095         if (dsi->enabled) {
3096                 if (dsi->ulpm) {
3097                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3098                                 dev_err(&dc->ndev->dev,
3099                                         "DSI failed to exit ulpm\n");
3100                                 goto fail;
3101                         }
3102                 }
3103
3104                 if (dsi->info.panel_reset) {
3105                         /*
3106                          * Certain panels need dc frames be sent before
3107                          * waking panel.
3108                          */
3109                         if (dsi->info.panel_send_dc_frames)
3110                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3111
3112                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3113                                                         dsi->info.dsi_init_cmd,
3114                                                         dsi->info.n_init_cmd);
3115                         if (err < 0) {
3116                                 dev_err(&dc->ndev->dev,
3117                                 "dsi: error sending dsi init cmd\n");
3118                                 goto fail;
3119                         }
3120                 } else if (dsi->info.dsi_late_resume_cmd) {
3121                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3122                                                 dsi->info.dsi_late_resume_cmd,
3123                                                 dsi->info.n_late_resume_cmd);
3124                         if (err < 0) {
3125                                 dev_err(&dc->ndev->dev,
3126                                 "dsi: error sending late resume cmd\n");
3127                                 goto fail;
3128                         }
3129                 }
3130         } else {
3131                 err = tegra_dsi_init_hw(dc, dsi);
3132                 if (err < 0) {
3133                         dev_err(&dc->ndev->dev,
3134                                 "dsi: not able to init dsi hardware\n");
3135                         goto fail;
3136                 }
3137
3138                 if (dsi->ulpm) {
3139                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3140                                 dev_err(&dc->ndev->dev,
3141                                         "DSI failed to enter ulpm\n");
3142                                 goto fail;
3143                         }
3144
3145                         tegra_dsi_pad_enable(dsi);
3146
3147                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3148                                 dev_err(&dc->ndev->dev,
3149                                         "DSI failed to exit ulpm\n");
3150                                 goto fail;
3151                         }
3152                 }
3153
3154                 /*
3155                  * Certain panels need dc frames be sent before
3156                  * waking panel.
3157                  */
3158                 if (dsi->info.panel_send_dc_frames)
3159                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3160
3161                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3162                 if (err < 0) {
3163                         dev_err(&dc->ndev->dev,
3164                                 "dsi: not able to set to lp mode\n");
3165                         goto fail;
3166                 }
3167
3168                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3169                                                 dsi->info.n_init_cmd);
3170                 if (err < 0) {
3171                         dev_err(&dc->ndev->dev,
3172                                 "dsi: error while sending dsi init cmd\n");
3173                         goto fail;
3174                 }
3175
3176                 err = tegra_dsi_set_to_hs_mode(dc, dsi);
3177                 if (err < 0) {
3178                         dev_err(&dc->ndev->dev,
3179                                 "dsi: not able to set to hs mode\n");
3180                         goto fail;
3181                 }
3182
3183                 dsi->enabled = true;
3184         }
3185
3186         if (dsi->out_ops && dsi->out_ops->enable)
3187                 dsi->out_ops->enable(dsi);
3188
3189         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3190                 tegra_dsi_start_dc_stream(dc, dsi);
3191
3192 fail:
3193         tegra_dc_io_end(dc);
3194         tegra_dc_dsi_release_host(dc);
3195         mutex_unlock(&dsi->lock);
3196 }
3197
3198 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3199 {
3200         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3201
3202         tegra_dc_dsi_debug_create(dsi);
3203
3204         if (dsi->info.dsi2lvds_bridge_enable)
3205                 dsi->out_ops = &tegra_dsi2lvds_ops;
3206         else
3207                 dsi->out_ops = NULL;
3208
3209         if (dsi->out_ops && dsi->out_ops->init)
3210                 dsi->out_ops->init(dsi);
3211
3212         tegra_dsi_init_sw(dc, dsi);
3213         /* TODO: Configure the CSI pad configuration */
3214 }
3215
3216 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3217                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3218 {
3219         u16 i;
3220         u16 len;
3221
3222         memcpy(dst, src, sizeof(*dst) * n_cmd);
3223
3224         for (i = 0; i < n_cmd; i++)
3225                 if (src[i].pdata) {
3226                         len = sizeof(*src[i].pdata) *
3227                                         src[i].sp_len_dly.data_len;
3228                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3229                         if (!dst[i].pdata)
3230                                 goto free_cmd_pdata;
3231                         memcpy(dst[i].pdata, src[i].pdata, len);
3232                 }
3233
3234         return 0;
3235
3236 free_cmd_pdata:
3237         for (--i; i >= 0; i--)
3238                 if (dst[i].pdata)
3239                         kfree(dst[i].pdata);
3240         return -ENOMEM;
3241 }
3242
3243 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
3244                                         struct tegra_dsi_out *p_dsi)
3245 {
3246         struct tegra_dsi_cmd *p_init_cmd;
3247         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3248         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3249         struct tegra_dsi_cmd *p_suspend_cmd;
3250         int err;
3251
3252         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
3253                 return -EINVAL;
3254
3255         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3256                                 p_dsi->n_init_cmd, GFP_KERNEL);
3257         if (!p_init_cmd)
3258                 return -ENOMEM;
3259
3260         if (p_dsi->dsi_early_suspend_cmd) {
3261                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3262                                         p_dsi->n_early_suspend_cmd,
3263                                         GFP_KERNEL);
3264                 if (!p_early_suspend_cmd) {
3265                         err = -ENOMEM;
3266                         goto err_free_init_cmd;
3267                 }
3268         }
3269
3270         if (p_dsi->dsi_late_resume_cmd) {
3271                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3272                                         p_dsi->n_late_resume_cmd,
3273                                         GFP_KERNEL);
3274                 if (!p_late_resume_cmd) {
3275                         err = -ENOMEM;
3276                         goto err_free_p_early_suspend_cmd;
3277                 }
3278         }
3279
3280         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3281                                 GFP_KERNEL);
3282         if (!p_suspend_cmd) {
3283                 err = -ENOMEM;
3284                 goto err_free_p_late_resume_cmd;
3285         }
3286
3287         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3288
3289         /* Copy panel init cmd */
3290         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3291                                                 p_init_cmd, p_dsi->n_init_cmd);
3292         if (err < 0)
3293                 goto err_free;
3294         dsi->info.dsi_init_cmd = p_init_cmd;
3295
3296         /* Copy panel early suspend cmd */
3297         if (p_dsi->dsi_early_suspend_cmd) {
3298                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3299                                         p_early_suspend_cmd,
3300                                         p_dsi->n_early_suspend_cmd);
3301                 if (err < 0)
3302                         goto err_free;
3303                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3304         }
3305
3306         /* Copy panel late resume cmd */
3307         if (p_dsi->dsi_late_resume_cmd) {
3308                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3309                                                 p_late_resume_cmd,
3310                                                 p_dsi->n_late_resume_cmd);
3311                 if (err < 0)
3312                         goto err_free;
3313                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3314         }
3315
3316         /* Copy panel suspend cmd */
3317         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3318                                         p_dsi->n_suspend_cmd);
3319         if (err < 0)
3320                 goto err_free;
3321         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3322
3323         if (!dsi->info.panel_reset_timeout_msec)
3324                 dsi->info.panel_reset_timeout_msec =
3325                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3326
3327         if (!dsi->info.panel_buffer_size_byte)
3328                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3329
3330         if (!dsi->info.max_panel_freq_khz) {
3331                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3332
3333                 if (dsi->info.video_burst_mode >
3334                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3335                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3336                                         "is not set for DSI burst mode.\n");
3337                         dsi->info.video_burst_mode =
3338                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3339                 }
3340         }
3341
3342         if (!dsi->info.lp_cmd_mode_freq_khz)
3343                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3344
3345         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3346                 dev_warn(&dsi->dc->ndev->dev,
3347                         "DSI: Failed to get chip info\n");
3348
3349         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3350                 dsi->info.lp_read_cmd_mode_freq_khz =
3351                         dsi->info.lp_cmd_mode_freq_khz;
3352
3353         /* host mode is for testing only */
3354         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3355         return 0;
3356
3357 err_free:
3358         kfree(p_suspend_cmd);
3359 err_free_p_late_resume_cmd:
3360         kfree(p_late_resume_cmd);
3361 err_free_p_early_suspend_cmd:
3362         kfree(p_early_suspend_cmd);
3363 err_free_init_cmd:
3364         kfree(p_init_cmd);
3365         return err;
3366 }
3367
3368 /* returns next null enumeration from  tegra_dsi_instance */
3369 static inline int tegra_dsi_get_enumeration(void)
3370 {
3371         int i = 0;
3372         for (; i < MAX_DSI_INSTANCE; i++) {
3373                 if (!tegra_dsi_instance[i])
3374                         return i;
3375         }
3376         return -EINVAL;
3377 }
3378
3379 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3380 {
3381         struct tegra_dc_dsi_data *dsi;
3382         struct resource *res;
3383         struct resource *base_res;
3384         void __iomem *base;
3385         struct clk *dc_clk = NULL;
3386         struct clk *dsi_clk = NULL;
3387         struct clk *dsi_fixed_clk = NULL;
3388         struct tegra_dsi_out *dsi_pdata;
3389         int err = 0;
3390         int dsi_enum = -1;
3391
3392         dsi_enum = tegra_dsi_get_enumeration();
3393         if (dsi_enum < 0) {
3394                 err = -EINVAL;
3395                 dev_err(&dc->ndev->dev, "dsi: invalid enum retured\n");
3396                 return err;
3397         }
3398
3399         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3400         if (!dsi) {
3401                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3402                 return -ENOMEM;
3403         }
3404         tegra_dsi_instance[dsi_enum] = dsi;
3405
3406         if (dc->out->dsi->ganged_type) {
3407                 if (dsi_enum)
3408                         res = nvhost_get_resource_byname(dc->ndev,
3409                                                 IORESOURCE_MEM,
3410                                                 "ganged_dsib_regs");
3411                 else
3412                         res = nvhost_get_resource_byname(dc->ndev,
3413                                                 IORESOURCE_MEM,
3414                                                 "ganged_dsia_regs");
3415         } else {
3416                 res = nvhost_get_resource_byname(dc->ndev,
3417                                         IORESOURCE_MEM,
3418                                         "dsi_regs");
3419         }
3420
3421         if (!res) {
3422                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3423                 err = -ENOENT;
3424                 goto err_free_dsi;
3425         }
3426
3427         base_res = request_mem_region(res->start, resource_size(res),
3428                                 dc->ndev->name);
3429         if (!base_res) {
3430                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3431                 err = -EBUSY;
3432                 goto err_free_dsi;
3433         }
3434
3435         base = ioremap(res->start, resource_size(res));
3436         if (!base) {
3437                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3438                 err = -EBUSY;
3439                 goto err_release_regs;
3440         }
3441
3442         dsi_pdata = dc->pdata->default_out->dsi;
3443         if (!dsi_pdata) {
3444                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
3445                 goto err_release_regs;
3446         }
3447
3448         if (dsi_enum)
3449                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3450         else
3451                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3452
3453         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3454
3455         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3456                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3457                 err = -EBUSY;
3458                 goto err_release_regs;
3459         }
3460
3461         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3462         if (IS_ERR_OR_NULL(dc_clk)) {
3463                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3464                         dev_name(&dc->ndev->dev));
3465                 err = -EBUSY;
3466                 goto err_clk_put;
3467         }
3468
3469         mutex_init(&dsi->lock);
3470         dsi->controller_index = dsi_enum;
3471         dsi->dc = dc;
3472         dsi->base = base;
3473         dsi->base_res = base_res;
3474         dsi->dc_clk = dc_clk;
3475         dsi->dsi_clk = dsi_clk;
3476         dsi->dsi_fixed_clk = dsi_fixed_clk;
3477
3478         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3479         if (err < 0)
3480                 goto err_dsi_data;
3481
3482         tegra_dc_set_outdata(dc, dsi);
3483         __tegra_dc_dsi_init(dc);
3484
3485         return 0;
3486
3487 err_dsi_data:
3488 err_clk_put:
3489         clk_put(dsi_clk);
3490         clk_put(dsi_fixed_clk);
3491 err_release_regs:
3492         release_resource(base_res);
3493 err_free_dsi:
3494         kfree(dsi);
3495
3496         return err;
3497 }
3498
3499 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
3500 {
3501         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3502         u16 i;
3503         u32 val;
3504
3505         mutex_lock(&dsi->lock);
3506
3507         if (dsi->out_ops && dsi->out_ops->destroy)
3508                 dsi->out_ops->destroy(dsi);
3509
3510         /* free up the pdata */
3511         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3512                 if (dsi->info.dsi_init_cmd[i].pdata)
3513                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3514         }
3515         kfree(dsi->info.dsi_init_cmd);
3516
3517         /* Disable dc stream */
3518         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3519                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3520
3521         /* Disable dsi phy clock */
3522         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3523                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3524
3525         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3526         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3527
3528         iounmap(dsi->base);
3529         release_resource(dsi->base_res);
3530
3531         clk_put(dsi->dc_clk);
3532         clk_put(dsi->dsi_clk);
3533
3534         mutex_unlock(&dsi->lock);
3535
3536         mutex_destroy(&dsi->lock);
3537         kfree(dsi);
3538 }
3539
3540 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3541                                                         u32 settings)
3542 {
3543         struct clk *parent_clk = NULL;
3544         struct clk *base_clk = NULL;
3545
3546         /* Disable dsi fast and slow clock */
3547         parent_clk = clk_get_parent(dsi->dsi_clk);
3548         base_clk = clk_get_parent(parent_clk);
3549         if (dsi->info.dsi_instance)
3550                 tegra_clk_cfg_ex(base_clk,
3551                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3552                                 settings);
3553         else
3554                 tegra_clk_cfg_ex(base_clk,
3555                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3556                                 settings);
3557 }
3558
3559 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
3560                                 struct tegra_dc_dsi_data *dsi, u32 suspend_aggr)
3561 {
3562         int val = 0;
3563         int err = 0;
3564
3565         if (!dsi->enabled) {
3566                 err = -EPERM;
3567                 goto fail;
3568         }
3569
3570         switch (suspend_aggr) {
3571         case DSI_SUSPEND_FULL:
3572                 /* Suspend DSI panel */
3573                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3574                 if (err < 0) {
3575                         dev_err(&dc->ndev->dev,
3576                         "DSI failed to go to LP mode\n");
3577                         goto fail;
3578                 }
3579
3580                 err = tegra_dsi_send_panel_cmd(dc, dsi,
3581                                 dsi->info.dsi_suspend_cmd,
3582                                 dsi->info.n_suspend_cmd);
3583                 /*
3584                  * Certain panels need dc frames be sent after
3585                  * putting panel to sleep.
3586                  */
3587                 if (dsi->info.panel_send_dc_frames)
3588                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3589
3590                 if (err < 0) {
3591                         dev_err(&dc->ndev->dev,
3592                                 "dsi: Error sending suspend cmd\n");
3593                         goto fail;
3594                 }
3595         case DSI_HOST_SUSPEND_LV2:
3596                 /* Set DSI to ULPM and suspend pads. DSI will be set to the
3597                  * lowest power state in this level. */
3598                 if (!dsi->ulpm) {
3599                         err = tegra_dsi_enter_ulpm(dsi);
3600                         if (err < 0) {
3601                                 dev_err(&dc->ndev->dev,
3602                                         "DSI failed to enter ulpm\n");
3603                                 goto fail;
3604                         }
3605                 }
3606
3607                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3608                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3609                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
3610                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3611
3612                 /* Suspend core-logic */
3613                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3614                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3615         case DSI_HOST_SUSPEND_LV1:
3616                 /* Disable dsi fast and slow clock */
3617                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3618         case DSI_HOST_SUSPEND_LV0:
3619                 /* Disable dsi source clock */
3620                 tegra_dsi_clk_disable(dsi);
3621                 break;
3622         case DSI_NO_SUSPEND:
3623                 break;
3624         default:
3625                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3626                                                 "is not supported.\n");
3627         }
3628
3629         dsi->enabled = false;
3630
3631         return 0;
3632 fail:
3633         return err;
3634 }
3635
3636 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
3637 {
3638         int err = 0;
3639         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3640
3641         if (dsi->host_suspended)
3642                 return 0;
3643
3644         dsi->host_suspended = true;
3645
3646         tegra_dsi_stop_dc_stream(dc, dsi);
3647
3648         err = tegra_dsi_deep_sleep(dc, dsi, dsi->info.suspend_aggr);
3649         if (err < 0)
3650                 dev_err(&dc->ndev->dev,
3651                         "DSI failed to enter deep sleep\n");
3652
3653         tegra_dc_clk_disable(dc);
3654
3655         return err;
3656 }
3657
3658 static int tegra_dsi_host_resume(struct tegra_dc *dc)
3659 {
3660         int val = 0;
3661         int err = 0;
3662         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3663
3664         if (!dsi->host_suspended)
3665                 return 0;
3666
3667         tegra_dc_clk_enable(dc);
3668         switch (dsi->info.suspend_aggr) {
3669         case DSI_HOST_SUSPEND_LV0:
3670                 tegra_dsi_clk_enable(dsi);
3671                 break;
3672         case DSI_HOST_SUSPEND_LV1:
3673                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3674                 tegra_dsi_clk_enable(dsi);
3675                 break;
3676         case DSI_HOST_SUSPEND_LV2:
3677                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3678                 tegra_dsi_clk_enable(dsi);
3679
3680                 tegra_dsi_writel(dsi,
3681                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3682                         DSI_POWER_CONTROL);
3683
3684                 if (dsi->ulpm) {
3685                         err = tegra_dsi_enter_ulpm(dsi);
3686                         if (err < 0) {
3687                                 dev_err(&dc->ndev->dev,
3688                                         "DSI failed to enter ulpm\n");
3689                                 goto fail;
3690                         }
3691
3692                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3693                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3694                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3695                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3696                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3697
3698                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3699                                 dev_err(&dc->ndev->dev,
3700                                         "DSI failed to exit ulpm\n");
3701                                 goto fail;
3702                         }
3703                 }
3704                 break;
3705         case DSI_NO_SUSPEND:
3706                 break;
3707         default:
3708                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3709                                                 "is not supported.\n");
3710         }
3711
3712         tegra_dsi_start_dc_stream(dc, dsi);
3713         dsi->enabled = true;
3714         dsi->host_suspended = false;
3715 fail:
3716         return err;
3717 }
3718
3719 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
3720 {
3721         int err;
3722         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3723
3724         tegra_dc_io_start(dc);
3725         mutex_lock(&dsi->lock);
3726
3727         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3728                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
3729
3730         if (dsi->out_ops && dsi->out_ops->disable)
3731                 dsi->out_ops->disable(dsi);
3732
3733         if (dsi->info.power_saving_suspend) {
3734                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3735                         dev_err(&dc->ndev->dev,
3736                                 "DSI failed to enter deep sleep\n");
3737                         goto fail;
3738                 }
3739         } else {
3740                 if (dsi->info.dsi_early_suspend_cmd) {
3741                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3742                                 dsi->info.dsi_early_suspend_cmd,
3743                                 dsi->info.n_early_suspend_cmd);
3744                         if (err < 0) {
3745                                 dev_err(&dc->ndev->dev,
3746                                 "dsi: Error sending early suspend cmd\n");
3747                                 goto fail;
3748                         }
3749                 }
3750
3751                 if (!dsi->ulpm) {
3752                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3753                                 dev_err(&dc->ndev->dev,
3754                                         "DSI failed to enter ulpm\n");
3755                                 goto fail;
3756                         }
3757                 }
3758         }
3759
3760 fail:
3761         mutex_unlock(&dsi->lock);
3762         tegra_dc_io_end(dc);
3763 }
3764
3765 #ifdef CONFIG_PM
3766 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
3767 {
3768         struct tegra_dc_dsi_data *dsi;
3769
3770         dsi = tegra_dc_get_outdata(dc);
3771
3772         if (!dsi->enabled)
3773                 return;
3774
3775         tegra_dc_io_start(dc);
3776         mutex_lock(&dsi->lock);
3777
3778         if (dsi->out_ops && dsi->out_ops->suspend)
3779                 dsi->out_ops->suspend(dsi);
3780
3781         if (!dsi->info.power_saving_suspend) {
3782                 if (dsi->ulpm) {
3783                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3784                                 dev_err(&dc->ndev->dev,
3785                                         "DSI failed to exit ulpm");
3786                                 goto fail;
3787                         }
3788                 }
3789
3790                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3791                         dev_err(&dc->ndev->dev,
3792                                 "DSI failed to enter deep sleep\n");
3793                         goto fail;
3794                 }
3795         }
3796 fail:
3797         mutex_unlock(&dsi->lock);
3798         tegra_dc_io_end(dc);
3799 }
3800
3801 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
3802 {
3803         struct tegra_dc_dsi_data *dsi;
3804
3805         dsi = tegra_dc_get_outdata(dc);
3806
3807         /* No dsi config required since tegra_dc_dsi_enable
3808          * will reconfigure the controller from scratch
3809          */
3810
3811          if (dsi->out_ops && dsi->out_ops->resume)
3812                 dsi->out_ops->resume(dsi);
3813 }
3814
3815 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
3816 {
3817         _tegra_dc_dsi_suspend(dc);
3818
3819         if (dc->out->dsi->ganged_type) {
3820                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3821                 _tegra_dc_dsi_suspend(dc);
3822                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3823         }
3824 }
3825
3826 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3827 {
3828         _tegra_dc_dsi_resume(dc);
3829
3830         if (dc->out->dsi->ganged_type) {
3831                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3832                 _tegra_dc_dsi_resume(dc);
3833                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3834         }
3835 }
3836 #endif
3837
3838 static int tegra_dc_dsi_init(struct tegra_dc *dc)
3839 {
3840         int err = 0;
3841
3842         err = _tegra_dc_dsi_init(dc);
3843         if (err < 0) {
3844                 dev_err(&dc->ndev->dev,
3845                         "dsi: Instance A init failed\n");
3846                 goto fail;
3847         }
3848
3849         if (dc->out->dsi->ganged_type) {
3850                 err = _tegra_dc_dsi_init(dc);
3851                 if (err < 0) {
3852                         dev_err(&dc->ndev->dev,
3853                                 "dsi: Instance B init failed\n");
3854                         goto fail;
3855                 }
3856                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3857         }
3858 fail:
3859         return err;
3860 }
3861
3862 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
3863 {
3864         _tegra_dc_dsi_destroy(dc);
3865
3866         if (dc->out->dsi->ganged_type) {
3867                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3868                 _tegra_dc_dsi_destroy(dc);
3869                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3870         }
3871 }
3872
3873 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
3874 {
3875         _tegra_dc_dsi_enable(dc);
3876
3877         if (dc->out->dsi->ganged_type) {
3878                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3879                 _tegra_dc_dsi_enable(dc);
3880                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3881         }
3882 }
3883
3884 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
3885         .init = tegra_dc_dsi_init,
3886         .destroy = tegra_dc_dsi_destroy,
3887         .enable = tegra_dc_dsi_enable,
3888         .disable = tegra_dc_dsi_disable,
3889         .hold = tegra_dc_dsi_hold_host,
3890         .release = tegra_dc_dsi_release_host,
3891         .idle = tegra_dc_dsi_idle,
3892 #ifdef CONFIG_PM
3893         .suspend = tegra_dc_dsi_suspend,
3894         .resume = tegra_dc_dsi_resume,
3895 #endif
3896 };