2 * drivers/video/tegra/dc/dc_priv.h
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_H
19 #define __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_H
22 #include <linux/mutex.h>
23 #include <linux/wait.h>
24 #include <linux/completion.h>
25 #include <linux/switch.h>
29 #include "../host/dev.h"
30 #include "../host/host1x/host1x_syncpt.h"
32 #include <mach/tegra_dc_ext.h>
34 #define WIN_IS_TILED(win) ((win)->flags & TEGRA_WIN_FLAG_TILED)
35 #define WIN_IS_ENABLED(win) ((win)->flags & TEGRA_WIN_FLAG_ENABLED)
37 #define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0)
39 /* DDR: 8 bytes transfer per clock */
40 #define DDR_BW_TO_FREQ(bw) ((bw) / 8)
42 #if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
43 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
45 #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
50 struct tegra_dc_blend {
51 unsigned z[DC_N_WINDOWS];
52 unsigned flags[DC_N_WINDOWS];
55 struct tegra_dc_out_ops {
56 /* initialize output. dc clocks are not on at this point */
57 int (*init)(struct tegra_dc *dc);
58 /* destroy output. dc clocks are not on at this point */
59 void (*destroy)(struct tegra_dc *dc);
60 /* detect connected display. can sleep.*/
61 bool (*detect)(struct tegra_dc *dc);
62 /* enable output. dc clocks are on at this point */
63 void (*enable)(struct tegra_dc *dc);
64 /* disable output. dc clocks are on at this point */
65 void (*disable)(struct tegra_dc *dc);
67 /* suspend output. dc clocks are on at this point */
68 void (*suspend)(struct tegra_dc *dc);
69 /* resume output. dc clocks are on at this point */
70 void (*resume)(struct tegra_dc *dc);
74 struct nvhost_device *ndev;
75 struct tegra_dc_platform_data *pdata;
77 struct resource *base_res;
91 struct tegra_dc_out *out;
92 struct tegra_dc_out_ops *out_ops;
95 struct tegra_dc_mode mode;
97 struct tegra_dc_win windows[DC_N_WINDOWS];
98 struct tegra_dc_blend blend;
101 wait_queue_head_t wq;
105 struct resource *fb_mem;
106 struct tegra_fb_info *fb;
108 struct tegra_overlay_info *overlay;
114 } syncpt[DC_N_WINDOWS];
117 unsigned long underflow_mask;
118 struct work_struct reset_work;
121 struct switch_dev modeset_switch;
124 struct completion frame_end_complete;
126 struct work_struct vblank_work;
135 struct tegra_dc_ext *ext;
137 #ifdef CONFIG_DEBUG_FS
138 struct dentry *debugdir;
140 struct tegra_dc_lut fb_lut;
143 static inline void tegra_dc_io_start(struct tegra_dc *dc)
145 nvhost_module_busy(dc->ndev->host->dev);
148 static inline void tegra_dc_io_end(struct tegra_dc *dc)
150 nvhost_module_idle(dc->ndev->host->dev);
153 static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
156 BUG_ON(!nvhost_module_powered(dc->ndev->host->dev));
157 return readl(dc->base + reg * 4);
160 static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long val,
163 BUG_ON(!nvhost_module_powered(dc->ndev->host->dev));
164 writel(val, dc->base + reg * 4);
167 static inline void _tegra_dc_write_table(struct tegra_dc *dc, const u32 *table,
172 for (i = 0; i < len; i++)
173 tegra_dc_writel(dc, table[i * 2 + 1], table[i * 2]);
176 #define tegra_dc_write_table(dc, table) \
177 _tegra_dc_write_table(dc, table, ARRAY_SIZE(table) / 2)
179 static inline void tegra_dc_set_outdata(struct tegra_dc *dc, void *data)
184 static inline void *tegra_dc_get_outdata(struct tegra_dc *dc)
189 static inline unsigned long tegra_dc_get_default_emc_clk_rate(
192 return dc->pdata->emc_clk_rate ? dc->pdata->emc_clk_rate : ULONG_MAX;
195 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk);
197 extern struct tegra_dc_out_ops tegra_dc_rgb_ops;
198 extern struct tegra_dc_out_ops tegra_dc_hdmi_ops;
199 extern struct tegra_dc_out_ops tegra_dc_dsi_ops;
201 /* defined in dc_sysfs.c, used by dc.c */
202 void __devexit tegra_dc_remove_sysfs(struct device *dev);
203 void tegra_dc_create_sysfs(struct device *dev);
205 /* defined in dc.c, used by dc_sysfs.c */
206 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable);
207 bool tegra_dc_stats_get(struct tegra_dc *dc);
209 /* defined in dc.c, used by overlay.c */
210 unsigned int tegra_dc_has_multiple_dc(void);
211 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *wins[], int n);
213 /* defined in dc.c, used by dc_sysfs.c */
214 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc);
215 void tegra_dc_enable_crc(struct tegra_dc *dc);
216 void tegra_dc_disable_crc(struct tegra_dc *dc);
218 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
219 const struct tegra_dc_out_pin *pins,
220 const unsigned int n_pins);