video: tegra: dc: Add dc backup clock source support
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134         case TEGRA_WIN_FMT_YCbCr422R:
135         case TEGRA_WIN_FMT_YUV422R:
136         case TEGRA_WIN_FMT_YCbCr422RA:
137         case TEGRA_WIN_FMT_YUV422RA:
138                 return 8;
139
140         case TEGRA_WIN_FMT_YCbCr422:
141         case TEGRA_WIN_FMT_YUV422:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155         case TEGRA_WIN_FMT_YCbCr422R:
156         case TEGRA_WIN_FMT_YUV422R:
157         case TEGRA_WIN_FMT_YCbCr422RA:
158         case TEGRA_WIN_FMT_YUV422RA:
159                 return true;
160         }
161         return false;
162 }
163
164 #define DUMP_REG(a) do {                        \
165         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
166                  #a, a, tegra_dc_readl(dc, a));               \
167         print(data, buff);                                    \
168         } while (0)
169
170 static void _dump_regs(struct tegra_dc *dc, void *data,
171                        void (* print)(void *data, const char *str))
172 {
173         int i;
174         char buff[256];
175
176         tegra_dc_io_start(dc);
177         clk_enable(dc->clk);
178
179         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
180         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
181         DUMP_REG(DC_CMD_SIGNAL_RAISE);
182         DUMP_REG(DC_CMD_INT_STATUS);
183         DUMP_REG(DC_CMD_INT_MASK);
184         DUMP_REG(DC_CMD_INT_ENABLE);
185         DUMP_REG(DC_CMD_INT_TYPE);
186         DUMP_REG(DC_CMD_INT_POLARITY);
187         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
188         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
190         DUMP_REG(DC_CMD_STATE_ACCESS);
191         DUMP_REG(DC_CMD_STATE_CONTROL);
192         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
193         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
194
195         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
196         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
197         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
198         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
199         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
200         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
201         DUMP_REG(DC_DISP_REF_TO_SYNC);
202         DUMP_REG(DC_DISP_SYNC_WIDTH);
203         DUMP_REG(DC_DISP_BACK_PORCH);
204         DUMP_REG(DC_DISP_DISP_ACTIVE);
205         DUMP_REG(DC_DISP_FRONT_PORCH);
206         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
211         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
212         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
213         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
216         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
217         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
218         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
221         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
229         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
230         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
231         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
233         DUMP_REG(DC_DISP_M0_CONTROL);
234         DUMP_REG(DC_DISP_M1_CONTROL);
235         DUMP_REG(DC_DISP_DI_CONTROL);
236         DUMP_REG(DC_DISP_PP_CONTROL);
237         DUMP_REG(DC_DISP_PP_SELECT_A);
238         DUMP_REG(DC_DISP_PP_SELECT_B);
239         DUMP_REG(DC_DISP_PP_SELECT_C);
240         DUMP_REG(DC_DISP_PP_SELECT_D);
241         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
242         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
243         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
244         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
245         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
246         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
247         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
248         DUMP_REG(DC_DISP_BORDER_COLOR);
249         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
250         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
251         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
253         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
254         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
255         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
256         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
257         DUMP_REG(DC_DISP_CURSOR_POSITION);
258         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
259         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
260         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
261         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
264         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
265         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
266         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
269         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
270         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
271
272
273         for (i = 0; i < 3; i++) {
274                 print(data, "\n");
275                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
276                 print(data, buff);
277
278                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
279                                 DC_CMD_DISPLAY_WINDOW_HEADER);
280                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
281                 DUMP_REG(DC_WIN_WIN_OPTIONS);
282                 DUMP_REG(DC_WIN_BYTE_SWAP);
283                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
284                 DUMP_REG(DC_WIN_COLOR_DEPTH);
285                 DUMP_REG(DC_WIN_POSITION);
286                 DUMP_REG(DC_WIN_SIZE);
287                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
288                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
289                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
290                 DUMP_REG(DC_WIN_DDA_INCREMENT);
291                 DUMP_REG(DC_WIN_LINE_STRIDE);
292                 DUMP_REG(DC_WIN_BUF_STRIDE);
293                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
294                 DUMP_REG(DC_WIN_BLEND_NOKEY);
295                 DUMP_REG(DC_WIN_BLEND_1WIN);
296                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
297                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
298                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
299                 DUMP_REG(DC_WINBUF_START_ADDR);
300                 DUMP_REG(DC_WINBUF_START_ADDR_U);
301                 DUMP_REG(DC_WINBUF_START_ADDR_V);
302                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
303                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
304                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
305                 DUMP_REG(DC_WIN_CSC_YOF);
306                 DUMP_REG(DC_WIN_CSC_KYRGB);
307                 DUMP_REG(DC_WIN_CSC_KUR);
308                 DUMP_REG(DC_WIN_CSC_KVR);
309                 DUMP_REG(DC_WIN_CSC_KUG);
310                 DUMP_REG(DC_WIN_CSC_KVG);
311                 DUMP_REG(DC_WIN_CSC_KUB);
312                 DUMP_REG(DC_WIN_CSC_KVB);
313         }
314
315         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
316         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
317         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
318         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
319         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
321         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
322         DUMP_REG(DC_DISP_M1_CONTROL);
323         DUMP_REG(DC_COM_PM1_CONTROL);
324         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
325         DUMP_REG(DC_DISP_SD_CONTROL);
326
327         clk_disable(dc->clk);
328         tegra_dc_io_end(dc);
329 }
330
331 #undef DUMP_REG
332
333 #ifdef DEBUG
334 static void dump_regs_print(void *data, const char *str)
335 {
336         struct tegra_dc *dc = data;
337         dev_dbg(&dc->ndev->dev, "%s", str);
338 }
339
340 static void dump_regs(struct tegra_dc *dc)
341 {
342         _dump_regs(dc, dc, dump_regs_print);
343 }
344 #else /* !DEBUG */
345
346 static void dump_regs(struct tegra_dc *dc) {}
347
348 #endif /* DEBUG */
349
350 #ifdef CONFIG_DEBUG_FS
351
352 static void dbg_regs_print(void *data, const char *str)
353 {
354         struct seq_file *s = data;
355
356         seq_printf(s, "%s", str);
357 }
358
359 #undef DUMP_REG
360
361 static int dbg_dc_show(struct seq_file *s, void *unused)
362 {
363         struct tegra_dc *dc = s->private;
364
365         _dump_regs(dc, s, dbg_regs_print);
366
367         return 0;
368 }
369
370
371 static int dbg_dc_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_show, inode->i_private);
374 }
375
376 static const struct file_operations regs_fops = {
377         .open           = dbg_dc_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386         struct tegra_dc_mode *m;
387
388         mutex_lock(&dc->lock);
389         m = &dc->mode;
390         seq_printf(s,
391                 "pclk: %d\n"
392                 "h_ref_to_sync: %d\n"
393                 "v_ref_to_sync: %d\n"
394                 "h_sync_width: %d\n"
395                 "v_sync_width: %d\n"
396                 "h_back_porch: %d\n"
397                 "v_back_porch: %d\n"
398                 "h_active: %d\n"
399                 "v_active: %d\n"
400                 "h_front_porch: %d\n"
401                 "v_front_porch: %d\n"
402                 "stereo_mode: %d\n",
403                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
404                 m->h_sync_width, m->v_sync_width,
405                 m->h_back_porch, m->v_back_porch,
406                 m->h_active, m->v_active,
407                 m->h_front_porch, m->v_front_porch,
408                 m->stereo_mode);
409         mutex_unlock(&dc->lock);
410         return 0;
411 }
412
413 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
414 {
415         return single_open(file, dbg_dc_mode_show, inode->i_private);
416 }
417
418 static const struct file_operations mode_fops = {
419         .open           = dbg_dc_mode_open,
420         .read           = seq_read,
421         .llseek         = seq_lseek,
422         .release        = single_release,
423 };
424
425 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
426 {
427         struct tegra_dc *dc = s->private;
428
429         mutex_lock(&dc->lock);
430         seq_printf(s,
431                 "underflows: %llu\n"
432                 "underflows_a: %llu\n"
433                 "underflows_b: %llu\n"
434                 "underflows_c: %llu\n",
435                 dc->stats.underflows,
436                 dc->stats.underflows_a,
437                 dc->stats.underflows_b,
438                 dc->stats.underflows_c);
439         mutex_unlock(&dc->lock);
440
441         return 0;
442 }
443
444 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
445 {
446         return single_open(file, dbg_dc_stats_show, inode->i_private);
447 }
448
449 static const struct file_operations stats_fops = {
450         .open           = dbg_dc_stats_open,
451         .read           = seq_read,
452         .llseek         = seq_lseek,
453         .release        = single_release,
454 };
455
456 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
457 {
458         if (dc->debugdir)
459                 debugfs_remove_recursive(dc->debugdir);
460         dc->debugdir = NULL;
461 }
462
463 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
464 {
465         struct dentry *retval;
466
467         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
468         if (!dc->debugdir)
469                 goto remove_out;
470
471         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
472                 &regs_fops);
473         if (!retval)
474                 goto remove_out;
475
476         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
477                 &mode_fops);
478         if (!retval)
479                 goto remove_out;
480
481         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
482                 &stats_fops);
483         if (!retval)
484                 goto remove_out;
485
486         return;
487 remove_out:
488         dev_err(&dc->ndev->dev, "could not create debugfs\n");
489         tegra_dc_remove_debugfs(dc);
490 }
491
492 #else /* !CONFIG_DEBUGFS */
493 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
494 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
495 #endif /* CONFIG_DEBUGFS */
496
497 static int tegra_dc_set(struct tegra_dc *dc, int index)
498 {
499         int ret = 0;
500
501         mutex_lock(&tegra_dc_lock);
502         if (index >= TEGRA_MAX_DC) {
503                 ret = -EINVAL;
504                 goto out;
505         }
506
507         if (dc != NULL && tegra_dcs[index] != NULL) {
508                 ret = -EBUSY;
509                 goto out;
510         }
511
512         tegra_dcs[index] = dc;
513
514 out:
515         mutex_unlock(&tegra_dc_lock);
516
517         return ret;
518 }
519
520 unsigned int tegra_dc_has_multiple_dc(void)
521 {
522         unsigned int idx;
523         unsigned int cnt = 0;
524         struct tegra_dc *dc;
525
526         mutex_lock(&tegra_dc_lock);
527         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
528                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
529         mutex_unlock(&tegra_dc_lock);
530
531         return (cnt > 1);
532 }
533
534 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
535 {
536         if (idx < TEGRA_MAX_DC)
537                 return tegra_dcs[idx];
538         else
539                 return NULL;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_dc);
542
543 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
544 {
545         if (win >= dc->n_windows)
546                 return NULL;
547
548         return &dc->windows[win];
549 }
550 EXPORT_SYMBOL(tegra_dc_get_window);
551
552 static int get_topmost_window(u32 *depths, unsigned long *wins)
553 {
554         int idx, best = -1;
555
556         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
557                 if (best == -1 || depths[idx] < depths[best])
558                         best = idx;
559         }
560         clear_bit(best, wins);
561         return best;
562 }
563
564 bool tegra_dc_get_connected(struct tegra_dc *dc)
565 {
566         return dc->connected;
567 }
568 EXPORT_SYMBOL(tegra_dc_get_connected);
569
570 static u32 blend_topwin(u32 flags)
571 {
572         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
573                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
574         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
575                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
576         else
577                 return BLEND(NOKEY, FIX, 0xff, 0xff);
578 }
579
580 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
581 {
582         int other;
583
584         for (other = 0; other < DC_N_WINDOWS; other++) {
585                 if (other != idx && (xy-- == 0))
586                         break;
587         }
588         if (BIT(other) & behind_mask)
589                 return blend_topwin(flags[idx]);
590         else if (flags[other])
591                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
592         else
593                 return BLEND(NOKEY, FIX, 0x00, 0x00);
594 }
595
596 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
597 {
598         unsigned long infront_mask;
599         int first;
600
601         infront_mask = ~(behind_mask | BIT(idx));
602         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
603         first = ffs(infront_mask) - 1;
604
605         if (!infront_mask)
606                 return blend_topwin(flags[idx]);
607         else if (behind_mask && first != -1 && flags[first])
608                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
609         else
610                 return BLEND(NOKEY, FIX, 0x0, 0x0);
611 }
612
613 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
614 {
615         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
616
617         while (mask) {
618                 int idx = get_topmost_window(blend->z, &mask);
619
620                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
621                                 DC_CMD_DISPLAY_WINDOW_HEADER);
622                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
623                                 DC_WIN_BLEND_NOKEY);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_1WIN);
626                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
627                                 DC_WIN_BLEND_2WIN_X);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
629                                 DC_WIN_BLEND_2WIN_Y);
630                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
631                                 DC_WIN_BLEND_3WIN_XY);
632         }
633 }
634
635 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 {
637         csc->yof   = 0x00f0;
638         csc->kyrgb = 0x012a;
639         csc->kur   = 0x0000;
640         csc->kvr   = 0x0198;
641         csc->kug   = 0x039b;
642         csc->kvg   = 0x032f;
643         csc->kub   = 0x0204;
644         csc->kvb   = 0x0000;
645 }
646
647 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
648 {
649         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
650         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
651         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
652         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
653         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
654         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
655         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
656         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
657 }
658
659 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
660 {
661         mutex_lock(&dc->lock);
662
663         if (!dc->enabled) {
664                 mutex_unlock(&dc->lock);
665                 return -EFAULT;
666         }
667
668         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
669                         DC_CMD_DISPLAY_WINDOW_HEADER);
670
671         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
672
673         mutex_unlock(&dc->lock);
674
675         return 0;
676 }
677 EXPORT_SYMBOL(tegra_dc_update_csc);
678
679 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
680 {
681         int i;
682         for (i = 0; i < 256; i++)
683                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
684 }
685
686 static int tegra_dc_loop_lut(struct tegra_dc *dc,
687                              struct tegra_dc_win *win,
688                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
689 {
690         struct tegra_dc_lut *lut = &win->lut;
691         struct tegra_dc_lut *global_lut = &dc->fb_lut;
692         int i;
693         for (i = 0; i < 256; i++) {
694
695                 u32 r = (u32)lut->r[i];
696                 u32 g = (u32)lut->g[i];
697                 u32 b = (u32)lut->b[i];
698
699                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
700                         r = (u32)global_lut->r[r];
701                         g = (u32)global_lut->g[g];
702                         b = (u32)global_lut->b[b];
703                 }
704
705                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
706                         return 0;
707         }
708         return 1;
709 }
710
711 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
712 {
713         if (rgb != (i | (i<<8) | (i<<16)))
714                 return 0;
715         return 1;
716 }
717
718 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
719 {
720         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
721         return 1;
722 }
723
724 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
725 {
726         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
727
728         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
729
730         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
731                 val |= CP_ENABLE;
732         else
733                 val &= ~CP_ENABLE;
734
735         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
736 }
737
738 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
739 {
740         struct tegra_dc_win *win = &dc->windows[win_idx];
741
742         mutex_lock(&dc->lock);
743
744         if (!dc->enabled) {
745                 mutex_unlock(&dc->lock);
746                 return -EFAULT;
747         }
748
749         if (fbovr > 0)
750                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
751         else if (fbovr == 0)
752                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753
754         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
756         else
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
758
759         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
760                         DC_CMD_DISPLAY_WINDOW_HEADER);
761
762         tegra_dc_set_lut(dc, win);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768
769 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
770 {
771         if (win_idx > -1)
772                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
773
774         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
775                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
776                 if (err)
777                         return err;
778         }
779
780         return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_update_lut);
783
784 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
785 {
786         unsigned i;
787         unsigned v0 = 128;
788         unsigned v1 = 0;
789         /* linear horizontal and vertical filters */
790         for (i = 0; i < 16; i++) {
791                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
792                                 DC_WIN_H_FILTER_P(i));
793
794                 tegra_dc_writel(dc, v0,
795                                 DC_WIN_V_FILTER_P(i));
796                 v0 -= 8;
797                 v1 += 8;
798         }
799 }
800
801 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
802         struct tegra_dc_win *w)
803 {
804         /* windows A, B, C for first and second display */
805         static const enum tegra_la_id la_id_tab[2][3] = {
806                 /* first display */
807                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
808                         TEGRA_LA_DISPLAY_0C },
809                 /* second display */
810                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
811                         TEGRA_LA_DISPLAY_0CB },
812         };
813         /* window B V-filter tap for first and second display. */
814         static const enum tegra_la_id vfilter_tab[2] = {
815                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
816         };
817         unsigned long bw;
818
819         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
820         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
821         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
822
823         bw = w->new_bandwidth;
824
825         /* tegra_dc_get_bandwidth() treats V filter windows as double
826          * bandwidth, but LA has a seperate client for V filter */
827         if (w->idx == 1 && win_use_v_filter(w))
828                 bw /= 2;
829
830         /* our bandwidth is in bytes/sec, but LA takes MBps.
831          * round up bandwidth to 1MBps */
832         bw = bw / 1000000 + 1;
833
834 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
835         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
836         /* if window B, also set the 1B client for the 2-tap V filter. */
837         if (w->idx == 1)
838                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
839 #endif
840
841         w->bandwidth = w->new_bandwidth;
842 }
843
844 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
845                                                    struct tegra_dc_win *b)
846 {
847         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
848                 return 0;
849
850         /* because memory access to load the fifo can overlap, only care
851          * if windows overlap vertically */
852         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
853                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
854 }
855
856 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
857                                                  int n)
858 {
859         unsigned i;
860         unsigned j;
861         unsigned overlap_count;
862         unsigned max_bw = 0;
863
864         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
865                          "inaccurate.\n");
866
867         /* If we had a large number of windows, we would compute adjacency
868          * graph representing 2 window overlaps, find all cliques in the graph,
869          * assign bandwidth to each clique, and then select the clique with
870          * maximum bandwidth. But because we have at most 3 windows,
871          * implementing proper Bron-Kerbosh algorithm would be an overkill,
872          * brute force will suffice.
873          *
874          * Thus: find maximum bandwidth for either single or a pair of windows
875          * and count number of window pair overlaps. If there are three
876          * pairs, all 3 window overlap.
877          */
878
879         overlap_count = 0;
880         for (i = 0; i < n; i++) {
881                 unsigned int bw1;
882
883                 if (wins[i] == NULL)
884                         continue;
885                 bw1 = wins[i]->new_bandwidth;
886                 if (bw1 > max_bw)
887                         /* Single window */
888                         max_bw = bw1;
889
890                 for (j = i + 1; j < n; j++) {
891                         if (wins[j] == NULL)
892                                 continue;
893                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
894                                 unsigned int bw2 = wins[j]->new_bandwidth;
895                                 if (bw1 + bw2 > max_bw)
896                                         /* Window pair overlaps */
897                                         max_bw = bw1 + bw2;
898                                 overlap_count++;
899                         }
900                 }
901         }
902
903         if (overlap_count == 3)
904                 /* All three windows overlap */
905                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
906                          wins[2]->new_bandwidth;
907
908         return max_bw;
909 }
910
911 /*
912  * Calculate peak EMC bandwidth for each enabled window =
913  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
914  * (windows_tiling ? 2 : 1)
915  *
916  *
917  * note:
918  * (*) We use 2 tap V filter, so need double BW if use V filter
919  * (*) Tiling mode on T30 and DDR3 requires double BW
920  */
921 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
922         struct tegra_dc_win *w)
923 {
924         unsigned long ret;
925         int tiled_windows_bw_multiplier;
926         unsigned long bpp;
927
928         if (!WIN_IS_ENABLED(w))
929                 return 0;
930
931         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
932             w->out_w == 0 || w->out_h == 0)
933                 return 0;
934
935         tiled_windows_bw_multiplier =
936                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
937
938         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
939          * but the size reported by tegra_dc_fmt_bpp for the planar version
940          * is of the luma plane's size only. */
941         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
942                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
943         /* perform calculations with most significant bits of pixel clock
944          * to prevent overflow of long. */
945         ret = (unsigned long)(dc->mode.pclk >> 16) *
946                 bpp / 8 *
947                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
948                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
949
950 /*
951  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
952  * will request 147MBps from EMC.
953  */
954         ret = ret * 2 + ret / 10;
955
956         /* if overflowed */
957         if (ret > (1UL << 31))
958                 return ULONG_MAX;
959
960         return ret << 16; /* restore the scaling we did above */
961 }
962
963 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
964 {
965         int i;
966
967         BUG_ON(n > DC_N_WINDOWS);
968
969         /* emc rate and latency allowance both need to know per window
970          * bandwidths */
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *w = windows[i];
973                 if (w)
974                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
975         }
976
977         return tegra_dc_find_max_bandwidth(windows, n);
978 }
979
980 /* to save power, call when display memory clients would be idle */
981 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
982 {
983         if (dc->emc_clk_rate)
984                 clk_disable(dc->emc_clk);
985         dc->emc_clk_rate = 0;
986 }
987
988 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
989 {
990         unsigned i;
991
992         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
993                 if (!dc->emc_clk_rate) /* going from 0 to non-zero */
994                         clk_enable(dc->emc_clk);
995                 dc->emc_clk_rate = dc->new_emc_clk_rate;
996                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
997         }
998
999         for (i = 0; i < DC_N_WINDOWS; i++) {
1000                 struct tegra_dc_win *w = &dc->windows[i];
1001                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1002                         tegra_dc_set_latency_allowance(dc, w);
1003         }
1004 }
1005
1006 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1007 {
1008         unsigned long new_rate;
1009         struct tegra_dc *dc;
1010
1011         if (!use_dynamic_emc)
1012                 return 0;
1013
1014         dc = windows[0]->dc;
1015
1016         /* calculate the new rate based on this POST */
1017         new_rate = tegra_dc_get_bandwidth(windows, n);
1018         new_rate = EMC_BW_TO_FREQ(new_rate);
1019
1020         if (tegra_dc_has_multiple_dc())
1021                 new_rate = ULONG_MAX;
1022
1023         dc->new_emc_clk_rate = new_rate;
1024
1025         return 0;
1026 }
1027
1028 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1029                                   bool v, unsigned Bpp)
1030 {
1031         /*
1032          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1033          *           (post_scaled_size_in_pixels - 1)), MAX)
1034          * Where the value of MAX is as follows:
1035          * For V_DDA_INCREMENT: 15.0 (0xF000)
1036          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1037          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1038          */
1039
1040         fixed20_12 out = dfixed_init(out_int);
1041         u32 dda_inc;
1042         int max;
1043
1044         if (v) {
1045                 max = 15;
1046         } else {
1047                 switch (Bpp) {
1048                 default:
1049                         WARN_ON_ONCE(1);
1050                         /* fallthrough */
1051                 case 4:
1052                         max = 4;
1053                         break;
1054                 case 2:
1055                         max = 8;
1056                         break;
1057                 }
1058         }
1059
1060         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1061         in.full -= dfixed_const(1);
1062
1063         dda_inc = dfixed_div(in, out);
1064
1065         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1066
1067         return dda_inc;
1068 }
1069
1070 static inline u32 compute_initial_dda(fixed20_12 in)
1071 {
1072         return dfixed_frac(in);
1073 }
1074
1075 /* does not support updating windows on multiple dcs in one call */
1076 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1077 {
1078         struct tegra_dc *dc;
1079         unsigned long update_mask = GENERAL_ACT_REQ;
1080         unsigned long val;
1081         bool update_blend = false;
1082         int i;
1083
1084         dc = windows[0]->dc;
1085
1086         mutex_lock(&dc->lock);
1087
1088         if (!dc->enabled) {
1089                 mutex_unlock(&dc->lock);
1090                 return -EFAULT;
1091         }
1092
1093         if (no_vsync)
1094                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1095         else
1096                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1097
1098         for (i = 0; i < n; i++) {
1099                 struct tegra_dc_win *win = windows[i];
1100                 unsigned h_dda;
1101                 unsigned v_dda;
1102                 fixed20_12 h_offset, v_offset;
1103                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1104                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1105                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1106                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1107                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1108                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1109                 const bool filter_h = win_use_h_filter(win);
1110                 const bool filter_v = win_use_v_filter(win);
1111
1112                 if (win->z != dc->blend.z[win->idx]) {
1113                         dc->blend.z[win->idx] = win->z;
1114                         update_blend = true;
1115                 }
1116                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1117                         dc->blend.flags[win->idx]) {
1118                         dc->blend.flags[win->idx] =
1119                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1120                         update_blend = true;
1121                 }
1122
1123                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1124                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1125
1126                 if (!no_vsync)
1127                         update_mask |= WIN_A_ACT_REQ << win->idx;
1128
1129                 if (!WIN_IS_ENABLED(win)) {
1130                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1131                         continue;
1132                 }
1133
1134                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1135                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1136
1137                 tegra_dc_writel(dc,
1138                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1139                                 DC_WIN_POSITION);
1140                 tegra_dc_writel(dc,
1141                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1142                                 DC_WIN_SIZE);
1143                 tegra_dc_writel(dc,
1144                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1145                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1146                                 DC_WIN_PRESCALED_SIZE);
1147
1148                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1149                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1150                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1151                                 DC_WIN_DDA_INCREMENT);
1152                 h_dda = compute_initial_dda(win->x);
1153                 v_dda = compute_initial_dda(win->y);
1154                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1155                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1156
1157                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1158                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1159                 tegra_dc_writel(dc,
1160                                 (unsigned long)win->phys_addr,
1161                                 DC_WINBUF_START_ADDR);
1162
1163                 if (!yuvp) {
1164                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1165                 } else {
1166                         tegra_dc_writel(dc,
1167                                         (unsigned long)win->phys_addr_u,
1168                                         DC_WINBUF_START_ADDR_U);
1169                         tegra_dc_writel(dc,
1170                                         (unsigned long)win->phys_addr_v,
1171                                         DC_WINBUF_START_ADDR_V);
1172                         tegra_dc_writel(dc,
1173                                         LINE_STRIDE(win->stride) |
1174                                         UV_LINE_STRIDE(win->stride_uv),
1175                                         DC_WIN_LINE_STRIDE);
1176                 }
1177
1178                 h_offset = win->x;
1179                 if (invert_h) {
1180                         h_offset.full += win->w.full - dfixed_const(1);
1181                 }
1182
1183                 v_offset = win->y;
1184                 if (invert_v) {
1185                         v_offset.full += win->h.full - dfixed_const(1);
1186                 }
1187
1188                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1189                                 DC_WINBUF_ADDR_H_OFFSET);
1190                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1191                                 DC_WINBUF_ADDR_V_OFFSET);
1192
1193                 if (WIN_IS_TILED(win))
1194                         tegra_dc_writel(dc,
1195                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1196                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1197                                         DC_WIN_BUFFER_ADDR_MODE);
1198                 else
1199                         tegra_dc_writel(dc,
1200                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1201                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1202                                         DC_WIN_BUFFER_ADDR_MODE);
1203
1204                 val = WIN_ENABLE;
1205                 if (yuvp)
1206                         val |= CSC_ENABLE;
1207                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1208                         val |= COLOR_EXPAND;
1209
1210                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1211                         val |= CP_ENABLE;
1212
1213                 if (filter_h)
1214                         val |= H_FILTER_ENABLE;
1215                 if (filter_v)
1216                         val |= V_FILTER_ENABLE;
1217
1218                 if (invert_h)
1219                         val |= H_DIRECTION_DECREMENT;
1220                 if (invert_v)
1221                         val |= V_DIRECTION_DECREMENT;
1222
1223                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1224
1225                 win->dirty = no_vsync ? 0 : 1;
1226
1227                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1228                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1229                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1230                         __func__, win->idx, win->z,
1231                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1232                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1233                         win->out_x, win->out_y, win->out_w, win->out_h,
1234                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1235         }
1236
1237         if (update_blend) {
1238                 tegra_dc_set_blending(dc, &dc->blend);
1239                 for (i = 0; i < DC_N_WINDOWS; i++) {
1240                         if (!no_vsync)
1241                                 dc->windows[i].dirty = 1;
1242                         update_mask |= WIN_A_ACT_REQ << i;
1243                 }
1244         }
1245
1246         tegra_dc_set_dynamic_emc(windows, n);
1247
1248         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1249
1250         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1251         if (!no_vsync) {
1252                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1253                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1254                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1255         } else {
1256                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1257                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1258                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1259         }
1260
1261         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1262
1263         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1264                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1265
1266         /* update EMC clock if calculated bandwidth has changed */
1267         tegra_dc_program_bandwidth(dc);
1268
1269         mutex_unlock(&dc->lock);
1270
1271         return 0;
1272 }
1273 EXPORT_SYMBOL(tegra_dc_update_windows);
1274
1275 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1276 {
1277         return dc->syncpt[i].id;
1278 }
1279 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1280
1281 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1282 {
1283         u32 max;
1284
1285         mutex_lock(&dc->lock);
1286         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1287                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1288         dc->syncpt[i].max = max;
1289         mutex_unlock(&dc->lock);
1290
1291         return max;
1292 }
1293
1294 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1295 {
1296         mutex_lock(&dc->lock);
1297         if ( dc->enabled )
1298                 while (dc->syncpt[i].min < val) {
1299                         dc->syncpt[i].min++;
1300                         nvhost_syncpt_cpu_incr(
1301                                         &nvhost_get_host(dc->ndev)->syncpt,
1302                                         dc->syncpt[i].id);
1303                 }
1304         mutex_unlock(&dc->lock);
1305 }
1306
1307 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1308                                              int n)
1309 {
1310         int i;
1311
1312         for (i = 0; i < n; i++) {
1313                 if (windows[i]->dirty)
1314                         return false;
1315         }
1316
1317         return true;
1318 }
1319
1320 /* does not support syncing windows on multiple dcs in one call */
1321 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1322 {
1323         if (n < 1 || n > DC_N_WINDOWS)
1324                 return -EINVAL;
1325
1326         if (!windows[0]->dc->enabled)
1327                 return -EFAULT;
1328
1329 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1330         /* Don't want to timeout on simulator */
1331         return wait_event_interruptible(windows[0]->dc->wq,
1332                 tegra_dc_windows_are_clean(windows, n));
1333 #else
1334         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1335                                          tegra_dc_windows_are_clean(windows, n),
1336                                          HZ);
1337 #endif
1338 }
1339 EXPORT_SYMBOL(tegra_dc_sync_windows);
1340
1341 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1342 {
1343 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1344         return clk_get_rate(dc->clk);
1345 #else
1346         return 27000000;
1347 #endif
1348 }
1349
1350 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1351 {
1352         unsigned long rate;
1353         unsigned long div;
1354
1355         rate = tegra_dc_clk_get_rate(dc);
1356
1357         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1358
1359         if (div < 2)
1360                 return 0;
1361
1362         return rate * 2 / div;
1363 }
1364
1365 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1366 {
1367         unsigned long rate;
1368         unsigned long div;
1369
1370         rate = clk_get_rate(parent);
1371
1372         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1373
1374         if (div < 2)
1375                 return 0;
1376
1377         return rate * 2 / div;
1378 }
1379
1380 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1381 {
1382         int pclk;
1383
1384         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1385                 unsigned long rate;
1386                 struct clk *parent_clk =
1387                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1388
1389                 if (dc->out->parent_clk_backup &&
1390                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1391                         rate = tegra_dc_pclk_predict_rate(
1392                                 parent_clk, dc->mode.pclk);
1393                         /* use pll_d as last resort */
1394                         if (rate < (dc->mode.pclk / 100 * 99) ||
1395                             rate > (dc->mode.pclk / 100 * 109))
1396                                 parent_clk = clk_get_sys(
1397                                         NULL, dc->out->parent_clk_backup);
1398                 }
1399
1400                 if (clk_get_parent(clk) != parent_clk)
1401                         clk_set_parent(clk, parent_clk);
1402
1403                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1404                         struct clk *base_clk = clk_get_parent(parent_clk);
1405
1406                         /* Assuming either pll_d or pll_d2 is used */
1407                         rate = dc->mode.pclk * 2;
1408
1409                         if (rate != clk_get_rate(base_clk))
1410                                 clk_set_rate(base_clk, rate);
1411                 }
1412         }
1413
1414         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1415                 unsigned long rate;
1416                 struct clk *parent_clk =
1417                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1418                 struct clk *base_clk = clk_get_parent(parent_clk);
1419
1420                 /* needs to match tegra_dc_hdmi_supported_modes[]
1421                 and tegra_pll_d_freq_table[] */
1422                 if (dc->mode.pclk > 70000000)
1423                         rate = 594000000;
1424                 else if (dc->mode.pclk > 25200000)
1425                         rate = 216000000;
1426                 else
1427                         rate = 504000000;
1428
1429                 if (rate != clk_get_rate(base_clk))
1430                         clk_set_rate(base_clk, rate);
1431
1432                 if (clk_get_parent(clk) != parent_clk)
1433                         clk_set_parent(clk, parent_clk);
1434         }
1435
1436         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1437                 unsigned long rate;
1438                 struct clk *parent_clk;
1439                 struct clk *base_clk;
1440
1441                 if (clk == dc->clk) {
1442                         parent_clk = clk_get_sys(NULL,
1443                                         dc->out->parent_clk ? : "pll_d_out0");
1444                         base_clk = clk_get_parent(parent_clk);
1445                         tegra_clk_cfg_ex(base_clk,
1446                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1447                 } else {
1448                         if (dc->pdata->default_out->dsi->dsi_instance) {
1449                                 parent_clk = clk_get_sys(NULL,
1450                                         dc->out->parent_clk ? : "pll_d2_out0");
1451                                 base_clk = clk_get_parent(parent_clk);
1452                                 tegra_clk_cfg_ex(base_clk,
1453                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1454                         } else {
1455                                 parent_clk = clk_get_sys(NULL,
1456                                         dc->out->parent_clk ? : "pll_d_out0");
1457                                 base_clk = clk_get_parent(parent_clk);
1458                                 tegra_clk_cfg_ex(base_clk,
1459                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1460                         }
1461                 }
1462
1463                 rate = dc->mode.pclk * 2;
1464                 if (rate != clk_get_rate(base_clk))
1465                         clk_set_rate(base_clk, rate);
1466
1467                 if (clk_get_parent(clk) != parent_clk)
1468                         clk_set_parent(clk, parent_clk);
1469         }
1470
1471         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1472         tegra_dvfs_set_rate(clk, pclk);
1473 }
1474
1475 /* return non-zero if constraint is violated */
1476 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1477 {
1478         long a, b;
1479
1480         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1481         a = 0;
1482
1483         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1484         b = mode->h_front_porch - 1;
1485
1486         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1487         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1488                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1489         /* check Constraint 1 and 6 */
1490         if (a > b)
1491                 return 1;
1492
1493         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1494         if (mode->h_sync_width < 1)
1495                 return 4;
1496
1497         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1498         if (mode->h_active < 16)
1499                 return 7;
1500
1501         if (href) {
1502                 if (b > a && a % 2)
1503                         *href = a + 1; /* use smallest even value */
1504                 else
1505                         *href = a; /* even or only possible value */
1506         }
1507
1508         return 0;
1509 }
1510
1511 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1512 {
1513         long a;
1514         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1515
1516         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1517         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1518                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1519
1520         /* Constraint 6 */
1521         if (mode->v_front_porch < a + 1)
1522                 a = mode->v_front_porch - 1;
1523
1524         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1525         if (mode->v_sync_width < 1)
1526                 return 4;
1527
1528         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1529         if (mode->v_active < 16)
1530                 return 7;
1531
1532         if (vref)
1533                 *vref = a;
1534         return 0;
1535 }
1536
1537 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1538 {
1539         int ret;
1540         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1541         if (ret)
1542                 return ret;
1543         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1544         if (ret)
1545                 return ret;
1546
1547         return 0;
1548 }
1549
1550 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1551 {
1552         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1553         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1554                 return false;
1555
1556         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1557         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1558                 return false;
1559
1560         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1561          * (vertical blank). */
1562         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1563                 return false;
1564
1565         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1566         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1567                 return false;
1568
1569         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1570         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1571                 return false;
1572
1573         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1574          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1575         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1576                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1577                 return false;
1578
1579         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1580         if (mode->h_active < 16 || mode->v_active < 16)
1581                 return false;
1582
1583         return true;
1584 }
1585
1586 #ifdef DEBUG
1587 /* return in 1000ths of a Hertz */
1588 static int calc_refresh(const struct tegra_dc_mode *m)
1589 {
1590         long h_total, v_total, refresh;
1591         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1592                 m->h_sync_width;
1593         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1594                 m->v_sync_width;
1595         refresh = m->pclk / h_total;
1596         refresh *= 1000;
1597         refresh /= v_total;
1598         return refresh;
1599 }
1600
1601 static void print_mode(struct tegra_dc *dc,
1602                         const struct tegra_dc_mode *mode, const char *note)
1603 {
1604         if (mode) {
1605                 int refresh = calc_refresh(dc, mode);
1606                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1607                         note ? note : "",
1608                         mode->h_active, mode->v_active,
1609                         refresh / 1000, refresh % 1000,
1610                         mode->pclk);
1611         }
1612 }
1613 #else /* !DEBUG */
1614 static inline void print_mode(struct tegra_dc *dc,
1615                         const struct tegra_dc_mode *mode, const char *note) { }
1616 #endif /* DEBUG */
1617
1618 static inline void enable_dc_irq(unsigned int irq)
1619 {
1620 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1621         enable_irq(irq);
1622 #else
1623         /* Always disable DC interrupts on FPGA. */
1624         disable_irq(irq);
1625 #endif
1626 }
1627
1628 static inline void disable_dc_irq(unsigned int irq)
1629 {
1630         disable_irq(irq);
1631 }
1632
1633 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1634 {
1635         unsigned long val;
1636         unsigned long rate;
1637         unsigned long div;
1638         unsigned long pclk;
1639
1640         print_mode(dc, mode, __func__);
1641
1642         /* use default EMC rate when switching modes */
1643         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1644         tegra_dc_program_bandwidth(dc);
1645
1646         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1647         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1648                         DC_DISP_REF_TO_SYNC);
1649         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1650                         DC_DISP_SYNC_WIDTH);
1651         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1652                         DC_DISP_BACK_PORCH);
1653         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1654                         DC_DISP_DISP_ACTIVE);
1655         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1656                         DC_DISP_FRONT_PORCH);
1657
1658         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1659                         DC_DISP_DATA_ENABLE_OPTIONS);
1660
1661         /* TODO: MIPI/CRT/HDMI clock cals */
1662
1663         val = DISP_DATA_FORMAT_DF1P1C;
1664
1665         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1666                 val |= DISP_DATA_ALIGNMENT_MSB;
1667         else
1668                 val |= DISP_DATA_ALIGNMENT_LSB;
1669
1670         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1671                 val |= DISP_DATA_ORDER_RED_BLUE;
1672         else
1673                 val |= DISP_DATA_ORDER_BLUE_RED;
1674
1675         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1676
1677         rate = tegra_dc_clk_get_rate(dc);
1678
1679         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1680         if (pclk < (mode->pclk / 100 * 99) ||
1681             pclk > (mode->pclk / 100 * 109)) {
1682                 dev_err(&dc->ndev->dev,
1683                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1684                         rate, mode->pclk,
1685                         pclk, (mode->pclk / 100 * 99),
1686                         (mode->pclk / 100 * 109));
1687                 return -EINVAL;
1688         }
1689
1690         div = (rate * 2 / pclk) - 2;
1691
1692         tegra_dc_writel(dc, 0x00010001,
1693                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1694         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1695                         DC_DISP_DISP_CLOCK_CONTROL);
1696
1697 #ifdef CONFIG_SWITCH
1698         switch_set_state(&dc->modeset_switch,
1699                          (mode->h_active << 16) | mode->v_active);
1700 #endif
1701
1702         return 0;
1703 }
1704
1705
1706 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1707 {
1708         memcpy(&dc->mode, mode, sizeof(dc->mode));
1709
1710         print_mode(dc, mode, __func__);
1711
1712         return 0;
1713 }
1714 EXPORT_SYMBOL(tegra_dc_set_mode);
1715
1716 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1717                 const struct fb_videomode *fbmode, bool stereo_mode)
1718 {
1719         struct tegra_dc_mode mode;
1720
1721         if (!fbmode->pixclock)
1722                 return -EINVAL;
1723
1724         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1725         mode.h_sync_width = fbmode->hsync_len;
1726         mode.v_sync_width = fbmode->vsync_len;
1727         mode.h_back_porch = fbmode->left_margin;
1728         mode.v_back_porch = fbmode->upper_margin;
1729         mode.h_active = fbmode->xres;
1730         mode.v_active = fbmode->yres;
1731         mode.h_front_porch = fbmode->right_margin;
1732         mode.v_front_porch = fbmode->lower_margin;
1733         mode.stereo_mode = stereo_mode;
1734         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1735                 /* HDMI controller requires h_ref=1, v_ref=1 */
1736                 mode.h_ref_to_sync = 1;
1737                 mode.v_ref_to_sync = 1;
1738         } else {
1739                 calc_ref_to_sync(&mode);
1740         }
1741         if (!check_ref_to_sync(&mode)) {
1742                 dev_err(&dc->ndev->dev,
1743                                 "Display timing doesn't meet restrictions.\n");
1744                 return -EINVAL;
1745         }
1746         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1747                 mode.h_active, mode.v_active, mode.pclk,
1748                 mode.h_ref_to_sync, mode.v_ref_to_sync
1749         );
1750
1751         if (mode.stereo_mode) {
1752                 mode.pclk *= 2;
1753                 /* total v_active = yres*2 + activespace */
1754                 mode.v_active = fbmode->yres*2 +
1755                                 fbmode->vsync_len +
1756                                 fbmode->upper_margin +
1757                                 fbmode->lower_margin;
1758         }
1759
1760         mode.flags = 0;
1761
1762         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1763                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1764
1765         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1766                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1767
1768         return tegra_dc_set_mode(dc, &mode);
1769 }
1770 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1771
1772 void
1773 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1774 {
1775         unsigned int ctrl;
1776         unsigned long out_sel;
1777         unsigned long cmd_state;
1778
1779         mutex_lock(&dc->lock);
1780         if (!dc->enabled) {
1781                 mutex_unlock(&dc->lock);
1782                 return;
1783         }
1784
1785         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1786                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1787                 cfg->clk_select);
1788
1789         /* The new value should be effected immediately */
1790         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1791         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1792
1793         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1794                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1795         else
1796                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1797
1798         switch (cfg->which_pwm) {
1799         case TEGRA_PWM_PM0:
1800                 /* Select the LM0 on PM0 */
1801                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1802                 out_sel &= ~(7 << 0);
1803                 out_sel |= (3 << 0);
1804                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1805                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1806                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1807                 break;
1808         case TEGRA_PWM_PM1:
1809                 /* Select the LM1 on PM1 */
1810                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1811                 out_sel &= ~(7 << 4);
1812                 out_sel |= (3 << 4);
1813                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1814                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1815                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1816                 break;
1817         default:
1818                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1819                 break;
1820         }
1821         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1822         mutex_unlock(&dc->lock);
1823 }
1824 EXPORT_SYMBOL(tegra_dc_config_pwm);
1825
1826 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1827                                 const struct tegra_dc_out_pin *pins,
1828                                 const unsigned int n_pins)
1829 {
1830         unsigned int i;
1831
1832         int name;
1833         int pol;
1834
1835         u32 pol1, pol3;
1836
1837         u32 set1, unset1;
1838         u32 set3, unset3;
1839
1840         set1 = set3 = unset1 = unset3 = 0;
1841
1842         for (i = 0; i < n_pins; i++) {
1843                 name = (pins + i)->name;
1844                 pol  = (pins + i)->pol;
1845
1846                 /* set polarity by name */
1847                 switch (name) {
1848                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1849                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1850                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1851                         else
1852                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1853                         break;
1854                 case TEGRA_DC_OUT_PIN_H_SYNC:
1855                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1856                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1857                         else
1858                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1859                         break;
1860                 case TEGRA_DC_OUT_PIN_V_SYNC:
1861                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1862                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1863                         else
1864                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1865                         break;
1866                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1867                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1868                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1869                         else
1870                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1871                         break;
1872                 default:
1873                         printk("Invalid argument in function %s\n",
1874                                __FUNCTION__);
1875                         break;
1876                 }
1877         }
1878
1879         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1880         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1881
1882         pol1 |= set1;
1883         pol1 &= ~unset1;
1884
1885         pol3 |= set3;
1886         pol3 &= ~unset3;
1887
1888         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1889         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1890 }
1891
1892 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1893 {
1894         dc->out = out;
1895
1896         if (out->n_modes > 0)
1897                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1898
1899         switch (out->type) {
1900         case TEGRA_DC_OUT_RGB:
1901                 dc->out_ops = &tegra_dc_rgb_ops;
1902                 break;
1903
1904         case TEGRA_DC_OUT_HDMI:
1905                 dc->out_ops = &tegra_dc_hdmi_ops;
1906                 break;
1907
1908         case TEGRA_DC_OUT_DSI:
1909                 dc->out_ops = &tegra_dc_dsi_ops;
1910                 break;
1911
1912         default:
1913                 dc->out_ops = NULL;
1914                 break;
1915         }
1916
1917         if (dc->out_ops && dc->out_ops->init)
1918                 dc->out_ops->init(dc);
1919
1920 }
1921
1922 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1923 {
1924         if (dc->out)
1925                 return dc->out->height;
1926         else
1927                 return 0;
1928 }
1929 EXPORT_SYMBOL(tegra_dc_get_out_height);
1930
1931 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1932 {
1933         if (dc->out)
1934                 return dc->out->width;
1935         else
1936                 return 0;
1937 }
1938 EXPORT_SYMBOL(tegra_dc_get_out_width);
1939
1940 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1941 {
1942         if (dc->out && dc->out->max_pixclock)
1943                 return dc->out->max_pixclock;
1944         else
1945                 return 0;
1946 }
1947 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1948
1949 void tegra_dc_enable_crc(struct tegra_dc *dc)
1950 {
1951         u32 val;
1952         tegra_dc_io_start(dc);
1953
1954         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1955                 CRC_ENABLE_ENABLE;
1956         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1957         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1958         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1959 }
1960
1961 void tegra_dc_disable_crc(struct tegra_dc *dc)
1962 {
1963         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1964         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1965         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1966
1967         tegra_dc_io_end(dc);
1968 }
1969
1970 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1971 {
1972         int crc = 0;
1973
1974         if(!dc) {
1975                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1976                 goto crc_error;
1977         }
1978
1979         /* TODO: Replace mdelay with code to sync VBlANK, since
1980          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1981         mdelay(TEGRA_CRC_LATCHED_DELAY);
1982
1983         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1984 crc_error:
1985         return crc;
1986 }
1987
1988 static void tegra_dc_vblank(struct work_struct *work)
1989 {
1990         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1991         bool nvsd_updated = false;
1992
1993         mutex_lock(&dc->lock);
1994
1995         /* Update the SD brightness */
1996         if (dc->enabled && dc->out->sd_settings)
1997                 nvsd_updated = nvsd_update_brightness(dc);
1998
1999         mutex_unlock(&dc->lock);
2000
2001         /* Do the actual brightness update outside of the mutex */
2002         if (nvsd_updated && dc->out->sd_settings &&
2003             dc->out->sd_settings->bl_device) {
2004
2005                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2006                 struct backlight_device *bl = platform_get_drvdata(pdev);
2007                 if (bl)
2008                         backlight_update_status(bl);
2009         }
2010 }
2011
2012 static void tegra_dc_one_shot_worker(struct work_struct *work)
2013 {
2014         struct tegra_dc *dc = container_of(work, struct tegra_dc, one_shot_work);
2015         /* memory client has gone idle */
2016         tegra_dc_clear_bandwidth(dc);
2017 }
2018
2019 /* return an arbitrarily large number if count overflow occurs.
2020  * make it a nice base-10 number to show up in stats output */
2021 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2022 {
2023         unsigned count = tegra_dc_readl(dc, reg);
2024         tegra_dc_writel(dc, 0, reg);
2025         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2026 }
2027
2028 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2029 {
2030         u32 val;
2031         int i;
2032
2033         dc->stats.underflows++;
2034         if (dc->underflow_mask & WIN_A_UF_INT)
2035                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2036                         DC_WINBUF_AD_UFLOW_STATUS);
2037         if (dc->underflow_mask & WIN_B_UF_INT)
2038                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2039                         DC_WINBUF_BD_UFLOW_STATUS);
2040         if (dc->underflow_mask & WIN_C_UF_INT)
2041                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2042                         DC_WINBUF_CD_UFLOW_STATUS);
2043
2044         /* Check for any underflow reset conditions */
2045         for (i = 0; i < DC_N_WINDOWS; i++) {
2046                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2047                         dc->windows[i].underflows++;
2048
2049 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2050                         if (dc->windows[i].underflows > 4)
2051                                 schedule_work(&dc->reset_work);
2052 #endif
2053                 } else {
2054                         dc->windows[i].underflows = 0;
2055                 }
2056         }
2057
2058         /* Clear the underflow mask now that we've checked it. */
2059         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2060         dc->underflow_mask = 0;
2061         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2062         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2063 }
2064
2065 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2066 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2067 {
2068         u32 val, i;
2069         u32 completed = 0;
2070         u32 dirty = 0;
2071
2072         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2073         for (i = 0; i < DC_N_WINDOWS; i++) {
2074 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2075                 /* FIXME: this is not needed when the simulator
2076                    clears WIN_x_UPDATE bits as in HW */
2077                 dc->windows[i].dirty = 0;
2078                 completed = 1;
2079 #else
2080                 if (!(val & (WIN_A_UPDATE << i))) {
2081                         dc->windows[i].dirty = 0;
2082                         completed = 1;
2083                 } else {
2084                         dirty = 1;
2085                 }
2086 #endif
2087         }
2088
2089         if (!dirty) {
2090                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2091                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2092                         val &= ~V_BLANK_INT;
2093                 else
2094                         val &= ~FRAME_END_INT;
2095                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2096         }
2097
2098         if (completed) {
2099                 if (!dirty) {
2100                         /* With the last completed window, go ahead
2101                            and enable the vblank interrupt for nvsd. */
2102                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2103                         val |= V_BLANK_INT;
2104                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2105                 }
2106
2107                 wake_up(&dc->wq);
2108         }
2109 }
2110
2111 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2112 {
2113         if (status & V_BLANK_INT) {
2114                 /* Sync up windows. */
2115                 tegra_dc_trigger_windows(dc);
2116
2117                 /* Schedule any additional bottom-half vblank actvities. */
2118                 schedule_work(&dc->vblank_work);
2119         }
2120
2121         if (status & FRAME_END_INT) {
2122                 schedule_work(&dc->one_shot_work);
2123
2124                 /* Mark the frame_end as complete. */
2125                 if (!completion_done(&dc->frame_end_complete))
2126                         complete(&dc->frame_end_complete);
2127         }
2128 }
2129
2130 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2131 {
2132         if (status & V_BLANK_INT) {
2133                 /* Schedule any additional bottom-half vblank actvities. */
2134                 schedule_work(&dc->vblank_work);
2135         }
2136
2137         if (status & FRAME_END_INT) {
2138                 /* Mark the frame_end as complete. */
2139                 if (!completion_done(&dc->frame_end_complete))
2140                         complete(&dc->frame_end_complete);
2141
2142                 tegra_dc_trigger_windows(dc);
2143         }
2144 }
2145 #endif
2146
2147 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2148 {
2149 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2150         struct tegra_dc *dc = ptr;
2151         unsigned long status;
2152         unsigned long underflow_mask;
2153         u32 val;
2154
2155         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2156                 WARN(1, "IRQ when DC not powered!\n");
2157                 tegra_dc_io_start(dc);
2158                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2159                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2160                 tegra_dc_io_end(dc);
2161                 return IRQ_HANDLED;
2162         }
2163
2164         /* clear all status flags except underflow, save those for the worker */
2165         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2166         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2167         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2168         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2169
2170         /*
2171          * Overlays can get thier internal state corrupted during and underflow
2172          * condition.  The only way to fix this state is to reset the DC.
2173          * if we get 4 consecutive frames with underflows, assume we're
2174          * hosed and reset.
2175          */
2176         underflow_mask = status & ALL_UF_INT;
2177
2178         /* Check underflow */
2179         if (underflow_mask) {
2180                 dc->underflow_mask |= underflow_mask;
2181                 schedule_delayed_work(&dc->underflow_work,
2182                         msecs_to_jiffies(1));
2183         }
2184
2185         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2186                 tegra_dc_one_shot_irq(dc, status);
2187         else
2188                 tegra_dc_continuous_irq(dc, status);
2189
2190         return IRQ_HANDLED;
2191 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2192         return IRQ_NONE;
2193 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2194 }
2195
2196 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2197 {
2198         u32 color_control;
2199
2200         switch (dc->out->depth) {
2201         case 3:
2202                 color_control = BASE_COLOR_SIZE111;
2203                 break;
2204
2205         case 6:
2206                 color_control = BASE_COLOR_SIZE222;
2207                 break;
2208
2209         case 8:
2210                 color_control = BASE_COLOR_SIZE332;
2211                 break;
2212
2213         case 9:
2214                 color_control = BASE_COLOR_SIZE333;
2215                 break;
2216
2217         case 12:
2218                 color_control = BASE_COLOR_SIZE444;
2219                 break;
2220
2221         case 15:
2222                 color_control = BASE_COLOR_SIZE555;
2223                 break;
2224
2225         case 16:
2226                 color_control = BASE_COLOR_SIZE565;
2227                 break;
2228
2229         case 18:
2230                 color_control = BASE_COLOR_SIZE666;
2231                 break;
2232
2233         default:
2234                 color_control = BASE_COLOR_SIZE888;
2235                 break;
2236         }
2237
2238         switch (dc->out->dither) {
2239         case TEGRA_DC_DISABLE_DITHER:
2240                 color_control |= DITHER_CONTROL_DISABLE;
2241                 break;
2242         case TEGRA_DC_ORDERED_DITHER:
2243                 color_control |= DITHER_CONTROL_ORDERED;
2244                 break;
2245         case TEGRA_DC_ERRDIFF_DITHER:
2246                 /* The line buffer for error-diffusion dither is limited
2247                  * to 1280 pixels per line. This limits the maximum
2248                  * horizontal active area size to 1280 pixels when error
2249                  * diffusion is enabled.
2250                  */
2251                 BUG_ON(dc->mode.h_active > 1280);
2252                 color_control |= DITHER_CONTROL_ERRDIFF;
2253                 break;
2254         }
2255
2256         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2257 }
2258
2259 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2260 {
2261         u32 syncpt_id;
2262
2263         switch (dc->ndev->id) {
2264         case 0:
2265                 switch (idx) {
2266                 case 0:
2267                         syncpt_id = NVSYNCPT_DISP0_A;
2268                         break;
2269                 case 1:
2270                         syncpt_id = NVSYNCPT_DISP0_B;
2271                         break;
2272                 case 2:
2273                         syncpt_id = NVSYNCPT_DISP0_C;
2274                         break;
2275                 default:
2276                         BUG();
2277                         break;
2278                 }
2279                 break;
2280         case 1:
2281                 switch (idx) {
2282                 case 0:
2283                         syncpt_id = NVSYNCPT_DISP1_A;
2284                         break;
2285                 case 1:
2286                         syncpt_id = NVSYNCPT_DISP1_B;
2287                         break;
2288                 case 2:
2289                         syncpt_id = NVSYNCPT_DISP1_C;
2290                         break;
2291                 default:
2292                         BUG();
2293                         break;
2294                 }
2295                 break;
2296         default:
2297                 BUG();
2298                 break;
2299         }
2300
2301         return syncpt_id;
2302 }
2303
2304 static void tegra_dc_init(struct tegra_dc *dc)
2305 {
2306         int i;
2307
2308         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2309         if (dc->ndev->id == 0) {
2310                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2311                                       TEGRA_MC_PRIO_MED);
2312                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2313                                       TEGRA_MC_PRIO_MED);
2314                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2315                                       TEGRA_MC_PRIO_MED);
2316                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2317                                       TEGRA_MC_PRIO_MED);
2318                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2319                                       TEGRA_MC_PRIO_HIGH);
2320         } else if (dc->ndev->id == 1) {
2321                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2322                                       TEGRA_MC_PRIO_MED);
2323                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2324                                       TEGRA_MC_PRIO_MED);
2325                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2326                                       TEGRA_MC_PRIO_MED);
2327                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2328                                       TEGRA_MC_PRIO_MED);
2329                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2330                                       TEGRA_MC_PRIO_HIGH);
2331         }
2332         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2333                         DC_CMD_CONT_SYNCPT_VSYNC);
2334         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2335         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2336         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2337         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2338
2339         /* enable interrupts for vblank, frame_end and underflows */
2340         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2341                 DC_CMD_INT_ENABLE);
2342         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2343
2344         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2345
2346         tegra_dc_set_color_control(dc);
2347         for (i = 0; i < DC_N_WINDOWS; i++) {
2348                 struct tegra_dc_win *win = &dc->windows[i];
2349                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2350                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2351                 tegra_dc_set_csc(dc, &win->csc);
2352                 tegra_dc_set_lut(dc, win);
2353                 tegra_dc_set_scaling_filter(dc);
2354         }
2355
2356
2357         for (i = 0; i < dc->n_windows; i++) {
2358                 u32 syncpt = get_syncpt(dc, i);
2359
2360                 dc->syncpt[i].id = syncpt;
2361
2362                 dc->syncpt[i].min = dc->syncpt[i].max =
2363                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2364                                         syncpt);
2365         }
2366
2367         print_mode(dc, &dc->mode, __func__);
2368
2369         if (dc->mode.pclk)
2370                 tegra_dc_program_mode(dc, &dc->mode);
2371
2372         /* Initialize SD AFTER the modeset.
2373            nvsd_init handles the sd_settings = NULL case. */
2374         nvsd_init(dc, dc->out->sd_settings);
2375 }
2376
2377 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2378 {
2379         if (dc->out->enable)
2380                 dc->out->enable();
2381
2382         tegra_dc_setup_clk(dc, dc->clk);
2383         clk_enable(dc->clk);
2384
2385         /* do not accept interrupts during initialization */
2386         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2387         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2388
2389         enable_dc_irq(dc->irq);
2390
2391         tegra_dc_init(dc);
2392
2393         if (dc->out_ops && dc->out_ops->enable)
2394                 dc->out_ops->enable(dc);
2395
2396         if (dc->out->postpoweron)
2397                 dc->out->postpoweron();
2398
2399         /* force a full blending update */
2400         dc->blend.z[0] = -1;
2401
2402         tegra_dc_ext_enable(dc->ext);
2403
2404         return true;
2405 }
2406
2407 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2408 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2409 {
2410         if (dc->out->enable)
2411                 dc->out->enable();
2412
2413         tegra_dc_setup_clk(dc, dc->clk);
2414         clk_enable(dc->clk);
2415
2416         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2417                 mutex_lock(&tegra_dcs[1]->lock);
2418                 disable_irq(tegra_dcs[1]->irq);
2419         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2420                 mutex_lock(&tegra_dcs[0]->lock);
2421                 disable_irq(tegra_dcs[0]->irq);
2422         }
2423
2424         msleep(5);
2425         tegra_periph_reset_assert(dc->clk);
2426         msleep(2);
2427 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2428         tegra_periph_reset_deassert(dc->clk);
2429         msleep(1);
2430 #endif
2431
2432         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2433                 enable_dc_irq(tegra_dcs[1]->irq);
2434                 mutex_unlock(&tegra_dcs[1]->lock);
2435         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2436                 enable_dc_irq(tegra_dcs[0]->irq);
2437                 mutex_unlock(&tegra_dcs[0]->lock);
2438         }
2439
2440         enable_dc_irq(dc->irq);
2441
2442         tegra_dc_init(dc);
2443
2444         if (dc->out_ops && dc->out_ops->enable)
2445                 dc->out_ops->enable(dc);
2446
2447         if (dc->out->postpoweron)
2448                 dc->out->postpoweron();
2449
2450         /* force a full blending update */
2451         dc->blend.z[0] = -1;
2452
2453         return true;
2454 }
2455 #endif
2456
2457 static bool _tegra_dc_enable(struct tegra_dc *dc)
2458 {
2459         if (dc->mode.pclk == 0)
2460                 return false;
2461
2462         if (!dc->out)
2463                 return false;
2464
2465         tegra_dc_io_start(dc);
2466
2467         return _tegra_dc_controller_enable(dc);
2468 }
2469
2470 void tegra_dc_enable(struct tegra_dc *dc)
2471 {
2472         mutex_lock(&dc->lock);
2473
2474         if (!dc->enabled)
2475                 dc->enabled = _tegra_dc_enable(dc);
2476
2477         mutex_unlock(&dc->lock);
2478 }
2479
2480 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2481 {
2482         unsigned i;
2483
2484         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2485         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2486         disable_irq(dc->irq);
2487
2488         if (dc->out_ops && dc->out_ops->disable)
2489                 dc->out_ops->disable(dc);
2490
2491         tegra_dc_clear_bandwidth(dc);
2492         clk_disable(dc->clk);
2493         tegra_dvfs_set_rate(dc->clk, 0);
2494
2495         if (dc->out && dc->out->disable)
2496                 dc->out->disable();
2497
2498         for (i = 0; i < dc->n_windows; i++) {
2499                 struct tegra_dc_win *w = &dc->windows[i];
2500
2501                 /* reset window bandwidth */
2502                 w->bandwidth = 0;
2503                 w->new_bandwidth = 0;
2504
2505                 /* disable windows */
2506                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2507
2508                 /* flush any pending syncpt waits */
2509                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2510                         dc->syncpt[i].min++;
2511                         nvhost_syncpt_cpu_incr(
2512                                 &nvhost_get_host(dc->ndev)->syncpt,
2513                                 dc->syncpt[i].id);
2514                 }
2515         }
2516 }
2517
2518 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2519 {
2520 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2521         u32 val;
2522         if (dc->enabled)  {
2523                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2524                 if (enable)
2525                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2526                 else
2527                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2528                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2529         }
2530 #endif
2531 }
2532
2533 bool tegra_dc_stats_get(struct tegra_dc *dc)
2534 {
2535 #if 0 /* right now it is always enabled */
2536         u32 val;
2537         bool res;
2538
2539         if (dc->enabled)  {
2540                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2541                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2542         } else {
2543                 res = false;
2544         }
2545
2546         return res;
2547 #endif
2548         return true;
2549 }
2550
2551 /* make the screen blank by disabling all windows */
2552 void tegra_dc_blank(struct tegra_dc *dc)
2553 {
2554         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2555         unsigned i;
2556
2557         for (i = 0; i < DC_N_WINDOWS; i++) {
2558                 dcwins[i] = tegra_dc_get_window(dc, i);
2559                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2560         }
2561
2562         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2563         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2564 }
2565
2566 static void _tegra_dc_disable(struct tegra_dc *dc)
2567 {
2568         _tegra_dc_controller_disable(dc);
2569         tegra_dc_io_end(dc);
2570 }
2571
2572 void tegra_dc_disable(struct tegra_dc *dc)
2573 {
2574         if (dc->overlay)
2575                 tegra_overlay_disable(dc->overlay);
2576
2577         tegra_dc_ext_disable(dc->ext);
2578
2579         /* it's important that new underflow work isn't scheduled before the
2580          * lock is acquired. */
2581         cancel_delayed_work_sync(&dc->underflow_work);
2582
2583         mutex_lock(&dc->lock);
2584
2585         if (dc->enabled) {
2586                 dc->enabled = false;
2587
2588                 if (!dc->suspended)
2589                         _tegra_dc_disable(dc);
2590         }
2591
2592 #ifdef CONFIG_SWITCH
2593         switch_set_state(&dc->modeset_switch, 0);
2594 #endif
2595
2596         mutex_unlock(&dc->lock);
2597 }
2598
2599 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2600 static void tegra_dc_reset_worker(struct work_struct *work)
2601 {
2602         struct tegra_dc *dc =
2603                 container_of(work, struct tegra_dc, reset_work);
2604
2605         unsigned long val = 0;
2606
2607         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2608
2609         tegra_dc_ext_disable(dc->ext);
2610
2611         mutex_lock(&shared_lock);
2612         mutex_lock(&dc->lock);
2613
2614         if (dc->enabled == false)
2615                 goto unlock;
2616
2617         dc->enabled = false;
2618
2619         /*
2620          * off host read bus
2621          */
2622         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2623         val &= ~(0x00000100);
2624         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2625
2626         /*
2627          * set DC to STOP mode
2628          */
2629         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2630
2631         msleep(10);
2632
2633         _tegra_dc_controller_disable(dc);
2634
2635         /* _tegra_dc_controller_reset_enable deasserts reset */
2636         _tegra_dc_controller_reset_enable(dc);
2637
2638         dc->enabled = true;
2639 unlock:
2640         mutex_unlock(&dc->lock);
2641         mutex_unlock(&shared_lock);
2642 }
2643 #endif
2644
2645 static void tegra_dc_underflow_worker(struct work_struct *work)
2646 {
2647         struct tegra_dc *dc = container_of(
2648                 to_delayed_work(work), struct tegra_dc, underflow_work);
2649
2650         mutex_lock(&dc->lock);
2651         if (dc->enabled) {
2652                 tegra_dc_underflow_handler(dc);
2653         }
2654         mutex_unlock(&dc->lock);
2655 }
2656
2657 #ifdef CONFIG_SWITCH
2658 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2659 {
2660         struct tegra_dc *dc =
2661                 container_of(sdev, struct tegra_dc, modeset_switch);
2662
2663         if (!sdev->state)
2664                 return sprintf(buf, "offline\n");
2665
2666         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2667 }
2668 #endif
2669
2670 static int tegra_dc_probe(struct nvhost_device *ndev)
2671 {
2672         struct tegra_dc *dc;
2673         struct clk *clk;
2674         struct clk *emc_clk;
2675         struct resource *res;
2676         struct resource *base_res;
2677         struct resource *fb_mem = NULL;
2678         int ret = 0;
2679         void __iomem *base;
2680         int irq;
2681         int i;
2682
2683         if (!ndev->dev.platform_data) {
2684                 dev_err(&ndev->dev, "no platform data\n");
2685                 return -ENOENT;
2686         }
2687
2688         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2689         if (!dc) {
2690                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2691                 return -ENOMEM;
2692         }
2693
2694         irq = nvhost_get_irq_byname(ndev, "irq");
2695         if (irq <= 0) {
2696                 dev_err(&ndev->dev, "no irq\n");
2697                 ret = -ENOENT;
2698                 goto err_free;
2699         }
2700
2701         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2702         if (!res) {
2703                 dev_err(&ndev->dev, "no mem resource\n");
2704                 ret = -ENOENT;
2705                 goto err_free;
2706         }
2707
2708         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2709         if (!base_res) {
2710                 dev_err(&ndev->dev, "request_mem_region failed\n");
2711                 ret = -EBUSY;
2712                 goto err_free;
2713         }
2714
2715         base = ioremap(res->start, resource_size(res));
2716         if (!base) {
2717                 dev_err(&ndev->dev, "registers can't be mapped\n");
2718                 ret = -EBUSY;
2719                 goto err_release_resource_reg;
2720         }
2721
2722         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2723
2724         clk = clk_get(&ndev->dev, NULL);
2725         if (IS_ERR_OR_NULL(clk)) {
2726                 dev_err(&ndev->dev, "can't get clock\n");
2727                 ret = -ENOENT;
2728                 goto err_iounmap_reg;
2729         }
2730
2731         emc_clk = clk_get(&ndev->dev, "emc");
2732         if (IS_ERR_OR_NULL(emc_clk)) {
2733                 dev_err(&ndev->dev, "can't get emc clock\n");
2734                 ret = -ENOENT;
2735                 goto err_put_clk;
2736         }
2737
2738         dc->clk = clk;
2739         dc->emc_clk = emc_clk;
2740
2741         dc->base_res = base_res;
2742         dc->base = base;
2743         dc->irq = irq;
2744         dc->ndev = ndev;
2745         dc->pdata = ndev->dev.platform_data;
2746
2747         /*
2748          * The emc is a shared clock, it will be set based on
2749          * the requirements for each user on the bus.
2750          */
2751         dc->emc_clk_rate = 0;
2752
2753         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2754                 dc->enabled = true;
2755
2756         mutex_init(&dc->lock);
2757         init_completion(&dc->frame_end_complete);
2758         init_waitqueue_head(&dc->wq);
2759 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2760         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2761 #endif
2762         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2763         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2764         INIT_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2765
2766         tegra_dc_init_lut_defaults(&dc->fb_lut);
2767
2768         dc->n_windows = DC_N_WINDOWS;
2769         for (i = 0; i < dc->n_windows; i++) {
2770                 struct tegra_dc_win *win = &dc->windows[i];
2771                 win->idx = i;
2772                 win->dc = dc;
2773                 tegra_dc_init_csc_defaults(&win->csc);
2774                 tegra_dc_init_lut_defaults(&win->lut);
2775         }
2776
2777         ret = tegra_dc_set(dc, ndev->id);
2778         if (ret < 0) {
2779                 dev_err(&ndev->dev, "can't add dc\n");
2780                 goto err_free_irq;
2781         }
2782
2783         nvhost_set_drvdata(ndev, dc);
2784
2785 #ifdef CONFIG_SWITCH
2786         dc->modeset_switch.name = dev_name(&ndev->dev);
2787         dc->modeset_switch.state = 0;
2788         dc->modeset_switch.print_state = switch_modeset_print_mode;
2789         switch_dev_register(&dc->modeset_switch);
2790 #endif
2791
2792         if (dc->pdata->default_out)
2793                 tegra_dc_set_out(dc, dc->pdata->default_out);
2794         else
2795                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2796
2797         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2798                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2799
2800         dc->ext = tegra_dc_ext_register(ndev, dc);
2801         if (IS_ERR_OR_NULL(dc->ext)) {
2802                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2803                 dc->ext = NULL;
2804         }
2805
2806         /* interrupt handler must be registered before tegra_fb_register() */
2807         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2808                         dev_name(&ndev->dev), dc)) {
2809                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2810                 ret = -EBUSY;
2811                 goto err_put_emc_clk;
2812         }
2813
2814         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2815         disable_dc_irq(dc->irq);
2816
2817         mutex_lock(&dc->lock);
2818         if (dc->enabled)
2819                 _tegra_dc_enable(dc);
2820         mutex_unlock(&dc->lock);
2821
2822         tegra_dc_create_debugfs(dc);
2823
2824         dev_info(&ndev->dev, "probed\n");
2825
2826         if (dc->pdata->fb) {
2827                 if (dc->pdata->fb->bits_per_pixel == -1) {
2828                         unsigned long fmt;
2829                         tegra_dc_writel(dc,
2830                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2831                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2832
2833                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2834                         dc->pdata->fb->bits_per_pixel =
2835                                 tegra_dc_fmt_bpp(fmt);
2836                 }
2837
2838                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2839                 if (IS_ERR_OR_NULL(dc->fb))
2840                         dc->fb = NULL;
2841         }
2842
2843         if (dc->fb) {
2844                 dc->overlay = tegra_overlay_register(ndev, dc);
2845                 if (IS_ERR_OR_NULL(dc->overlay))
2846                         dc->overlay = NULL;
2847         }
2848
2849         if (dc->out && dc->out->hotplug_init)
2850                 dc->out->hotplug_init();
2851
2852         if (dc->out_ops && dc->out_ops->detect)
2853                 dc->out_ops->detect(dc);
2854         else
2855                 dc->connected = true;
2856
2857         tegra_dc_create_sysfs(&dc->ndev->dev);
2858
2859         return 0;
2860
2861 err_free_irq:
2862         free_irq(irq, dc);
2863 err_put_emc_clk:
2864         clk_put(emc_clk);
2865 err_put_clk:
2866         clk_put(clk);
2867 err_iounmap_reg:
2868         iounmap(base);
2869         if (fb_mem)
2870                 release_resource(fb_mem);
2871 err_release_resource_reg:
2872         release_resource(base_res);
2873 err_free:
2874         kfree(dc);
2875
2876         return ret;
2877 }
2878
2879 static int tegra_dc_remove(struct nvhost_device *ndev)
2880 {
2881         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2882
2883         tegra_dc_remove_sysfs(&dc->ndev->dev);
2884         tegra_dc_remove_debugfs(dc);
2885
2886         if (dc->overlay) {
2887                 tegra_overlay_unregister(dc->overlay);
2888         }
2889
2890         if (dc->fb) {
2891                 tegra_fb_unregister(dc->fb);
2892                 if (dc->fb_mem)
2893                         release_resource(dc->fb_mem);
2894         }
2895
2896         tegra_dc_ext_disable(dc->ext);
2897
2898         if (dc->ext)
2899                 tegra_dc_ext_unregister(dc->ext);
2900
2901         if (dc->enabled)
2902                 _tegra_dc_disable(dc);
2903
2904 #ifdef CONFIG_SWITCH
2905         switch_dev_unregister(&dc->modeset_switch);
2906 #endif
2907         free_irq(dc->irq, dc);
2908         clk_put(dc->emc_clk);
2909         clk_put(dc->clk);
2910         iounmap(dc->base);
2911         if (dc->fb_mem)
2912                 release_resource(dc->base_res);
2913         kfree(dc);
2914         tegra_dc_set(NULL, ndev->id);
2915         return 0;
2916 }
2917
2918 #ifdef CONFIG_PM
2919 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2920 {
2921         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2922
2923         dev_info(&ndev->dev, "suspend\n");
2924
2925         if (dc->overlay)
2926                 tegra_overlay_disable(dc->overlay);
2927
2928         tegra_dc_ext_disable(dc->ext);
2929
2930         mutex_lock(&dc->lock);
2931
2932         if (dc->out_ops && dc->out_ops->suspend)
2933                 dc->out_ops->suspend(dc);
2934
2935         if (dc->enabled) {
2936                 _tegra_dc_disable(dc);
2937
2938                 dc->suspended = true;
2939         }
2940
2941         if (dc->out && dc->out->postsuspend) {
2942                 dc->out->postsuspend();
2943                 msleep(100); /* avoid resume event due to voltage falling */
2944         }
2945
2946         mutex_unlock(&dc->lock);
2947
2948         return 0;
2949 }
2950
2951 static int tegra_dc_resume(struct nvhost_device *ndev)
2952 {
2953         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2954
2955         dev_info(&ndev->dev, "resume\n");
2956
2957         mutex_lock(&dc->lock);
2958         dc->suspended = false;
2959
2960         if (dc->enabled)
2961                 _tegra_dc_enable(dc);
2962
2963         if (dc->out && dc->out->hotplug_init)
2964                 dc->out->hotplug_init();
2965
2966         if (dc->out_ops && dc->out_ops->resume)
2967                 dc->out_ops->resume(dc);
2968         mutex_unlock(&dc->lock);
2969
2970         return 0;
2971 }
2972
2973 #endif /* CONFIG_PM */
2974
2975 extern int suspend_set(const char *val, struct kernel_param *kp)
2976 {
2977         if (!strcmp(val, "dump"))
2978                 dump_regs(tegra_dcs[0]);
2979 #ifdef CONFIG_PM
2980         else if (!strcmp(val, "suspend"))
2981                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2982         else if (!strcmp(val, "resume"))
2983                 tegra_dc_resume(tegra_dcs[0]->ndev);
2984 #endif
2985
2986         return 0;
2987 }
2988
2989 extern int suspend_get(char *buffer, struct kernel_param *kp)
2990 {
2991         return 0;
2992 }
2993
2994 int suspend;
2995
2996 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2997
2998 struct nvhost_driver tegra_dc_driver = {
2999         .driver = {
3000                 .name = "tegradc",
3001                 .owner = THIS_MODULE,
3002         },
3003         .probe = tegra_dc_probe,
3004         .remove = tegra_dc_remove,
3005 #ifdef CONFIG_PM
3006         .suspend = tegra_dc_suspend,
3007         .resume = tegra_dc_resume,
3008 #endif
3009 };
3010
3011 static int __init tegra_dc_module_init(void)
3012 {
3013         int ret = tegra_dc_ext_module_init();
3014         if (ret)
3015                 return ret;
3016         return nvhost_driver_register(&tegra_dc_driver);
3017 }
3018
3019 static void __exit tegra_dc_module_exit(void)
3020 {
3021         nvhost_driver_unregister(&tegra_dc_driver);
3022         tegra_dc_ext_module_exit();
3023 }
3024
3025 module_exit(tegra_dc_module_exit);
3026 module_init(tegra_dc_module_init);