video: tegra: dc: add per window global alpha
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39 #ifdef CONFIG_SWITCH
40 #include <linux/switch.h>
41 #endif
42
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
62 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
63 #else
64 /* ignore underflows when on simulation and fpga platform */
65 #define ALL_UF_INT (0)
66 #endif
67
68 static int no_vsync;
69 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
70         .refresh = 60,
71         .xres = 640,
72         .yres = 480,
73         .pixclock = KHZ2PICOS(25200),
74         .hsync_len = 96,        /* h_sync_width */
75         .vsync_len = 2,         /* v_sync_width */
76         .left_margin = 48,      /* h_back_porch */
77         .upper_margin = 33,     /* v_back_porch */
78         .right_margin = 16,     /* h_front_porch */
79         .lower_margin = 10,     /* v_front_porch */
80         .vmode = 0,
81         .sync = 0,
82 };
83
84 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
85
86 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
87
88 static int use_dynamic_emc = 1;
89
90 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
91
92 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
93
94 DEFINE_MUTEX(tegra_dc_lock);
95 DEFINE_MUTEX(shared_lock);
96
97 static inline bool win_use_v_filter(struct tegra_dc *dc, const struct tegra_dc_win *win)
98 {
99         return tegra_dc_feature_has_filter(dc, win->idx, HAS_V_FILTER) &&
100                 win->h.full != dfixed_const(win->out_h);
101 }
102 static inline bool win_use_h_filter(struct tegra_dc *dc, const struct tegra_dc_win *win)
103 {
104         return tegra_dc_feature_has_filter(dc, win->idx, HAS_H_FILTER) &&
105                 win->w.full != dfixed_const(win->out_w);
106 }
107
108 static inline int tegra_dc_fmt_bpp(int fmt)
109 {
110         switch (fmt) {
111         case TEGRA_WIN_FMT_P1:
112                 return 1;
113
114         case TEGRA_WIN_FMT_P2:
115                 return 2;
116
117         case TEGRA_WIN_FMT_P4:
118                 return 4;
119
120         case TEGRA_WIN_FMT_P8:
121                 return 8;
122
123         case TEGRA_WIN_FMT_B4G4R4A4:
124         case TEGRA_WIN_FMT_B5G5R5A:
125         case TEGRA_WIN_FMT_B5G6R5:
126         case TEGRA_WIN_FMT_AB5G5R5:
127                 return 16;
128
129         case TEGRA_WIN_FMT_B8G8R8A8:
130         case TEGRA_WIN_FMT_R8G8B8A8:
131         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
132         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
133                 return 32;
134
135         /* for planar formats, size of the Y plane, 8bit */
136         case TEGRA_WIN_FMT_YCbCr420P:
137         case TEGRA_WIN_FMT_YUV420P:
138         case TEGRA_WIN_FMT_YCbCr422P:
139         case TEGRA_WIN_FMT_YUV422P:
140         case TEGRA_WIN_FMT_YCbCr422R:
141         case TEGRA_WIN_FMT_YUV422R:
142         case TEGRA_WIN_FMT_YCbCr422RA:
143         case TEGRA_WIN_FMT_YUV422RA:
144                 return 8;
145
146         /* YUYV packed into 32-bits */
147         case TEGRA_WIN_FMT_YCbCr422:
148         case TEGRA_WIN_FMT_YUV422:
149                 return 16;
150         }
151         return 0;
152 }
153
154 static inline bool tegra_dc_is_yuv(int fmt)
155 {
156         switch (fmt) {
157         case TEGRA_WIN_FMT_YUV420P:
158         case TEGRA_WIN_FMT_YCbCr420P:
159         case TEGRA_WIN_FMT_YCbCr422P:
160         case TEGRA_WIN_FMT_YUV422P:
161         case TEGRA_WIN_FMT_YCbCr422:
162         case TEGRA_WIN_FMT_YUV422:
163         case TEGRA_WIN_FMT_YCbCr422R:
164         case TEGRA_WIN_FMT_YUV422R:
165         case TEGRA_WIN_FMT_YCbCr422RA:
166         case TEGRA_WIN_FMT_YUV422RA:
167                 return true;
168         }
169         return false;
170 }
171
172 static inline bool tegra_dc_is_yuv_planar(int fmt)
173 {
174         switch (fmt) {
175         case TEGRA_WIN_FMT_YUV420P:
176         case TEGRA_WIN_FMT_YCbCr420P:
177         case TEGRA_WIN_FMT_YCbCr422P:
178         case TEGRA_WIN_FMT_YUV422P:
179         case TEGRA_WIN_FMT_YCbCr422R:
180         case TEGRA_WIN_FMT_YUV422R:
181         case TEGRA_WIN_FMT_YCbCr422RA:
182         case TEGRA_WIN_FMT_YUV422RA:
183                 return true;
184         }
185         return false;
186 }
187
188 #define DUMP_REG(a) do {                        \
189         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
190                  #a, a, tegra_dc_readl(dc, a));               \
191         print(data, buff);                                    \
192         } while (0)
193
194 #define print_mode_info(dc, mode) do {                        \
195         trace_printk("%s:Mode settings: "                              \
196                         "ref_to_sync: H = %d V = %d, "                  \
197                         "sync_width: H = %d V = %d, "                   \
198                         "back_porch: H = %d V = %d, "                   \
199                         "active: H = %d V = %d, "                       \
200                         "front_porch: H = %d V = %d, "                  \
201                         "pclk = %d, stereo mode = %d\n",                \
202                         dc->ndev->name,                                 \
203                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
204                         mode.h_sync_width, mode.v_sync_width,           \
205                         mode.h_back_porch, mode.v_back_porch,           \
206                         mode.h_active, mode.v_active,                   \
207                         mode.h_front_porch, mode.v_front_porch,         \
208                         mode.pclk, mode.stereo_mode);                   \
209         } while (0)
210
211 #define print_underflow_info(dc) do {                 \
212         trace_printk("%s:Underflow stats: underflows : %llu, "      \
213                         "undeflows_a : %llu, "                          \
214                         "underflows_b : %llu, "                         \
215                         "underflows_c : %llu\n",                        \
216                         dc->ndev->name,                                 \
217                         dc->stats.underflows,                           \
218                         dc->stats.underflows_a, dc->stats.underflows_b, \
219                         dc->stats.underflows_c);                        \
220         } while (0)
221
222 static void _dump_regs(struct tegra_dc *dc, void *data,
223                        void (* print)(void *data, const char *str))
224 {
225         int i;
226         char buff[256];
227
228         tegra_dc_io_start(dc);
229         clk_enable(dc->clk);
230
231         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
232         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
233         DUMP_REG(DC_CMD_SIGNAL_RAISE);
234         DUMP_REG(DC_CMD_INT_STATUS);
235         DUMP_REG(DC_CMD_INT_MASK);
236         DUMP_REG(DC_CMD_INT_ENABLE);
237         DUMP_REG(DC_CMD_INT_TYPE);
238         DUMP_REG(DC_CMD_INT_POLARITY);
239         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
240         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
241         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
242         DUMP_REG(DC_CMD_STATE_ACCESS);
243         DUMP_REG(DC_CMD_STATE_CONTROL);
244         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
245         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
246
247         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
248         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
249         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
250         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
251         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
252         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
253         DUMP_REG(DC_DISP_REF_TO_SYNC);
254         DUMP_REG(DC_DISP_SYNC_WIDTH);
255         DUMP_REG(DC_DISP_BACK_PORCH);
256         DUMP_REG(DC_DISP_DISP_ACTIVE);
257         DUMP_REG(DC_DISP_FRONT_PORCH);
258         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
259         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
260         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
261         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
262         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
263         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
264         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
265         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
266         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
267         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
268         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
269         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
270         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
271         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
272         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
273         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
274         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
275         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
276         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
277         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
278         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
279         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
280         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
281         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
282         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
283         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
284         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
285         DUMP_REG(DC_DISP_M0_CONTROL);
286         DUMP_REG(DC_DISP_M1_CONTROL);
287         DUMP_REG(DC_DISP_DI_CONTROL);
288         DUMP_REG(DC_DISP_PP_CONTROL);
289         DUMP_REG(DC_DISP_PP_SELECT_A);
290         DUMP_REG(DC_DISP_PP_SELECT_B);
291         DUMP_REG(DC_DISP_PP_SELECT_C);
292         DUMP_REG(DC_DISP_PP_SELECT_D);
293         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
294         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
295         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
296         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
297         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
298         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
299         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
300         DUMP_REG(DC_DISP_BORDER_COLOR);
301         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
302         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
303         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
304         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
305         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
306         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
307         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
308         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
309         DUMP_REG(DC_DISP_CURSOR_POSITION);
310         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
311         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
312         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
313         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
314         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
315         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
316         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
317         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
318         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
319         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
320         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
321         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
322         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
323
324
325         for (i = 0; i < 3; i++) {
326                 print(data, "\n");
327                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
328                 print(data, buff);
329
330                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
331                                 DC_CMD_DISPLAY_WINDOW_HEADER);
332                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
333                 DUMP_REG(DC_WIN_WIN_OPTIONS);
334                 DUMP_REG(DC_WIN_BYTE_SWAP);
335                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
336                 DUMP_REG(DC_WIN_COLOR_DEPTH);
337                 DUMP_REG(DC_WIN_POSITION);
338                 DUMP_REG(DC_WIN_SIZE);
339                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
340                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
341                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
342                 DUMP_REG(DC_WIN_DDA_INCREMENT);
343                 DUMP_REG(DC_WIN_LINE_STRIDE);
344                 DUMP_REG(DC_WIN_BUF_STRIDE);
345                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
346                 DUMP_REG(DC_WIN_BLEND_NOKEY);
347                 DUMP_REG(DC_WIN_BLEND_1WIN);
348                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
349                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
350                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
351                 DUMP_REG(DC_WINBUF_START_ADDR);
352                 DUMP_REG(DC_WINBUF_START_ADDR_U);
353                 DUMP_REG(DC_WINBUF_START_ADDR_V);
354                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
355                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
356                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
357                 DUMP_REG(DC_WIN_CSC_YOF);
358                 DUMP_REG(DC_WIN_CSC_KYRGB);
359                 DUMP_REG(DC_WIN_CSC_KUR);
360                 DUMP_REG(DC_WIN_CSC_KVR);
361                 DUMP_REG(DC_WIN_CSC_KUG);
362                 DUMP_REG(DC_WIN_CSC_KVG);
363                 DUMP_REG(DC_WIN_CSC_KUB);
364                 DUMP_REG(DC_WIN_CSC_KVB);
365         }
366
367         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
368         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
369         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
370         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
371         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
372         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
373         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
374         DUMP_REG(DC_DISP_M1_CONTROL);
375         DUMP_REG(DC_COM_PM1_CONTROL);
376         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
377         DUMP_REG(DC_DISP_SD_CONTROL);
378
379         clk_disable(dc->clk);
380         tegra_dc_io_end(dc);
381 }
382
383 #undef DUMP_REG
384
385 #ifdef DEBUG
386 static void dump_regs_print(void *data, const char *str)
387 {
388         struct tegra_dc *dc = data;
389         dev_dbg(&dc->ndev->dev, "%s", str);
390 }
391
392 static void dump_regs(struct tegra_dc *dc)
393 {
394         _dump_regs(dc, dc, dump_regs_print);
395 }
396 #else /* !DEBUG */
397
398 static void dump_regs(struct tegra_dc *dc) {}
399
400 #endif /* DEBUG */
401
402 #ifdef CONFIG_DEBUG_FS
403
404 static void dbg_regs_print(void *data, const char *str)
405 {
406         struct seq_file *s = data;
407
408         seq_printf(s, "%s", str);
409 }
410
411 #undef DUMP_REG
412
413 static int dbg_dc_show(struct seq_file *s, void *unused)
414 {
415         struct tegra_dc *dc = s->private;
416
417         _dump_regs(dc, s, dbg_regs_print);
418
419         return 0;
420 }
421
422
423 static int dbg_dc_open(struct inode *inode, struct file *file)
424 {
425         return single_open(file, dbg_dc_show, inode->i_private);
426 }
427
428 static const struct file_operations regs_fops = {
429         .open           = dbg_dc_open,
430         .read           = seq_read,
431         .llseek         = seq_lseek,
432         .release        = single_release,
433 };
434
435 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
436 {
437         struct tegra_dc *dc = s->private;
438         struct tegra_dc_mode *m;
439
440         mutex_lock(&dc->lock);
441         m = &dc->mode;
442         seq_printf(s,
443                 "pclk: %d\n"
444                 "h_ref_to_sync: %d\n"
445                 "v_ref_to_sync: %d\n"
446                 "h_sync_width: %d\n"
447                 "v_sync_width: %d\n"
448                 "h_back_porch: %d\n"
449                 "v_back_porch: %d\n"
450                 "h_active: %d\n"
451                 "v_active: %d\n"
452                 "h_front_porch: %d\n"
453                 "v_front_porch: %d\n"
454                 "stereo_mode: %d\n",
455                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
456                 m->h_sync_width, m->v_sync_width,
457                 m->h_back_porch, m->v_back_porch,
458                 m->h_active, m->v_active,
459                 m->h_front_porch, m->v_front_porch,
460                 m->stereo_mode);
461         mutex_unlock(&dc->lock);
462         return 0;
463 }
464
465 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
466 {
467         return single_open(file, dbg_dc_mode_show, inode->i_private);
468 }
469
470 static const struct file_operations mode_fops = {
471         .open           = dbg_dc_mode_open,
472         .read           = seq_read,
473         .llseek         = seq_lseek,
474         .release        = single_release,
475 };
476
477 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
478 {
479         struct tegra_dc *dc = s->private;
480
481         mutex_lock(&dc->lock);
482         seq_printf(s,
483                 "underflows: %llu\n"
484                 "underflows_a: %llu\n"
485                 "underflows_b: %llu\n"
486                 "underflows_c: %llu\n",
487                 dc->stats.underflows,
488                 dc->stats.underflows_a,
489                 dc->stats.underflows_b,
490                 dc->stats.underflows_c);
491         mutex_unlock(&dc->lock);
492
493         return 0;
494 }
495
496 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
497 {
498         return single_open(file, dbg_dc_stats_show, inode->i_private);
499 }
500
501 static const struct file_operations stats_fops = {
502         .open           = dbg_dc_stats_open,
503         .read           = seq_read,
504         .llseek         = seq_lseek,
505         .release        = single_release,
506 };
507
508 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
509 {
510         if (dc->debugdir)
511                 debugfs_remove_recursive(dc->debugdir);
512         dc->debugdir = NULL;
513 }
514
515 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
516 {
517         struct dentry *retval;
518
519         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
520         if (!dc->debugdir)
521                 goto remove_out;
522
523         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
524                 &regs_fops);
525         if (!retval)
526                 goto remove_out;
527
528         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
529                 &mode_fops);
530         if (!retval)
531                 goto remove_out;
532
533         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
534                 &stats_fops);
535         if (!retval)
536                 goto remove_out;
537
538         return;
539 remove_out:
540         dev_err(&dc->ndev->dev, "could not create debugfs\n");
541         tegra_dc_remove_debugfs(dc);
542 }
543
544 #else /* !CONFIG_DEBUGFS */
545 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
546 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
547 #endif /* CONFIG_DEBUGFS */
548
549 static int tegra_dc_set(struct tegra_dc *dc, int index)
550 {
551         int ret = 0;
552
553         mutex_lock(&tegra_dc_lock);
554         if (index >= TEGRA_MAX_DC) {
555                 ret = -EINVAL;
556                 goto out;
557         }
558
559         if (dc != NULL && tegra_dcs[index] != NULL) {
560                 ret = -EBUSY;
561                 goto out;
562         }
563
564         tegra_dcs[index] = dc;
565
566 out:
567         mutex_unlock(&tegra_dc_lock);
568
569         return ret;
570 }
571
572 static unsigned int tegra_dc_has_multiple_dc(void)
573 {
574         unsigned int idx;
575         unsigned int cnt = 0;
576         struct tegra_dc *dc;
577
578         mutex_lock(&tegra_dc_lock);
579         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
580                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
581         mutex_unlock(&tegra_dc_lock);
582
583         return (cnt > 1);
584 }
585
586 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
587 {
588         if (idx < TEGRA_MAX_DC)
589                 return tegra_dcs[idx];
590         else
591                 return NULL;
592 }
593 EXPORT_SYMBOL(tegra_dc_get_dc);
594
595 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
596 {
597         if (win >= dc->n_windows)
598                 return NULL;
599
600         return &dc->windows[win];
601 }
602 EXPORT_SYMBOL(tegra_dc_get_window);
603
604 static int get_topmost_window(u32 *depths, unsigned long *wins)
605 {
606         int idx, best = -1;
607
608         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
609                 if (best == -1 || depths[idx] < depths[best])
610                         best = idx;
611         }
612         clear_bit(best, wins);
613         return best;
614 }
615
616 bool tegra_dc_get_connected(struct tegra_dc *dc)
617 {
618         return dc->connected;
619 }
620 EXPORT_SYMBOL(tegra_dc_get_connected);
621
622 bool tegra_dc_hpd(struct tegra_dc *dc)
623 {
624         int sense;
625         int level;
626
627         level = gpio_get_value(dc->out->hotplug_gpio);
628
629         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
630
631         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
632                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
633 }
634 EXPORT_SYMBOL(tegra_dc_hpd);
635
636 static u32 blend_topwin(u32 flags)
637 {
638         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
639                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
640         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
641                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
642         else
643                 return BLEND(NOKEY, FIX, 0xff, 0xff);
644 }
645
646 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
647 {
648         int other;
649
650         for (other = 0; other < DC_N_WINDOWS; other++) {
651                 if (other != idx && (xy-- == 0))
652                         break;
653         }
654         if (BIT(other) & behind_mask)
655                 return blend_topwin(flags[idx]);
656         else if (flags[other])
657                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
658         else
659                 return BLEND(NOKEY, FIX, 0x00, 0x00);
660 }
661
662 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
663 {
664         unsigned long infront_mask;
665         int first;
666
667         infront_mask = ~(behind_mask | BIT(idx));
668         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
669         first = ffs(infront_mask) - 1;
670
671         if (!infront_mask)
672                 return blend_topwin(flags[idx]);
673         else if (behind_mask && first != -1 && flags[first])
674                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
675         else
676                 return BLEND(NOKEY, FIX, 0x0, 0x0);
677 }
678
679 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
680 {
681         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
682
683         while (mask) {
684                 int idx = get_topmost_window(blend->z, &mask);
685
686                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
687                                 DC_CMD_DISPLAY_WINDOW_HEADER);
688                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
689                                 DC_WIN_BLEND_NOKEY);
690                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
691                                 DC_WIN_BLEND_1WIN);
692                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
693                                 DC_WIN_BLEND_2WIN_X);
694                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
695                                 DC_WIN_BLEND_2WIN_Y);
696                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
697                                 DC_WIN_BLEND_3WIN_XY);
698         }
699 }
700
701 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
702 {
703         csc->yof   = 0x00f0;
704         csc->kyrgb = 0x012a;
705         csc->kur   = 0x0000;
706         csc->kvr   = 0x0198;
707         csc->kug   = 0x039b;
708         csc->kvg   = 0x032f;
709         csc->kub   = 0x0204;
710         csc->kvb   = 0x0000;
711 }
712
713 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
714 {
715         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
716         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
717         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
718         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
719         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
720         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
721         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
722         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
723 }
724
725 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
726 {
727         mutex_lock(&dc->lock);
728
729         if (!dc->enabled) {
730                 mutex_unlock(&dc->lock);
731                 return -EFAULT;
732         }
733
734         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
735                         DC_CMD_DISPLAY_WINDOW_HEADER);
736
737         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
738
739         mutex_unlock(&dc->lock);
740
741         return 0;
742 }
743 EXPORT_SYMBOL(tegra_dc_update_csc);
744
745 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
746 {
747         int i;
748         for (i = 0; i < 256; i++)
749                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
750 }
751
752 static int tegra_dc_loop_lut(struct tegra_dc *dc,
753                              struct tegra_dc_win *win,
754                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
755 {
756         struct tegra_dc_lut *lut = &win->lut;
757         struct tegra_dc_lut *global_lut = &dc->fb_lut;
758         int i;
759         for (i = 0; i < 256; i++) {
760
761                 u32 r = (u32)lut->r[i];
762                 u32 g = (u32)lut->g[i];
763                 u32 b = (u32)lut->b[i];
764
765                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
766                         r = (u32)global_lut->r[r];
767                         g = (u32)global_lut->g[g];
768                         b = (u32)global_lut->b[b];
769                 }
770
771                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
772                         return 0;
773         }
774         return 1;
775 }
776
777 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
778 {
779         if (rgb != (i | (i<<8) | (i<<16)))
780                 return 0;
781         return 1;
782 }
783
784 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
785 {
786         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
787         return 1;
788 }
789
790 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
791 {
792         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
793
794         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
795
796         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
797                 val |= CP_ENABLE;
798         else
799                 val &= ~CP_ENABLE;
800
801         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
802 }
803
804 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
805 {
806         struct tegra_dc_win *win = &dc->windows[win_idx];
807
808         mutex_lock(&dc->lock);
809
810         if (!dc->enabled) {
811                 mutex_unlock(&dc->lock);
812                 return -EFAULT;
813         }
814
815         if (fbovr > 0)
816                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
817         else if (fbovr == 0)
818                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
819
820         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
821                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
822         else
823                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
824
825         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
826                         DC_CMD_DISPLAY_WINDOW_HEADER);
827
828         tegra_dc_set_lut(dc, win);
829
830         mutex_unlock(&dc->lock);
831
832         tegra_dc_update_windows(&win, 1);
833
834         return 0;
835 }
836
837 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
838 {
839         if (win_idx > -1)
840                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
841
842         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
843                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
844                 if (err)
845                         return err;
846         }
847
848         return 0;
849 }
850 EXPORT_SYMBOL(tegra_dc_update_lut);
851
852 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
853 {
854         unsigned i;
855         unsigned v0 = 128;
856         unsigned v1 = 0;
857         /* linear horizontal and vertical filters */
858         for (i = 0; i < 16; i++) {
859                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
860                                 DC_WIN_H_FILTER_P(i));
861
862                 tegra_dc_writel(dc, v0,
863                                 DC_WIN_V_FILTER_P(i));
864                 v0 -= 8;
865                 v1 += 8;
866         }
867 }
868
869 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
870         struct tegra_dc_win *w)
871 {
872         /* windows A, B, C for first and second display */
873         static const enum tegra_la_id la_id_tab[2][3] = {
874                 /* first display */
875                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
876                         TEGRA_LA_DISPLAY_0C },
877                 /* second display */
878                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
879                         TEGRA_LA_DISPLAY_0CB },
880         };
881         /* window B V-filter tap for first and second display. */
882         static const enum tegra_la_id vfilter_tab[2] = {
883                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
884         };
885         unsigned long bw;
886
887         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
888         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
889         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
890
891         bw = w->new_bandwidth;
892
893         /* tegra_dc_get_bandwidth() treats V filter windows as double
894          * bandwidth, but LA has a seperate client for V filter */
895         if (w->idx == 1 && win_use_v_filter(dc, w))
896                 bw /= 2;
897
898         /* our bandwidth is in kbytes/sec, but LA takes MBps.
899          * round up bandwidth to next 1MBps */
900         bw = bw / 1000 + 1;
901
902 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
903         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
904         /* if window B, also set the 1B client for the 2-tap V filter. */
905         if (w->idx == 1)
906                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
907 #endif
908
909         w->bandwidth = w->new_bandwidth;
910 }
911
912 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
913                                                    struct tegra_dc_win *b)
914 {
915         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
916                 return 0;
917
918         /* because memory access to load the fifo can overlap, only care
919          * if windows overlap vertically */
920         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
921                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
922 }
923
924 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
925                                                  int n)
926 {
927         unsigned i;
928         unsigned j;
929         unsigned overlap_count;
930         unsigned max_bw = 0;
931
932         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
933                          "inaccurate.\n");
934
935         /* If we had a large number of windows, we would compute adjacency
936          * graph representing 2 window overlaps, find all cliques in the graph,
937          * assign bandwidth to each clique, and then select the clique with
938          * maximum bandwidth. But because we have at most 3 windows,
939          * implementing proper Bron-Kerbosh algorithm would be an overkill,
940          * brute force will suffice.
941          *
942          * Thus: find maximum bandwidth for either single or a pair of windows
943          * and count number of window pair overlaps. If there are three
944          * pairs, all 3 window overlap.
945          */
946
947         overlap_count = 0;
948         for (i = 0; i < n; i++) {
949                 unsigned int bw1;
950
951                 if (wins[i] == NULL)
952                         continue;
953                 bw1 = wins[i]->new_bandwidth;
954                 if (bw1 > max_bw)
955                         /* Single window */
956                         max_bw = bw1;
957
958                 for (j = i + 1; j < n; j++) {
959                         if (wins[j] == NULL)
960                                 continue;
961                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
962                                 unsigned int bw2 = wins[j]->new_bandwidth;
963                                 if (bw1 + bw2 > max_bw)
964                                         /* Window pair overlaps */
965                                         max_bw = bw1 + bw2;
966                                 overlap_count++;
967                         }
968                 }
969         }
970
971         if (overlap_count == 3)
972                 /* All three windows overlap */
973                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
974                          wins[2]->new_bandwidth;
975
976         return max_bw;
977 }
978
979 /*
980  * Calculate peak EMC bandwidth for each enabled window =
981  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
982  * (windows_tiling ? 2 : 1)
983  *
984  * note:
985  * (*) We use 2 tap V filter, so need double BW if use V filter
986  * (*) Tiling mode on T30 and DDR3 requires double BW
987  *
988  * return:
989  * bandwidth in kBps
990  */
991 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
992         struct tegra_dc_win *w)
993 {
994         unsigned long ret;
995         int tiled_windows_bw_multiplier;
996         unsigned long bpp;
997
998         if (!WIN_IS_ENABLED(w))
999                 return 0;
1000
1001         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
1002             w->out_w == 0 || w->out_h == 0)
1003                 return 0;
1004
1005         tiled_windows_bw_multiplier =
1006                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
1007
1008         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
1009          * but the size reported by tegra_dc_fmt_bpp for the planar version
1010          * is of the luma plane's size only. */
1011         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
1012                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
1013         ret = dc->mode.pclk / 1000UL * bpp / 8 * (win_use_v_filter(dc, w) ? 2 : 1)
1014                 * dfixed_trunc(w->w) / w->out_w *
1015                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
1016         /*
1017          * Assuming ~35% efficiency: i.e. if we calculate we need 70MBps, we
1018          * will request 200MBps from EMC.
1019          */
1020         ret = ret * 29 / 10;
1021
1022         return ret;
1023 }
1024
1025 static unsigned long tegra_dc_get_bandwidth(
1026         struct tegra_dc_win *windows[], int n)
1027 {
1028         int i;
1029
1030         BUG_ON(n > DC_N_WINDOWS);
1031
1032         /* emc rate and latency allowance both need to know per window
1033          * bandwidths */
1034         for (i = 0; i < n; i++) {
1035                 struct tegra_dc_win *w = windows[i];
1036
1037                 if (w)
1038                         w->new_bandwidth =
1039                                 tegra_dc_calc_win_bandwidth(w->dc, w);
1040         }
1041
1042         return tegra_dc_find_max_bandwidth(windows, n);
1043 }
1044
1045 /* to save power, call when display memory clients would be idle */
1046 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
1047 {
1048         trace_printk("%s:%s rate=%d\n", dc->ndev->name, __func__,
1049                 dc->emc_clk_rate);
1050         if (tegra_is_clk_enabled(dc->emc_clk))
1051                 clk_disable(dc->emc_clk);
1052         dc->emc_clk_rate = 0;
1053 }
1054
1055 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
1056 {
1057         unsigned i;
1058
1059         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
1060                 /* going from 0 to non-zero */
1061                 if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk))
1062                         clk_enable(dc->emc_clk);
1063
1064                 dc->emc_clk_rate = dc->new_emc_clk_rate;
1065                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
1066
1067                 if (!dc->new_emc_clk_rate) /* going from non-zero to 0 */
1068                         clk_disable(dc->emc_clk);
1069         }
1070
1071         for (i = 0; i < DC_N_WINDOWS; i++) {
1072                 struct tegra_dc_win *w = &dc->windows[i];
1073
1074                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1075                         tegra_dc_set_latency_allowance(dc, w);
1076                 trace_printk("%s:win%u bandwidth=%d\n", dc->ndev->name, w->idx,
1077                         w->bandwidth);
1078         }
1079 }
1080
1081 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1082 {
1083         unsigned long new_rate;
1084         struct tegra_dc *dc;
1085
1086         if (!use_dynamic_emc)
1087                 return 0;
1088
1089         dc = windows[0]->dc;
1090
1091         /* calculate the new rate based on this POST */
1092         new_rate = tegra_dc_get_bandwidth(windows, n);
1093         if (WARN_ONCE(new_rate > (ULONG_MAX / 1000), "bandwidth maxed out\n"))
1094                 new_rate = ULONG_MAX;
1095         else
1096                 new_rate = EMC_BW_TO_FREQ(new_rate * 1000);
1097
1098         if (tegra_dc_has_multiple_dc())
1099                 new_rate = ULONG_MAX;
1100
1101         trace_printk("%s:new_emc_clk_rate=%ld\n", dc->ndev->name, new_rate);
1102         dc->new_emc_clk_rate = new_rate;
1103
1104         return 0;
1105 }
1106
1107 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1108                                   bool v, unsigned Bpp)
1109 {
1110         /*
1111          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1112          *           (post_scaled_size_in_pixels - 1)), MAX)
1113          * Where the value of MAX is as follows:
1114          * For V_DDA_INCREMENT: 15.0 (0xF000)
1115          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1116          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1117          */
1118
1119         fixed20_12 out = dfixed_init(out_int);
1120         u32 dda_inc;
1121         int max;
1122
1123         if (v) {
1124                 max = 15;
1125         } else {
1126                 switch (Bpp) {
1127                 default:
1128                         WARN_ON_ONCE(1);
1129                         /* fallthrough */
1130                 case 4:
1131                         max = 4;
1132                         break;
1133                 case 2:
1134                         max = 8;
1135                         break;
1136                 }
1137         }
1138
1139         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1140         in.full -= dfixed_const(1);
1141
1142         dda_inc = dfixed_div(in, out);
1143
1144         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1145
1146         return dda_inc;
1147 }
1148
1149 static inline u32 compute_initial_dda(fixed20_12 in)
1150 {
1151         return dfixed_frac(in);
1152 }
1153
1154 /* does not support updating windows on multiple dcs in one call */
1155 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1156 {
1157         struct tegra_dc *dc;
1158         unsigned long update_mask = GENERAL_ACT_REQ;
1159         unsigned long val;
1160         bool update_blend = false;
1161         int i;
1162
1163         dc = windows[0]->dc;
1164
1165         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1166                 /* Acquire one_shot_lock to avoid race condition between
1167                  * cancellation of old delayed work and schedule of new
1168                  * delayed work. */
1169                 mutex_lock(&dc->one_shot_lock);
1170                 cancel_delayed_work_sync(&dc->one_shot_work);
1171         }
1172         mutex_lock(&dc->lock);
1173
1174         if (!dc->enabled) {
1175                 mutex_unlock(&dc->lock);
1176                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1177                         mutex_unlock(&dc->one_shot_lock);
1178                 return -EFAULT;
1179         }
1180
1181         if (no_vsync)
1182                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1183         else
1184                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1185
1186         for (i = 0; i < n; i++) {
1187                 struct tegra_dc_win *win = windows[i];
1188                 unsigned h_dda;
1189                 unsigned v_dda;
1190                 fixed20_12 h_offset, v_offset;
1191                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1192                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1193                 bool yuv = tegra_dc_is_yuv(win->fmt);
1194                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1195                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1196                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1197                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1198                 const bool filter_h = win_use_h_filter(dc, win);
1199                 const bool filter_v = win_use_v_filter(dc, win);
1200
1201                 if (win->z != dc->blend.z[win->idx]) {
1202                         dc->blend.z[win->idx] = win->z;
1203                         update_blend = true;
1204                 }
1205                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1206                         dc->blend.flags[win->idx]) {
1207                         dc->blend.flags[win->idx] =
1208                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1209                         update_blend = true;
1210                 }
1211
1212                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1213                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1214
1215                 if (!no_vsync)
1216                         update_mask |= WIN_A_ACT_REQ << win->idx;
1217
1218                 if (!WIN_IS_ENABLED(win)) {
1219                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1220                         continue;
1221                 }
1222
1223                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
1224                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
1225
1226                 tegra_dc_writel(dc,
1227                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1228                                 DC_WIN_POSITION);
1229                 tegra_dc_writel(dc,
1230                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1231                                 DC_WIN_SIZE);
1232
1233                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
1234                         tegra_dc_writel(dc,
1235                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1236                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1237                                         DC_WIN_PRESCALED_SIZE);
1238
1239                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1240                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1241                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1242                                         DC_WIN_DDA_INCREMENT);
1243                         h_dda = compute_initial_dda(win->x);
1244                         v_dda = compute_initial_dda(win->y);
1245                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1246                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1247                 }
1248
1249                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1250                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1251                 tegra_dc_writel(dc,
1252                                 (unsigned long)win->phys_addr,
1253                                 DC_WINBUF_START_ADDR);
1254
1255                 if (!yuvp) {
1256                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1257                 } else {
1258                         tegra_dc_writel(dc,
1259                                         (unsigned long)win->phys_addr_u,
1260                                         DC_WINBUF_START_ADDR_U);
1261                         tegra_dc_writel(dc,
1262                                         (unsigned long)win->phys_addr_v,
1263                                         DC_WINBUF_START_ADDR_V);
1264                         tegra_dc_writel(dc,
1265                                         LINE_STRIDE(win->stride) |
1266                                         UV_LINE_STRIDE(win->stride_uv),
1267                                         DC_WIN_LINE_STRIDE);
1268                 }
1269
1270                 h_offset = win->x;
1271                 if (invert_h) {
1272                         h_offset.full += win->w.full - dfixed_const(1);
1273                 }
1274
1275                 v_offset = win->y;
1276                 if (invert_v) {
1277                         v_offset.full += win->h.full - dfixed_const(1);
1278                 }
1279
1280                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1281                                 DC_WINBUF_ADDR_H_OFFSET);
1282                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1283                                 DC_WINBUF_ADDR_V_OFFSET);
1284
1285                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
1286                         if (WIN_IS_TILED(win))
1287                                 tegra_dc_writel(dc,
1288                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1289                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1290                                                 DC_WIN_BUFFER_ADDR_MODE);
1291                         else
1292                                 tegra_dc_writel(dc,
1293                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1294                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1295                                                 DC_WIN_BUFFER_ADDR_MODE);
1296                 }
1297
1298                 val = WIN_ENABLE;
1299                 if (yuv)
1300                         val |= CSC_ENABLE;
1301                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1302                         val |= COLOR_EXPAND;
1303
1304                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1305                         val |= CP_ENABLE;
1306
1307                 if (filter_h)
1308                         val |= H_FILTER_ENABLE;
1309                 if (filter_v)
1310                         val |= V_FILTER_ENABLE;
1311
1312                 if (invert_h)
1313                         val |= H_DIRECTION_DECREMENT;
1314                 if (invert_v)
1315                         val |= V_DIRECTION_DECREMENT;
1316
1317                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1318
1319 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1320                 if (win->global_alpha == 255)
1321                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1322                 else
1323                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1324                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1325 #endif
1326
1327                 win->dirty = no_vsync ? 0 : 1;
1328
1329                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1330                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1331                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1332                         __func__, win->idx, win->z,
1333                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1334                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1335                         win->out_x, win->out_y, win->out_w, win->out_h,
1336                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1337                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1338                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1339                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1340         }
1341
1342         if (update_blend) {
1343                 tegra_dc_set_blending(dc, &dc->blend);
1344                 for (i = 0; i < DC_N_WINDOWS; i++) {
1345                         if (!no_vsync)
1346                                 dc->windows[i].dirty = 1;
1347                         update_mask |= WIN_A_ACT_REQ << i;
1348                 }
1349         }
1350
1351         tegra_dc_set_dynamic_emc(windows, n);
1352
1353         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1354
1355         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1356         if (!no_vsync) {
1357                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1358                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1359                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1360         } else {
1361                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1362                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1363                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1364         }
1365
1366         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1367                 schedule_delayed_work(&dc->one_shot_work,
1368                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1369
1370         /* update EMC clock if calculated bandwidth has changed */
1371         tegra_dc_program_bandwidth(dc);
1372
1373         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1374                 update_mask |= NC_HOST_TRIG;
1375
1376         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1377         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1378
1379         mutex_unlock(&dc->lock);
1380         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1381                 mutex_unlock(&dc->one_shot_lock);
1382
1383         return 0;
1384 }
1385 EXPORT_SYMBOL(tegra_dc_update_windows);
1386
1387 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1388 {
1389         return dc->syncpt[i].id;
1390 }
1391 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1392
1393 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1394 {
1395         u32 max;
1396
1397         mutex_lock(&dc->lock);
1398         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1399                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1400         dc->syncpt[i].max = max;
1401         mutex_unlock(&dc->lock);
1402
1403         return max;
1404 }
1405
1406 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1407 {
1408         mutex_lock(&dc->lock);
1409         if ( dc->enabled )
1410                 while (dc->syncpt[i].min < val) {
1411                         dc->syncpt[i].min++;
1412                         nvhost_syncpt_cpu_incr(
1413                                         &nvhost_get_host(dc->ndev)->syncpt,
1414                                         dc->syncpt[i].id);
1415                 }
1416         mutex_unlock(&dc->lock);
1417 }
1418
1419 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1420                                              int n)
1421 {
1422         int i;
1423
1424         for (i = 0; i < n; i++) {
1425                 if (windows[i]->dirty)
1426                         return false;
1427         }
1428
1429         return true;
1430 }
1431
1432 /* does not support syncing windows on multiple dcs in one call */
1433 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1434 {
1435         int ret;
1436         if (n < 1 || n > DC_N_WINDOWS)
1437                 return -EINVAL;
1438
1439         if (!windows[0]->dc->enabled)
1440                 return -EFAULT;
1441
1442 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1443         /* Don't want to timeout on simulator */
1444         ret = wait_event_interruptible(windows[0]->dc->wq,
1445                 tegra_dc_windows_are_clean(windows, n));
1446 #else
1447         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1448                         windows[0]->dc->ndev->name);
1449         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1450                                          tegra_dc_windows_are_clean(windows, n),
1451                                          HZ);
1452         trace_printk("%s:After wait_event_interruptible_timeout\n",
1453                         windows[0]->dc->ndev->name);
1454 #endif
1455         return ret;
1456 }
1457 EXPORT_SYMBOL(tegra_dc_sync_windows);
1458
1459 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1460 {
1461 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1462         return clk_get_rate(dc->clk);
1463 #else
1464         return 27000000;
1465 #endif
1466 }
1467
1468 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1469 {
1470         unsigned long rate;
1471         unsigned long div;
1472
1473         rate = tegra_dc_clk_get_rate(dc);
1474
1475         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1476
1477         if (div < 2)
1478                 return 0;
1479
1480         return rate * 2 / div;
1481 }
1482
1483 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1484 {
1485         unsigned long rate;
1486         unsigned long div;
1487
1488         rate = clk_get_rate(parent);
1489
1490         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1491
1492         if (div < 2)
1493                 return 0;
1494
1495         return rate * 2 / div;
1496 }
1497
1498 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1499 {
1500         int pclk;
1501
1502         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1503                 unsigned long rate;
1504                 struct clk *parent_clk =
1505                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1506
1507                 if (dc->out->parent_clk_backup &&
1508                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1509                         rate = tegra_dc_pclk_predict_rate(
1510                                 parent_clk, dc->mode.pclk);
1511                         /* use pll_d as last resort */
1512                         if (rate < (dc->mode.pclk / 100 * 99) ||
1513                             rate > (dc->mode.pclk / 100 * 109))
1514                                 parent_clk = clk_get_sys(
1515                                         NULL, dc->out->parent_clk_backup);
1516                 }
1517
1518                 if (clk_get_parent(clk) != parent_clk)
1519                         clk_set_parent(clk, parent_clk);
1520
1521                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1522                         struct clk *base_clk = clk_get_parent(parent_clk);
1523
1524                         /* Assuming either pll_d or pll_d2 is used */
1525                         rate = dc->mode.pclk * 2;
1526
1527                         if (rate != clk_get_rate(base_clk))
1528                                 clk_set_rate(base_clk, rate);
1529                 }
1530         }
1531
1532         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1533                 unsigned long rate;
1534                 struct clk *parent_clk =
1535                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1536                 struct clk *base_clk = clk_get_parent(parent_clk);
1537
1538                 /*
1539                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1540                  * The required rate needs to be setup at 4x multiplier,
1541                  * as out0 is 1/2 of the actual PLL output.
1542                  */
1543
1544                 rate = dc->mode.pclk * 4;
1545                 if (rate != clk_get_rate(base_clk))
1546                         clk_set_rate(base_clk, rate);
1547
1548                 if (clk_get_parent(clk) != parent_clk)
1549                         clk_set_parent(clk, parent_clk);
1550         }
1551
1552         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1553                 unsigned long rate;
1554                 struct clk *parent_clk;
1555                 struct clk *base_clk;
1556
1557                 if (clk == dc->clk) {
1558                         parent_clk = clk_get_sys(NULL,
1559                                         dc->out->parent_clk ? : "pll_d_out0");
1560                         base_clk = clk_get_parent(parent_clk);
1561                         tegra_clk_cfg_ex(base_clk,
1562                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1563                 } else {
1564                         if (dc->pdata->default_out->dsi->dsi_instance) {
1565                                 parent_clk = clk_get_sys(NULL,
1566                                         dc->out->parent_clk ? : "pll_d2_out0");
1567                                 base_clk = clk_get_parent(parent_clk);
1568                                 tegra_clk_cfg_ex(base_clk,
1569                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1570                         } else {
1571                                 parent_clk = clk_get_sys(NULL,
1572                                         dc->out->parent_clk ? : "pll_d_out0");
1573                                 base_clk = clk_get_parent(parent_clk);
1574                                 tegra_clk_cfg_ex(base_clk,
1575                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1576                         }
1577                 }
1578
1579                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1580                 if (rate != clk_get_rate(base_clk))
1581                         clk_set_rate(base_clk, rate);
1582
1583                 if (clk_get_parent(clk) != parent_clk)
1584                         clk_set_parent(clk, parent_clk);
1585         }
1586
1587         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1588         tegra_dvfs_set_rate(clk, pclk);
1589 }
1590
1591 /* return non-zero if constraint is violated */
1592 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1593 {
1594         long a, b;
1595
1596         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1597         a = 0;
1598
1599         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1600         b = mode->h_front_porch - 1;
1601
1602         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1603         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1604                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1605         /* check Constraint 1 and 6 */
1606         if (a > b)
1607                 return 1;
1608
1609         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1610         if (mode->h_sync_width < 1)
1611                 return 4;
1612
1613         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1614         if (mode->h_active < 16)
1615                 return 7;
1616
1617         if (href) {
1618                 if (b > a && a % 2)
1619                         *href = a + 1; /* use smallest even value */
1620                 else
1621                         *href = a; /* even or only possible value */
1622         }
1623
1624         return 0;
1625 }
1626
1627 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1628 {
1629         long a;
1630         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1631
1632         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1633         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1634                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1635
1636         /* Constraint 6 */
1637         if (mode->v_front_porch < a + 1)
1638                 a = mode->v_front_porch - 1;
1639
1640         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1641         if (mode->v_sync_width < 1)
1642                 return 4;
1643
1644         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1645         if (mode->v_active < 16)
1646                 return 7;
1647
1648         if (vref)
1649                 *vref = a;
1650         return 0;
1651 }
1652
1653 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1654 {
1655         int ret;
1656         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1657         if (ret)
1658                 return ret;
1659         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1660         if (ret)
1661                 return ret;
1662
1663         return 0;
1664 }
1665
1666 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1667 {
1668         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1669         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1670                 return false;
1671
1672         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1673         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1674                 return false;
1675
1676         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1677          * (vertical blank). */
1678         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1679                 return false;
1680
1681         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1682         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1683                 return false;
1684
1685         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1686         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1687                 return false;
1688
1689         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1690          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1691         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1692                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1693                 return false;
1694
1695         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1696         if (mode->h_active < 16 || mode->v_active < 16)
1697                 return false;
1698
1699         return true;
1700 }
1701
1702 #ifdef DEBUG
1703 /* return in 1000ths of a Hertz */
1704 static int calc_refresh(const struct tegra_dc_mode *m)
1705 {
1706         long h_total, v_total, refresh;
1707         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1708                 m->h_sync_width;
1709         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1710                 m->v_sync_width;
1711         refresh = m->pclk / h_total;
1712         refresh *= 1000;
1713         refresh /= v_total;
1714         return refresh;
1715 }
1716
1717 static void print_mode(struct tegra_dc *dc,
1718                         const struct tegra_dc_mode *mode, const char *note)
1719 {
1720         if (mode) {
1721                 int refresh = calc_refresh(dc, mode);
1722                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1723                         note ? note : "",
1724                         mode->h_active, mode->v_active,
1725                         refresh / 1000, refresh % 1000,
1726                         mode->pclk);
1727         }
1728 }
1729 #else /* !DEBUG */
1730 static inline void print_mode(struct tegra_dc *dc,
1731                         const struct tegra_dc_mode *mode, const char *note) { }
1732 #endif /* DEBUG */
1733
1734 static inline void enable_dc_irq(unsigned int irq)
1735 {
1736 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1737         enable_irq(irq);
1738 #else
1739         /* Always disable DC interrupts on FPGA. */
1740         disable_irq(irq);
1741 #endif
1742 }
1743
1744 static inline void disable_dc_irq(unsigned int irq)
1745 {
1746         disable_irq(irq);
1747 }
1748
1749 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1750 {
1751         unsigned long val;
1752         unsigned long rate;
1753         unsigned long div;
1754         unsigned long pclk;
1755
1756         print_mode(dc, mode, __func__);
1757
1758         /* use default EMC rate when switching modes */
1759         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1760         tegra_dc_program_bandwidth(dc);
1761
1762         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1763         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1764                         DC_DISP_REF_TO_SYNC);
1765         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1766                         DC_DISP_SYNC_WIDTH);
1767         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1768                         DC_DISP_BACK_PORCH);
1769         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1770                         DC_DISP_DISP_ACTIVE);
1771         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1772                         DC_DISP_FRONT_PORCH);
1773
1774         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1775                         DC_DISP_DATA_ENABLE_OPTIONS);
1776
1777         /* TODO: MIPI/CRT/HDMI clock cals */
1778
1779         val = DISP_DATA_FORMAT_DF1P1C;
1780
1781         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1782                 val |= DISP_DATA_ALIGNMENT_MSB;
1783         else
1784                 val |= DISP_DATA_ALIGNMENT_LSB;
1785
1786         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1787                 val |= DISP_DATA_ORDER_RED_BLUE;
1788         else
1789                 val |= DISP_DATA_ORDER_BLUE_RED;
1790
1791         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1792
1793         rate = tegra_dc_clk_get_rate(dc);
1794
1795         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1796         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1797         if (pclk < (mode->pclk / 100 * 99) ||
1798             pclk > (mode->pclk / 100 * 109)) {
1799                 dev_err(&dc->ndev->dev,
1800                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1801                         rate, mode->pclk,
1802                         pclk, (mode->pclk / 100 * 99),
1803                         (mode->pclk / 100 * 109));
1804                 return -EINVAL;
1805         }
1806
1807         div = (rate * 2 / pclk) - 2;
1808         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1809
1810         tegra_dc_writel(dc, 0x00010001,
1811                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1812         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1813                         DC_DISP_DISP_CLOCK_CONTROL);
1814
1815 #ifdef CONFIG_SWITCH
1816         switch_set_state(&dc->modeset_switch,
1817                          (mode->h_active << 16) | mode->v_active);
1818 #endif
1819
1820         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1821         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1822
1823         print_mode_info(dc, dc->mode);
1824         return 0;
1825 }
1826
1827
1828 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1829 {
1830         memcpy(&dc->mode, mode, sizeof(dc->mode));
1831
1832         print_mode(dc, mode, __func__);
1833
1834         return 0;
1835 }
1836 EXPORT_SYMBOL(tegra_dc_set_mode);
1837
1838 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1839                 const struct fb_videomode *fbmode, bool stereo_mode)
1840 {
1841         struct tegra_dc_mode mode;
1842
1843         if (!fbmode->pixclock)
1844                 return -EINVAL;
1845
1846         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1847         mode.h_sync_width = fbmode->hsync_len;
1848         mode.v_sync_width = fbmode->vsync_len;
1849         mode.h_back_porch = fbmode->left_margin;
1850         mode.v_back_porch = fbmode->upper_margin;
1851         mode.h_active = fbmode->xres;
1852         mode.v_active = fbmode->yres;
1853         mode.h_front_porch = fbmode->right_margin;
1854         mode.v_front_porch = fbmode->lower_margin;
1855         mode.stereo_mode = stereo_mode;
1856         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1857                 /* HDMI controller requires h_ref=1, v_ref=1 */
1858                 mode.h_ref_to_sync = 1;
1859                 mode.v_ref_to_sync = 1;
1860         } else {
1861                 calc_ref_to_sync(&mode);
1862         }
1863         if (!check_ref_to_sync(&mode)) {
1864                 dev_err(&dc->ndev->dev,
1865                                 "Display timing doesn't meet restrictions.\n");
1866                 return -EINVAL;
1867         }
1868         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1869                 mode.h_active, mode.v_active, mode.pclk,
1870                 mode.h_ref_to_sync, mode.v_ref_to_sync
1871         );
1872
1873 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1874         /* Double the pixel clock and update v_active only for frame packed mode */
1875         if (mode.stereo_mode) {
1876                 mode.pclk *= 2;
1877                 /* total v_active = yres*2 + activespace */
1878                 mode.v_active = fbmode->yres*2 +
1879                                 fbmode->vsync_len +
1880                                 fbmode->upper_margin +
1881                                 fbmode->lower_margin;
1882         }
1883 #endif
1884
1885         mode.flags = 0;
1886
1887         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1888                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1889
1890         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1891                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1892
1893         return tegra_dc_set_mode(dc, &mode);
1894 }
1895 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1896
1897 void
1898 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1899 {
1900         unsigned int ctrl;
1901         unsigned long out_sel;
1902         unsigned long cmd_state;
1903
1904         mutex_lock(&dc->lock);
1905         if (!dc->enabled) {
1906                 mutex_unlock(&dc->lock);
1907                 return;
1908         }
1909
1910         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1911                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1912                 cfg->clk_select);
1913
1914         /* The new value should be effected immediately */
1915         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1916         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1917
1918         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1919                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1920         else
1921                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1922
1923         switch (cfg->which_pwm) {
1924         case TEGRA_PWM_PM0:
1925                 /* Select the LM0 on PM0 */
1926                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1927                 out_sel &= ~(7 << 0);
1928                 out_sel |= (3 << 0);
1929                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1930                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1931                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1932                 break;
1933         case TEGRA_PWM_PM1:
1934                 /* Select the LM1 on PM1 */
1935                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1936                 out_sel &= ~(7 << 4);
1937                 out_sel |= (3 << 4);
1938                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1939                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1940                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1941                 break;
1942         default:
1943                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1944                 break;
1945         }
1946         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1947         mutex_unlock(&dc->lock);
1948 }
1949 EXPORT_SYMBOL(tegra_dc_config_pwm);
1950
1951 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1952                                 const struct tegra_dc_out_pin *pins,
1953                                 const unsigned int n_pins)
1954 {
1955         unsigned int i;
1956
1957         int name;
1958         int pol;
1959
1960         u32 pol1, pol3;
1961
1962         u32 set1, unset1;
1963         u32 set3, unset3;
1964
1965         set1 = set3 = unset1 = unset3 = 0;
1966
1967         for (i = 0; i < n_pins; i++) {
1968                 name = (pins + i)->name;
1969                 pol  = (pins + i)->pol;
1970
1971                 /* set polarity by name */
1972                 switch (name) {
1973                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1974                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1975                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1976                         else
1977                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1978                         break;
1979                 case TEGRA_DC_OUT_PIN_H_SYNC:
1980                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1981                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1982                         else
1983                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1984                         break;
1985                 case TEGRA_DC_OUT_PIN_V_SYNC:
1986                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1987                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1988                         else
1989                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1990                         break;
1991                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1992                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1993                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1994                         else
1995                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1996                         break;
1997                 default:
1998                         printk("Invalid argument in function %s\n",
1999                                __FUNCTION__);
2000                         break;
2001                 }
2002         }
2003
2004         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2005         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2006
2007         pol1 |= set1;
2008         pol1 &= ~unset1;
2009
2010         pol3 |= set3;
2011         pol3 &= ~unset3;
2012
2013         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2014         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2015 }
2016
2017 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2018 {
2019         dc->out = out;
2020
2021         if (out->n_modes > 0)
2022                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
2023
2024         switch (out->type) {
2025         case TEGRA_DC_OUT_RGB:
2026                 dc->out_ops = &tegra_dc_rgb_ops;
2027                 break;
2028
2029         case TEGRA_DC_OUT_HDMI:
2030                 dc->out_ops = &tegra_dc_hdmi_ops;
2031                 break;
2032
2033         case TEGRA_DC_OUT_DSI:
2034                 dc->out_ops = &tegra_dc_dsi_ops;
2035                 break;
2036
2037         default:
2038                 dc->out_ops = NULL;
2039                 break;
2040         }
2041
2042         if (dc->out_ops && dc->out_ops->init)
2043                 dc->out_ops->init(dc);
2044
2045 }
2046
2047 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2048 {
2049         if (dc->out)
2050                 return dc->out->height;
2051         else
2052                 return 0;
2053 }
2054 EXPORT_SYMBOL(tegra_dc_get_out_height);
2055
2056 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2057 {
2058         if (dc->out)
2059                 return dc->out->width;
2060         else
2061                 return 0;
2062 }
2063 EXPORT_SYMBOL(tegra_dc_get_out_width);
2064
2065 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2066 {
2067         if (dc->out && dc->out->max_pixclock)
2068                 return dc->out->max_pixclock;
2069         else
2070                 return 0;
2071 }
2072 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2073
2074 void tegra_dc_enable_crc(struct tegra_dc *dc)
2075 {
2076         u32 val;
2077         tegra_dc_io_start(dc);
2078
2079         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2080                 CRC_ENABLE_ENABLE;
2081         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2082         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2083         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2084 }
2085
2086 void tegra_dc_disable_crc(struct tegra_dc *dc)
2087 {
2088         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2089         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2090         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2091
2092         tegra_dc_io_end(dc);
2093 }
2094
2095 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2096 {
2097         int crc = 0;
2098
2099         if (!dc) {
2100                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2101                 goto crc_error;
2102         }
2103
2104         /* TODO: Replace mdelay with code to sync VBlANK, since
2105          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2106         mdelay(TEGRA_CRC_LATCHED_DELAY);
2107
2108         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2109 crc_error:
2110         return crc;
2111 }
2112
2113 static void tegra_dc_vblank(struct work_struct *work)
2114 {
2115         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2116         bool nvsd_updated = false;
2117
2118         mutex_lock(&dc->lock);
2119
2120         /* Update the SD brightness */
2121         if (dc->enabled && dc->out->sd_settings)
2122                 nvsd_updated = nvsd_update_brightness(dc);
2123
2124         mutex_unlock(&dc->lock);
2125
2126         /* Do the actual brightness update outside of the mutex */
2127         if (nvsd_updated && dc->out->sd_settings &&
2128             dc->out->sd_settings->bl_device) {
2129
2130                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2131                 struct backlight_device *bl = platform_get_drvdata(pdev);
2132                 if (bl)
2133                         backlight_update_status(bl);
2134         }
2135 }
2136
2137 /* Must acquire dc lock and dc one-shot lock before invoking this function.
2138  * Acquire dc one-shot lock first and then dc lock. */
2139 void tegra_dc_host_trigger(struct tegra_dc *dc)
2140 {
2141         /* We release the lock here to prevent deadlock between
2142          * cancel_delayed_work_sync and one-shot work. */
2143         mutex_unlock(&dc->lock);
2144
2145         cancel_delayed_work_sync(&dc->one_shot_work);
2146         mutex_lock(&dc->lock);
2147
2148         schedule_delayed_work(&dc->one_shot_work,
2149                                 msecs_to_jiffies(dc->one_shot_delay_ms));
2150         tegra_dc_program_bandwidth(dc);
2151         tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
2152 }
2153
2154 static void tegra_dc_one_shot_worker(struct work_struct *work)
2155 {
2156         struct tegra_dc *dc = container_of(
2157                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2158         mutex_lock(&dc->lock);
2159         /* memory client has gone idle */
2160         tegra_dc_clear_bandwidth(dc);
2161         mutex_unlock(&dc->lock);
2162 }
2163
2164 /* return an arbitrarily large number if count overflow occurs.
2165  * make it a nice base-10 number to show up in stats output */
2166 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2167 {
2168         unsigned count = tegra_dc_readl(dc, reg);
2169         tegra_dc_writel(dc, 0, reg);
2170         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2171 }
2172
2173 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2174 {
2175         u32 val;
2176         int i;
2177
2178         dc->stats.underflows++;
2179         if (dc->underflow_mask & WIN_A_UF_INT) {
2180                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2181                         DC_WINBUF_AD_UFLOW_STATUS);
2182                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
2183         }
2184         if (dc->underflow_mask & WIN_B_UF_INT) {
2185                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2186                         DC_WINBUF_BD_UFLOW_STATUS);
2187                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
2188         }
2189         if (dc->underflow_mask & WIN_C_UF_INT) {
2190                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2191                         DC_WINBUF_CD_UFLOW_STATUS);
2192                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
2193         }
2194
2195         /* Check for any underflow reset conditions */
2196         for (i = 0; i < DC_N_WINDOWS; i++) {
2197                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2198                         dc->windows[i].underflows++;
2199
2200 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2201                         if (dc->windows[i].underflows > 4) {
2202                                 schedule_work(&dc->reset_work);
2203                                 /* reset counter */
2204                                 dc->windows[i].underflows = 0;
2205                                 trace_printk("%s:Reset work scheduled for "
2206                                                 "window %c\n",
2207                                                 dc->ndev->name, (65 + i));
2208                         }
2209 #endif
2210                 } else {
2211                         dc->windows[i].underflows = 0;
2212                 }
2213         }
2214
2215         /* Clear the underflow mask now that we've checked it. */
2216         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2217         dc->underflow_mask = 0;
2218         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2219         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2220         print_underflow_info(dc);
2221 }
2222
2223 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2224 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2225 {
2226 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2227         u32 val;
2228
2229         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2230         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2231             return true;
2232 #endif
2233         return false;
2234 }
2235
2236 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2237 {
2238         u32 val, i;
2239         u32 completed = 0;
2240         u32 dirty = 0;
2241
2242         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2243         for (i = 0; i < DC_N_WINDOWS; i++) {
2244 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2245                 /* FIXME: this is not needed when the simulator
2246                    clears WIN_x_UPDATE bits as in HW */
2247                 dc->windows[i].dirty = 0;
2248                 completed = 1;
2249 #else
2250                 if (!(val & (WIN_A_UPDATE << i))) {
2251                         dc->windows[i].dirty = 0;
2252                         completed = 1;
2253                 } else {
2254                         dirty = 1;
2255                 }
2256 #endif
2257         }
2258
2259         if (!dirty) {
2260                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2261                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2262                         val &= ~V_BLANK_INT;
2263                 else
2264                         val &= ~FRAME_END_INT;
2265                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2266         }
2267
2268         if (completed) {
2269                 if (!dirty) {
2270                         /* With the last completed window, go ahead
2271                            and enable the vblank interrupt for nvsd. */
2272                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2273                         val |= V_BLANK_INT;
2274                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2275                 }
2276
2277                 wake_up(&dc->wq);
2278         }
2279 }
2280
2281 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2282 {
2283         if (status & V_BLANK_INT) {
2284                 /* Sync up windows. */
2285                 tegra_dc_trigger_windows(dc);
2286
2287                 /* Schedule any additional bottom-half vblank actvities. */
2288                 schedule_work(&dc->vblank_work);
2289         }
2290
2291         if (status & FRAME_END_INT) {
2292                 /* Mark the frame_end as complete. */
2293                 if (!completion_done(&dc->frame_end_complete))
2294                         complete(&dc->frame_end_complete);
2295         }
2296 }
2297
2298 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2299 {
2300         if (status & V_BLANK_INT) {
2301                 /* Schedule any additional bottom-half vblank actvities. */
2302                 schedule_work(&dc->vblank_work);
2303
2304                 /* All windows updated. Mask subsequent V_BLANK interrupts */
2305                 if (!tegra_dc_windows_are_dirty(dc)) {
2306                         u32 val;
2307
2308                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2309                         val &= ~V_BLANK_INT;
2310                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2311                 }
2312         }
2313
2314         if (status & FRAME_END_INT) {
2315                 /* Mark the frame_end as complete. */
2316                 if (!completion_done(&dc->frame_end_complete))
2317                         complete(&dc->frame_end_complete);
2318
2319                 tegra_dc_trigger_windows(dc);
2320         }
2321 }
2322 #endif
2323
2324 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2325 {
2326 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2327         struct tegra_dc *dc = ptr;
2328         unsigned long status;
2329         unsigned long underflow_mask;
2330         u32 val;
2331
2332         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2333                 WARN(1, "IRQ when DC not powered!\n");
2334                 tegra_dc_io_start(dc);
2335                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2336                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2337                 tegra_dc_io_end(dc);
2338                 return IRQ_HANDLED;
2339         }
2340
2341         /* clear all status flags except underflow, save those for the worker */
2342         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2343         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2344         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2345         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2346
2347         /*
2348          * Overlays can get thier internal state corrupted during and underflow
2349          * condition.  The only way to fix this state is to reset the DC.
2350          * if we get 4 consecutive frames with underflows, assume we're
2351          * hosed and reset.
2352          */
2353         underflow_mask = status & ALL_UF_INT;
2354
2355         /* Check underflow */
2356         if (underflow_mask) {
2357                 dc->underflow_mask |= underflow_mask;
2358                 schedule_delayed_work(&dc->underflow_work,
2359                         msecs_to_jiffies(1));
2360         }
2361
2362         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2363                 tegra_dc_one_shot_irq(dc, status);
2364         else
2365                 tegra_dc_continuous_irq(dc, status);
2366
2367         return IRQ_HANDLED;
2368 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2369         return IRQ_NONE;
2370 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2371 }
2372
2373 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2374 {
2375         u32 color_control;
2376
2377         switch (dc->out->depth) {
2378         case 3:
2379                 color_control = BASE_COLOR_SIZE111;
2380                 break;
2381
2382         case 6:
2383                 color_control = BASE_COLOR_SIZE222;
2384                 break;
2385
2386         case 8:
2387                 color_control = BASE_COLOR_SIZE332;
2388                 break;
2389
2390         case 9:
2391                 color_control = BASE_COLOR_SIZE333;
2392                 break;
2393
2394         case 12:
2395                 color_control = BASE_COLOR_SIZE444;
2396                 break;
2397
2398         case 15:
2399                 color_control = BASE_COLOR_SIZE555;
2400                 break;
2401
2402         case 16:
2403                 color_control = BASE_COLOR_SIZE565;
2404                 break;
2405
2406         case 18:
2407                 color_control = BASE_COLOR_SIZE666;
2408                 break;
2409
2410         default:
2411                 color_control = BASE_COLOR_SIZE888;
2412                 break;
2413         }
2414
2415         switch (dc->out->dither) {
2416         case TEGRA_DC_DISABLE_DITHER:
2417                 color_control |= DITHER_CONTROL_DISABLE;
2418                 break;
2419         case TEGRA_DC_ORDERED_DITHER:
2420                 color_control |= DITHER_CONTROL_ORDERED;
2421                 break;
2422         case TEGRA_DC_ERRDIFF_DITHER:
2423                 /* The line buffer for error-diffusion dither is limited
2424                  * to 1280 pixels per line. This limits the maximum
2425                  * horizontal active area size to 1280 pixels when error
2426                  * diffusion is enabled.
2427                  */
2428                 BUG_ON(dc->mode.h_active > 1280);
2429                 color_control |= DITHER_CONTROL_ERRDIFF;
2430                 break;
2431         }
2432
2433         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2434 }
2435
2436 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2437 {
2438         u32 syncpt_id;
2439
2440         switch (dc->ndev->id) {
2441         case 0:
2442                 switch (idx) {
2443                 case 0:
2444                         syncpt_id = NVSYNCPT_DISP0_A;
2445                         break;
2446                 case 1:
2447                         syncpt_id = NVSYNCPT_DISP0_B;
2448                         break;
2449                 case 2:
2450                         syncpt_id = NVSYNCPT_DISP0_C;
2451                         break;
2452                 default:
2453                         BUG();
2454                         break;
2455                 }
2456                 break;
2457         case 1:
2458                 switch (idx) {
2459                 case 0:
2460                         syncpt_id = NVSYNCPT_DISP1_A;
2461                         break;
2462                 case 1:
2463                         syncpt_id = NVSYNCPT_DISP1_B;
2464                         break;
2465                 case 2:
2466                         syncpt_id = NVSYNCPT_DISP1_C;
2467                         break;
2468                 default:
2469                         BUG();
2470                         break;
2471                 }
2472                 break;
2473         default:
2474                 BUG();
2475                 break;
2476         }
2477
2478         return syncpt_id;
2479 }
2480
2481 static int tegra_dc_init(struct tegra_dc *dc)
2482 {
2483         int i;
2484
2485         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2486         if (dc->ndev->id == 0) {
2487                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2488                                       TEGRA_MC_PRIO_MED);
2489                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2490                                       TEGRA_MC_PRIO_MED);
2491                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2492                                       TEGRA_MC_PRIO_MED);
2493                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2494                                       TEGRA_MC_PRIO_MED);
2495                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2496                                       TEGRA_MC_PRIO_HIGH);
2497         } else if (dc->ndev->id == 1) {
2498                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2499                                       TEGRA_MC_PRIO_MED);
2500                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2501                                       TEGRA_MC_PRIO_MED);
2502                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2503                                       TEGRA_MC_PRIO_MED);
2504                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2505                                       TEGRA_MC_PRIO_MED);
2506                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2507                                       TEGRA_MC_PRIO_HIGH);
2508         }
2509         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2510                         DC_CMD_CONT_SYNCPT_VSYNC);
2511         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2512         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2513         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2514         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2515
2516         /* enable interrupts for vblank, frame_end and underflows */
2517         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2518                 DC_CMD_INT_ENABLE);
2519         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2520
2521         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2522
2523         tegra_dc_set_color_control(dc);
2524         for (i = 0; i < DC_N_WINDOWS; i++) {
2525                 struct tegra_dc_win *win = &dc->windows[i];
2526                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2527                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2528                 tegra_dc_set_csc(dc, &win->csc);
2529                 tegra_dc_set_lut(dc, win);
2530                 tegra_dc_set_scaling_filter(dc);
2531         }
2532
2533
2534         for (i = 0; i < dc->n_windows; i++) {
2535                 u32 syncpt = get_syncpt(dc, i);
2536
2537                 dc->syncpt[i].id = syncpt;
2538
2539                 dc->syncpt[i].min = dc->syncpt[i].max =
2540                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2541                                         syncpt);
2542         }
2543
2544         print_mode(dc, &dc->mode, __func__);
2545
2546         if (dc->mode.pclk)
2547                 if (tegra_dc_program_mode(dc, &dc->mode))
2548                         return -EINVAL;
2549
2550         /* Initialize SD AFTER the modeset.
2551            nvsd_init handles the sd_settings = NULL case. */
2552         nvsd_init(dc, dc->out->sd_settings);
2553
2554         return 0;
2555 }
2556
2557 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2558 {
2559         int failed_init = 0;
2560
2561         if (dc->out->enable)
2562                 dc->out->enable();
2563
2564         tegra_dc_setup_clk(dc, dc->clk);
2565         clk_enable(dc->clk);
2566
2567         /* do not accept interrupts during initialization */
2568         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2569         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2570
2571         enable_dc_irq(dc->irq);
2572
2573         failed_init = tegra_dc_init(dc);
2574         if (failed_init) {
2575                 _tegra_dc_controller_disable(dc);
2576                 return false;
2577         }
2578
2579         if (dc->out_ops && dc->out_ops->enable)
2580                 dc->out_ops->enable(dc);
2581
2582         if (dc->out->postpoweron)
2583                 dc->out->postpoweron();
2584
2585         /* force a full blending update */
2586         dc->blend.z[0] = -1;
2587
2588         tegra_dc_ext_enable(dc->ext);
2589
2590         trace_printk("%s:enable\n", dc->ndev->name);
2591         return true;
2592 }
2593
2594 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2595 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2596 {
2597         bool ret = true;
2598
2599         if (dc->out->enable)
2600                 dc->out->enable();
2601
2602         tegra_dc_setup_clk(dc, dc->clk);
2603         clk_enable(dc->clk);
2604
2605         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2606                 mutex_lock(&tegra_dcs[1]->lock);
2607                 disable_irq(tegra_dcs[1]->irq);
2608         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2609                 mutex_lock(&tegra_dcs[0]->lock);
2610                 disable_irq(tegra_dcs[0]->irq);
2611         }
2612
2613         msleep(5);
2614         tegra_periph_reset_assert(dc->clk);
2615         msleep(2);
2616 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2617         tegra_periph_reset_deassert(dc->clk);
2618         msleep(1);
2619 #endif
2620
2621         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2622                 enable_dc_irq(tegra_dcs[1]->irq);
2623                 mutex_unlock(&tegra_dcs[1]->lock);
2624         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2625                 enable_dc_irq(tegra_dcs[0]->irq);
2626                 mutex_unlock(&tegra_dcs[0]->lock);
2627         }
2628
2629         enable_dc_irq(dc->irq);
2630
2631         if (tegra_dc_init(dc)) {
2632                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2633                 ret = false;
2634         }
2635
2636         if (dc->out_ops && dc->out_ops->enable)
2637                 dc->out_ops->enable(dc);
2638
2639         if (dc->out->postpoweron)
2640                 dc->out->postpoweron();
2641
2642         /* force a full blending update */
2643         dc->blend.z[0] = -1;
2644
2645         tegra_dc_ext_enable(dc->ext);
2646
2647         if (!ret) {
2648                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2649                 _tegra_dc_controller_disable(dc);
2650         }
2651
2652         trace_printk("%s:reset enable\n", dc->ndev->name);
2653         return ret;
2654 }
2655 #endif
2656
2657 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2658 {
2659         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2660 }
2661
2662 static bool _tegra_dc_enable(struct tegra_dc *dc)
2663 {
2664         if (dc->mode.pclk == 0) {
2665                 switch (dc->out->type) {
2666                 case TEGRA_DC_OUT_HDMI:
2667                 /* DC enable called but no videomode is loaded.
2668                      Check if HDMI is connected, then set fallback mdoe */
2669                 if (tegra_dc_hpd(dc)) {
2670                         if (_tegra_dc_set_default_videomode(dc))
2671                                 return false;
2672                 } else
2673                         return false;
2674
2675                 break;
2676
2677                 /* Do nothing for other outputs for now */
2678                 case TEGRA_DC_OUT_RGB:
2679
2680                 case TEGRA_DC_OUT_DSI:
2681
2682                 default:
2683                         return false;
2684                 }
2685         }
2686
2687         if (!dc->out)
2688                 return false;
2689
2690         tegra_dc_io_start(dc);
2691
2692         return _tegra_dc_controller_enable(dc);
2693 }
2694
2695 void tegra_dc_enable(struct tegra_dc *dc)
2696 {
2697         mutex_lock(&dc->lock);
2698
2699         if (!dc->enabled)
2700                 dc->enabled = _tegra_dc_enable(dc);
2701
2702         mutex_unlock(&dc->lock);
2703         print_mode_info(dc, dc->mode);
2704 }
2705
2706 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2707 {
2708         unsigned i;
2709
2710         if (dc->out_ops && dc->out_ops->disable)
2711                 dc->out_ops->disable(dc);
2712
2713         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2714         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2715         disable_irq(dc->irq);
2716
2717         tegra_dc_clear_bandwidth(dc);
2718         clk_disable(dc->clk);
2719         tegra_dvfs_set_rate(dc->clk, 0);
2720
2721         if (dc->out && dc->out->disable)
2722                 dc->out->disable();
2723
2724         for (i = 0; i < dc->n_windows; i++) {
2725                 struct tegra_dc_win *w = &dc->windows[i];
2726
2727                 /* reset window bandwidth */
2728                 w->bandwidth = 0;
2729                 w->new_bandwidth = 0;
2730
2731                 /* disable windows */
2732                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2733
2734                 /* flush any pending syncpt waits */
2735                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2736                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2737                                 dc->syncpt[i].id);
2738                         dc->syncpt[i].min++;
2739                         nvhost_syncpt_cpu_incr(
2740                                 &nvhost_get_host(dc->ndev)->syncpt,
2741                                 dc->syncpt[i].id);
2742                 }
2743         }
2744         trace_printk("%s:disabled\n", dc->ndev->name);
2745 }
2746
2747 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2748 {
2749 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2750         u32 val;
2751         if (dc->enabled)  {
2752                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2753                 if (enable)
2754                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2755                 else
2756                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2757                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2758         }
2759 #endif
2760 }
2761
2762 bool tegra_dc_stats_get(struct tegra_dc *dc)
2763 {
2764 #if 0 /* right now it is always enabled */
2765         u32 val;
2766         bool res;
2767
2768         if (dc->enabled)  {
2769                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2770                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2771         } else {
2772                 res = false;
2773         }
2774
2775         return res;
2776 #endif
2777         return true;
2778 }
2779
2780 /* make the screen blank by disabling all windows */
2781 void tegra_dc_blank(struct tegra_dc *dc)
2782 {
2783         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2784         unsigned i;
2785
2786         for (i = 0; i < DC_N_WINDOWS; i++) {
2787                 dcwins[i] = tegra_dc_get_window(dc, i);
2788                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2789         }
2790
2791         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2792         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2793 }
2794
2795 static void _tegra_dc_disable(struct tegra_dc *dc)
2796 {
2797         _tegra_dc_controller_disable(dc);
2798         tegra_dc_io_end(dc);
2799 }
2800
2801 void tegra_dc_disable(struct tegra_dc *dc)
2802 {
2803         tegra_dc_ext_disable(dc->ext);
2804
2805         /* it's important that new underflow work isn't scheduled before the
2806          * lock is acquired. */
2807         cancel_delayed_work_sync(&dc->underflow_work);
2808         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2809                 mutex_lock(&dc->one_shot_lock);
2810                 cancel_delayed_work_sync(&dc->one_shot_work);
2811         }
2812
2813         mutex_lock(&dc->lock);
2814
2815         if (dc->enabled) {
2816                 dc->enabled = false;
2817
2818                 if (!dc->suspended)
2819                         _tegra_dc_disable(dc);
2820         }
2821
2822 #ifdef CONFIG_SWITCH
2823         switch_set_state(&dc->modeset_switch, 0);
2824 #endif
2825
2826         mutex_unlock(&dc->lock);
2827         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2828                 mutex_unlock(&dc->one_shot_lock);
2829         print_mode_info(dc, dc->mode);
2830 }
2831
2832 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2833 static void tegra_dc_reset_worker(struct work_struct *work)
2834 {
2835         struct tegra_dc *dc =
2836                 container_of(work, struct tegra_dc, reset_work);
2837
2838         unsigned long val = 0;
2839
2840         mutex_lock(&shared_lock);
2841
2842         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2843
2844         tegra_dc_ext_disable(dc->ext);
2845
2846         mutex_lock(&dc->lock);
2847
2848         if (dc->enabled == false)
2849                 goto unlock;
2850
2851         dc->enabled = false;
2852
2853         /*
2854          * off host read bus
2855          */
2856         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2857         val &= ~(0x00000100);
2858         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2859
2860         /*
2861          * set DC to STOP mode
2862          */
2863         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2864
2865         msleep(10);
2866
2867         _tegra_dc_controller_disable(dc);
2868
2869         /* _tegra_dc_controller_reset_enable deasserts reset */
2870         _tegra_dc_controller_reset_enable(dc);
2871
2872         dc->enabled = true;
2873
2874         /* reopen host read bus */
2875         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2876         val &= ~(0x00000100);
2877         val |= 0x100;
2878         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2879
2880 unlock:
2881         mutex_unlock(&dc->lock);
2882         mutex_unlock(&shared_lock);
2883         trace_printk("%s:reset complete\n", dc->ndev->name);
2884 }
2885 #endif
2886
2887 static void tegra_dc_underflow_worker(struct work_struct *work)
2888 {
2889         struct tegra_dc *dc = container_of(
2890                 to_delayed_work(work), struct tegra_dc, underflow_work);
2891
2892         mutex_lock(&dc->lock);
2893         if (dc->enabled) {
2894                 tegra_dc_underflow_handler(dc);
2895         }
2896         mutex_unlock(&dc->lock);
2897 }
2898
2899 #ifdef CONFIG_SWITCH
2900 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2901 {
2902         struct tegra_dc *dc =
2903                 container_of(sdev, struct tegra_dc, modeset_switch);
2904
2905         if (!sdev->state)
2906                 return sprintf(buf, "offline\n");
2907
2908         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2909 }
2910 #endif
2911
2912 static int tegra_dc_probe(struct nvhost_device *ndev)
2913 {
2914         struct tegra_dc *dc;
2915         struct clk *clk;
2916         struct clk *emc_clk;
2917         struct resource *res;
2918         struct resource *base_res;
2919         struct resource *fb_mem = NULL;
2920         int ret = 0;
2921         void __iomem *base;
2922         int irq;
2923         int i;
2924
2925         if (!ndev->dev.platform_data) {
2926                 dev_err(&ndev->dev, "no platform data\n");
2927                 return -ENOENT;
2928         }
2929
2930         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2931         if (!dc) {
2932                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2933                 return -ENOMEM;
2934         }
2935
2936         irq = nvhost_get_irq_byname(ndev, "irq");
2937         if (irq <= 0) {
2938                 dev_err(&ndev->dev, "no irq\n");
2939                 ret = -ENOENT;
2940                 goto err_free;
2941         }
2942
2943         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2944         if (!res) {
2945                 dev_err(&ndev->dev, "no mem resource\n");
2946                 ret = -ENOENT;
2947                 goto err_free;
2948         }
2949
2950         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2951         if (!base_res) {
2952                 dev_err(&ndev->dev, "request_mem_region failed\n");
2953                 ret = -EBUSY;
2954                 goto err_free;
2955         }
2956
2957         base = ioremap(res->start, resource_size(res));
2958         if (!base) {
2959                 dev_err(&ndev->dev, "registers can't be mapped\n");
2960                 ret = -EBUSY;
2961                 goto err_release_resource_reg;
2962         }
2963
2964         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2965
2966         clk = clk_get(&ndev->dev, NULL);
2967         if (IS_ERR_OR_NULL(clk)) {
2968                 dev_err(&ndev->dev, "can't get clock\n");
2969                 ret = -ENOENT;
2970                 goto err_iounmap_reg;
2971         }
2972
2973         emc_clk = clk_get(&ndev->dev, "emc");
2974         if (IS_ERR_OR_NULL(emc_clk)) {
2975                 dev_err(&ndev->dev, "can't get emc clock\n");
2976                 ret = -ENOENT;
2977                 goto err_put_clk;
2978         }
2979
2980         dc->clk = clk;
2981         dc->emc_clk = emc_clk;
2982         dc->shift_clk_div = 1;
2983         /* Initialize one shot work delay, it will be assigned by dsi
2984          * according to refresh rate later. */
2985         dc->one_shot_delay_ms = 40;
2986
2987         dc->base_res = base_res;
2988         dc->base = base;
2989         dc->irq = irq;
2990         dc->ndev = ndev;
2991         dc->pdata = ndev->dev.platform_data;
2992
2993         /*
2994          * The emc is a shared clock, it will be set based on
2995          * the requirements for each user on the bus.
2996          */
2997         dc->emc_clk_rate = 0;
2998
2999         mutex_init(&dc->lock);
3000         mutex_init(&dc->one_shot_lock);
3001         init_completion(&dc->frame_end_complete);
3002         init_waitqueue_head(&dc->wq);
3003 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3004         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3005 #endif
3006         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3007         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3008         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3009
3010         tegra_dc_init_lut_defaults(&dc->fb_lut);
3011
3012         dc->n_windows = DC_N_WINDOWS;
3013         for (i = 0; i < dc->n_windows; i++) {
3014                 struct tegra_dc_win *win = &dc->windows[i];
3015                 win->idx = i;
3016                 win->dc = dc;
3017                 tegra_dc_init_csc_defaults(&win->csc);
3018                 tegra_dc_init_lut_defaults(&win->lut);
3019         }
3020
3021         ret = tegra_dc_set(dc, ndev->id);
3022         if (ret < 0) {
3023                 dev_err(&ndev->dev, "can't add dc\n");
3024                 goto err_free_irq;
3025         }
3026
3027         nvhost_set_drvdata(ndev, dc);
3028
3029 #ifdef CONFIG_SWITCH
3030         dc->modeset_switch.name = dev_name(&ndev->dev);
3031         dc->modeset_switch.state = 0;
3032         dc->modeset_switch.print_state = switch_modeset_print_mode;
3033         switch_dev_register(&dc->modeset_switch);
3034 #endif
3035
3036         tegra_dc_feature_register(dc);
3037
3038         if (dc->pdata->default_out)
3039                 tegra_dc_set_out(dc, dc->pdata->default_out);
3040         else
3041                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
3042
3043         dc->vblank_syncpt = (dc->ndev->id == 0) ?
3044                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
3045
3046         dc->ext = tegra_dc_ext_register(ndev, dc);
3047         if (IS_ERR_OR_NULL(dc->ext)) {
3048                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3049                 dc->ext = NULL;
3050         }
3051
3052         mutex_lock(&dc->lock);
3053         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
3054                 dc->enabled = _tegra_dc_enable(dc);
3055         mutex_unlock(&dc->lock);
3056
3057         /* interrupt handler must be registered before tegra_fb_register() */
3058         if (request_irq(irq, tegra_dc_irq, 0,
3059                         dev_name(&ndev->dev), dc)) {
3060                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3061                 ret = -EBUSY;
3062                 goto err_put_emc_clk;
3063         }
3064
3065         tegra_dc_create_debugfs(dc);
3066
3067         dev_info(&ndev->dev, "probed\n");
3068
3069         if (dc->pdata->fb) {
3070                 if (dc->pdata->fb->bits_per_pixel == -1) {
3071                         unsigned long fmt;
3072                         tegra_dc_writel(dc,
3073                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3074                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3075
3076                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3077                         dc->pdata->fb->bits_per_pixel =
3078                                 tegra_dc_fmt_bpp(fmt);
3079                 }
3080
3081                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3082                 if (IS_ERR_OR_NULL(dc->fb))
3083                         dc->fb = NULL;
3084         }
3085
3086         if (dc->out && dc->out->hotplug_init)
3087                 dc->out->hotplug_init();
3088
3089         if (dc->out_ops && dc->out_ops->detect)
3090                 dc->out_ops->detect(dc);
3091         else
3092                 dc->connected = true;
3093
3094         tegra_dc_create_sysfs(&dc->ndev->dev);
3095
3096         return 0;
3097
3098 err_free_irq:
3099         free_irq(irq, dc);
3100 err_put_emc_clk:
3101         clk_put(emc_clk);
3102 err_put_clk:
3103         clk_put(clk);
3104 err_iounmap_reg:
3105         iounmap(base);
3106         if (fb_mem)
3107                 release_resource(fb_mem);
3108 err_release_resource_reg:
3109         release_resource(base_res);
3110 err_free:
3111         kfree(dc);
3112
3113         return ret;
3114 }
3115
3116 static int tegra_dc_remove(struct nvhost_device *ndev)
3117 {
3118         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3119
3120         tegra_dc_remove_sysfs(&dc->ndev->dev);
3121         tegra_dc_remove_debugfs(dc);
3122
3123         if (dc->fb) {
3124                 tegra_fb_unregister(dc->fb);
3125                 if (dc->fb_mem)
3126                         release_resource(dc->fb_mem);
3127         }
3128
3129         tegra_dc_ext_disable(dc->ext);
3130
3131         if (dc->ext)
3132                 tegra_dc_ext_unregister(dc->ext);
3133
3134         if (dc->enabled)
3135                 _tegra_dc_disable(dc);
3136
3137 #ifdef CONFIG_SWITCH
3138         switch_dev_unregister(&dc->modeset_switch);
3139 #endif
3140         free_irq(dc->irq, dc);
3141         clk_put(dc->emc_clk);
3142         clk_put(dc->clk);
3143         iounmap(dc->base);
3144         if (dc->fb_mem)
3145                 release_resource(dc->base_res);
3146         kfree(dc);
3147         tegra_dc_set(NULL, ndev->id);
3148         return 0;
3149 }
3150
3151 #ifdef CONFIG_PM
3152 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3153 {
3154         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3155
3156         trace_printk("%s:suspend\n", dc->ndev->name);
3157         dev_info(&ndev->dev, "suspend\n");
3158
3159         tegra_dc_ext_disable(dc->ext);
3160
3161         mutex_lock(&dc->lock);
3162
3163         if (dc->out_ops && dc->out_ops->suspend)
3164                 dc->out_ops->suspend(dc);
3165
3166         if (dc->enabled) {
3167                 _tegra_dc_disable(dc);
3168
3169                 dc->suspended = true;
3170         }
3171
3172         if (dc->out && dc->out->postsuspend) {
3173                 dc->out->postsuspend();
3174                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3175                         /*
3176                          * avoid resume event due to voltage falling
3177                          */
3178                         msleep(100);
3179         }
3180
3181         mutex_unlock(&dc->lock);
3182
3183         return 0;
3184 }
3185
3186 static int tegra_dc_resume(struct nvhost_device *ndev)
3187 {
3188         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3189
3190         trace_printk("%s:resume\n", dc->ndev->name);
3191         dev_info(&ndev->dev, "resume\n");
3192
3193         mutex_lock(&dc->lock);
3194         dc->suspended = false;
3195
3196         if (dc->enabled)
3197                 _tegra_dc_enable(dc);
3198
3199         if (dc->out && dc->out->hotplug_init)
3200                 dc->out->hotplug_init();
3201
3202         if (dc->out_ops && dc->out_ops->resume)
3203                 dc->out_ops->resume(dc);
3204         mutex_unlock(&dc->lock);
3205
3206         return 0;
3207 }
3208
3209 #endif /* CONFIG_PM */
3210
3211 extern int suspend_set(const char *val, struct kernel_param *kp)
3212 {
3213         if (!strcmp(val, "dump"))
3214                 dump_regs(tegra_dcs[0]);
3215 #ifdef CONFIG_PM
3216         else if (!strcmp(val, "suspend"))
3217                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3218         else if (!strcmp(val, "resume"))
3219                 tegra_dc_resume(tegra_dcs[0]->ndev);
3220 #endif
3221
3222         return 0;
3223 }
3224
3225 extern int suspend_get(char *buffer, struct kernel_param *kp)
3226 {
3227         return 0;
3228 }
3229
3230 int suspend;
3231
3232 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3233
3234 struct nvhost_driver tegra_dc_driver = {
3235         .driver = {
3236                 .name = "tegradc",
3237                 .owner = THIS_MODULE,
3238         },
3239         .probe = tegra_dc_probe,
3240         .remove = tegra_dc_remove,
3241 #ifdef CONFIG_PM
3242         .suspend = tegra_dc_suspend,
3243         .resume = tegra_dc_resume,
3244 #endif
3245 };
3246
3247 static int __init tegra_dc_module_init(void)
3248 {
3249         int ret = tegra_dc_ext_module_init();
3250         if (ret)
3251                 return ret;
3252         return nvhost_driver_register(&tegra_dc_driver);
3253 }
3254
3255 static void __exit tegra_dc_module_exit(void)
3256 {
3257         nvhost_driver_unregister(&tegra_dc_driver);
3258         tegra_dc_ext_module_exit();
3259 }
3260
3261 module_exit(tegra_dc_module_exit);
3262 module_init(tegra_dc_module_init);