drivers/video/tegra/dc/dc.c

   1 /*
   2  * drivers/video/tegra/dc/dc.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (C) 2010-2011 NVIDIA Corporation
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/mutex.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/workqueue.h>
  32 #include <linux/ktime.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/backlight.h>
  36 #include <video/tegrafb.h>
  37
  38 #include <mach/clk.h>
  39 #include <mach/dc.h>
  40 #include <mach/fb.h>
  41 #include <mach/mc.h>
  42 #include <mach/nvhost.h>
  43 #include <mach/latency_allowance.h>
  44
  45 #include "dc_reg.h"
  46 #include "dc_priv.h"
  47 #include "overlay.h"
  48 #include "nvsd.h"
  49
  50 #define TEGRA_CRC_LATCHED_DELAY         34
  51
  52 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
  53 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
  54 #else
  55 /* ignore underflows when on simulation and fpga platform */
  56 #define ALL_UF_INT (0)
  57 #endif
  58
  59 static int no_vsync;
  60
  61 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
  62
  63 static int use_dynamic_emc = 1;
  64
  65 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
  66
  67 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
  68
  69 DEFINE_MUTEX(tegra_dc_lock);
  70 DEFINE_MUTEX(shared_lock);
  71
  72 static inline int tegra_dc_fmt_bpp(int fmt)
  73 {
  74         switch (fmt) {
  75         case TEGRA_WIN_FMT_P1:
  76                 return 1;
  77
  78         case TEGRA_WIN_FMT_P2:
  79                 return 2;
  80
  81         case TEGRA_WIN_FMT_P4:
  82                 return 4;
  83
  84         case TEGRA_WIN_FMT_P8:
  85                 return 8;
  86
  87         case TEGRA_WIN_FMT_B4G4R4A4:
  88         case TEGRA_WIN_FMT_B5G5R5A:
  89         case TEGRA_WIN_FMT_B5G6R5:
  90         case TEGRA_WIN_FMT_AB5G5R5:
  91                 return 16;
  92
  93         case TEGRA_WIN_FMT_B8G8R8A8:
  94         case TEGRA_WIN_FMT_R8G8B8A8:
  95         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
  96         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
  97                 return 32;
  98
  99         /* for planar formats, size of the Y plane, 8bit */
 100         case TEGRA_WIN_FMT_YCbCr420P:
 101         case TEGRA_WIN_FMT_YUV420P:
 102         case TEGRA_WIN_FMT_YCbCr422P:
 103         case TEGRA_WIN_FMT_YUV422P:
 104                 return 8;
 105
 106         case TEGRA_WIN_FMT_YCbCr422:
 107         case TEGRA_WIN_FMT_YUV422:
 108         case TEGRA_WIN_FMT_YCbCr422R:
 109         case TEGRA_WIN_FMT_YUV422R:
 110         case TEGRA_WIN_FMT_YCbCr422RA:
 111         case TEGRA_WIN_FMT_YUV422RA:
 112                 /* FIXME: need to know the bpp of these formats */
 113                 return 0;
 114         }
 115         return 0;
 116 }
 117
 118 static inline bool tegra_dc_is_yuv_planar(int fmt)
 119 {
 120         switch (fmt) {
 121         case TEGRA_WIN_FMT_YUV420P:
 122         case TEGRA_WIN_FMT_YCbCr420P:
 123         case TEGRA_WIN_FMT_YCbCr422P:
 124         case TEGRA_WIN_FMT_YUV422P:
 125                 return true;
 126         }
 127         return false;
 128 }
 129
 130 #define DUMP_REG(a) do {                        \
 131         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
 132                  #a, a, tegra_dc_readl(dc, a));               \
 133         print(data, buff);                                    \
 134         } while (0)
 135
 136 static void _dump_regs(struct tegra_dc *dc, void *data,
 137                        void (* print)(void *data, const char *str))
 138 {
 139         int i;
 140         char buff[256];
 141
 142         tegra_dc_io_start(dc);
 143         clk_enable(dc->clk);
 144
 145         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 146         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 147         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 148         DUMP_REG(DC_CMD_INT_STATUS);
 149         DUMP_REG(DC_CMD_INT_MASK);
 150         DUMP_REG(DC_CMD_INT_ENABLE);
 151         DUMP_REG(DC_CMD_INT_TYPE);
 152         DUMP_REG(DC_CMD_INT_POLARITY);
 153         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 154         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 155         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 156         DUMP_REG(DC_CMD_STATE_ACCESS);
 157         DUMP_REG(DC_CMD_STATE_CONTROL);
 158         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 159         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 160
 161         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 162         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 163         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 164         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
 165         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
 166         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 167         DUMP_REG(DC_DISP_REF_TO_SYNC);
 168         DUMP_REG(DC_DISP_SYNC_WIDTH);
 169         DUMP_REG(DC_DISP_BACK_PORCH);
 170         DUMP_REG(DC_DISP_DISP_ACTIVE);
 171         DUMP_REG(DC_DISP_FRONT_PORCH);
 172         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 173         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 174         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 175         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 176         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 177         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 178         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 179         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 180         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 181         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 182         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 183         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 184         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 185         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 186         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 187         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 188         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 189         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 190         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 191         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 192         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 193         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 194         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 195         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 196         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 197         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 198         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 199         DUMP_REG(DC_DISP_M0_CONTROL);
 200         DUMP_REG(DC_DISP_M1_CONTROL);
 201         DUMP_REG(DC_DISP_DI_CONTROL);
 202         DUMP_REG(DC_DISP_PP_CONTROL);
 203         DUMP_REG(DC_DISP_PP_SELECT_A);
 204         DUMP_REG(DC_DISP_PP_SELECT_B);
 205         DUMP_REG(DC_DISP_PP_SELECT_C);
 206         DUMP_REG(DC_DISP_PP_SELECT_D);
 207         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 208         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 209         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 210         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 211         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 212         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 213         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 214         DUMP_REG(DC_DISP_BORDER_COLOR);
 215         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 216         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 217         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 218         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 219         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 220         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 221         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 222         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 223         DUMP_REG(DC_DISP_CURSOR_POSITION);
 224         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 225         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 226         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 227         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 228         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 229         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 230         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 231         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 232         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 233         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
 234         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 235         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 236         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 237
 238
 239         for (i = 0; i < 3; i++) {
 240                 print(data, "\n");
 241                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
 242                 print(data, buff);
 243
 244                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
 245                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 246                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 247                 DUMP_REG(DC_WIN_WIN_OPTIONS);
 248                 DUMP_REG(DC_WIN_BYTE_SWAP);
 249                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
 250                 DUMP_REG(DC_WIN_COLOR_DEPTH);
 251                 DUMP_REG(DC_WIN_POSITION);
 252                 DUMP_REG(DC_WIN_SIZE);
 253                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
 254                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
 255                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
 256                 DUMP_REG(DC_WIN_DDA_INCREMENT);
 257                 DUMP_REG(DC_WIN_LINE_STRIDE);
 258                 DUMP_REG(DC_WIN_BUF_STRIDE);
 259                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 260                 DUMP_REG(DC_WIN_BLEND_NOKEY);
 261                 DUMP_REG(DC_WIN_BLEND_1WIN);
 262                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
 263                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 264                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 265                 DUMP_REG(DC_WINBUF_START_ADDR);
 266                 DUMP_REG(DC_WINBUF_START_ADDR_U);
 267                 DUMP_REG(DC_WINBUF_START_ADDR_V);
 268                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 269                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 270                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 271                 DUMP_REG(DC_WIN_CSC_YOF);
 272                 DUMP_REG(DC_WIN_CSC_KYRGB);
 273                 DUMP_REG(DC_WIN_CSC_KUR);
 274                 DUMP_REG(DC_WIN_CSC_KVR);
 275                 DUMP_REG(DC_WIN_CSC_KUG);
 276                 DUMP_REG(DC_WIN_CSC_KVG);
 277                 DUMP_REG(DC_WIN_CSC_KUB);
 278                 DUMP_REG(DC_WIN_CSC_KVB);
 279         }
 280
 281         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 282         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
 283         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
 284         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
 285         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
 286         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
 287         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 288         DUMP_REG(DC_DISP_M1_CONTROL);
 289         DUMP_REG(DC_COM_PM1_CONTROL);
 290         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
 291         DUMP_REG(DC_DISP_SD_CONTROL);
 292
 293         clk_disable(dc->clk);
 294         tegra_dc_io_end(dc);
 295 }
 296
 297 #undef DUMP_REG
 298
 299 #ifdef DEBUG
 300 static void dump_regs_print(void *data, const char *str)
 301 {
 302         struct tegra_dc *dc = data;
 303         dev_dbg(&dc->ndev->dev, "%s", str);
 304 }
 305
 306 static void dump_regs(struct tegra_dc *dc)
 307 {
 308         _dump_regs(dc, dc, dump_regs_print);
 309 }
 310 #else /* !DEBUG */
 311
 312 static void dump_regs(struct tegra_dc *dc) {}
 313
 314 #endif /* DEBUG */
 315
 316 #ifdef CONFIG_DEBUG_FS
 317
 318 static void dbg_regs_print(void *data, const char *str)
 319 {
 320         struct seq_file *s = data;
 321
 322         seq_printf(s, "%s", str);
 323 }
 324
 325 #undef DUMP_REG
 326
 327 static int dbg_dc_show(struct seq_file *s, void *unused)
 328 {
 329         struct tegra_dc *dc = s->private;
 330
 331         _dump_regs(dc, s, dbg_regs_print);
 332
 333         return 0;
 334 }
 335
 336
 337 static int dbg_dc_open(struct inode *inode, struct file *file)
 338 {
 339         return single_open(file, dbg_dc_show, inode->i_private);
 340 }
 341
 342 static const struct file_operations regs_fops = {
 343         .open           = dbg_dc_open,
 344         .read           = seq_read,
 345         .llseek         = seq_lseek,
 346         .release        = single_release,
 347 };
 348
 349 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
 350 {
 351         struct tegra_dc *dc = s->private;
 352         struct tegra_dc_mode *m;
 353
 354         mutex_lock(&dc->lock);
 355         m = &dc->mode;
 356         seq_printf(s,
 357                 "pclk: %d\n"
 358                 "h_ref_to_sync: %d\n"
 359                 "v_ref_to_sync: %d\n"
 360                 "h_sync_width: %d\n"
 361                 "v_sync_width: %d\n"
 362                 "h_back_porch: %d\n"
 363                 "v_back_porch: %d\n"
 364                 "h_active: %d\n"
 365                 "v_active: %d\n"
 366                 "h_front_porch: %d\n"
 367                 "v_front_porch: %d\n"
 368                 "stereo_mode: %d\n",
 369                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
 370                 m->h_sync_width, m->v_sync_width,
 371                 m->h_back_porch, m->v_back_porch,
 372                 m->h_active, m->v_active,
 373                 m->h_front_porch, m->v_front_porch,
 374                 m->stereo_mode);
 375         mutex_unlock(&dc->lock);
 376         return 0;
 377 }
 378
 379 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
 380 {
 381         return single_open(file, dbg_dc_mode_show, inode->i_private);
 382 }
 383
 384 static const struct file_operations mode_fops = {
 385         .open           = dbg_dc_mode_open,
 386         .read           = seq_read,
 387         .llseek         = seq_lseek,
 388         .release        = single_release,
 389 };
 390
 391 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
 392 {
 393         struct tegra_dc *dc = s->private;
 394
 395         mutex_lock(&dc->lock);
 396         seq_printf(s,
 397                 "underflows: %u\n"
 398                 "underflows_a: %u\n"
 399                 "underflows_b: %u\n"
 400                 "underflows_c: %u\n",
 401                 dc->stats.underflows,
 402                 dc->stats.underflows_a,
 403                 dc->stats.underflows_b,
 404                 dc->stats.underflows_c);
 405         mutex_unlock(&dc->lock);
 406
 407         return 0;
 408 }
 409
 410 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
 411 {
 412         return single_open(file, dbg_dc_stats_show, inode->i_private);
 413 }
 414
 415 static const struct file_operations stats_fops = {
 416         .open           = dbg_dc_stats_open,
 417         .read           = seq_read,
 418         .llseek         = seq_lseek,
 419         .release        = single_release,
 420 };
 421
 422 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
 423 {
 424         if (dc->debugdir)
 425                 debugfs_remove_recursive(dc->debugdir);
 426         dc->debugdir = NULL;
 427 }
 428
 429 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
 430 {
 431         struct dentry *retval;
 432
 433         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
 434         if (!dc->debugdir)
 435                 goto remove_out;
 436
 437         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
 438                 &regs_fops);
 439         if (!retval)
 440                 goto remove_out;
 441
 442         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
 443                 &mode_fops);
 444         if (!retval)
 445                 goto remove_out;
 446
 447         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
 448                 &stats_fops);
 449         if (!retval)
 450                 goto remove_out;
 451
 452         return;
 453 remove_out:
 454         dev_err(&dc->ndev->dev, "could not create debugfs\n");
 455         tegra_dc_remove_debugfs(dc);
 456 }
 457
 458 #else /* !CONFIG_DEBUGFS */
 459 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
 460 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
 461 #endif /* CONFIG_DEBUGFS */
 462
 463 static int tegra_dc_set(struct tegra_dc *dc, int index)
 464 {
 465         int ret = 0;
 466
 467         mutex_lock(&tegra_dc_lock);
 468         if (index >= TEGRA_MAX_DC) {
 469                 ret = -EINVAL;
 470                 goto out;
 471         }
 472
 473         if (dc != NULL && tegra_dcs[index] != NULL) {
 474                 ret = -EBUSY;
 475                 goto out;
 476         }
 477
 478         tegra_dcs[index] = dc;
 479
 480 out:
 481         mutex_unlock(&tegra_dc_lock);
 482
 483         return ret;
 484 }
 485
 486 static unsigned int tegra_dc_has_multiple_dc(void)
 487 {
 488         unsigned int idx;
 489         unsigned int cnt = 0;
 490         struct tegra_dc *dc;
 491
 492         mutex_lock(&tegra_dc_lock);
 493         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
 494                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
 495         mutex_unlock(&tegra_dc_lock);
 496
 497         return (cnt > 1);
 498 }
 499
 500 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
 501 {
 502         if (idx < TEGRA_MAX_DC)
 503                 return tegra_dcs[idx];
 504         else
 505                 return NULL;
 506 }
 507 EXPORT_SYMBOL(tegra_dc_get_dc);
 508
 509 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
 510 {
 511         if (win >= dc->n_windows)
 512                 return NULL;
 513
 514         return &dc->windows[win];
 515 }
 516 EXPORT_SYMBOL(tegra_dc_get_window);
 517
 518 static int get_topmost_window(u32 *depths, unsigned long *wins)
 519 {
 520         int idx, best = -1;
 521
 522         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
 523                 if (best == -1 || depths[idx] < depths[best])
 524                         best = idx;
 525         }
 526         clear_bit(best, wins);
 527         return best;
 528 }
 529
 530 static u32 blend_topwin(u32 flags)
 531 {
 532         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
 533                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
 534         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
 535                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
 536         else
 537                 return BLEND(NOKEY, FIX, 0xff, 0xff);
 538 }
 539
 540 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
 541 {
 542         int other;
 543
 544         for (other = 0; other < DC_N_WINDOWS; other++) {
 545                 if (other != idx && (xy-- == 0))
 546                         break;
 547         }
 548         if (BIT(other) & behind_mask)
 549                 return blend_topwin(flags[idx]);
 550         else if (flags[other])
 551                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
 552         else
 553                 return BLEND(NOKEY, FIX, 0x00, 0x00);
 554 }
 555
 556 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
 557 {
 558         unsigned long infront_mask;
 559         int first;
 560
 561         infront_mask = ~(behind_mask | BIT(idx));
 562         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
 563         first = ffs(infront_mask) - 1;
 564
 565         if (!infront_mask)
 566                 return blend_topwin(flags[idx]);
 567         else if (behind_mask && first != -1 && flags[first])
 568                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
 569         else
 570                 return BLEND(NOKEY, FIX, 0x0, 0x0);
 571 }
 572
 573 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
 574 {
 575         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
 576
 577         while (mask) {
 578                 int idx = get_topmost_window(blend->z, &mask);
 579
 580                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
 581                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 582                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
 583                                 DC_WIN_BLEND_NOKEY);
 584                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
 585                                 DC_WIN_BLEND_1WIN);
 586                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
 587                                 DC_WIN_BLEND_2WIN_X);
 588                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
 589                                 DC_WIN_BLEND_2WIN_Y);
 590                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
 591                                 DC_WIN_BLEND_3WIN_XY);
 592         }
 593 }
 594
 595 static void tegra_dc_set_csc(struct tegra_dc *dc)
 596 {
 597         tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 598         tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 599         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 600         tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 601         tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 602         tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 603         tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 604         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 605 }
 606
 607 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
 608 {
 609         unsigned i;
 610         unsigned v0 = 128;
 611         unsigned v1 = 0;
 612         /* linear horizontal and vertical filters */
 613         for (i = 0; i < 16; i++) {
 614                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
 615                                 DC_WIN_H_FILTER_P(i));
 616
 617                 tegra_dc_writel(dc, v0,
 618                                 DC_WIN_V_FILTER_P(i));
 619                 v0 -= 8;
 620                 v1 += 8;
 621         }
 622 }
 623
 624 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
 625         struct tegra_dc_win *w)
 626 {
 627         /* windows A, B, C for first and second display */
 628         static const enum tegra_la_id la_id_tab[2][3] = {
 629                 /* first display */
 630                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
 631                         TEGRA_LA_DISPLAY_0C },
 632                 /* second display */
 633                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
 634                         TEGRA_LA_DISPLAY_0CB },
 635         };
 636         /* window B V-filter tap for first and second display. */
 637         static const enum tegra_la_id vfilter_tab[2] = {
 638                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
 639         };
 640         unsigned long bw;
 641
 642         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
 643         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
 644         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
 645
 646         /* tegra_dc_get_bandwidth() treats V filter windows as double
 647          * bandwidth, but LA has a seperate client for V filter */
 648         if (w->idx == 1 && WIN_USE_V_FILTER(w))
 649                 bw /= 2;
 650
 651         /* our bandwidth is in bytes/sec, but LA takes MBps.
 652          * round up bandwidth to 1MBps */
 653         bw = w->new_bandwidth / 1000000 + 1;
 654
 655         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
 656
 657         /* if window B, also set the 1B client for the 2-tap V filter. */
 658         if (w->idx == 1)
 659                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
 660
 661         w->bandwidth = w->new_bandwidth;
 662 }
 663
 664 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
 665                                                    struct tegra_dc_win *b)
 666 {
 667         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
 668                 return 0;
 669         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
 670                ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
 671 }
 672
 673 static unsigned int tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
 674                                                 int n)
 675 {
 676         /* We have n windows and knows their geometries and bandwidthes. If any
 677          * of them overlapped vertically, the overlapped area bandwidth get
 678          * combined.
 679          *
 680          * This function will find the maximum bandwidth of overlapped area.
 681          * If there is no windows overlapped, then return the maximum
 682          * bandwidth of windows.
 683          */
 684
 685         WARN_ONCE(n != 3, "Code assumes 3 windows, possibly reading junk.\n");
 686         /* We know win_2 is always overlapped with win_0 and win_1. */
 687         if (tegra_dc_windows_is_overlapped(wins[0], wins[1]))
 688                 return wins[0]->new_bandwidth + wins[1]->new_bandwidth +
 689                         wins[2]->new_bandwidth;
 690         else
 691                 return max(wins[0]->new_bandwidth, wins[1]->new_bandwidth) +
 692                         wins[2]->new_bandwidth;
 693
 694 }
 695
 696 /*
 697  * Calculate peak EMC bandwidth for each enabled window =
 698  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
 699  * (windows_tiling ? 2 : 1)
 700  *
 701  *
 702  * note:
 703  * (*) We use 2 tap V filter, so need double BW if use V filter
 704  * (*) Tiling mode on T30 and DDR3 requires double BW
 705  */
 706 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
 707         struct tegra_dc_win *w)
 708 {
 709         unsigned long ret;
 710         int tiled_windows_bw_multiplier;
 711
 712         if (!WIN_IS_ENABLED(w))
 713                 return 0;
 714
 715         tiled_windows_bw_multiplier =
 716                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
 717
 718         /* perform calculations with most significant bits of pixel clock
 719          * to prevent overflow of long. */
 720         ret = (unsigned long)(dc->pixel_clk >> 16) *
 721                 (tegra_dc_fmt_bpp(w->fmt) / 8) *
 722                 (WIN_USE_V_FILTER(w) ? 2 : 1) * w->w / w->out_w *
 723                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
 724
 725 /*
 726  * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we
 727  * will request 140MBps from EMC.
 728  */
 729 #define MEM_EFFICIENCY_SHIFT 1
 730         ret <<= MEM_EFFICIENCY_SHIFT;
 731 #undef MEM_EFFICIENCY_SHIFT
 732
 733         /* if overflowed */
 734         if (ret > (1UL << 31))
 735                 return ULONG_MAX;
 736
 737         return ret << 16; /* restore the scaling we did above */
 738 }
 739
 740 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
 741 {
 742         int i;
 743         struct tegra_dc *dc;
 744
 745         if (windows[0] == NULL)
 746                 return tegra_dc_get_default_emc_clk_rate(dc);
 747
 748         dc = windows[0]->dc;
 749         BUG_ON(n > DC_N_WINDOWS);
 750         /* emc rate and latency allowance both need to know per window
 751          * bandwidths */
 752         for (i = 0; i < n; i++) {
 753                 struct tegra_dc_win *w = windows[i];
 754                 if (w)
 755                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(dc, w);
 756         }
 757
 758         return tegra_dc_find_max_bandwidth(windows, n);
 759 }
 760
 761 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
 762 {
 763         unsigned i;
 764
 765         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
 766                 dc->emc_clk_rate = dc->new_emc_clk_rate;
 767                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
 768         }
 769
 770         for (i = 0; i < DC_N_WINDOWS; i++) {
 771                 struct tegra_dc_win *w = &dc->windows[i];
 772                 if (w->bandwidth != w->new_bandwidth)
 773                         tegra_dc_set_latency_allowance(dc, w);
 774         }
 775 }
 776
 777 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
 778 {
 779         unsigned long new_rate;
 780         struct tegra_dc *dc;
 781
 782         if (!use_dynamic_emc)
 783                 return 0;
 784
 785         dc = windows[0]->dc;
 786
 787         /* calculate the new rate based on this POST */
 788         new_rate = tegra_dc_get_bandwidth(windows, n);
 789         new_rate = EMC_BW_TO_FREQ(new_rate);
 790
 791         WARN_ONCE(new_rate > tegra_dc_get_default_emc_clk_rate(dc),
 792                 "Calculated EMC bandwidth is %luHz, "
 793                 "maximum allowed EMC bandwidth is %luHz\n",
 794                 new_rate, tegra_dc_get_default_emc_clk_rate(dc));
 795
 796         if (tegra_dc_has_multiple_dc())
 797                 new_rate = tegra_dc_get_default_emc_clk_rate(dc);
 798
 799         dc->new_emc_clk_rate = new_rate;
 800
 801         return 0;
 802 }
 803
 804 /* does not support updating windows on multiple dcs in one call */
 805 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
 806 {
 807         struct tegra_dc *dc;
 808         unsigned long update_mask = GENERAL_ACT_REQ;
 809         unsigned long val;
 810         bool update_blend = false;
 811         int i;
 812
 813         dc = windows[0]->dc;
 814
 815         mutex_lock(&dc->lock);
 816
 817         if (!dc->enabled) {
 818                 mutex_unlock(&dc->lock);
 819                 return -EFAULT;
 820         }
 821
 822         if (no_vsync)
 823                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
 824         else
 825                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
 826
 827         for (i = 0; i < n; i++) {
 828                 struct tegra_dc_win *win = windows[i];
 829                 unsigned h_dda;
 830                 unsigned v_dda;
 831                 unsigned h_offset;
 832                 unsigned v_offset;
 833                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
 834                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
 835                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
 836
 837                 if (win->z != dc->blend.z[win->idx]) {
 838                         dc->blend.z[win->idx] = win->z;
 839                         update_blend = true;
 840                 }
 841                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
 842                         dc->blend.flags[win->idx]) {
 843                         dc->blend.flags[win->idx] =
 844                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
 845                         update_blend = true;
 846                 }
 847
 848                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
 849                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 850
 851                 if (!no_vsync)
 852                         update_mask |= WIN_A_ACT_REQ << win->idx;
 853
 854                 if (!WIN_IS_ENABLED(win)) {
 855                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
 856                         continue;
 857                 }
 858
 859                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
 860                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
 861
 862                 tegra_dc_writel(dc,
 863                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
 864                                 DC_WIN_POSITION);
 865                 tegra_dc_writel(dc,
 866                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
 867                                 DC_WIN_SIZE);
 868                 tegra_dc_writel(dc,
 869                                 V_PRESCALED_SIZE(win->h) |
 870                                 H_PRESCALED_SIZE(win->w * tegra_dc_fmt_bpp(win->fmt) / 8),
 871                                 DC_WIN_PRESCALED_SIZE);
 872
 873                 h_dda = ((win->w - 1) * 0x1000) / max_t(int, win->out_w - 1, 1);
 874                 v_dda = ((win->h - 1) * 0x1000) / max_t(int, win->out_h - 1, 1);
 875                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
 876                                 DC_WIN_DDA_INCREMENT);
 877                 tegra_dc_writel(dc, 0, DC_WIN_H_INITIAL_DDA);
 878                 tegra_dc_writel(dc, 0, DC_WIN_V_INITIAL_DDA);
 879
 880                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 881                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 882                 tegra_dc_writel(dc,
 883                                 (unsigned long)win->phys_addr +
 884                                 (unsigned long)win->offset,
 885                                 DC_WINBUF_START_ADDR);
 886
 887                 if (!yuvp) {
 888                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
 889                 } else {
 890                         tegra_dc_writel(dc,
 891                                         (unsigned long)win->phys_addr +
 892                                         (unsigned long)win->offset_u,
 893                                         DC_WINBUF_START_ADDR_U);
 894                         tegra_dc_writel(dc,
 895                                         (unsigned long)win->phys_addr +
 896                                         (unsigned long)win->offset_v,
 897                                         DC_WINBUF_START_ADDR_V);
 898                         tegra_dc_writel(dc,
 899                                         LINE_STRIDE(win->stride) |
 900                                         UV_LINE_STRIDE(win->stride_uv),
 901                                         DC_WIN_LINE_STRIDE);
 902                 }
 903
 904                 h_offset = win->x;
 905                 if (invert_h) {
 906                         h_offset += win->w - 1;
 907                 }
 908                 h_offset *= tegra_dc_fmt_bpp(win->fmt) / 8;
 909
 910                 v_offset = win->y;
 911                 if (invert_v) {
 912                         v_offset += win->h - 1;
 913                 }
 914
 915                 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 916                 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 917
 918                 if (WIN_IS_TILED(win))
 919                         tegra_dc_writel(dc,
 920                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
 921                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
 922                                         DC_WIN_BUFFER_ADDR_MODE);
 923                 else
 924                         tegra_dc_writel(dc,
 925                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
 926                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
 927                                         DC_WIN_BUFFER_ADDR_MODE);
 928
 929                 val = WIN_ENABLE;
 930                 if (yuvp)
 931                         val |= CSC_ENABLE;
 932                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
 933                         val |= COLOR_EXPAND;
 934
 935                 /* only B and C have H filer, force it on if scaling */
 936                 if (win->idx != 0 && win->w != win->out_w)
 937                         win->flags |= TEGRA_WIN_FLAG_H_FILTER;
 938                 /* only B has V filter, set it if scaling */
 939                 if (win->idx == 1 && win->h != win->out_h)
 940                         win->flags |= TEGRA_WIN_FLAG_V_FILTER;
 941
 942                 if (WIN_USE_H_FILTER(win))
 943                         val |= H_FILTER_ENABLE;
 944                 if (WIN_USE_V_FILTER(win))
 945                         val |= V_FILTER_ENABLE;
 946
 947                 if (invert_h)
 948                         val |= H_DIRECTION_DECREMENT;
 949                 if (invert_v)
 950                         val |= V_DIRECTION_DECREMENT;
 951
 952                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
 953
 954                 win->dirty = no_vsync ? 0 : 1;
 955         }
 956
 957         if (update_blend) {
 958                 tegra_dc_set_blending(dc, &dc->blend);
 959                 for (i = 0; i < DC_N_WINDOWS; i++) {
 960                         if (!no_vsync)
 961                                 dc->windows[i].dirty = 1;
 962                         update_mask |= WIN_A_ACT_REQ << i;
 963                 }
 964         }
 965
 966         tegra_dc_set_dynamic_emc(windows, n);
 967
 968         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
 969
 970         if (!no_vsync) {
 971                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
 972                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
 973                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
 974         } else {
 975                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
 976                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
 977
 978                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
 979         }
 980
 981         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
 982
 983         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
 984                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
 985
 986         mutex_unlock(&dc->lock);
 987
 988         return 0;
 989 }
 990 EXPORT_SYMBOL(tegra_dc_update_windows);
 991
 992 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc)
 993 {
 994         return dc->syncpt_id;
 995 }
 996 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
 997
 998 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc)
 999 {
1000         u32 max;
1001
1002         mutex_lock(&dc->lock);
1003         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt, dc->syncpt_id,
1004                                         ((dc->enabled) ? 1 : 0) );
1005         dc->syncpt_max = max;
1006         mutex_unlock(&dc->lock);
1007
1008         return max;
1009 }
1010
1011 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val)
1012 {
1013         mutex_lock(&dc->lock);
1014         if ( dc->enabled )
1015                 while (dc->syncpt_min < val) {
1016                         dc->syncpt_min++;
1017                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1018                                 dc->syncpt_id);
1019                 }
1020         mutex_unlock(&dc->lock);
1021 }
1022
1023 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1024                                              int n)
1025 {
1026         int i;
1027
1028         for (i = 0; i < n; i++) {
1029                 if (windows[i]->dirty)
1030                         return false;
1031         }
1032
1033         return true;
1034 }
1035
1036 /* does not support syncing windows on multiple dcs in one call */
1037 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1038 {
1039         if (n < 1 || n > DC_N_WINDOWS)
1040                 return -EINVAL;
1041
1042         if (!windows[0]->dc->enabled)
1043                 return -EFAULT;
1044
1045         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1046                                          tegra_dc_windows_are_clean(windows, n),
1047                                          HZ);
1048 }
1049 EXPORT_SYMBOL(tegra_dc_sync_windows);
1050
1051 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1052 {
1053 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1054         return 27000000;
1055 #else
1056         return clk_get_rate(dc->clk);
1057 #endif
1058 }
1059
1060 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1061 {
1062         unsigned long rate;
1063         unsigned long div;
1064
1065         rate = tegra_dc_clk_get_rate(dc);
1066
1067         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1068
1069         if (div < 2)
1070                 return 0;
1071
1072         return rate * 2 / div;
1073 }
1074
1075 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1076 {
1077         int pclk;
1078
1079         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1080                 struct clk *parent_clk =
1081                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1082
1083                 if (clk_get_parent(clk) != parent_clk)
1084                         clk_set_parent(clk, parent_clk);
1085         }
1086
1087         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1088                 unsigned long rate;
1089                 struct clk *parent_clk =
1090                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1091                 struct clk *base_clk = clk_get_parent(parent_clk);
1092
1093                 if (dc->mode.pclk > 70000000)
1094                         rate = 594000000;
1095                 else
1096                         rate = 216000000;
1097
1098                 if (rate != clk_get_rate(base_clk))
1099                         clk_set_rate(base_clk, rate);
1100
1101                 if (clk_get_parent(clk) != parent_clk)
1102                         clk_set_parent(clk, parent_clk);
1103         }
1104
1105         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1106                 unsigned long rate;
1107                 struct clk *parent_clk;
1108                 struct clk *base_clk;
1109
1110                 if (clk == dc->clk) {
1111                         parent_clk = clk_get_sys(NULL,
1112                                         dc->out->parent_clk ? : "pll_d_out0");
1113                         base_clk = clk_get_parent(parent_clk);
1114                         tegra_clk_cfg_ex(base_clk,
1115                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1116                 } else {
1117                         if (dc->pdata->default_out->dsi->dsi_instance) {
1118                                 parent_clk = clk_get_sys(NULL,
1119                                         dc->out->parent_clk ? : "pll_d2_out0");
1120                                 base_clk = clk_get_parent(parent_clk);
1121                                 tegra_clk_cfg_ex(base_clk,
1122                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1123                         } else {
1124                                 parent_clk = clk_get_sys(NULL,
1125                                         dc->out->parent_clk ? : "pll_d_out0");
1126                                 base_clk = clk_get_parent(parent_clk);
1127                         }
1128                 }
1129
1130                 rate = dc->mode.pclk;
1131                 if (rate != clk_get_rate(base_clk))
1132                         clk_set_rate(base_clk, rate);
1133
1134                 if (clk_get_parent(clk) != parent_clk)
1135                         clk_set_parent(clk, parent_clk);
1136         }
1137
1138         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1139         tegra_dvfs_set_rate(clk, pclk);
1140 }
1141
1142 /* return non-zero if constraint is violated */
1143 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1144 {
1145         long a, b;
1146
1147         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1148         a = 0;
1149
1150         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1151         b = mode->h_front_porch - 1;
1152
1153         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1154         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1155                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1156         /* check Constraint 1 and 6 */
1157         if (a > b)
1158                 return 1;
1159
1160         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1161         if (mode->h_sync_width < 1)
1162                 return 4;
1163
1164         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1165         if (mode->h_active < 16)
1166                 return 7;
1167
1168         if (href) {
1169                 if (b > a && a % 2)
1170                         *href = a + 1; /* use smallest even value */
1171                 else
1172                         *href = a; /* even or only possible value */
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1179 {
1180         long a;
1181         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1182
1183         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1184         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1185                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1186
1187         /* Constraint 6 */
1188         if (mode->v_front_porch < a + 1)
1189                 a = mode->v_front_porch - 1;
1190
1191         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1192         if (mode->v_sync_width < 1)
1193                 return 4;
1194
1195         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1196         if (mode->v_active < 16)
1197                 return 7;
1198
1199         if (vref)
1200                 *vref = a;
1201         return 0;
1202 }
1203
1204 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1205 {
1206         int ret;
1207         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1208         if (ret)
1209                 return ret;
1210         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1211         if (ret)
1212                 return ret;
1213
1214         return 0;
1215 }
1216
1217 #ifdef DEBUG
1218 /* return in 1000ths of a Hertz */
1219 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1220 {
1221         long h_total, v_total, refresh;
1222         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1223                 m->h_sync_width;
1224         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1225                 m->v_sync_width;
1226         refresh = dc->pixel_clk / h_total;
1227         refresh *= 1000;
1228         refresh /= v_total;
1229         return refresh;
1230 }
1231
1232 static void print_mode(struct tegra_dc *dc,
1233                         const struct tegra_dc_mode *mode, const char *note)
1234 {
1235         if (mode) {
1236                 int refresh = calc_refresh(mode);
1237                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1238                         note ? note : "",
1239                         mode->h_active, mode->v_active,
1240                         refresh / 1000, refresh % 1000,
1241                         mode->pclk);
1242         }
1243 }
1244 #else /* !DEBUG */
1245 static inline void print_mode(struct tegra_dc *dc,
1246                         const struct tegra_dc_mode *mode, const char *note) { }
1247 #endif /* DEBUG */
1248
1249 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1250 {
1251         unsigned long val;
1252         unsigned long rate;
1253         unsigned long div;
1254         unsigned long pclk;
1255
1256         print_mode(dc, mode, __func__);
1257
1258         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1259         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1260                         DC_DISP_REF_TO_SYNC);
1261         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1262                         DC_DISP_SYNC_WIDTH);
1263         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1264                         DC_DISP_BACK_PORCH);
1265         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1266                         DC_DISP_DISP_ACTIVE);
1267         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1268                         DC_DISP_FRONT_PORCH);
1269
1270         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1271                         DC_DISP_DATA_ENABLE_OPTIONS);
1272
1273         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1274         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1275                 val |= PIN1_LVS_OUTPUT;
1276         else
1277                 val &= ~PIN1_LVS_OUTPUT;
1278
1279         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1280                 val |= PIN1_LHS_OUTPUT;
1281         else
1282                 val &= ~PIN1_LHS_OUTPUT;
1283         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1284
1285         /* TODO: MIPI/CRT/HDMI clock cals */
1286
1287         val = DISP_DATA_FORMAT_DF1P1C;
1288
1289         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1290                 val |= DISP_DATA_ALIGNMENT_MSB;
1291         else
1292                 val |= DISP_DATA_ALIGNMENT_LSB;
1293
1294         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1295                 val |= DISP_DATA_ORDER_RED_BLUE;
1296         else
1297                 val |= DISP_DATA_ORDER_BLUE_RED;
1298
1299         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1300
1301         rate = tegra_dc_clk_get_rate(dc);
1302
1303         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1304         if (pclk < (mode->pclk / 100 * 99) ||
1305             pclk > (mode->pclk / 100 * 109)) {
1306                 dev_err(&dc->ndev->dev,
1307                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1308                         rate, mode->pclk,
1309                         pclk, (mode->pclk / 100 * 99),
1310                         (mode->pclk / 100 * 109));
1311                 return -EINVAL;
1312         }
1313
1314         div = (rate * 2 / pclk) - 2;
1315
1316         tegra_dc_writel(dc, 0x00010001,
1317                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1318         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1319                         DC_DISP_DISP_CLOCK_CONTROL);
1320
1321         dc->pixel_clk = dc->mode.pclk;
1322
1323         return 0;
1324 }
1325
1326
1327 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1328 {
1329         memcpy(&dc->mode, mode, sizeof(dc->mode));
1330
1331         print_mode(dc, mode, __func__);
1332
1333         return 0;
1334 }
1335 EXPORT_SYMBOL(tegra_dc_set_mode);
1336
1337 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1338                 const struct fb_videomode *fbmode, bool stereo_mode)
1339 {
1340         struct tegra_dc_mode mode;
1341
1342         if (!fbmode->pixclock)
1343                 return -EINVAL;
1344
1345         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1346         mode.h_sync_width = fbmode->hsync_len;
1347         mode.v_sync_width = fbmode->vsync_len;
1348         mode.h_back_porch = fbmode->left_margin;
1349         mode.v_back_porch = fbmode->upper_margin;
1350         mode.h_active = fbmode->xres;
1351         mode.v_active = fbmode->yres;
1352         mode.h_front_porch = fbmode->right_margin;
1353         mode.v_front_porch = fbmode->lower_margin;
1354         mode.stereo_mode = stereo_mode;
1355         if (calc_ref_to_sync(&mode)) {
1356                 dev_err(&dc->ndev->dev, "bad href/vref values, overriding.\n");
1357                 mode.h_ref_to_sync = 11;
1358                 mode.v_ref_to_sync = 1;
1359         }
1360         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1361                 mode.h_active, mode.v_active, mode.pclk,
1362                 mode.h_ref_to_sync, mode.v_ref_to_sync
1363         );
1364
1365         if (mode.stereo_mode) {
1366                 mode.pclk *= 2;
1367                 /* total v_active = yres*2 + activespace */
1368                 mode.v_active = fbmode->yres*2 +
1369                                 fbmode->vsync_len +
1370                                 fbmode->upper_margin +
1371                                 fbmode->lower_margin;
1372         }
1373
1374         mode.flags = 0;
1375
1376         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1377                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1378
1379         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1380                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1381
1382         return tegra_dc_set_mode(dc, &mode);
1383 }
1384 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1385
1386 void
1387 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1388 {
1389         unsigned int ctrl;
1390         unsigned long out_sel;
1391         unsigned long cmd_state;
1392
1393         mutex_lock(&dc->lock);
1394         if (!dc->enabled) {
1395                 mutex_unlock(&dc->lock);
1396                 return;
1397         }
1398
1399         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1400                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1401                 cfg->clk_select);
1402
1403         /* The new value should be effected immediately */
1404         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1405         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1406
1407         switch (cfg->which_pwm) {
1408         case TEGRA_PWM_PM0:
1409                 /* Select the LM0 on PM0 */
1410                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1411                 out_sel &= ~(7 << 0);
1412                 out_sel |= (3 << 0);
1413                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1414                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1415                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1416                 break;
1417         case TEGRA_PWM_PM1:
1418                 /* Select the LM1 on PM1 */
1419                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1420                 out_sel &= ~(7 << 4);
1421                 out_sel |= (3 << 4);
1422                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1423                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1424                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1425                 break;
1426         default:
1427                 dev_err(&dc->ndev->dev, "Error\n");
1428                 break;
1429         }
1430         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1431         mutex_unlock(&dc->lock);
1432 }
1433 EXPORT_SYMBOL(tegra_dc_config_pwm);
1434
1435 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1436                                 const struct tegra_dc_out_pin *pins,
1437                                 const unsigned int n_pins)
1438 {
1439         unsigned int i;
1440
1441         int name;
1442         int pol;
1443
1444         u32 pol1, pol3;
1445
1446         u32 set1, unset1;
1447         u32 set3, unset3;
1448
1449         set1 = set3 = unset1 = unset3 = 0;
1450
1451         for (i = 0; i < n_pins; i++) {
1452                 name = (pins + i)->name;
1453                 pol  = (pins + i)->pol;
1454
1455                 /* set polarity by name */
1456                 switch (name) {
1457                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1458                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1459                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1460                         else
1461                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1462                         break;
1463                 case TEGRA_DC_OUT_PIN_H_SYNC:
1464                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1465                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1466                         else
1467                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1468                         break;
1469                 case TEGRA_DC_OUT_PIN_V_SYNC:
1470                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1471                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1472                         else
1473                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1474                         break;
1475                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1476                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1477                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1478                         else
1479                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1480                         break;
1481                 default:
1482                         printk("Invalid argument in function %s\n",
1483                                __FUNCTION__);
1484                         break;
1485                 }
1486         }
1487
1488         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1489         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1490
1491         pol1 |= set1;
1492         pol1 &= ~unset1;
1493
1494         pol3 |= set3;
1495         pol3 &= ~unset3;
1496
1497         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1498         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1499 }
1500
1501 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1502 {
1503         dc->out = out;
1504
1505         if (out->n_modes > 0)
1506                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1507
1508         switch (out->type) {
1509         case TEGRA_DC_OUT_RGB:
1510                 dc->out_ops = &tegra_dc_rgb_ops;
1511                 break;
1512
1513         case TEGRA_DC_OUT_HDMI:
1514                 dc->out_ops = &tegra_dc_hdmi_ops;
1515                 break;
1516
1517         case TEGRA_DC_OUT_DSI:
1518                 dc->out_ops = &tegra_dc_dsi_ops;
1519                 break;
1520
1521         default:
1522                 dc->out_ops = NULL;
1523                 break;
1524         }
1525
1526         if (dc->out_ops && dc->out_ops->init)
1527                 dc->out_ops->init(dc);
1528
1529 }
1530
1531 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1532 {
1533         if (dc->out)
1534                 return dc->out->height;
1535         else
1536                 return 0;
1537 }
1538 EXPORT_SYMBOL(tegra_dc_get_out_height);
1539
1540 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1541 {
1542         if (dc->out)
1543                 return dc->out->width;
1544         else
1545                 return 0;
1546 }
1547 EXPORT_SYMBOL(tegra_dc_get_out_width);
1548
1549 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1550 {
1551         if (dc->out && dc->out->max_pixclock)
1552                 return dc->out->max_pixclock;
1553         else
1554                 return 0;
1555 }
1556 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1557
1558 void tegra_dc_enable_crc(struct tegra_dc *dc)
1559 {
1560         u32 val;
1561         tegra_dc_io_start(dc);
1562
1563         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1564                 CRC_ENABLE_ENABLE;
1565         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1566         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1567         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1568 }
1569
1570 void tegra_dc_disable_crc(struct tegra_dc *dc)
1571 {
1572         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1573         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1574         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1575
1576         tegra_dc_io_end(dc);
1577 }
1578
1579 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1580 {
1581         int crc = 0;
1582         u32 val = 0;
1583
1584         if(!dc) {
1585                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1586                 goto crc_error;
1587         }
1588
1589         /* TODO: Replace mdelay with code to sync VBlANK, since
1590          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1591         mdelay(TEGRA_CRC_LATCHED_DELAY);
1592
1593         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1594 crc_error:
1595         return crc;
1596 }
1597
1598 static void tegra_dc_vblank(struct work_struct *work)
1599 {
1600         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1601         bool nvsd_updated = false;
1602
1603         mutex_lock(&dc->lock);
1604
1605         /* update EMC clock if calculated bandwidth has changed */
1606         tegra_dc_program_bandwidth(dc);
1607
1608         /* Update the SD brightness */
1609         nvsd_updated = nvsd_update_brightness(dc);
1610
1611         mutex_unlock(&dc->lock);
1612
1613         /* Do the actual brightness update outside of the mutex */
1614         if (nvsd_updated && dc->out->sd_settings &&
1615             dc->out->sd_settings->bl_device) {
1616
1617                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1618                 struct backlight_device *bl = platform_get_drvdata(pdev);
1619                 if (bl)
1620                         backlight_update_status(bl);
1621         }
1622 }
1623
1624 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1625 {
1626 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1627         struct tegra_dc *dc = ptr;
1628         unsigned long status;
1629         unsigned long val;
1630         unsigned long underflow_mask;
1631         int i;
1632
1633         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1634         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1635
1636         /*
1637          * Overlays can get thier internal state corrupted during and underflow
1638          * condition.  The only way to fix this state is to reset the DC.
1639          * if we get 4 consecutive frames with underflows, assume we're
1640          * hosed and reset.
1641          */
1642         underflow_mask = status & ALL_UF_INT;
1643
1644         if (underflow_mask) {
1645                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1646                 val |= V_BLANK_INT;
1647                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1648                 dc->underflow_mask |= underflow_mask;
1649                 dc->stats.underflows++;
1650                 if (status & WIN_A_UF_INT)
1651                         dc->stats.underflows_a++;
1652                 if (status & WIN_B_UF_INT)
1653                         dc->stats.underflows_b++;
1654                 if (status & WIN_C_UF_INT)
1655                         dc->stats.underflows_c++;
1656         }
1657
1658         if (status & V_BLANK_INT) {
1659                 int i;
1660
1661                 /* Check for any underflow reset conditions */
1662                 for (i = 0; i< DC_N_WINDOWS; i++) {
1663                         if (dc->underflow_mask & (WIN_A_UF_INT <<i)) {
1664                                 dc->windows[i].underflows++;
1665
1666 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1667                                 if (dc->windows[i].underflows > 4)
1668                                         schedule_work(&dc->reset_work);
1669 #endif
1670                         } else {
1671                                 dc->windows[i].underflows = 0;
1672                         }
1673                 }
1674
1675                 if (!dc->underflow_mask) {
1676                         /* If we have no underflow to check, go ahead
1677                            and disable the interrupt */
1678                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1679                         val &= ~V_BLANK_INT;
1680                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1681                 }
1682
1683                 /* Clear the underflow mask now that we've checked it. */
1684                 dc->underflow_mask = 0;
1685
1686                 /* Schedule any additional bottom-half vblank actvities. */
1687                 schedule_work(&dc->vblank_work);
1688
1689                 /* Mark the vblank as complete. */
1690                 complete(&dc->vblank_complete);
1691         }
1692
1693         if (status & FRAME_END_INT) {
1694                 int completed = 0;
1695                 int dirty = 0;
1696
1697                 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1698                 for (i = 0; i < DC_N_WINDOWS; i++) {
1699                         if (!(val & (WIN_A_UPDATE << i))) {
1700                                 dc->windows[i].dirty = 0;
1701                                 completed = 1;
1702                         } else {
1703                                 dirty = 1;
1704                         }
1705                 }
1706
1707                 if (!dirty) {
1708                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1709                         val &= ~FRAME_END_INT;
1710                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1711                 }
1712
1713                 if (completed) {
1714                         if (!dirty) {
1715                                 /* With the last completed window, go ahead
1716                                    and enable the vblank interrupt for nvsd. */
1717                                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1718                                 val |= V_BLANK_INT;
1719                                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1720
1721                                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1722                                 val |= V_BLANK_INT;
1723                                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1724                         }
1725
1726                         /* Wake up the workqueue regardless. */
1727                         wake_up(&dc->wq);
1728                 }
1729         }
1730
1731         return IRQ_HANDLED;
1732 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1733         return IRQ_NONE;
1734 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1735 }
1736
1737 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1738 {
1739         u32 color_control;
1740
1741         switch (dc->out->depth) {
1742         case 3:
1743                 color_control = BASE_COLOR_SIZE111;
1744                 break;
1745
1746         case 6:
1747                 color_control = BASE_COLOR_SIZE222;
1748                 break;
1749
1750         case 8:
1751                 color_control = BASE_COLOR_SIZE332;
1752                 break;
1753
1754         case 9:
1755                 color_control = BASE_COLOR_SIZE333;
1756                 break;
1757
1758         case 12:
1759                 color_control = BASE_COLOR_SIZE444;
1760                 break;
1761
1762         case 15:
1763                 color_control = BASE_COLOR_SIZE555;
1764                 break;
1765
1766         case 16:
1767                 color_control = BASE_COLOR_SIZE565;
1768                 break;
1769
1770         case 18:
1771                 color_control = BASE_COLOR_SIZE666;
1772                 break;
1773
1774         default:
1775                 color_control = BASE_COLOR_SIZE888;
1776                 break;
1777         }
1778
1779         switch (dc->out->dither) {
1780         case TEGRA_DC_DISABLE_DITHER:
1781                 color_control |= DITHER_CONTROL_DISABLE;
1782                 break;
1783         case TEGRA_DC_ORDERED_DITHER:
1784                 color_control |= DITHER_CONTROL_ORDERED;
1785                 break;
1786         case TEGRA_DC_ERRDIFF_DITHER:
1787                 /* The line buffer for error-diffusion dither is limited
1788                  * to 640 pixels per line. This limits the maximum
1789                  * horizontal active area size to 640 pixels when error
1790                  * diffusion is enabled.
1791                  */
1792                 BUG_ON(dc->mode.h_active > 640);
1793                 color_control |= DITHER_CONTROL_ERRDIFF;
1794                 break;
1795         }
1796
1797         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1798 }
1799
1800 static void tegra_dc_init(struct tegra_dc *dc)
1801 {
1802         u32 disp_syncpt = 0;
1803         u32 vblank_syncpt = 0;
1804         int i;
1805
1806         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1807         if (dc->ndev->id == 0) {
1808                 disp_syncpt = NVSYNCPT_DISP0;
1809                 vblank_syncpt = NVSYNCPT_VBLANK0;
1810
1811                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1812                                       TEGRA_MC_PRIO_MED);
1813                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1814                                       TEGRA_MC_PRIO_MED);
1815                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1816                                       TEGRA_MC_PRIO_MED);
1817                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1818                                       TEGRA_MC_PRIO_MED);
1819                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1820                                       TEGRA_MC_PRIO_HIGH);
1821         } else if (dc->ndev->id == 1) {
1822                 disp_syncpt = NVSYNCPT_DISP1;
1823                 vblank_syncpt = NVSYNCPT_VBLANK1;
1824
1825                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1826                                       TEGRA_MC_PRIO_MED);
1827                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1828                                       TEGRA_MC_PRIO_MED);
1829                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1830                                       TEGRA_MC_PRIO_MED);
1831                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1832                                       TEGRA_MC_PRIO_MED);
1833                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1834                                       TEGRA_MC_PRIO_HIGH);
1835         }
1836         tegra_dc_writel(dc, 0x00000100 | vblank_syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1837         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1838         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1839         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1840         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1841
1842         tegra_dc_writel(dc, (FRAME_END_INT |
1843                              V_BLANK_INT |
1844                              ALL_UF_INT), DC_CMD_INT_MASK);
1845         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_ENABLE);
1846
1847         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1848
1849         tegra_dc_set_color_control(dc);
1850         for (i = 0; i < DC_N_WINDOWS; i++) {
1851                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1852                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1853                 tegra_dc_set_csc(dc);
1854                 tegra_dc_set_scaling_filter(dc);
1855         }
1856
1857
1858         dc->syncpt_id = disp_syncpt;
1859
1860         dc->syncpt_min = dc->syncpt_max =
1861                 nvhost_syncpt_read(&dc->ndev->host->syncpt, disp_syncpt);
1862
1863         print_mode(dc, &dc->mode, __func__);
1864
1865         if (dc->mode.pclk)
1866                 tegra_dc_program_mode(dc, &dc->mode);
1867
1868         /* Initialize SD AFTER the modeset.
1869            nvsd_init handles the sd_settings = NULL case. */
1870         nvsd_init(dc, dc->out->sd_settings);
1871 }
1872
1873 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1874 {
1875         if (dc->out->enable)
1876                 dc->out->enable();
1877
1878         tegra_dc_setup_clk(dc, dc->clk);
1879         tegra_periph_reset_assert(dc->clk);
1880         clk_enable(dc->clk);
1881         clk_enable(dc->emc_clk);
1882         enable_irq(dc->irq);
1883
1884         tegra_dc_init(dc);
1885
1886         if (dc->out_ops && dc->out_ops->enable)
1887                 dc->out_ops->enable(dc);
1888
1889         if (dc->out->out_pins)
1890                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1891                                             dc->out->n_out_pins);
1892
1893         if (dc->out->postpoweron)
1894                 dc->out->postpoweron();
1895
1896         /* force a full blending update */
1897         dc->blend.z[0] = -1;
1898
1899         return true;
1900 }
1901
1902 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1903 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1904 {
1905         if (dc->out->enable)
1906                 dc->out->enable();
1907
1908         tegra_dc_setup_clk(dc, dc->clk);
1909         clk_enable(dc->clk);
1910         clk_enable(dc->emc_clk);
1911
1912         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1913                 mutex_lock(&tegra_dcs[1]->lock);
1914                 disable_irq(tegra_dcs[1]->irq);
1915         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1916                 mutex_lock(&tegra_dcs[0]->lock);
1917                 disable_irq(tegra_dcs[0]->irq);
1918         }
1919
1920         msleep(5);
1921         tegra_periph_reset_assert(dc->clk);
1922         msleep(2);
1923 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1924         tegra_periph_reset_deassert(dc->clk);
1925         msleep(1);
1926 #endif
1927
1928         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1929                 enable_irq(tegra_dcs[1]->irq);
1930                 mutex_unlock(&tegra_dcs[1]->lock);
1931         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1932                 enable_irq(tegra_dcs[0]->irq);
1933                 mutex_unlock(&tegra_dcs[0]->lock);
1934         }
1935
1936         enable_irq(dc->irq);
1937
1938         tegra_dc_init(dc);
1939
1940         if (dc->out_ops && dc->out_ops->enable)
1941                 dc->out_ops->enable(dc);
1942
1943         if (dc->out->out_pins)
1944                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1945                                             dc->out->n_out_pins);
1946
1947         if (dc->out->postpoweron)
1948                 dc->out->postpoweron();
1949
1950         /* force a full blending update */
1951         dc->blend.z[0] = -1;
1952
1953         return true;
1954 }
1955 #endif
1956
1957 static bool _tegra_dc_enable(struct tegra_dc *dc)
1958 {
1959         if (dc->mode.pclk == 0)
1960                 return false;
1961
1962         if (!dc->out)
1963                 return false;
1964
1965         tegra_dc_io_start(dc);
1966
1967         return _tegra_dc_controller_enable(dc);
1968 }
1969
1970 void tegra_dc_enable(struct tegra_dc *dc)
1971 {
1972         mutex_lock(&dc->lock);
1973
1974         if (!dc->enabled)
1975                 dc->enabled = _tegra_dc_enable(dc);
1976
1977         mutex_unlock(&dc->lock);
1978 }
1979
1980 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1981 {
1982         disable_irq(dc->irq);
1983
1984         if (dc->out_ops && dc->out_ops->disable)
1985                 dc->out_ops->disable(dc);
1986
1987         clk_disable(dc->emc_clk);
1988         clk_disable(dc->clk);
1989         tegra_dvfs_set_rate(dc->clk, 0);
1990
1991         if (dc->out && dc->out->disable)
1992                 dc->out->disable();
1993
1994         /* flush any pending syncpt waits */
1995         while (dc->syncpt_min < dc->syncpt_max) {
1996                 dc->syncpt_min++;
1997                 nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt, dc->syncpt_id);
1998         }
1999 }
2000
2001 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2002 {
2003 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2004         u32 val;
2005         if (dc->enabled)  {
2006                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2007                 if (enable)
2008                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2009                 else
2010                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2011                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2012         }
2013 #endif
2014 }
2015
2016 bool tegra_dc_stats_get(struct tegra_dc *dc)
2017 {
2018 #if 0 /* right now it is always enabled */
2019         u32 val;
2020         bool res;
2021
2022         if (dc->enabled)  {
2023                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2024                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2025         } else {
2026                 res = false;
2027         }
2028
2029         return res;
2030 #endif
2031         return true;
2032 }
2033
2034 static void _tegra_dc_disable(struct tegra_dc *dc)
2035 {
2036         _tegra_dc_controller_disable(dc);
2037         tegra_dc_io_end(dc);
2038 }
2039
2040 void tegra_dc_disable(struct tegra_dc *dc)
2041 {
2042         if (dc->overlay)
2043                 tegra_overlay_disable(dc->overlay);
2044
2045         mutex_lock(&dc->lock);
2046
2047         if (dc->enabled) {
2048                 dc->enabled = false;
2049
2050                 if (!dc->suspended)
2051                         _tegra_dc_disable(dc);
2052         }
2053
2054         mutex_unlock(&dc->lock);
2055 }
2056
2057 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2058 static void tegra_dc_reset_worker(struct work_struct *work)
2059 {
2060         struct tegra_dc *dc =
2061                 container_of(work, struct tegra_dc, reset_work);
2062
2063         unsigned long val = 0;
2064
2065         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2066
2067         mutex_lock(&shared_lock);
2068         mutex_lock(&dc->lock);
2069
2070         if (dc->enabled == false)
2071                 goto unlock;
2072
2073         dc->enabled = false;
2074
2075         /*
2076          * off host read bus
2077          */
2078         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2079         val &= ~(0x00000100);
2080         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2081
2082         /*
2083          * set DC to STOP mode
2084          */
2085         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2086
2087         msleep(10);
2088
2089         _tegra_dc_controller_disable(dc);
2090
2091         /* _tegra_dc_controller_reset_enable deasserts reset */
2092         _tegra_dc_controller_reset_enable(dc);
2093
2094         dc->enabled = true;
2095 unlock:
2096         mutex_unlock(&dc->lock);
2097         mutex_unlock(&shared_lock);
2098 }
2099 #endif
2100
2101
2102 static int tegra_dc_probe(struct nvhost_device *ndev)
2103 {
2104         struct tegra_dc *dc;
2105         struct clk *clk;
2106         struct clk *emc_clk;
2107         struct resource *res;
2108         struct resource *base_res;
2109         struct resource *fb_mem = NULL;
2110         int ret = 0;
2111         void __iomem *base;
2112         int irq;
2113         int i;
2114
2115         if (!ndev->dev.platform_data) {
2116                 dev_err(&ndev->dev, "no platform data\n");
2117                 return -ENOENT;
2118         }
2119
2120         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2121         if (!dc) {
2122                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2123                 return -ENOMEM;
2124         }
2125
2126         irq = nvhost_get_irq_byname(ndev, "irq");
2127         if (irq <= 0) {
2128                 dev_err(&ndev->dev, "no irq\n");
2129                 ret = -ENOENT;
2130                 goto err_free;
2131         }
2132
2133         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2134         if (!res) {
2135                 dev_err(&ndev->dev, "no mem resource\n");
2136                 ret = -ENOENT;
2137                 goto err_free;
2138         }
2139
2140         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2141         if (!base_res) {
2142                 dev_err(&ndev->dev, "request_mem_region failed\n");
2143                 ret = -EBUSY;
2144                 goto err_free;
2145         }
2146
2147         base = ioremap(res->start, resource_size(res));
2148         if (!base) {
2149                 dev_err(&ndev->dev, "registers can't be mapped\n");
2150                 ret = -EBUSY;
2151                 goto err_release_resource_reg;
2152         }
2153
2154         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2155
2156         clk = clk_get(&ndev->dev, NULL);
2157         if (IS_ERR_OR_NULL(clk)) {
2158                 dev_err(&ndev->dev, "can't get clock\n");
2159                 ret = -ENOENT;
2160                 goto err_iounmap_reg;
2161         }
2162
2163         emc_clk = clk_get(&ndev->dev, "emc");
2164         if (IS_ERR_OR_NULL(emc_clk)) {
2165                 dev_err(&ndev->dev, "can't get emc clock\n");
2166                 ret = -ENOENT;
2167                 goto err_put_clk;
2168         }
2169
2170         dc->clk = clk;
2171         dc->emc_clk = emc_clk;
2172
2173         dc->base_res = base_res;
2174         dc->base = base;
2175         dc->irq = irq;
2176         dc->ndev = ndev;
2177         dc->pdata = ndev->dev.platform_data;
2178
2179         /*
2180          * The emc is a shared clock, it will be set based on
2181          * the requirements for each user on the bus.
2182          */
2183         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2184         clk_set_rate(emc_clk, dc->emc_clk_rate);
2185
2186         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2187                 dc->enabled = true;
2188
2189         mutex_init(&dc->lock);
2190         init_completion(&dc->vblank_complete);
2191         init_waitqueue_head(&dc->wq);
2192 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2193         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2194 #endif
2195         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2196
2197         dc->n_windows = DC_N_WINDOWS;
2198         for (i = 0; i < dc->n_windows; i++) {
2199                 dc->windows[i].idx = i;
2200                 dc->windows[i].dc = dc;
2201         }
2202
2203         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2204                         dev_name(&ndev->dev), dc)) {
2205                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2206                 ret = -EBUSY;
2207                 goto err_put_emc_clk;
2208         }
2209
2210         /* hack to ballence enable_irq calls in _tegra_dc_enable() */
2211         disable_irq(dc->irq);
2212
2213         ret = tegra_dc_set(dc, ndev->id);
2214         if (ret < 0) {
2215                 dev_err(&ndev->dev, "can't add dc\n");
2216                 goto err_free_irq;
2217         }
2218
2219         nvhost_set_drvdata(ndev, dc);
2220
2221         if (dc->pdata->default_out)
2222                 tegra_dc_set_out(dc, dc->pdata->default_out);
2223         else
2224                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2225
2226         mutex_lock(&dc->lock);
2227         if (dc->enabled)
2228                 _tegra_dc_enable(dc);
2229         mutex_unlock(&dc->lock);
2230
2231         tegra_dc_create_debugfs(dc);
2232
2233         dev_info(&ndev->dev, "probed\n");
2234
2235         if (dc->pdata->fb) {
2236                 if (dc->pdata->fb->bits_per_pixel == -1) {
2237                         unsigned long fmt;
2238                         tegra_dc_writel(dc,
2239                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2240                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2241
2242                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2243                         dc->pdata->fb->bits_per_pixel =
2244                                 tegra_dc_fmt_bpp(fmt);
2245                 }
2246
2247                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2248                 if (IS_ERR_OR_NULL(dc->fb))
2249                         dc->fb = NULL;
2250         }
2251
2252         if (dc->fb) {
2253                 dc->overlay = tegra_overlay_register(ndev, dc);
2254                 if (IS_ERR_OR_NULL(dc->overlay))
2255                         dc->overlay = NULL;
2256         }
2257
2258         if (dc->out && dc->out->hotplug_init)
2259                 dc->out->hotplug_init();
2260
2261         if (dc->out_ops && dc->out_ops->detect)
2262                 dc->out_ops->detect(dc);
2263
2264         tegra_dc_create_sysfs(&dc->ndev->dev);
2265
2266         return 0;
2267
2268 err_free_irq:
2269         free_irq(irq, dc);
2270 err_put_emc_clk:
2271         clk_put(emc_clk);
2272 err_put_clk:
2273         clk_put(clk);
2274 err_iounmap_reg:
2275         iounmap(base);
2276         if (fb_mem)
2277                 release_resource(fb_mem);
2278 err_release_resource_reg:
2279         release_resource(base_res);
2280 err_free:
2281         kfree(dc);
2282
2283         return ret;
2284 }
2285
2286 static int tegra_dc_remove(struct nvhost_device *ndev)
2287 {
2288         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2289
2290         tegra_dc_remove_sysfs(&dc->ndev->dev);
2291         tegra_dc_remove_debugfs(dc);
2292
2293         if (dc->overlay) {
2294                 tegra_overlay_unregister(dc->overlay);
2295         }
2296
2297         if (dc->fb) {
2298                 tegra_fb_unregister(dc->fb);
2299                 if (dc->fb_mem)
2300                         release_resource(dc->fb_mem);
2301         }
2302
2303
2304         if (dc->enabled)
2305                 _tegra_dc_disable(dc);
2306
2307         free_irq(dc->irq, dc);
2308         clk_put(dc->emc_clk);
2309         clk_put(dc->clk);
2310         iounmap(dc->base);
2311         if (dc->fb_mem)
2312                 release_resource(dc->base_res);
2313         kfree(dc);
2314         tegra_dc_set(NULL, ndev->id);
2315         return 0;
2316 }
2317
2318 #ifdef CONFIG_PM
2319 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2320 {
2321         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2322
2323         dev_info(&ndev->dev, "suspend\n");
2324
2325         if (dc->overlay)
2326                 tegra_overlay_disable(dc->overlay);
2327
2328         mutex_lock(&dc->lock);
2329
2330         if (dc->out_ops && dc->out_ops->suspend)
2331                 dc->out_ops->suspend(dc);
2332
2333         if (dc->enabled) {
2334                 tegra_fb_suspend(dc->fb);
2335                 _tegra_dc_disable(dc);
2336
2337                 dc->suspended = true;
2338         }
2339
2340         if (dc->out && dc->out->postsuspend) {
2341                 dc->out->postsuspend();
2342                 msleep(100); /* avoid resume event due to voltage falling */
2343         }
2344
2345         mutex_unlock(&dc->lock);
2346
2347         return 0;
2348 }
2349
2350 static int tegra_dc_resume(struct nvhost_device *ndev)
2351 {
2352         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2353
2354         dev_info(&ndev->dev, "resume\n");
2355
2356         mutex_lock(&dc->lock);
2357         dc->suspended = false;
2358
2359         if (dc->enabled)
2360                 _tegra_dc_enable(dc);
2361
2362         if (dc->out && dc->out->hotplug_init)
2363                 dc->out->hotplug_init();
2364
2365         if (dc->out_ops && dc->out_ops->resume)
2366                 dc->out_ops->resume(dc);
2367         mutex_unlock(&dc->lock);
2368
2369         return 0;
2370 }
2371
2372 #endif /* CONFIG_PM */
2373
2374 extern int suspend_set(const char *val, struct kernel_param *kp)
2375 {
2376         if (!strcmp(val, "dump"))
2377                 dump_regs(tegra_dcs[0]);
2378 #ifdef CONFIG_PM
2379         else if (!strcmp(val, "suspend"))
2380                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2381         else if (!strcmp(val, "resume"))
2382                 tegra_dc_resume(tegra_dcs[0]->ndev);
2383 #endif
2384
2385         return 0;
2386 }
2387
2388 extern int suspend_get(char *buffer, struct kernel_param *kp)
2389 {
2390         return 0;
2391 }
2392
2393 int suspend;
2394
2395 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2396
2397 struct nvhost_driver tegra_dc_driver = {
2398         .driver = {
2399                 .name = "tegradc",
2400                 .owner = THIS_MODULE,
2401         },
2402         .probe = tegra_dc_probe,
2403         .remove = tegra_dc_remove,
2404 #ifdef CONFIG_PM
2405         .suspend = tegra_dc_suspend,
2406         .resume = tegra_dc_resume,
2407 #endif
2408 };
2409
2410 static int __init tegra_dc_module_init(void)
2411 {
2412         return nvhost_driver_register(&tegra_dc_driver);
2413 }
2414
2415 static void __exit tegra_dc_module_exit(void)
2416 {
2417         nvhost_driver_unregister(&tegra_dc_driver);
2418 }
2419
2420 module_exit(tegra_dc_module_exit);
2421 module_init(tegra_dc_module_init);