video: tegra: dc: Fix the EMC bandwidth clear.
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134         case TEGRA_WIN_FMT_YCbCr422R:
135         case TEGRA_WIN_FMT_YUV422R:
136         case TEGRA_WIN_FMT_YCbCr422RA:
137         case TEGRA_WIN_FMT_YUV422RA:
138                 return 8;
139
140         case TEGRA_WIN_FMT_YCbCr422:
141         case TEGRA_WIN_FMT_YUV422:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155         case TEGRA_WIN_FMT_YCbCr422R:
156         case TEGRA_WIN_FMT_YUV422R:
157         case TEGRA_WIN_FMT_YCbCr422RA:
158         case TEGRA_WIN_FMT_YUV422RA:
159                 return true;
160         }
161         return false;
162 }
163
164 #define DUMP_REG(a) do {                        \
165         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
166                  #a, a, tegra_dc_readl(dc, a));               \
167         print(data, buff);                                    \
168         } while (0)
169
170 static void _dump_regs(struct tegra_dc *dc, void *data,
171                        void (* print)(void *data, const char *str))
172 {
173         int i;
174         char buff[256];
175
176         tegra_dc_io_start(dc);
177         clk_enable(dc->clk);
178
179         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
180         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
181         DUMP_REG(DC_CMD_SIGNAL_RAISE);
182         DUMP_REG(DC_CMD_INT_STATUS);
183         DUMP_REG(DC_CMD_INT_MASK);
184         DUMP_REG(DC_CMD_INT_ENABLE);
185         DUMP_REG(DC_CMD_INT_TYPE);
186         DUMP_REG(DC_CMD_INT_POLARITY);
187         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
188         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
190         DUMP_REG(DC_CMD_STATE_ACCESS);
191         DUMP_REG(DC_CMD_STATE_CONTROL);
192         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
193         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
194
195         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
196         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
197         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
198         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
199         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
200         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
201         DUMP_REG(DC_DISP_REF_TO_SYNC);
202         DUMP_REG(DC_DISP_SYNC_WIDTH);
203         DUMP_REG(DC_DISP_BACK_PORCH);
204         DUMP_REG(DC_DISP_DISP_ACTIVE);
205         DUMP_REG(DC_DISP_FRONT_PORCH);
206         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
211         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
212         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
213         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
216         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
217         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
218         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
221         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
229         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
230         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
231         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
233         DUMP_REG(DC_DISP_M0_CONTROL);
234         DUMP_REG(DC_DISP_M1_CONTROL);
235         DUMP_REG(DC_DISP_DI_CONTROL);
236         DUMP_REG(DC_DISP_PP_CONTROL);
237         DUMP_REG(DC_DISP_PP_SELECT_A);
238         DUMP_REG(DC_DISP_PP_SELECT_B);
239         DUMP_REG(DC_DISP_PP_SELECT_C);
240         DUMP_REG(DC_DISP_PP_SELECT_D);
241         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
242         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
243         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
244         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
245         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
246         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
247         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
248         DUMP_REG(DC_DISP_BORDER_COLOR);
249         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
250         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
251         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
253         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
254         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
255         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
256         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
257         DUMP_REG(DC_DISP_CURSOR_POSITION);
258         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
259         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
260         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
261         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
264         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
265         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
266         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
269         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
270         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
271
272
273         for (i = 0; i < 3; i++) {
274                 print(data, "\n");
275                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
276                 print(data, buff);
277
278                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
279                                 DC_CMD_DISPLAY_WINDOW_HEADER);
280                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
281                 DUMP_REG(DC_WIN_WIN_OPTIONS);
282                 DUMP_REG(DC_WIN_BYTE_SWAP);
283                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
284                 DUMP_REG(DC_WIN_COLOR_DEPTH);
285                 DUMP_REG(DC_WIN_POSITION);
286                 DUMP_REG(DC_WIN_SIZE);
287                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
288                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
289                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
290                 DUMP_REG(DC_WIN_DDA_INCREMENT);
291                 DUMP_REG(DC_WIN_LINE_STRIDE);
292                 DUMP_REG(DC_WIN_BUF_STRIDE);
293                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
294                 DUMP_REG(DC_WIN_BLEND_NOKEY);
295                 DUMP_REG(DC_WIN_BLEND_1WIN);
296                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
297                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
298                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
299                 DUMP_REG(DC_WINBUF_START_ADDR);
300                 DUMP_REG(DC_WINBUF_START_ADDR_U);
301                 DUMP_REG(DC_WINBUF_START_ADDR_V);
302                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
303                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
304                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
305                 DUMP_REG(DC_WIN_CSC_YOF);
306                 DUMP_REG(DC_WIN_CSC_KYRGB);
307                 DUMP_REG(DC_WIN_CSC_KUR);
308                 DUMP_REG(DC_WIN_CSC_KVR);
309                 DUMP_REG(DC_WIN_CSC_KUG);
310                 DUMP_REG(DC_WIN_CSC_KVG);
311                 DUMP_REG(DC_WIN_CSC_KUB);
312                 DUMP_REG(DC_WIN_CSC_KVB);
313         }
314
315         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
316         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
317         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
318         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
319         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
321         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
322         DUMP_REG(DC_DISP_M1_CONTROL);
323         DUMP_REG(DC_COM_PM1_CONTROL);
324         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
325         DUMP_REG(DC_DISP_SD_CONTROL);
326
327         clk_disable(dc->clk);
328         tegra_dc_io_end(dc);
329 }
330
331 #undef DUMP_REG
332
333 #ifdef DEBUG
334 static void dump_regs_print(void *data, const char *str)
335 {
336         struct tegra_dc *dc = data;
337         dev_dbg(&dc->ndev->dev, "%s", str);
338 }
339
340 static void dump_regs(struct tegra_dc *dc)
341 {
342         _dump_regs(dc, dc, dump_regs_print);
343 }
344 #else /* !DEBUG */
345
346 static void dump_regs(struct tegra_dc *dc) {}
347
348 #endif /* DEBUG */
349
350 #ifdef CONFIG_DEBUG_FS
351
352 static void dbg_regs_print(void *data, const char *str)
353 {
354         struct seq_file *s = data;
355
356         seq_printf(s, "%s", str);
357 }
358
359 #undef DUMP_REG
360
361 static int dbg_dc_show(struct seq_file *s, void *unused)
362 {
363         struct tegra_dc *dc = s->private;
364
365         _dump_regs(dc, s, dbg_regs_print);
366
367         return 0;
368 }
369
370
371 static int dbg_dc_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_show, inode->i_private);
374 }
375
376 static const struct file_operations regs_fops = {
377         .open           = dbg_dc_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386         struct tegra_dc_mode *m;
387
388         mutex_lock(&dc->lock);
389         m = &dc->mode;
390         seq_printf(s,
391                 "pclk: %d\n"
392                 "h_ref_to_sync: %d\n"
393                 "v_ref_to_sync: %d\n"
394                 "h_sync_width: %d\n"
395                 "v_sync_width: %d\n"
396                 "h_back_porch: %d\n"
397                 "v_back_porch: %d\n"
398                 "h_active: %d\n"
399                 "v_active: %d\n"
400                 "h_front_porch: %d\n"
401                 "v_front_porch: %d\n"
402                 "stereo_mode: %d\n",
403                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
404                 m->h_sync_width, m->v_sync_width,
405                 m->h_back_porch, m->v_back_porch,
406                 m->h_active, m->v_active,
407                 m->h_front_porch, m->v_front_porch,
408                 m->stereo_mode);
409         mutex_unlock(&dc->lock);
410         return 0;
411 }
412
413 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
414 {
415         return single_open(file, dbg_dc_mode_show, inode->i_private);
416 }
417
418 static const struct file_operations mode_fops = {
419         .open           = dbg_dc_mode_open,
420         .read           = seq_read,
421         .llseek         = seq_lseek,
422         .release        = single_release,
423 };
424
425 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
426 {
427         struct tegra_dc *dc = s->private;
428
429         mutex_lock(&dc->lock);
430         seq_printf(s,
431                 "underflows: %llu\n"
432                 "underflows_a: %llu\n"
433                 "underflows_b: %llu\n"
434                 "underflows_c: %llu\n",
435                 dc->stats.underflows,
436                 dc->stats.underflows_a,
437                 dc->stats.underflows_b,
438                 dc->stats.underflows_c);
439         mutex_unlock(&dc->lock);
440
441         return 0;
442 }
443
444 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
445 {
446         return single_open(file, dbg_dc_stats_show, inode->i_private);
447 }
448
449 static const struct file_operations stats_fops = {
450         .open           = dbg_dc_stats_open,
451         .read           = seq_read,
452         .llseek         = seq_lseek,
453         .release        = single_release,
454 };
455
456 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
457 {
458         if (dc->debugdir)
459                 debugfs_remove_recursive(dc->debugdir);
460         dc->debugdir = NULL;
461 }
462
463 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
464 {
465         struct dentry *retval;
466
467         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
468         if (!dc->debugdir)
469                 goto remove_out;
470
471         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
472                 &regs_fops);
473         if (!retval)
474                 goto remove_out;
475
476         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
477                 &mode_fops);
478         if (!retval)
479                 goto remove_out;
480
481         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
482                 &stats_fops);
483         if (!retval)
484                 goto remove_out;
485
486         return;
487 remove_out:
488         dev_err(&dc->ndev->dev, "could not create debugfs\n");
489         tegra_dc_remove_debugfs(dc);
490 }
491
492 #else /* !CONFIG_DEBUGFS */
493 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
494 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
495 #endif /* CONFIG_DEBUGFS */
496
497 static int tegra_dc_set(struct tegra_dc *dc, int index)
498 {
499         int ret = 0;
500
501         mutex_lock(&tegra_dc_lock);
502         if (index >= TEGRA_MAX_DC) {
503                 ret = -EINVAL;
504                 goto out;
505         }
506
507         if (dc != NULL && tegra_dcs[index] != NULL) {
508                 ret = -EBUSY;
509                 goto out;
510         }
511
512         tegra_dcs[index] = dc;
513
514 out:
515         mutex_unlock(&tegra_dc_lock);
516
517         return ret;
518 }
519
520 unsigned int tegra_dc_has_multiple_dc(void)
521 {
522         unsigned int idx;
523         unsigned int cnt = 0;
524         struct tegra_dc *dc;
525
526         mutex_lock(&tegra_dc_lock);
527         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
528                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
529         mutex_unlock(&tegra_dc_lock);
530
531         return (cnt > 1);
532 }
533
534 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
535 {
536         if (idx < TEGRA_MAX_DC)
537                 return tegra_dcs[idx];
538         else
539                 return NULL;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_dc);
542
543 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
544 {
545         if (win >= dc->n_windows)
546                 return NULL;
547
548         return &dc->windows[win];
549 }
550 EXPORT_SYMBOL(tegra_dc_get_window);
551
552 static int get_topmost_window(u32 *depths, unsigned long *wins)
553 {
554         int idx, best = -1;
555
556         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
557                 if (best == -1 || depths[idx] < depths[best])
558                         best = idx;
559         }
560         clear_bit(best, wins);
561         return best;
562 }
563
564 bool tegra_dc_get_connected(struct tegra_dc *dc)
565 {
566         return dc->connected;
567 }
568 EXPORT_SYMBOL(tegra_dc_get_connected);
569
570 static u32 blend_topwin(u32 flags)
571 {
572         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
573                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
574         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
575                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
576         else
577                 return BLEND(NOKEY, FIX, 0xff, 0xff);
578 }
579
580 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
581 {
582         int other;
583
584         for (other = 0; other < DC_N_WINDOWS; other++) {
585                 if (other != idx && (xy-- == 0))
586                         break;
587         }
588         if (BIT(other) & behind_mask)
589                 return blend_topwin(flags[idx]);
590         else if (flags[other])
591                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
592         else
593                 return BLEND(NOKEY, FIX, 0x00, 0x00);
594 }
595
596 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
597 {
598         unsigned long infront_mask;
599         int first;
600
601         infront_mask = ~(behind_mask | BIT(idx));
602         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
603         first = ffs(infront_mask) - 1;
604
605         if (!infront_mask)
606                 return blend_topwin(flags[idx]);
607         else if (behind_mask && first != -1 && flags[first])
608                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
609         else
610                 return BLEND(NOKEY, FIX, 0x0, 0x0);
611 }
612
613 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
614 {
615         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
616
617         while (mask) {
618                 int idx = get_topmost_window(blend->z, &mask);
619
620                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
621                                 DC_CMD_DISPLAY_WINDOW_HEADER);
622                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
623                                 DC_WIN_BLEND_NOKEY);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_1WIN);
626                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
627                                 DC_WIN_BLEND_2WIN_X);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
629                                 DC_WIN_BLEND_2WIN_Y);
630                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
631                                 DC_WIN_BLEND_3WIN_XY);
632         }
633 }
634
635 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 {
637         csc->yof   = 0x00f0;
638         csc->kyrgb = 0x012a;
639         csc->kur   = 0x0000;
640         csc->kvr   = 0x0198;
641         csc->kug   = 0x039b;
642         csc->kvg   = 0x032f;
643         csc->kub   = 0x0204;
644         csc->kvb   = 0x0000;
645 }
646
647 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
648 {
649         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
650         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
651         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
652         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
653         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
654         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
655         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
656         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
657 }
658
659 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
660 {
661         mutex_lock(&dc->lock);
662
663         if (!dc->enabled) {
664                 mutex_unlock(&dc->lock);
665                 return -EFAULT;
666         }
667
668         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
669                         DC_CMD_DISPLAY_WINDOW_HEADER);
670
671         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
672
673         mutex_unlock(&dc->lock);
674
675         return 0;
676 }
677 EXPORT_SYMBOL(tegra_dc_update_csc);
678
679 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
680 {
681         int i;
682         for (i = 0; i < 256; i++)
683                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
684 }
685
686 static int tegra_dc_loop_lut(struct tegra_dc *dc,
687                              struct tegra_dc_win *win,
688                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
689 {
690         struct tegra_dc_lut *lut = &win->lut;
691         struct tegra_dc_lut *global_lut = &dc->fb_lut;
692         int i;
693         for (i = 0; i < 256; i++) {
694
695                 u32 r = (u32)lut->r[i];
696                 u32 g = (u32)lut->g[i];
697                 u32 b = (u32)lut->b[i];
698
699                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
700                         r = (u32)global_lut->r[r];
701                         g = (u32)global_lut->g[g];
702                         b = (u32)global_lut->b[b];
703                 }
704
705                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
706                         return 0;
707         }
708         return 1;
709 }
710
711 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
712 {
713         if (rgb != (i | (i<<8) | (i<<16)))
714                 return 0;
715         return 1;
716 }
717
718 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
719 {
720         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
721         return 1;
722 }
723
724 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
725 {
726         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
727
728         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
729
730         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
731                 val |= CP_ENABLE;
732         else
733                 val &= ~CP_ENABLE;
734
735         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
736 }
737
738 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
739 {
740         struct tegra_dc_win *win = &dc->windows[win_idx];
741
742         mutex_lock(&dc->lock);
743
744         if (!dc->enabled) {
745                 mutex_unlock(&dc->lock);
746                 return -EFAULT;
747         }
748
749         if (fbovr > 0)
750                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
751         else if (fbovr == 0)
752                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753
754         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
756         else
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
758
759         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
760                         DC_CMD_DISPLAY_WINDOW_HEADER);
761
762         tegra_dc_set_lut(dc, win);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768
769 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
770 {
771         if (win_idx > -1)
772                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
773
774         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
775                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
776                 if (err)
777                         return err;
778         }
779
780         return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_update_lut);
783
784 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
785 {
786         unsigned i;
787         unsigned v0 = 128;
788         unsigned v1 = 0;
789         /* linear horizontal and vertical filters */
790         for (i = 0; i < 16; i++) {
791                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
792                                 DC_WIN_H_FILTER_P(i));
793
794                 tegra_dc_writel(dc, v0,
795                                 DC_WIN_V_FILTER_P(i));
796                 v0 -= 8;
797                 v1 += 8;
798         }
799 }
800
801 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
802         struct tegra_dc_win *w)
803 {
804         /* windows A, B, C for first and second display */
805         static const enum tegra_la_id la_id_tab[2][3] = {
806                 /* first display */
807                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
808                         TEGRA_LA_DISPLAY_0C },
809                 /* second display */
810                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
811                         TEGRA_LA_DISPLAY_0CB },
812         };
813         /* window B V-filter tap for first and second display. */
814         static const enum tegra_la_id vfilter_tab[2] = {
815                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
816         };
817         unsigned long bw;
818
819         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
820         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
821         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
822
823         bw = w->new_bandwidth;
824
825         /* tegra_dc_get_bandwidth() treats V filter windows as double
826          * bandwidth, but LA has a seperate client for V filter */
827         if (w->idx == 1 && win_use_v_filter(w))
828                 bw /= 2;
829
830         /* our bandwidth is in bytes/sec, but LA takes MBps.
831          * round up bandwidth to 1MBps */
832         bw = bw / 1000000 + 1;
833
834 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
835         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
836         /* if window B, also set the 1B client for the 2-tap V filter. */
837         if (w->idx == 1)
838                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
839 #endif
840
841         w->bandwidth = w->new_bandwidth;
842 }
843
844 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
845                                                    struct tegra_dc_win *b)
846 {
847         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
848                 return 0;
849
850         /* because memory access to load the fifo can overlap, only care
851          * if windows overlap vertically */
852         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
853                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
854 }
855
856 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
857                                                  int n)
858 {
859         unsigned i;
860         unsigned j;
861         unsigned overlap_count;
862         unsigned max_bw = 0;
863
864         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
865                          "inaccurate.\n");
866
867         /* If we had a large number of windows, we would compute adjacency
868          * graph representing 2 window overlaps, find all cliques in the graph,
869          * assign bandwidth to each clique, and then select the clique with
870          * maximum bandwidth. But because we have at most 3 windows,
871          * implementing proper Bron-Kerbosh algorithm would be an overkill,
872          * brute force will suffice.
873          *
874          * Thus: find maximum bandwidth for either single or a pair of windows
875          * and count number of window pair overlaps. If there are three
876          * pairs, all 3 window overlap.
877          */
878
879         overlap_count = 0;
880         for (i = 0; i < n; i++) {
881                 unsigned int bw1;
882
883                 if (wins[i] == NULL)
884                         continue;
885                 bw1 = wins[i]->new_bandwidth;
886                 if (bw1 > max_bw)
887                         /* Single window */
888                         max_bw = bw1;
889
890                 for (j = i + 1; j < n; j++) {
891                         if (wins[j] == NULL)
892                                 continue;
893                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
894                                 unsigned int bw2 = wins[j]->new_bandwidth;
895                                 if (bw1 + bw2 > max_bw)
896                                         /* Window pair overlaps */
897                                         max_bw = bw1 + bw2;
898                                 overlap_count++;
899                         }
900                 }
901         }
902
903         if (overlap_count == 3)
904                 /* All three windows overlap */
905                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
906                          wins[2]->new_bandwidth;
907
908         return max_bw;
909 }
910
911 /*
912  * Calculate peak EMC bandwidth for each enabled window =
913  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
914  * (windows_tiling ? 2 : 1)
915  *
916  *
917  * note:
918  * (*) We use 2 tap V filter, so need double BW if use V filter
919  * (*) Tiling mode on T30 and DDR3 requires double BW
920  */
921 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
922         struct tegra_dc_win *w)
923 {
924         unsigned long ret;
925         int tiled_windows_bw_multiplier;
926         unsigned long bpp;
927
928         if (!WIN_IS_ENABLED(w))
929                 return 0;
930
931         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
932             w->out_w == 0 || w->out_h == 0)
933                 return 0;
934
935         tiled_windows_bw_multiplier =
936                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
937
938         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
939          * but the size reported by tegra_dc_fmt_bpp for the planar version
940          * is of the luma plane's size only. */
941         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
942                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
943         /* perform calculations with most significant bits of pixel clock
944          * to prevent overflow of long. */
945         ret = (unsigned long)(dc->mode.pclk >> 16) *
946                 bpp / 8 *
947                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
948                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
949
950 /*
951  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
952  * will request 147MBps from EMC.
953  */
954         ret = ret * 2 + ret / 10;
955
956         /* if overflowed */
957         if (ret > (1UL << 31))
958                 return ULONG_MAX;
959
960         return ret << 16; /* restore the scaling we did above */
961 }
962
963 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
964 {
965         int i;
966
967         BUG_ON(n > DC_N_WINDOWS);
968
969         /* emc rate and latency allowance both need to know per window
970          * bandwidths */
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *w = windows[i];
973                 if (w)
974                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
975         }
976
977         return tegra_dc_find_max_bandwidth(windows, n);
978 }
979
980 /* to save power, call when display memory clients would be idle */
981 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
982 {
983         if (tegra_is_clk_enabled(dc->emc_clk))
984                 clk_disable(dc->emc_clk);
985         dc->emc_clk_rate = 0;
986 }
987
988 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
989 {
990         unsigned i;
991
992         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
993                 /* going from 0 to non-zero */
994                 if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk))
995                         clk_enable(dc->emc_clk);
996                 dc->emc_clk_rate = dc->new_emc_clk_rate;
997                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
998         }
999
1000         for (i = 0; i < DC_N_WINDOWS; i++) {
1001                 struct tegra_dc_win *w = &dc->windows[i];
1002                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1003                         tegra_dc_set_latency_allowance(dc, w);
1004         }
1005 }
1006
1007 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1008 {
1009         unsigned long new_rate;
1010         struct tegra_dc *dc;
1011
1012         if (!use_dynamic_emc)
1013                 return 0;
1014
1015         dc = windows[0]->dc;
1016
1017         /* calculate the new rate based on this POST */
1018         new_rate = tegra_dc_get_bandwidth(windows, n);
1019         new_rate = EMC_BW_TO_FREQ(new_rate);
1020
1021         if (tegra_dc_has_multiple_dc())
1022                 new_rate = ULONG_MAX;
1023
1024         dc->new_emc_clk_rate = new_rate;
1025
1026         return 0;
1027 }
1028
1029 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1030                                   bool v, unsigned Bpp)
1031 {
1032         /*
1033          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1034          *           (post_scaled_size_in_pixels - 1)), MAX)
1035          * Where the value of MAX is as follows:
1036          * For V_DDA_INCREMENT: 15.0 (0xF000)
1037          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1038          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1039          */
1040
1041         fixed20_12 out = dfixed_init(out_int);
1042         u32 dda_inc;
1043         int max;
1044
1045         if (v) {
1046                 max = 15;
1047         } else {
1048                 switch (Bpp) {
1049                 default:
1050                         WARN_ON_ONCE(1);
1051                         /* fallthrough */
1052                 case 4:
1053                         max = 4;
1054                         break;
1055                 case 2:
1056                         max = 8;
1057                         break;
1058                 }
1059         }
1060
1061         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1062         in.full -= dfixed_const(1);
1063
1064         dda_inc = dfixed_div(in, out);
1065
1066         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1067
1068         return dda_inc;
1069 }
1070
1071 static inline u32 compute_initial_dda(fixed20_12 in)
1072 {
1073         return dfixed_frac(in);
1074 }
1075
1076 /* does not support updating windows on multiple dcs in one call */
1077 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1078 {
1079         struct tegra_dc *dc;
1080         unsigned long update_mask = GENERAL_ACT_REQ;
1081         unsigned long val;
1082         bool update_blend = false;
1083         int i;
1084
1085         dc = windows[0]->dc;
1086
1087         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1088                 /* Acquire one_shot_lock to avoid race condition between
1089                  * cancellation of old delayed work and schedule of new
1090                  * delayed work. */
1091                 mutex_lock(&dc->one_shot_lock);
1092                 cancel_delayed_work_sync(&dc->one_shot_work);
1093         }
1094         mutex_lock(&dc->lock);
1095
1096         if (!dc->enabled) {
1097                 mutex_unlock(&dc->lock);
1098                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1099                         mutex_unlock(&dc->one_shot_lock);
1100                 return -EFAULT;
1101         }
1102
1103         if (no_vsync)
1104                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1105         else
1106                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1107
1108         for (i = 0; i < DC_N_WINDOWS; i++) {
1109                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1110                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1111                 tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1112                 if (!no_vsync)
1113                         update_mask |= WIN_A_ACT_REQ << i;
1114         }
1115
1116         for (i = 0; i < n; i++) {
1117                 struct tegra_dc_win *win = windows[i];
1118                 unsigned h_dda;
1119                 unsigned v_dda;
1120                 fixed20_12 h_offset, v_offset;
1121                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1122                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1123                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1124                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1125                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1126                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1127                 const bool filter_h = win_use_h_filter(win);
1128                 const bool filter_v = win_use_v_filter(win);
1129
1130                 if (win->z != dc->blend.z[win->idx]) {
1131                         dc->blend.z[win->idx] = win->z;
1132                         update_blend = true;
1133                 }
1134                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1135                         dc->blend.flags[win->idx]) {
1136                         dc->blend.flags[win->idx] =
1137                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1138                         update_blend = true;
1139                 }
1140
1141                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1142                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1143
1144                 if (!no_vsync)
1145                         update_mask |= WIN_A_ACT_REQ << win->idx;
1146
1147                 if (!WIN_IS_ENABLED(win)) {
1148                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1149                         continue;
1150                 }
1151
1152                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1153                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1154
1155                 tegra_dc_writel(dc,
1156                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1157                                 DC_WIN_POSITION);
1158                 tegra_dc_writel(dc,
1159                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1160                                 DC_WIN_SIZE);
1161                 tegra_dc_writel(dc,
1162                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1163                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1164                                 DC_WIN_PRESCALED_SIZE);
1165
1166                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1167                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1168                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1169                                 DC_WIN_DDA_INCREMENT);
1170                 h_dda = compute_initial_dda(win->x);
1171                 v_dda = compute_initial_dda(win->y);
1172                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1173                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1174
1175                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1176                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1177                 tegra_dc_writel(dc,
1178                                 (unsigned long)win->phys_addr,
1179                                 DC_WINBUF_START_ADDR);
1180
1181                 if (!yuvp) {
1182                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1183                 } else {
1184                         tegra_dc_writel(dc,
1185                                         (unsigned long)win->phys_addr_u,
1186                                         DC_WINBUF_START_ADDR_U);
1187                         tegra_dc_writel(dc,
1188                                         (unsigned long)win->phys_addr_v,
1189                                         DC_WINBUF_START_ADDR_V);
1190                         tegra_dc_writel(dc,
1191                                         LINE_STRIDE(win->stride) |
1192                                         UV_LINE_STRIDE(win->stride_uv),
1193                                         DC_WIN_LINE_STRIDE);
1194                 }
1195
1196                 h_offset = win->x;
1197                 if (invert_h) {
1198                         h_offset.full += win->w.full - dfixed_const(1);
1199                 }
1200
1201                 v_offset = win->y;
1202                 if (invert_v) {
1203                         v_offset.full += win->h.full - dfixed_const(1);
1204                 }
1205
1206                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1207                                 DC_WINBUF_ADDR_H_OFFSET);
1208                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1209                                 DC_WINBUF_ADDR_V_OFFSET);
1210
1211                 if (WIN_IS_TILED(win))
1212                         tegra_dc_writel(dc,
1213                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1214                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1215                                         DC_WIN_BUFFER_ADDR_MODE);
1216                 else
1217                         tegra_dc_writel(dc,
1218                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1219                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1220                                         DC_WIN_BUFFER_ADDR_MODE);
1221
1222                 val = WIN_ENABLE;
1223                 if (yuvp)
1224                         val |= CSC_ENABLE;
1225                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1226                         val |= COLOR_EXPAND;
1227
1228                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1229                         val |= CP_ENABLE;
1230
1231                 if (filter_h)
1232                         val |= H_FILTER_ENABLE;
1233                 if (filter_v)
1234                         val |= V_FILTER_ENABLE;
1235
1236                 if (invert_h)
1237                         val |= H_DIRECTION_DECREMENT;
1238                 if (invert_v)
1239                         val |= V_DIRECTION_DECREMENT;
1240
1241                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1242
1243                 win->dirty = no_vsync ? 0 : 1;
1244
1245                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1246                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1247                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1248                         __func__, win->idx, win->z,
1249                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1250                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1251                         win->out_x, win->out_y, win->out_w, win->out_h,
1252                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1253         }
1254
1255         if (update_blend) {
1256                 tegra_dc_set_blending(dc, &dc->blend);
1257                 for (i = 0; i < DC_N_WINDOWS; i++) {
1258                         if (!no_vsync)
1259                                 dc->windows[i].dirty = 1;
1260                         update_mask |= WIN_A_ACT_REQ << i;
1261                 }
1262         }
1263
1264         tegra_dc_set_dynamic_emc(windows, n);
1265
1266         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1267
1268         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1269         if (!no_vsync) {
1270                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1271                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1272                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1273         } else {
1274                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1275                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1276                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1277         }
1278
1279         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1280                 schedule_delayed_work(&dc->one_shot_work,
1281                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1282
1283         /* update EMC clock if calculated bandwidth has changed */
1284         tegra_dc_program_bandwidth(dc);
1285
1286         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1287                 update_mask |= NC_HOST_TRIG;
1288
1289         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1290
1291         mutex_unlock(&dc->lock);
1292         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1293                 mutex_unlock(&dc->one_shot_lock);
1294
1295         return 0;
1296 }
1297 EXPORT_SYMBOL(tegra_dc_update_windows);
1298
1299 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1300 {
1301         return dc->syncpt[i].id;
1302 }
1303 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1304
1305 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1306 {
1307         u32 max;
1308
1309         mutex_lock(&dc->lock);
1310         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1311                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1312         dc->syncpt[i].max = max;
1313         mutex_unlock(&dc->lock);
1314
1315         return max;
1316 }
1317
1318 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1319 {
1320         mutex_lock(&dc->lock);
1321         if ( dc->enabled )
1322                 while (dc->syncpt[i].min < val) {
1323                         dc->syncpt[i].min++;
1324                         nvhost_syncpt_cpu_incr(
1325                                         &nvhost_get_host(dc->ndev)->syncpt,
1326                                         dc->syncpt[i].id);
1327                 }
1328         mutex_unlock(&dc->lock);
1329 }
1330
1331 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1332                                              int n)
1333 {
1334         int i;
1335
1336         for (i = 0; i < n; i++) {
1337                 if (windows[i]->dirty)
1338                         return false;
1339         }
1340
1341         return true;
1342 }
1343
1344 /* does not support syncing windows on multiple dcs in one call */
1345 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1346 {
1347         if (n < 1 || n > DC_N_WINDOWS)
1348                 return -EINVAL;
1349
1350         if (!windows[0]->dc->enabled)
1351                 return -EFAULT;
1352
1353 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1354         /* Don't want to timeout on simulator */
1355         return wait_event_interruptible(windows[0]->dc->wq,
1356                 tegra_dc_windows_are_clean(windows, n));
1357 #else
1358         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1359                                          tegra_dc_windows_are_clean(windows, n),
1360                                          HZ);
1361 #endif
1362 }
1363 EXPORT_SYMBOL(tegra_dc_sync_windows);
1364
1365 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1366 {
1367 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1368         return clk_get_rate(dc->clk);
1369 #else
1370         return 27000000;
1371 #endif
1372 }
1373
1374 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1375 {
1376         unsigned long rate;
1377         unsigned long div;
1378
1379         rate = tegra_dc_clk_get_rate(dc);
1380
1381         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1382
1383         if (div < 2)
1384                 return 0;
1385
1386         return rate * 2 / div;
1387 }
1388
1389 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1390 {
1391         unsigned long rate;
1392         unsigned long div;
1393
1394         rate = clk_get_rate(parent);
1395
1396         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1397
1398         if (div < 2)
1399                 return 0;
1400
1401         return rate * 2 / div;
1402 }
1403
1404 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1405 {
1406         int pclk;
1407
1408         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1409                 unsigned long rate;
1410                 struct clk *parent_clk =
1411                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1412
1413                 if (dc->out->parent_clk_backup &&
1414                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1415                         rate = tegra_dc_pclk_predict_rate(
1416                                 parent_clk, dc->mode.pclk);
1417                         /* use pll_d as last resort */
1418                         if (rate < (dc->mode.pclk / 100 * 99) ||
1419                             rate > (dc->mode.pclk / 100 * 109))
1420                                 parent_clk = clk_get_sys(
1421                                         NULL, dc->out->parent_clk_backup);
1422                 }
1423
1424                 if (clk_get_parent(clk) != parent_clk)
1425                         clk_set_parent(clk, parent_clk);
1426
1427                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1428                         struct clk *base_clk = clk_get_parent(parent_clk);
1429
1430                         /* Assuming either pll_d or pll_d2 is used */
1431                         rate = dc->mode.pclk * 2;
1432
1433                         if (rate != clk_get_rate(base_clk))
1434                                 clk_set_rate(base_clk, rate);
1435                 }
1436         }
1437
1438         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1439                 unsigned long rate;
1440                 struct clk *parent_clk =
1441                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1442                 struct clk *base_clk = clk_get_parent(parent_clk);
1443
1444                 /* needs to match tegra_dc_hdmi_supported_modes[]
1445                 and tegra_pll_d_freq_table[] */
1446                 if (dc->mode.pclk > 70000000)
1447                         rate = 594000000;
1448                 else if (dc->mode.pclk > 25200000)
1449                         rate = 216000000;
1450                 else
1451                         rate = 504000000;
1452
1453                 if (rate != clk_get_rate(base_clk))
1454                         clk_set_rate(base_clk, rate);
1455
1456                 if (clk_get_parent(clk) != parent_clk)
1457                         clk_set_parent(clk, parent_clk);
1458         }
1459
1460         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1461                 unsigned long rate;
1462                 struct clk *parent_clk;
1463                 struct clk *base_clk;
1464
1465                 if (clk == dc->clk) {
1466                         parent_clk = clk_get_sys(NULL,
1467                                         dc->out->parent_clk ? : "pll_d_out0");
1468                         base_clk = clk_get_parent(parent_clk);
1469                         tegra_clk_cfg_ex(base_clk,
1470                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1471                 } else {
1472                         if (dc->pdata->default_out->dsi->dsi_instance) {
1473                                 parent_clk = clk_get_sys(NULL,
1474                                         dc->out->parent_clk ? : "pll_d2_out0");
1475                                 base_clk = clk_get_parent(parent_clk);
1476                                 tegra_clk_cfg_ex(base_clk,
1477                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1478                         } else {
1479                                 parent_clk = clk_get_sys(NULL,
1480                                         dc->out->parent_clk ? : "pll_d_out0");
1481                                 base_clk = clk_get_parent(parent_clk);
1482                                 tegra_clk_cfg_ex(base_clk,
1483                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1484                         }
1485                 }
1486
1487                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1488                 if (rate != clk_get_rate(base_clk))
1489                         clk_set_rate(base_clk, rate);
1490
1491                 if (clk_get_parent(clk) != parent_clk)
1492                         clk_set_parent(clk, parent_clk);
1493         }
1494
1495         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1496         tegra_dvfs_set_rate(clk, pclk);
1497 }
1498
1499 /* return non-zero if constraint is violated */
1500 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1501 {
1502         long a, b;
1503
1504         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1505         a = 0;
1506
1507         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1508         b = mode->h_front_porch - 1;
1509
1510         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1511         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1512                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1513         /* check Constraint 1 and 6 */
1514         if (a > b)
1515                 return 1;
1516
1517         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1518         if (mode->h_sync_width < 1)
1519                 return 4;
1520
1521         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1522         if (mode->h_active < 16)
1523                 return 7;
1524
1525         if (href) {
1526                 if (b > a && a % 2)
1527                         *href = a + 1; /* use smallest even value */
1528                 else
1529                         *href = a; /* even or only possible value */
1530         }
1531
1532         return 0;
1533 }
1534
1535 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1536 {
1537         long a;
1538         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1539
1540         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1541         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1542                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1543
1544         /* Constraint 6 */
1545         if (mode->v_front_porch < a + 1)
1546                 a = mode->v_front_porch - 1;
1547
1548         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1549         if (mode->v_sync_width < 1)
1550                 return 4;
1551
1552         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1553         if (mode->v_active < 16)
1554                 return 7;
1555
1556         if (vref)
1557                 *vref = a;
1558         return 0;
1559 }
1560
1561 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1562 {
1563         int ret;
1564         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1565         if (ret)
1566                 return ret;
1567         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1568         if (ret)
1569                 return ret;
1570
1571         return 0;
1572 }
1573
1574 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1575 {
1576         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1577         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1578                 return false;
1579
1580         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1581         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1582                 return false;
1583
1584         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1585          * (vertical blank). */
1586         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1587                 return false;
1588
1589         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1590         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1591                 return false;
1592
1593         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1594         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1595                 return false;
1596
1597         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1598          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1599         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1600                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1601                 return false;
1602
1603         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1604         if (mode->h_active < 16 || mode->v_active < 16)
1605                 return false;
1606
1607         return true;
1608 }
1609
1610 #ifdef DEBUG
1611 /* return in 1000ths of a Hertz */
1612 static int calc_refresh(const struct tegra_dc_mode *m)
1613 {
1614         long h_total, v_total, refresh;
1615         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1616                 m->h_sync_width;
1617         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1618                 m->v_sync_width;
1619         refresh = m->pclk / h_total;
1620         refresh *= 1000;
1621         refresh /= v_total;
1622         return refresh;
1623 }
1624
1625 static void print_mode(struct tegra_dc *dc,
1626                         const struct tegra_dc_mode *mode, const char *note)
1627 {
1628         if (mode) {
1629                 int refresh = calc_refresh(dc, mode);
1630                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1631                         note ? note : "",
1632                         mode->h_active, mode->v_active,
1633                         refresh / 1000, refresh % 1000,
1634                         mode->pclk);
1635         }
1636 }
1637 #else /* !DEBUG */
1638 static inline void print_mode(struct tegra_dc *dc,
1639                         const struct tegra_dc_mode *mode, const char *note) { }
1640 #endif /* DEBUG */
1641
1642 static inline void enable_dc_irq(unsigned int irq)
1643 {
1644 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1645         enable_irq(irq);
1646 #else
1647         /* Always disable DC interrupts on FPGA. */
1648         disable_irq(irq);
1649 #endif
1650 }
1651
1652 static inline void disable_dc_irq(unsigned int irq)
1653 {
1654         disable_irq(irq);
1655 }
1656
1657 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1658 {
1659         unsigned long val;
1660         unsigned long rate;
1661         unsigned long div;
1662         unsigned long pclk;
1663
1664         print_mode(dc, mode, __func__);
1665
1666         /* use default EMC rate when switching modes */
1667         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1668         tegra_dc_program_bandwidth(dc);
1669
1670         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1671         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1672                         DC_DISP_REF_TO_SYNC);
1673         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1674                         DC_DISP_SYNC_WIDTH);
1675         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1676                         DC_DISP_BACK_PORCH);
1677         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1678                         DC_DISP_DISP_ACTIVE);
1679         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1680                         DC_DISP_FRONT_PORCH);
1681
1682         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1683                         DC_DISP_DATA_ENABLE_OPTIONS);
1684
1685         /* TODO: MIPI/CRT/HDMI clock cals */
1686
1687         val = DISP_DATA_FORMAT_DF1P1C;
1688
1689         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1690                 val |= DISP_DATA_ALIGNMENT_MSB;
1691         else
1692                 val |= DISP_DATA_ALIGNMENT_LSB;
1693
1694         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1695                 val |= DISP_DATA_ORDER_RED_BLUE;
1696         else
1697                 val |= DISP_DATA_ORDER_BLUE_RED;
1698
1699         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1700
1701         rate = tegra_dc_clk_get_rate(dc);
1702
1703         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1704         if (pclk < (mode->pclk / 100 * 99) ||
1705             pclk > (mode->pclk / 100 * 109)) {
1706                 dev_err(&dc->ndev->dev,
1707                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1708                         rate, mode->pclk,
1709                         pclk, (mode->pclk / 100 * 99),
1710                         (mode->pclk / 100 * 109));
1711                 return -EINVAL;
1712         }
1713
1714         div = (rate * 2 / pclk) - 2;
1715
1716         tegra_dc_writel(dc, 0x00010001,
1717                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1718         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1719                         DC_DISP_DISP_CLOCK_CONTROL);
1720
1721 #ifdef CONFIG_SWITCH
1722         switch_set_state(&dc->modeset_switch,
1723                          (mode->h_active << 16) | mode->v_active);
1724 #endif
1725
1726         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1727         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1728
1729         return 0;
1730 }
1731
1732
1733 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1734 {
1735         memcpy(&dc->mode, mode, sizeof(dc->mode));
1736
1737         print_mode(dc, mode, __func__);
1738
1739         return 0;
1740 }
1741 EXPORT_SYMBOL(tegra_dc_set_mode);
1742
1743 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1744                 const struct fb_videomode *fbmode, bool stereo_mode)
1745 {
1746         struct tegra_dc_mode mode;
1747
1748         if (!fbmode->pixclock)
1749                 return -EINVAL;
1750
1751         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1752         mode.h_sync_width = fbmode->hsync_len;
1753         mode.v_sync_width = fbmode->vsync_len;
1754         mode.h_back_porch = fbmode->left_margin;
1755         mode.v_back_porch = fbmode->upper_margin;
1756         mode.h_active = fbmode->xres;
1757         mode.v_active = fbmode->yres;
1758         mode.h_front_porch = fbmode->right_margin;
1759         mode.v_front_porch = fbmode->lower_margin;
1760         mode.stereo_mode = stereo_mode;
1761         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1762                 /* HDMI controller requires h_ref=1, v_ref=1 */
1763                 mode.h_ref_to_sync = 1;
1764                 mode.v_ref_to_sync = 1;
1765         } else {
1766                 calc_ref_to_sync(&mode);
1767         }
1768         if (!check_ref_to_sync(&mode)) {
1769                 dev_err(&dc->ndev->dev,
1770                                 "Display timing doesn't meet restrictions.\n");
1771                 return -EINVAL;
1772         }
1773         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1774                 mode.h_active, mode.v_active, mode.pclk,
1775                 mode.h_ref_to_sync, mode.v_ref_to_sync
1776         );
1777
1778 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1779         /* Double the pixel clock and update v_active only for frame packed mode */
1780         if (mode.stereo_mode) {
1781                 mode.pclk *= 2;
1782                 /* total v_active = yres*2 + activespace */
1783                 mode.v_active = fbmode->yres*2 +
1784                                 fbmode->vsync_len +
1785                                 fbmode->upper_margin +
1786                                 fbmode->lower_margin;
1787         }
1788 #endif
1789
1790         mode.flags = 0;
1791
1792         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1793                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1794
1795         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1796                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1797
1798         return tegra_dc_set_mode(dc, &mode);
1799 }
1800 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1801
1802 void
1803 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1804 {
1805         unsigned int ctrl;
1806         unsigned long out_sel;
1807         unsigned long cmd_state;
1808
1809         mutex_lock(&dc->lock);
1810         if (!dc->enabled) {
1811                 mutex_unlock(&dc->lock);
1812                 return;
1813         }
1814
1815         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1816                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1817                 cfg->clk_select);
1818
1819         /* The new value should be effected immediately */
1820         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1821         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1822
1823         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1824                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1825         else
1826                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1827
1828         switch (cfg->which_pwm) {
1829         case TEGRA_PWM_PM0:
1830                 /* Select the LM0 on PM0 */
1831                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1832                 out_sel &= ~(7 << 0);
1833                 out_sel |= (3 << 0);
1834                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1835                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1836                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1837                 break;
1838         case TEGRA_PWM_PM1:
1839                 /* Select the LM1 on PM1 */
1840                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1841                 out_sel &= ~(7 << 4);
1842                 out_sel |= (3 << 4);
1843                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1844                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1845                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1846                 break;
1847         default:
1848                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1849                 break;
1850         }
1851         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1852         mutex_unlock(&dc->lock);
1853 }
1854 EXPORT_SYMBOL(tegra_dc_config_pwm);
1855
1856 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1857                                 const struct tegra_dc_out_pin *pins,
1858                                 const unsigned int n_pins)
1859 {
1860         unsigned int i;
1861
1862         int name;
1863         int pol;
1864
1865         u32 pol1, pol3;
1866
1867         u32 set1, unset1;
1868         u32 set3, unset3;
1869
1870         set1 = set3 = unset1 = unset3 = 0;
1871
1872         for (i = 0; i < n_pins; i++) {
1873                 name = (pins + i)->name;
1874                 pol  = (pins + i)->pol;
1875
1876                 /* set polarity by name */
1877                 switch (name) {
1878                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1879                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1880                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1881                         else
1882                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1883                         break;
1884                 case TEGRA_DC_OUT_PIN_H_SYNC:
1885                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1886                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1887                         else
1888                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1889                         break;
1890                 case TEGRA_DC_OUT_PIN_V_SYNC:
1891                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1892                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1893                         else
1894                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1895                         break;
1896                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1897                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1898                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1899                         else
1900                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1901                         break;
1902                 default:
1903                         printk("Invalid argument in function %s\n",
1904                                __FUNCTION__);
1905                         break;
1906                 }
1907         }
1908
1909         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1910         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1911
1912         pol1 |= set1;
1913         pol1 &= ~unset1;
1914
1915         pol3 |= set3;
1916         pol3 &= ~unset3;
1917
1918         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1919         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1920 }
1921
1922 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1923 {
1924         dc->out = out;
1925
1926         if (out->n_modes > 0)
1927                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1928
1929         switch (out->type) {
1930         case TEGRA_DC_OUT_RGB:
1931                 dc->out_ops = &tegra_dc_rgb_ops;
1932                 break;
1933
1934         case TEGRA_DC_OUT_HDMI:
1935                 dc->out_ops = &tegra_dc_hdmi_ops;
1936                 break;
1937
1938         case TEGRA_DC_OUT_DSI:
1939                 dc->out_ops = &tegra_dc_dsi_ops;
1940                 break;
1941
1942         default:
1943                 dc->out_ops = NULL;
1944                 break;
1945         }
1946
1947         if (dc->out_ops && dc->out_ops->init)
1948                 dc->out_ops->init(dc);
1949
1950 }
1951
1952 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1953 {
1954         if (dc->out)
1955                 return dc->out->height;
1956         else
1957                 return 0;
1958 }
1959 EXPORT_SYMBOL(tegra_dc_get_out_height);
1960
1961 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1962 {
1963         if (dc->out)
1964                 return dc->out->width;
1965         else
1966                 return 0;
1967 }
1968 EXPORT_SYMBOL(tegra_dc_get_out_width);
1969
1970 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1971 {
1972         if (dc->out && dc->out->max_pixclock)
1973                 return dc->out->max_pixclock;
1974         else
1975                 return 0;
1976 }
1977 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1978
1979 void tegra_dc_enable_crc(struct tegra_dc *dc)
1980 {
1981         u32 val;
1982         tegra_dc_io_start(dc);
1983
1984         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1985                 CRC_ENABLE_ENABLE;
1986         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1987         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1988         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1989 }
1990
1991 void tegra_dc_disable_crc(struct tegra_dc *dc)
1992 {
1993         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1994         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1995         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1996
1997         tegra_dc_io_end(dc);
1998 }
1999
2000 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2001 {
2002         int crc = 0;
2003
2004         if(!dc) {
2005                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2006                 goto crc_error;
2007         }
2008
2009         /* TODO: Replace mdelay with code to sync VBlANK, since
2010          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2011         mdelay(TEGRA_CRC_LATCHED_DELAY);
2012
2013         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2014 crc_error:
2015         return crc;
2016 }
2017
2018 static void tegra_dc_vblank(struct work_struct *work)
2019 {
2020         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2021         bool nvsd_updated = false;
2022
2023         mutex_lock(&dc->lock);
2024
2025         /* Update the SD brightness */
2026         if (dc->enabled && dc->out->sd_settings)
2027                 nvsd_updated = nvsd_update_brightness(dc);
2028
2029         mutex_unlock(&dc->lock);
2030
2031         /* Do the actual brightness update outside of the mutex */
2032         if (nvsd_updated && dc->out->sd_settings &&
2033             dc->out->sd_settings->bl_device) {
2034
2035                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2036                 struct backlight_device *bl = platform_get_drvdata(pdev);
2037                 if (bl)
2038                         backlight_update_status(bl);
2039         }
2040 }
2041
2042 /* Must acquire dc lock and dc one-shot lock before invoking this function.
2043  * Acquire dc one-shot lock first and then dc lock. */
2044 void tegra_dc_host_trigger(struct tegra_dc *dc)
2045 {
2046         /* We release the lock here to prevent deadlock between
2047          * cancel_delayed_work_sync and one-shot work. */
2048         mutex_unlock(&dc->lock);
2049
2050         cancel_delayed_work_sync(&dc->one_shot_work);
2051         mutex_lock(&dc->lock);
2052
2053         schedule_delayed_work(&dc->one_shot_work,
2054                                 msecs_to_jiffies(dc->one_shot_delay_ms));
2055         tegra_dc_program_bandwidth(dc);
2056         tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
2057 }
2058
2059 static void tegra_dc_one_shot_worker(struct work_struct *work)
2060 {
2061         struct tegra_dc *dc = container_of(
2062                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2063         mutex_lock(&dc->lock);
2064         /* memory client has gone idle */
2065         tegra_dc_clear_bandwidth(dc);
2066         mutex_unlock(&dc->lock);
2067 }
2068
2069 /* return an arbitrarily large number if count overflow occurs.
2070  * make it a nice base-10 number to show up in stats output */
2071 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2072 {
2073         unsigned count = tegra_dc_readl(dc, reg);
2074         tegra_dc_writel(dc, 0, reg);
2075         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2076 }
2077
2078 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2079 {
2080         u32 val;
2081         int i;
2082
2083         dc->stats.underflows++;
2084         if (dc->underflow_mask & WIN_A_UF_INT)
2085                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2086                         DC_WINBUF_AD_UFLOW_STATUS);
2087         if (dc->underflow_mask & WIN_B_UF_INT)
2088                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2089                         DC_WINBUF_BD_UFLOW_STATUS);
2090         if (dc->underflow_mask & WIN_C_UF_INT)
2091                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2092                         DC_WINBUF_CD_UFLOW_STATUS);
2093
2094         /* Check for any underflow reset conditions */
2095         for (i = 0; i < DC_N_WINDOWS; i++) {
2096                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2097                         dc->windows[i].underflows++;
2098
2099 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2100                         if (dc->windows[i].underflows > 4)
2101                                 schedule_work(&dc->reset_work);
2102 #endif
2103                 } else {
2104                         dc->windows[i].underflows = 0;
2105                 }
2106         }
2107
2108         /* Clear the underflow mask now that we've checked it. */
2109         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2110         dc->underflow_mask = 0;
2111         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2112         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2113 }
2114
2115 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2116 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2117 {
2118 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2119         u32 val;
2120
2121         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2122         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2123             return true;
2124 #endif
2125         return false;
2126 }
2127
2128 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2129 {
2130         u32 val, i;
2131         u32 completed = 0;
2132         u32 dirty = 0;
2133
2134         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2135         for (i = 0; i < DC_N_WINDOWS; i++) {
2136 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2137                 /* FIXME: this is not needed when the simulator
2138                    clears WIN_x_UPDATE bits as in HW */
2139                 dc->windows[i].dirty = 0;
2140                 completed = 1;
2141 #else
2142                 if (!(val & (WIN_A_UPDATE << i))) {
2143                         dc->windows[i].dirty = 0;
2144                         completed = 1;
2145                 } else {
2146                         dirty = 1;
2147                 }
2148 #endif
2149         }
2150
2151         if (!dirty) {
2152                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2153                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2154                         val &= ~V_BLANK_INT;
2155                 else
2156                         val &= ~FRAME_END_INT;
2157                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2158         }
2159
2160         if (completed) {
2161                 if (!dirty) {
2162                         /* With the last completed window, go ahead
2163                            and enable the vblank interrupt for nvsd. */
2164                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2165                         val |= V_BLANK_INT;
2166                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2167                 }
2168
2169                 wake_up(&dc->wq);
2170         }
2171 }
2172
2173 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2174 {
2175         if (status & V_BLANK_INT) {
2176                 /* Sync up windows. */
2177                 tegra_dc_trigger_windows(dc);
2178
2179                 /* Schedule any additional bottom-half vblank actvities. */
2180                 schedule_work(&dc->vblank_work);
2181         }
2182
2183         if (status & FRAME_END_INT) {
2184                 /* Mark the frame_end as complete. */
2185                 if (!completion_done(&dc->frame_end_complete))
2186                         complete(&dc->frame_end_complete);
2187         }
2188 }
2189
2190 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2191 {
2192         if (status & V_BLANK_INT) {
2193                 /* Schedule any additional bottom-half vblank actvities. */
2194                 schedule_work(&dc->vblank_work);
2195
2196                 /* All windows updated. Mask subsequent V_BLANK interrupts */
2197                 if (!tegra_dc_windows_are_dirty(dc)) {
2198                         u32 val;
2199
2200                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2201                         val &= ~V_BLANK_INT;
2202                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2203                 }
2204         }
2205
2206         if (status & FRAME_END_INT) {
2207                 /* Mark the frame_end as complete. */
2208                 if (!completion_done(&dc->frame_end_complete))
2209                         complete(&dc->frame_end_complete);
2210
2211                 tegra_dc_trigger_windows(dc);
2212         }
2213 }
2214 #endif
2215
2216 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2217 {
2218 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2219         struct tegra_dc *dc = ptr;
2220         unsigned long status;
2221         unsigned long underflow_mask;
2222         u32 val;
2223
2224         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2225                 WARN(1, "IRQ when DC not powered!\n");
2226                 tegra_dc_io_start(dc);
2227                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2228                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2229                 tegra_dc_io_end(dc);
2230                 return IRQ_HANDLED;
2231         }
2232
2233         /* clear all status flags except underflow, save those for the worker */
2234         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2235         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2236         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2237         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2238
2239         /*
2240          * Overlays can get thier internal state corrupted during and underflow
2241          * condition.  The only way to fix this state is to reset the DC.
2242          * if we get 4 consecutive frames with underflows, assume we're
2243          * hosed and reset.
2244          */
2245         underflow_mask = status & ALL_UF_INT;
2246
2247         /* Check underflow */
2248         if (underflow_mask) {
2249                 dc->underflow_mask |= underflow_mask;
2250                 schedule_delayed_work(&dc->underflow_work,
2251                         msecs_to_jiffies(1));
2252         }
2253
2254         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2255                 tegra_dc_one_shot_irq(dc, status);
2256         else
2257                 tegra_dc_continuous_irq(dc, status);
2258
2259         return IRQ_HANDLED;
2260 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2261         return IRQ_NONE;
2262 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2263 }
2264
2265 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2266 {
2267         u32 color_control;
2268
2269         switch (dc->out->depth) {
2270         case 3:
2271                 color_control = BASE_COLOR_SIZE111;
2272                 break;
2273
2274         case 6:
2275                 color_control = BASE_COLOR_SIZE222;
2276                 break;
2277
2278         case 8:
2279                 color_control = BASE_COLOR_SIZE332;
2280                 break;
2281
2282         case 9:
2283                 color_control = BASE_COLOR_SIZE333;
2284                 break;
2285
2286         case 12:
2287                 color_control = BASE_COLOR_SIZE444;
2288                 break;
2289
2290         case 15:
2291                 color_control = BASE_COLOR_SIZE555;
2292                 break;
2293
2294         case 16:
2295                 color_control = BASE_COLOR_SIZE565;
2296                 break;
2297
2298         case 18:
2299                 color_control = BASE_COLOR_SIZE666;
2300                 break;
2301
2302         default:
2303                 color_control = BASE_COLOR_SIZE888;
2304                 break;
2305         }
2306
2307         switch (dc->out->dither) {
2308         case TEGRA_DC_DISABLE_DITHER:
2309                 color_control |= DITHER_CONTROL_DISABLE;
2310                 break;
2311         case TEGRA_DC_ORDERED_DITHER:
2312                 color_control |= DITHER_CONTROL_ORDERED;
2313                 break;
2314         case TEGRA_DC_ERRDIFF_DITHER:
2315                 /* The line buffer for error-diffusion dither is limited
2316                  * to 1280 pixels per line. This limits the maximum
2317                  * horizontal active area size to 1280 pixels when error
2318                  * diffusion is enabled.
2319                  */
2320                 BUG_ON(dc->mode.h_active > 1280);
2321                 color_control |= DITHER_CONTROL_ERRDIFF;
2322                 break;
2323         }
2324
2325         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2326 }
2327
2328 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2329 {
2330         u32 syncpt_id;
2331
2332         switch (dc->ndev->id) {
2333         case 0:
2334                 switch (idx) {
2335                 case 0:
2336                         syncpt_id = NVSYNCPT_DISP0_A;
2337                         break;
2338                 case 1:
2339                         syncpt_id = NVSYNCPT_DISP0_B;
2340                         break;
2341                 case 2:
2342                         syncpt_id = NVSYNCPT_DISP0_C;
2343                         break;
2344                 default:
2345                         BUG();
2346                         break;
2347                 }
2348                 break;
2349         case 1:
2350                 switch (idx) {
2351                 case 0:
2352                         syncpt_id = NVSYNCPT_DISP1_A;
2353                         break;
2354                 case 1:
2355                         syncpt_id = NVSYNCPT_DISP1_B;
2356                         break;
2357                 case 2:
2358                         syncpt_id = NVSYNCPT_DISP1_C;
2359                         break;
2360                 default:
2361                         BUG();
2362                         break;
2363                 }
2364                 break;
2365         default:
2366                 BUG();
2367                 break;
2368         }
2369
2370         return syncpt_id;
2371 }
2372
2373 static void tegra_dc_init(struct tegra_dc *dc)
2374 {
2375         int i;
2376
2377         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2378         if (dc->ndev->id == 0) {
2379                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2380                                       TEGRA_MC_PRIO_MED);
2381                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2382                                       TEGRA_MC_PRIO_MED);
2383                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2384                                       TEGRA_MC_PRIO_MED);
2385                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2386                                       TEGRA_MC_PRIO_MED);
2387                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2388                                       TEGRA_MC_PRIO_HIGH);
2389         } else if (dc->ndev->id == 1) {
2390                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2391                                       TEGRA_MC_PRIO_MED);
2392                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2393                                       TEGRA_MC_PRIO_MED);
2394                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2395                                       TEGRA_MC_PRIO_MED);
2396                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2397                                       TEGRA_MC_PRIO_MED);
2398                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2399                                       TEGRA_MC_PRIO_HIGH);
2400         }
2401         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2402                         DC_CMD_CONT_SYNCPT_VSYNC);
2403         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2404         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2405         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2406         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2407
2408         /* enable interrupts for vblank, frame_end and underflows */
2409         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2410                 DC_CMD_INT_ENABLE);
2411         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2412
2413         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2414
2415         tegra_dc_set_color_control(dc);
2416         for (i = 0; i < DC_N_WINDOWS; i++) {
2417                 struct tegra_dc_win *win = &dc->windows[i];
2418                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2419                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2420                 tegra_dc_set_csc(dc, &win->csc);
2421                 tegra_dc_set_lut(dc, win);
2422                 tegra_dc_set_scaling_filter(dc);
2423         }
2424
2425
2426         for (i = 0; i < dc->n_windows; i++) {
2427                 u32 syncpt = get_syncpt(dc, i);
2428
2429                 dc->syncpt[i].id = syncpt;
2430
2431                 dc->syncpt[i].min = dc->syncpt[i].max =
2432                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2433                                         syncpt);
2434         }
2435
2436         print_mode(dc, &dc->mode, __func__);
2437
2438         if (dc->mode.pclk)
2439                 tegra_dc_program_mode(dc, &dc->mode);
2440
2441         /* Initialize SD AFTER the modeset.
2442            nvsd_init handles the sd_settings = NULL case. */
2443         nvsd_init(dc, dc->out->sd_settings);
2444 }
2445
2446 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2447 {
2448         if (dc->out->enable)
2449                 dc->out->enable();
2450
2451         tegra_dc_setup_clk(dc, dc->clk);
2452         clk_enable(dc->clk);
2453
2454         /* do not accept interrupts during initialization */
2455         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2456         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2457
2458         enable_dc_irq(dc->irq);
2459
2460         tegra_dc_init(dc);
2461
2462         if (dc->out_ops && dc->out_ops->enable)
2463                 dc->out_ops->enable(dc);
2464
2465         if (dc->out->postpoweron)
2466                 dc->out->postpoweron();
2467
2468         /* force a full blending update */
2469         dc->blend.z[0] = -1;
2470
2471         tegra_dc_ext_enable(dc->ext);
2472
2473         return true;
2474 }
2475
2476 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2477 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2478 {
2479         if (dc->out->enable)
2480                 dc->out->enable();
2481
2482         tegra_dc_setup_clk(dc, dc->clk);
2483         clk_enable(dc->clk);
2484
2485         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2486                 mutex_lock(&tegra_dcs[1]->lock);
2487                 disable_irq(tegra_dcs[1]->irq);
2488         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2489                 mutex_lock(&tegra_dcs[0]->lock);
2490                 disable_irq(tegra_dcs[0]->irq);
2491         }
2492
2493         msleep(5);
2494         tegra_periph_reset_assert(dc->clk);
2495         msleep(2);
2496 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2497         tegra_periph_reset_deassert(dc->clk);
2498         msleep(1);
2499 #endif
2500
2501         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2502                 enable_dc_irq(tegra_dcs[1]->irq);
2503                 mutex_unlock(&tegra_dcs[1]->lock);
2504         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2505                 enable_dc_irq(tegra_dcs[0]->irq);
2506                 mutex_unlock(&tegra_dcs[0]->lock);
2507         }
2508
2509         enable_dc_irq(dc->irq);
2510
2511         tegra_dc_init(dc);
2512
2513         if (dc->out_ops && dc->out_ops->enable)
2514                 dc->out_ops->enable(dc);
2515
2516         if (dc->out->postpoweron)
2517                 dc->out->postpoweron();
2518
2519         /* force a full blending update */
2520         dc->blend.z[0] = -1;
2521
2522         tegra_dc_ext_enable(dc->ext);
2523
2524         return true;
2525 }
2526 #endif
2527
2528 static bool _tegra_dc_enable(struct tegra_dc *dc)
2529 {
2530         if (dc->mode.pclk == 0)
2531                 return false;
2532
2533         if (!dc->out)
2534                 return false;
2535
2536         tegra_dc_io_start(dc);
2537
2538         return _tegra_dc_controller_enable(dc);
2539 }
2540
2541 void tegra_dc_enable(struct tegra_dc *dc)
2542 {
2543         mutex_lock(&dc->lock);
2544
2545         if (!dc->enabled)
2546                 dc->enabled = _tegra_dc_enable(dc);
2547
2548         mutex_unlock(&dc->lock);
2549 }
2550
2551 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2552 {
2553         unsigned i;
2554
2555         if (dc->out_ops && dc->out_ops->disable)
2556                 dc->out_ops->disable(dc);
2557
2558         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2559         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2560         disable_irq(dc->irq);
2561
2562         tegra_dc_clear_bandwidth(dc);
2563         clk_disable(dc->clk);
2564         tegra_dvfs_set_rate(dc->clk, 0);
2565
2566         if (dc->out && dc->out->disable)
2567                 dc->out->disable();
2568
2569         for (i = 0; i < dc->n_windows; i++) {
2570                 struct tegra_dc_win *w = &dc->windows[i];
2571
2572                 /* reset window bandwidth */
2573                 w->bandwidth = 0;
2574                 w->new_bandwidth = 0;
2575
2576                 /* disable windows */
2577                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2578
2579                 /* flush any pending syncpt waits */
2580                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2581                         dc->syncpt[i].min++;
2582                         nvhost_syncpt_cpu_incr(
2583                                 &nvhost_get_host(dc->ndev)->syncpt,
2584                                 dc->syncpt[i].id);
2585                 }
2586         }
2587 }
2588
2589 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2590 {
2591 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2592         u32 val;
2593         if (dc->enabled)  {
2594                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2595                 if (enable)
2596                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2597                 else
2598                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2599                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2600         }
2601 #endif
2602 }
2603
2604 bool tegra_dc_stats_get(struct tegra_dc *dc)
2605 {
2606 #if 0 /* right now it is always enabled */
2607         u32 val;
2608         bool res;
2609
2610         if (dc->enabled)  {
2611                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2612                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2613         } else {
2614                 res = false;
2615         }
2616
2617         return res;
2618 #endif
2619         return true;
2620 }
2621
2622 /* make the screen blank by disabling all windows */
2623 void tegra_dc_blank(struct tegra_dc *dc)
2624 {
2625         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2626         unsigned i;
2627
2628         for (i = 0; i < DC_N_WINDOWS; i++) {
2629                 dcwins[i] = tegra_dc_get_window(dc, i);
2630                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2631         }
2632
2633         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2634         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2635 }
2636
2637 static void _tegra_dc_disable(struct tegra_dc *dc)
2638 {
2639         _tegra_dc_controller_disable(dc);
2640         tegra_dc_io_end(dc);
2641 }
2642
2643 void tegra_dc_disable(struct tegra_dc *dc)
2644 {
2645         if (dc->overlay)
2646                 tegra_overlay_disable(dc->overlay);
2647
2648         tegra_dc_ext_disable(dc->ext);
2649
2650         /* it's important that new underflow work isn't scheduled before the
2651          * lock is acquired. */
2652         cancel_delayed_work_sync(&dc->underflow_work);
2653         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2654                 mutex_lock(&dc->one_shot_lock);
2655                 cancel_delayed_work_sync(&dc->one_shot_work);
2656         }
2657
2658         mutex_lock(&dc->lock);
2659
2660         if (dc->enabled) {
2661                 dc->enabled = false;
2662
2663                 if (!dc->suspended)
2664                         _tegra_dc_disable(dc);
2665         }
2666
2667 #ifdef CONFIG_SWITCH
2668         switch_set_state(&dc->modeset_switch, 0);
2669 #endif
2670
2671         mutex_unlock(&dc->lock);
2672         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2673                 mutex_unlock(&dc->one_shot_lock);
2674 }
2675
2676 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2677 static void tegra_dc_reset_worker(struct work_struct *work)
2678 {
2679         struct tegra_dc *dc =
2680                 container_of(work, struct tegra_dc, reset_work);
2681
2682         unsigned long val = 0;
2683
2684         mutex_lock(&shared_lock);
2685
2686         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2687
2688         tegra_dc_ext_disable(dc->ext);
2689
2690         mutex_lock(&dc->lock);
2691
2692         if (dc->enabled == false)
2693                 goto unlock;
2694
2695         dc->enabled = false;
2696
2697         /*
2698          * off host read bus
2699          */
2700         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2701         val &= ~(0x00000100);
2702         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2703
2704         /*
2705          * set DC to STOP mode
2706          */
2707         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2708
2709         msleep(10);
2710
2711         _tegra_dc_controller_disable(dc);
2712
2713         /* _tegra_dc_controller_reset_enable deasserts reset */
2714         _tegra_dc_controller_reset_enable(dc);
2715
2716         dc->enabled = true;
2717 unlock:
2718         mutex_unlock(&dc->lock);
2719         mutex_unlock(&shared_lock);
2720 }
2721 #endif
2722
2723 static void tegra_dc_underflow_worker(struct work_struct *work)
2724 {
2725         struct tegra_dc *dc = container_of(
2726                 to_delayed_work(work), struct tegra_dc, underflow_work);
2727
2728         mutex_lock(&dc->lock);
2729         if (dc->enabled) {
2730                 tegra_dc_underflow_handler(dc);
2731         }
2732         mutex_unlock(&dc->lock);
2733 }
2734
2735 #ifdef CONFIG_SWITCH
2736 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2737 {
2738         struct tegra_dc *dc =
2739                 container_of(sdev, struct tegra_dc, modeset_switch);
2740
2741         if (!sdev->state)
2742                 return sprintf(buf, "offline\n");
2743
2744         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2745 }
2746 #endif
2747
2748 static int tegra_dc_probe(struct nvhost_device *ndev)
2749 {
2750         struct tegra_dc *dc;
2751         struct clk *clk;
2752         struct clk *emc_clk;
2753         struct resource *res;
2754         struct resource *base_res;
2755         struct resource *fb_mem = NULL;
2756         int ret = 0;
2757         void __iomem *base;
2758         int irq;
2759         int i;
2760
2761         if (!ndev->dev.platform_data) {
2762                 dev_err(&ndev->dev, "no platform data\n");
2763                 return -ENOENT;
2764         }
2765
2766         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2767         if (!dc) {
2768                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2769                 return -ENOMEM;
2770         }
2771
2772         irq = nvhost_get_irq_byname(ndev, "irq");
2773         if (irq <= 0) {
2774                 dev_err(&ndev->dev, "no irq\n");
2775                 ret = -ENOENT;
2776                 goto err_free;
2777         }
2778
2779         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2780         if (!res) {
2781                 dev_err(&ndev->dev, "no mem resource\n");
2782                 ret = -ENOENT;
2783                 goto err_free;
2784         }
2785
2786         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2787         if (!base_res) {
2788                 dev_err(&ndev->dev, "request_mem_region failed\n");
2789                 ret = -EBUSY;
2790                 goto err_free;
2791         }
2792
2793         base = ioremap(res->start, resource_size(res));
2794         if (!base) {
2795                 dev_err(&ndev->dev, "registers can't be mapped\n");
2796                 ret = -EBUSY;
2797                 goto err_release_resource_reg;
2798         }
2799
2800         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2801
2802         clk = clk_get(&ndev->dev, NULL);
2803         if (IS_ERR_OR_NULL(clk)) {
2804                 dev_err(&ndev->dev, "can't get clock\n");
2805                 ret = -ENOENT;
2806                 goto err_iounmap_reg;
2807         }
2808
2809         emc_clk = clk_get(&ndev->dev, "emc");
2810         if (IS_ERR_OR_NULL(emc_clk)) {
2811                 dev_err(&ndev->dev, "can't get emc clock\n");
2812                 ret = -ENOENT;
2813                 goto err_put_clk;
2814         }
2815
2816         dc->clk = clk;
2817         dc->emc_clk = emc_clk;
2818         dc->shift_clk_div = 1;
2819         /* Initialize one shot work delay, it will be assigned by dsi
2820          * according to refresh rate later. */
2821         dc->one_shot_delay_ms = 40;
2822
2823         dc->base_res = base_res;
2824         dc->base = base;
2825         dc->irq = irq;
2826         dc->ndev = ndev;
2827         dc->pdata = ndev->dev.platform_data;
2828
2829         /*
2830          * The emc is a shared clock, it will be set based on
2831          * the requirements for each user on the bus.
2832          */
2833         dc->emc_clk_rate = 0;
2834
2835         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2836                 dc->enabled = true;
2837
2838         mutex_init(&dc->lock);
2839         mutex_init(&dc->one_shot_lock);
2840         init_completion(&dc->frame_end_complete);
2841         init_waitqueue_head(&dc->wq);
2842 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2843         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2844 #endif
2845         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2846         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2847         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2848
2849         tegra_dc_init_lut_defaults(&dc->fb_lut);
2850
2851         dc->n_windows = DC_N_WINDOWS;
2852         for (i = 0; i < dc->n_windows; i++) {
2853                 struct tegra_dc_win *win = &dc->windows[i];
2854                 win->idx = i;
2855                 win->dc = dc;
2856                 tegra_dc_init_csc_defaults(&win->csc);
2857                 tegra_dc_init_lut_defaults(&win->lut);
2858         }
2859
2860         ret = tegra_dc_set(dc, ndev->id);
2861         if (ret < 0) {
2862                 dev_err(&ndev->dev, "can't add dc\n");
2863                 goto err_free_irq;
2864         }
2865
2866         nvhost_set_drvdata(ndev, dc);
2867
2868 #ifdef CONFIG_SWITCH
2869         dc->modeset_switch.name = dev_name(&ndev->dev);
2870         dc->modeset_switch.state = 0;
2871         dc->modeset_switch.print_state = switch_modeset_print_mode;
2872         switch_dev_register(&dc->modeset_switch);
2873 #endif
2874
2875         if (dc->pdata->default_out)
2876                 tegra_dc_set_out(dc, dc->pdata->default_out);
2877         else
2878                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2879
2880         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2881                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2882
2883         dc->ext = tegra_dc_ext_register(ndev, dc);
2884         if (IS_ERR_OR_NULL(dc->ext)) {
2885                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2886                 dc->ext = NULL;
2887         }
2888
2889         /* interrupt handler must be registered before tegra_fb_register() */
2890         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2891                         dev_name(&ndev->dev), dc)) {
2892                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2893                 ret = -EBUSY;
2894                 goto err_put_emc_clk;
2895         }
2896
2897         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2898         disable_dc_irq(dc->irq);
2899
2900         mutex_lock(&dc->lock);
2901         if (dc->enabled)
2902                 _tegra_dc_enable(dc);
2903         mutex_unlock(&dc->lock);
2904
2905         tegra_dc_create_debugfs(dc);
2906
2907         dev_info(&ndev->dev, "probed\n");
2908
2909         if (dc->pdata->fb) {
2910                 if (dc->pdata->fb->bits_per_pixel == -1) {
2911                         unsigned long fmt;
2912                         tegra_dc_writel(dc,
2913                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2914                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2915
2916                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2917                         dc->pdata->fb->bits_per_pixel =
2918                                 tegra_dc_fmt_bpp(fmt);
2919                 }
2920
2921                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2922                 if (IS_ERR_OR_NULL(dc->fb))
2923                         dc->fb = NULL;
2924         }
2925
2926         if (dc->fb) {
2927                 dc->overlay = tegra_overlay_register(ndev, dc);
2928                 if (IS_ERR_OR_NULL(dc->overlay))
2929                         dc->overlay = NULL;
2930         }
2931
2932         if (dc->out && dc->out->hotplug_init)
2933                 dc->out->hotplug_init();
2934
2935         if (dc->out_ops && dc->out_ops->detect)
2936                 dc->out_ops->detect(dc);
2937         else
2938                 dc->connected = true;
2939
2940         tegra_dc_create_sysfs(&dc->ndev->dev);
2941
2942         return 0;
2943
2944 err_free_irq:
2945         free_irq(irq, dc);
2946 err_put_emc_clk:
2947         clk_put(emc_clk);
2948 err_put_clk:
2949         clk_put(clk);
2950 err_iounmap_reg:
2951         iounmap(base);
2952         if (fb_mem)
2953                 release_resource(fb_mem);
2954 err_release_resource_reg:
2955         release_resource(base_res);
2956 err_free:
2957         kfree(dc);
2958
2959         return ret;
2960 }
2961
2962 static int tegra_dc_remove(struct nvhost_device *ndev)
2963 {
2964         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2965
2966         tegra_dc_remove_sysfs(&dc->ndev->dev);
2967         tegra_dc_remove_debugfs(dc);
2968
2969         if (dc->overlay) {
2970                 tegra_overlay_unregister(dc->overlay);
2971         }
2972
2973         if (dc->fb) {
2974                 tegra_fb_unregister(dc->fb);
2975                 if (dc->fb_mem)
2976                         release_resource(dc->fb_mem);
2977         }
2978
2979         tegra_dc_ext_disable(dc->ext);
2980
2981         if (dc->ext)
2982                 tegra_dc_ext_unregister(dc->ext);
2983
2984         if (dc->enabled)
2985                 _tegra_dc_disable(dc);
2986
2987 #ifdef CONFIG_SWITCH
2988         switch_dev_unregister(&dc->modeset_switch);
2989 #endif
2990         free_irq(dc->irq, dc);
2991         clk_put(dc->emc_clk);
2992         clk_put(dc->clk);
2993         iounmap(dc->base);
2994         if (dc->fb_mem)
2995                 release_resource(dc->base_res);
2996         kfree(dc);
2997         tegra_dc_set(NULL, ndev->id);
2998         return 0;
2999 }
3000
3001 #ifdef CONFIG_PM
3002 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3003 {
3004         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3005
3006         dev_info(&ndev->dev, "suspend\n");
3007
3008         if (dc->overlay)
3009                 tegra_overlay_disable(dc->overlay);
3010
3011         tegra_dc_ext_disable(dc->ext);
3012
3013         mutex_lock(&dc->lock);
3014
3015         if (dc->out_ops && dc->out_ops->suspend)
3016                 dc->out_ops->suspend(dc);
3017
3018         if (dc->enabled) {
3019                 _tegra_dc_disable(dc);
3020
3021                 dc->suspended = true;
3022         }
3023
3024         if (dc->out && dc->out->postsuspend) {
3025                 dc->out->postsuspend();
3026                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3027                         /*
3028                          * avoid resume event due to voltage falling
3029                          */
3030                         msleep(100);
3031         }
3032
3033         mutex_unlock(&dc->lock);
3034
3035         return 0;
3036 }
3037
3038 static int tegra_dc_resume(struct nvhost_device *ndev)
3039 {
3040         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3041
3042         dev_info(&ndev->dev, "resume\n");
3043
3044         mutex_lock(&dc->lock);
3045         dc->suspended = false;
3046
3047         if (dc->enabled)
3048                 _tegra_dc_enable(dc);
3049
3050         if (dc->out && dc->out->hotplug_init)
3051                 dc->out->hotplug_init();
3052
3053         if (dc->out_ops && dc->out_ops->resume)
3054                 dc->out_ops->resume(dc);
3055         mutex_unlock(&dc->lock);
3056
3057         return 0;
3058 }
3059
3060 #endif /* CONFIG_PM */
3061
3062 extern int suspend_set(const char *val, struct kernel_param *kp)
3063 {
3064         if (!strcmp(val, "dump"))
3065                 dump_regs(tegra_dcs[0]);
3066 #ifdef CONFIG_PM
3067         else if (!strcmp(val, "suspend"))
3068                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3069         else if (!strcmp(val, "resume"))
3070                 tegra_dc_resume(tegra_dcs[0]->ndev);
3071 #endif
3072
3073         return 0;
3074 }
3075
3076 extern int suspend_get(char *buffer, struct kernel_param *kp)
3077 {
3078         return 0;
3079 }
3080
3081 int suspend;
3082
3083 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3084
3085 struct nvhost_driver tegra_dc_driver = {
3086         .driver = {
3087                 .name = "tegradc",
3088                 .owner = THIS_MODULE,
3089         },
3090         .probe = tegra_dc_probe,
3091         .remove = tegra_dc_remove,
3092 #ifdef CONFIG_PM
3093         .suspend = tegra_dc_suspend,
3094         .resume = tegra_dc_resume,
3095 #endif
3096 };
3097
3098 static int __init tegra_dc_module_init(void)
3099 {
3100         int ret = tegra_dc_ext_module_init();
3101         if (ret)
3102                 return ret;
3103         return nvhost_driver_register(&tegra_dc_driver);
3104 }
3105
3106 static void __exit tegra_dc_module_exit(void)
3107 {
3108         nvhost_driver_unregister(&tegra_dc_driver);
3109         tegra_dc_ext_module_exit();
3110 }
3111
3112 module_exit(tegra_dc_module_exit);
3113 module_init(tegra_dc_module_init);