video: tegra: dc: fix boot issue with HDMI
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
62         .refresh = 60,
63         .xres = 640,
64         .yres = 480,
65         .pixclock = KHZ2PICOS(25200),
66         .hsync_len = 96,        /* h_sync_width */
67         .vsync_len = 2,         /* v_sync_width */
68         .left_margin = 48,      /* h_back_porch */
69         .upper_margin = 33,     /* v_back_porch */
70         .right_margin = 16,     /* h_front_porch */
71         .lower_margin = 10,     /* v_front_porch */
72         .vmode = 0,
73         .sync = 0,
74 };
75
76 static struct tegra_dc_mode override_disp_mode[3];
77
78 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
79
80 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
81
82 DEFINE_MUTEX(tegra_dc_lock);
83 DEFINE_MUTEX(shared_lock);
84
85 void tegra_dc_clk_enable(struct tegra_dc *dc)
86 {
87         if (!tegra_is_clk_enabled(dc->clk)) {
88                 clk_enable(dc->clk);
89                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
90         }
91 }
92
93 void tegra_dc_clk_disable(struct tegra_dc *dc)
94 {
95         if (tegra_is_clk_enabled(dc->clk)) {
96                 clk_disable(dc->clk);
97                 tegra_dvfs_set_rate(dc->clk, 0);
98         }
99 }
100
101 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
102 {
103         if (dc->out_ops->hold)
104                 dc->out_ops->hold(dc);
105 }
106
107 void tegra_dc_release_dc_out(struct tegra_dc *dc)
108 {
109         if (dc->out_ops->release)
110                 dc->out_ops->release(dc);
111 }
112
113 #define DUMP_REG(a) do {                        \
114         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
115                  #a, a, tegra_dc_readl(dc, a));               \
116         print(data, buff);                                    \
117         } while (0)
118
119 #define print_underflow_info(dc) do {                 \
120         trace_printk("%s:Underflow stats: underflows : %llu, "      \
121                         "undeflows_a : %llu, "                          \
122                         "underflows_b : %llu, "                         \
123                         "underflows_c : %llu\n",                        \
124                         dc->ndev->name,                                 \
125                         dc->stats.underflows,                           \
126                         dc->stats.underflows_a, dc->stats.underflows_b, \
127                         dc->stats.underflows_c);                        \
128         } while (0)
129
130 static void _dump_regs(struct tegra_dc *dc, void *data,
131                        void (* print)(void *data, const char *str))
132 {
133         int i;
134         char buff[256];
135
136         mutex_lock(&dc->lock);
137         tegra_dc_hold_dc_out(dc);
138         tegra_dc_io_start(dc);
139
140         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
141         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
142         DUMP_REG(DC_CMD_SIGNAL_RAISE);
143         DUMP_REG(DC_CMD_INT_STATUS);
144         DUMP_REG(DC_CMD_INT_MASK);
145         DUMP_REG(DC_CMD_INT_ENABLE);
146         DUMP_REG(DC_CMD_INT_TYPE);
147         DUMP_REG(DC_CMD_INT_POLARITY);
148         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
149         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
150         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
151         DUMP_REG(DC_CMD_STATE_ACCESS);
152         DUMP_REG(DC_CMD_STATE_CONTROL);
153         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
154         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
155
156         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
157         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
158         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
159         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
160         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
161         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
162         DUMP_REG(DC_DISP_REF_TO_SYNC);
163         DUMP_REG(DC_DISP_SYNC_WIDTH);
164         DUMP_REG(DC_DISP_BACK_PORCH);
165         DUMP_REG(DC_DISP_DISP_ACTIVE);
166         DUMP_REG(DC_DISP_FRONT_PORCH);
167         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
168         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
169         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
170         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
171         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
172         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
173         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
174         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
175         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
176         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
177         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
178         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
179         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
180         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
181         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
182         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
183         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
184         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
185         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
186         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
187         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
188         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
189         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
190         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
191         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
192         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
193         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
194         DUMP_REG(DC_DISP_M0_CONTROL);
195         DUMP_REG(DC_DISP_M1_CONTROL);
196         DUMP_REG(DC_DISP_DI_CONTROL);
197         DUMP_REG(DC_DISP_PP_CONTROL);
198         DUMP_REG(DC_DISP_PP_SELECT_A);
199         DUMP_REG(DC_DISP_PP_SELECT_B);
200         DUMP_REG(DC_DISP_PP_SELECT_C);
201         DUMP_REG(DC_DISP_PP_SELECT_D);
202         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
203         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
204         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
205         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
206         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
207         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
208         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
209         DUMP_REG(DC_DISP_BORDER_COLOR);
210         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
211         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
212         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
213         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
214         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
215         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
216         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
217         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
218         DUMP_REG(DC_DISP_CURSOR_POSITION);
219         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
220         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
221         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
222         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
223         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
224         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
225         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
226         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
227         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
228         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
229         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
230         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
231         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
232
233
234         for (i = 0; i < 3; i++) {
235                 print(data, "\n");
236                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
237                 print(data, buff);
238
239                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
240                                 DC_CMD_DISPLAY_WINDOW_HEADER);
241                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
242                 DUMP_REG(DC_WIN_WIN_OPTIONS);
243                 DUMP_REG(DC_WIN_BYTE_SWAP);
244                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
245                 DUMP_REG(DC_WIN_COLOR_DEPTH);
246                 DUMP_REG(DC_WIN_POSITION);
247                 DUMP_REG(DC_WIN_SIZE);
248                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
249                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
250                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
251                 DUMP_REG(DC_WIN_DDA_INCREMENT);
252                 DUMP_REG(DC_WIN_LINE_STRIDE);
253                 DUMP_REG(DC_WIN_BUF_STRIDE);
254                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
255                 DUMP_REG(DC_WIN_BLEND_NOKEY);
256                 DUMP_REG(DC_WIN_BLEND_1WIN);
257                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
258                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
259                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
260                 DUMP_REG(DC_WINBUF_START_ADDR);
261                 DUMP_REG(DC_WINBUF_START_ADDR_U);
262                 DUMP_REG(DC_WINBUF_START_ADDR_V);
263                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
264                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
265                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
266                 DUMP_REG(DC_WIN_CSC_YOF);
267                 DUMP_REG(DC_WIN_CSC_KYRGB);
268                 DUMP_REG(DC_WIN_CSC_KUR);
269                 DUMP_REG(DC_WIN_CSC_KVR);
270                 DUMP_REG(DC_WIN_CSC_KUG);
271                 DUMP_REG(DC_WIN_CSC_KVG);
272                 DUMP_REG(DC_WIN_CSC_KUB);
273                 DUMP_REG(DC_WIN_CSC_KVB);
274         }
275
276         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
277         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
278         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
279         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
280         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
281         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
282         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
283         DUMP_REG(DC_DISP_M1_CONTROL);
284         DUMP_REG(DC_COM_PM1_CONTROL);
285         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
286         DUMP_REG(DC_DISP_SD_CONTROL);
287
288         tegra_dc_io_end(dc);
289         tegra_dc_release_dc_out(dc);
290         mutex_unlock(&dc->lock);
291 }
292
293 #undef DUMP_REG
294
295 #ifdef DEBUG
296 static void dump_regs_print(void *data, const char *str)
297 {
298         struct tegra_dc *dc = data;
299         dev_dbg(&dc->ndev->dev, "%s", str);
300 }
301
302 static void dump_regs(struct tegra_dc *dc)
303 {
304         _dump_regs(dc, dc, dump_regs_print);
305 }
306 #else /* !DEBUG */
307
308 static void dump_regs(struct tegra_dc *dc) {}
309
310 #endif /* DEBUG */
311
312 #ifdef CONFIG_DEBUG_FS
313
314 static void dbg_regs_print(void *data, const char *str)
315 {
316         struct seq_file *s = data;
317
318         seq_printf(s, "%s", str);
319 }
320
321 #undef DUMP_REG
322
323 static int dbg_dc_show(struct seq_file *s, void *unused)
324 {
325         struct tegra_dc *dc = s->private;
326
327         _dump_regs(dc, s, dbg_regs_print);
328
329         return 0;
330 }
331
332
333 static int dbg_dc_open(struct inode *inode, struct file *file)
334 {
335         return single_open(file, dbg_dc_show, inode->i_private);
336 }
337
338 static const struct file_operations regs_fops = {
339         .open           = dbg_dc_open,
340         .read           = seq_read,
341         .llseek         = seq_lseek,
342         .release        = single_release,
343 };
344
345 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
346 {
347         struct tegra_dc *dc = s->private;
348         struct tegra_dc_mode *m;
349
350         mutex_lock(&dc->lock);
351         m = &dc->mode;
352         seq_printf(s,
353                 "pclk: %d\n"
354                 "h_ref_to_sync: %d\n"
355                 "v_ref_to_sync: %d\n"
356                 "h_sync_width: %d\n"
357                 "v_sync_width: %d\n"
358                 "h_back_porch: %d\n"
359                 "v_back_porch: %d\n"
360                 "h_active: %d\n"
361                 "v_active: %d\n"
362                 "h_front_porch: %d\n"
363                 "v_front_porch: %d\n"
364                 "stereo_mode: %d\n",
365                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
366                 m->h_sync_width, m->v_sync_width,
367                 m->h_back_porch, m->v_back_porch,
368                 m->h_active, m->v_active,
369                 m->h_front_porch, m->v_front_porch,
370                 m->stereo_mode);
371         mutex_unlock(&dc->lock);
372         return 0;
373 }
374
375 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
376 {
377         return single_open(file, dbg_dc_mode_show, inode->i_private);
378 }
379
380 static const struct file_operations mode_fops = {
381         .open           = dbg_dc_mode_open,
382         .read           = seq_read,
383         .llseek         = seq_lseek,
384         .release        = single_release,
385 };
386
387 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
388 {
389         struct tegra_dc *dc = s->private;
390
391         mutex_lock(&dc->lock);
392         seq_printf(s,
393                 "underflows: %llu\n"
394                 "underflows_a: %llu\n"
395                 "underflows_b: %llu\n"
396                 "underflows_c: %llu\n",
397                 dc->stats.underflows,
398                 dc->stats.underflows_a,
399                 dc->stats.underflows_b,
400                 dc->stats.underflows_c);
401         mutex_unlock(&dc->lock);
402
403         return 0;
404 }
405
406 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
407 {
408         return single_open(file, dbg_dc_stats_show, inode->i_private);
409 }
410
411 static const struct file_operations stats_fops = {
412         .open           = dbg_dc_stats_open,
413         .read           = seq_read,
414         .llseek         = seq_lseek,
415         .release        = single_release,
416 };
417
418 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
419 {
420         if (dc->debugdir)
421                 debugfs_remove_recursive(dc->debugdir);
422         dc->debugdir = NULL;
423 }
424
425 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
426 {
427         struct dentry *retval;
428
429         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
430         if (!dc->debugdir)
431                 goto remove_out;
432
433         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
434                 &regs_fops);
435         if (!retval)
436                 goto remove_out;
437
438         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
439                 &mode_fops);
440         if (!retval)
441                 goto remove_out;
442
443         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
444                 &stats_fops);
445         if (!retval)
446                 goto remove_out;
447
448         return;
449 remove_out:
450         dev_err(&dc->ndev->dev, "could not create debugfs\n");
451         tegra_dc_remove_debugfs(dc);
452 }
453
454 #else /* !CONFIG_DEBUGFS */
455 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
456 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
457 #endif /* CONFIG_DEBUGFS */
458
459 static int tegra_dc_set(struct tegra_dc *dc, int index)
460 {
461         int ret = 0;
462
463         mutex_lock(&tegra_dc_lock);
464         if (index >= TEGRA_MAX_DC) {
465                 ret = -EINVAL;
466                 goto out;
467         }
468
469         if (dc != NULL && tegra_dcs[index] != NULL) {
470                 ret = -EBUSY;
471                 goto out;
472         }
473
474         tegra_dcs[index] = dc;
475
476 out:
477         mutex_unlock(&tegra_dc_lock);
478
479         return ret;
480 }
481
482 unsigned int tegra_dc_has_multiple_dc(void)
483 {
484         unsigned int idx;
485         unsigned int cnt = 0;
486         struct tegra_dc *dc;
487
488         mutex_lock(&tegra_dc_lock);
489         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
490                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
491         mutex_unlock(&tegra_dc_lock);
492
493         return (cnt > 1);
494 }
495
496 /* get the stride size of a window.
497  * return: stride size in bytes for window win. or 0 if unavailble. */
498 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
499 {
500         u32 stride;
501
502         if (!dc->enabled)
503                 return 0;
504         BUG_ON(win > DC_N_WINDOWS);
505         mutex_lock(&dc->lock);
506         tegra_dc_hold_dc_out(dc);
507         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
508                 DC_CMD_DISPLAY_WINDOW_HEADER);
509         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
510         tegra_dc_release_dc_out(dc);
511         mutex_unlock(&dc->lock);
512         return GET_LINE_STRIDE(stride);
513 }
514 EXPORT_SYMBOL(tegra_dc_get_stride);
515
516 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
517 {
518         if (idx < TEGRA_MAX_DC)
519                 return tegra_dcs[idx];
520         else
521                 return NULL;
522 }
523 EXPORT_SYMBOL(tegra_dc_get_dc);
524
525 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
526 {
527         if (win >= dc->n_windows)
528                 return NULL;
529
530         return &dc->windows[win];
531 }
532 EXPORT_SYMBOL(tegra_dc_get_window);
533
534 bool tegra_dc_get_connected(struct tegra_dc *dc)
535 {
536         return dc->connected;
537 }
538 EXPORT_SYMBOL(tegra_dc_get_connected);
539
540 bool tegra_dc_hpd(struct tegra_dc *dc)
541 {
542         int sense;
543         int level;
544
545         level = gpio_get_value(dc->out->hotplug_gpio);
546
547         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
548
549         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
550                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
551 }
552 EXPORT_SYMBOL(tegra_dc_hpd);
553
554 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
555 {
556         unsigned i;
557         unsigned v0 = 128;
558         unsigned v1 = 0;
559         /* linear horizontal and vertical filters */
560         for (i = 0; i < 16; i++) {
561                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
562                                 DC_WIN_H_FILTER_P(i));
563
564                 tegra_dc_writel(dc, v0,
565                                 DC_WIN_V_FILTER_P(i));
566                 v0 -= 8;
567                 v1 += 8;
568         }
569 }
570
571 static inline void disable_dc_irq(unsigned int irq)
572 {
573         disable_irq(irq);
574 }
575
576 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
577 {
578         return dc->syncpt[i].id;
579 }
580 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
581
582 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
583 {
584         u32 max;
585
586         mutex_lock(&dc->lock);
587         tegra_dc_hold_dc_out(dc);
588         max = nvhost_syncpt_incr_max_ext(dc->ndev,
589                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
590         dc->syncpt[i].max = max;
591         tegra_dc_release_dc_out(dc);
592         mutex_unlock(&dc->lock);
593
594         return max;
595 }
596
597 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
598 {
599         mutex_lock(&dc->lock);
600         if (dc->enabled) {
601                 tegra_dc_hold_dc_out(dc);
602                 while (dc->syncpt[i].min < val) {
603                         dc->syncpt[i].min++;
604                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
605                 }
606                 tegra_dc_release_dc_out(dc);
607         }
608         mutex_unlock(&dc->lock);
609 }
610
611 void
612 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
613 {
614         unsigned int ctrl;
615         unsigned long out_sel;
616         unsigned long cmd_state;
617
618         mutex_lock(&dc->lock);
619         if (!dc->enabled) {
620                 mutex_unlock(&dc->lock);
621                 return;
622         }
623
624         tegra_dc_hold_dc_out(dc);
625
626         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
627                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
628                 cfg->clk_select);
629
630         /* The new value should be effected immediately */
631         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
632         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
633
634         switch (cfg->which_pwm) {
635         case TEGRA_PWM_PM0:
636                 /* Select the LM0 on PM0 */
637                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
638                 out_sel &= ~(7 << 0);
639                 out_sel |= (3 << 0);
640                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
641                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
642                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
643                 break;
644         case TEGRA_PWM_PM1:
645                 /* Select the LM1 on PM1 */
646                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
647                 out_sel &= ~(7 << 4);
648                 out_sel |= (3 << 4);
649                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
650                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
651                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
652                 break;
653         default:
654                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
655                 break;
656         }
657         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
658         tegra_dc_release_dc_out(dc);
659         mutex_unlock(&dc->lock);
660 }
661 EXPORT_SYMBOL(tegra_dc_config_pwm);
662
663 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
664                                 const struct tegra_dc_out_pin *pins,
665                                 const unsigned int n_pins)
666 {
667         unsigned int i;
668
669         int name;
670         int pol;
671
672         u32 pol1, pol3;
673
674         u32 set1, unset1;
675         u32 set3, unset3;
676
677         set1 = set3 = unset1 = unset3 = 0;
678
679         for (i = 0; i < n_pins; i++) {
680                 name = (pins + i)->name;
681                 pol  = (pins + i)->pol;
682
683                 /* set polarity by name */
684                 switch (name) {
685                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
686                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
687                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
688                         else
689                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
690                         break;
691                 case TEGRA_DC_OUT_PIN_H_SYNC:
692                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
693                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
694                         else
695                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
696                         break;
697                 case TEGRA_DC_OUT_PIN_V_SYNC:
698                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
699                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
700                         else
701                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
702                         break;
703                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
704                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
705                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
706                         else
707                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
708                         break;
709                 default:
710                         printk("Invalid argument in function %s\n",
711                                __FUNCTION__);
712                         break;
713                 }
714         }
715
716         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
717         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
718
719         pol1 |= set1;
720         pol1 &= ~unset1;
721
722         pol3 |= set3;
723         pol3 &= ~unset3;
724
725         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
726         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
727 }
728
729 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
730 {
731         if (dc->out->type == TEGRA_DC_OUT_RGB ||
732                 dc->out->type == TEGRA_DC_OUT_HDMI ||
733                 dc->out->type == TEGRA_DC_OUT_DSI)
734                 return override_disp_mode[dc->out->type].pclk ?
735                         &override_disp_mode[dc->out->type] : NULL;
736         else
737                 return NULL;
738 }
739
740 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
741 {
742         struct tegra_dc_mode *mode;
743
744         dc->out = out;
745         mode = tegra_dc_get_override_mode(dc);
746
747         if (mode)
748                 tegra_dc_set_mode(dc, mode);
749         else if (out->n_modes > 0)
750                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
751
752         switch (out->type) {
753         case TEGRA_DC_OUT_RGB:
754                 dc->out_ops = &tegra_dc_rgb_ops;
755                 break;
756
757         case TEGRA_DC_OUT_HDMI:
758                 dc->out_ops = &tegra_dc_hdmi_ops;
759                 break;
760
761         case TEGRA_DC_OUT_DSI:
762                 dc->out_ops = &tegra_dc_dsi_ops;
763                 break;
764
765         default:
766                 dc->out_ops = NULL;
767                 break;
768         }
769
770         if (dc->out_ops && dc->out_ops->init)
771                 dc->out_ops->init(dc);
772
773 }
774
775 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
776 {
777         if (dc->out)
778                 return dc->out->height;
779         else
780                 return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_get_out_height);
783
784 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
785 {
786         if (dc->out)
787                 return dc->out->width;
788         else
789                 return 0;
790 }
791 EXPORT_SYMBOL(tegra_dc_get_out_width);
792
793 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
794 {
795         if (dc->out && dc->out->max_pixclock)
796                 return dc->out->max_pixclock;
797         else
798                 return 0;
799 }
800 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
801
802 void tegra_dc_enable_crc(struct tegra_dc *dc)
803 {
804         u32 val;
805
806         mutex_lock(&dc->lock);
807         tegra_dc_hold_dc_out(dc);
808         tegra_dc_io_start(dc);
809
810         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
811                 CRC_ENABLE_ENABLE;
812         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
813         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
814         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
815         tegra_dc_release_dc_out(dc);
816         mutex_unlock(&dc->lock);
817 }
818
819 void tegra_dc_disable_crc(struct tegra_dc *dc)
820 {
821         mutex_lock(&dc->lock);
822         tegra_dc_hold_dc_out(dc);
823         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
824         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
825         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
826
827         tegra_dc_io_end(dc);
828         tegra_dc_release_dc_out(dc);
829         mutex_unlock(&dc->lock);
830 }
831
832 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
833 {
834         int crc = 0;
835
836         if (!dc) {
837                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
838                 goto crc_error;
839         }
840
841         /* TODO: Replace mdelay with code to sync VBlANK, since
842          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
843         mdelay(TEGRA_CRC_LATCHED_DELAY);
844
845         mutex_lock(&dc->lock);
846         tegra_dc_hold_dc_out(dc);
847         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
848         tegra_dc_release_dc_out(dc);
849         mutex_unlock(&dc->lock);
850 crc_error:
851         return crc;
852 }
853
854 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
855 {
856 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
857         u32 val;
858
859         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
860         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
861             return true;
862 #endif
863         return false;
864 }
865
866 static inline void enable_dc_irq(unsigned int irq)
867 {
868 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
869         enable_irq(irq);
870 #else
871         /* Always disable DC interrupts on FPGA. */
872         disable_irq(irq);
873 #endif
874 }
875
876 static void tegra_dc_vblank(struct work_struct *work)
877 {
878         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
879         bool nvsd_updated = false;
880
881         mutex_lock(&dc->lock);
882
883         if (!dc->enabled) {
884                 mutex_unlock(&dc->lock);
885                 return;
886         }
887
888         tegra_dc_hold_dc_out(dc);
889         /* use the new frame's bandwidth setting instead of max(current, new),
890          * skip this if we're using tegra_dc_one_shot_worker() */
891         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
892                 tegra_dc_program_bandwidth(dc, true);
893
894         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
895         if (!tegra_dc_windows_are_dirty(dc))
896                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
897
898         /* Update the SD brightness */
899         if (dc->enabled && dc->out->sd_settings) {
900                 nvsd_updated = nvsd_update_brightness(dc);
901                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
902                  * V_BLANK_NVSD bit of vblank ref-count. */
903                 if (nvsd_updated) {
904                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
905                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
906                 } else {
907                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
908                 }
909         }
910
911         /* Mask vblank interrupt if ref-count is zero. */
912         if (!dc->vblank_ref_count)
913                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
914
915         tegra_dc_release_dc_out(dc);
916         mutex_unlock(&dc->lock);
917
918         /* Do the actual brightness update outside of the mutex */
919         if (nvsd_updated && dc->out->sd_settings &&
920             dc->out->sd_settings->bl_device) {
921
922                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
923                 struct backlight_device *bl = platform_get_drvdata(pdev);
924                 if (bl)
925                         backlight_update_status(bl);
926         }
927 }
928
929 static void tegra_dc_one_shot_worker(struct work_struct *work)
930 {
931         struct tegra_dc *dc = container_of(
932                 to_delayed_work(work), struct tegra_dc, one_shot_work);
933         mutex_lock(&dc->lock);
934
935         /* memory client has gone idle */
936         tegra_dc_clear_bandwidth(dc);
937
938         if (dc->out_ops->idle)
939                 dc->out_ops->idle(dc);
940
941         mutex_unlock(&dc->lock);
942 }
943
944 /* return an arbitrarily large number if count overflow occurs.
945  * make it a nice base-10 number to show up in stats output */
946 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
947 {
948         unsigned count = tegra_dc_readl(dc, reg);
949         tegra_dc_writel(dc, 0, reg);
950         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
951 }
952
953 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
954 {
955         u32 val;
956         int i;
957
958         dc->stats.underflows++;
959         if (dc->underflow_mask & WIN_A_UF_INT) {
960                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
961                         DC_WINBUF_AD_UFLOW_STATUS);
962                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
963         }
964         if (dc->underflow_mask & WIN_B_UF_INT) {
965                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
966                         DC_WINBUF_BD_UFLOW_STATUS);
967                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
968         }
969         if (dc->underflow_mask & WIN_C_UF_INT) {
970                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
971                         DC_WINBUF_CD_UFLOW_STATUS);
972                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
973         }
974
975         /* Check for any underflow reset conditions */
976         for (i = 0; i < DC_N_WINDOWS; i++) {
977                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
978                         dc->windows[i].underflows++;
979
980 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
981                         if (dc->windows[i].underflows > 4) {
982                                 schedule_work(&dc->reset_work);
983                                 /* reset counter */
984                                 dc->windows[i].underflows = 0;
985                                 trace_printk("%s:Reset work scheduled for "
986                                                 "window %c\n",
987                                                 dc->ndev->name, (65 + i));
988                         }
989 #endif
990 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
991                         if (dc->windows[i].underflows > 4) {
992                                 trace_printk("%s:window %c in underflow state."
993                                         " enable UF_LINE_FLUSH to clear up\n",
994                                         dc->ndev->name, (65 + i));
995                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
996                                                 DC_DISP_DISP_MISC_CONTROL);
997                                 tegra_dc_writel(dc, GENERAL_UPDATE,
998                                                 DC_CMD_STATE_CONTROL);
999                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1000                                                 DC_CMD_STATE_CONTROL);
1001
1002                                 tegra_dc_writel(dc, 0,
1003                                                 DC_DISP_DISP_MISC_CONTROL);
1004                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1005                                                 DC_CMD_STATE_CONTROL);
1006                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1007                                                 DC_CMD_STATE_CONTROL);
1008                         }
1009 #endif
1010                 } else {
1011                         dc->windows[i].underflows = 0;
1012                 }
1013         }
1014
1015         /* Clear the underflow mask now that we've checked it. */
1016         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1017         dc->underflow_mask = 0;
1018         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1019         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1020         print_underflow_info(dc);
1021 }
1022
1023 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1024 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1025 {
1026         if (status & V_BLANK_INT) {
1027                 /* Sync up windows. */
1028                 tegra_dc_trigger_windows(dc);
1029
1030                 /* Schedule any additional bottom-half vblank actvities. */
1031                 queue_work(system_freezable_wq, &dc->vblank_work);
1032         }
1033
1034         if (status & FRAME_END_INT) {
1035                 /* Mark the frame_end as complete. */
1036                 if (!completion_done(&dc->frame_end_complete))
1037                         complete(&dc->frame_end_complete);
1038         }
1039 }
1040
1041 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1042 {
1043         /* Schedule any additional bottom-half vblank actvities. */
1044         if (status & V_BLANK_INT)
1045                 queue_work(system_freezable_wq, &dc->vblank_work);
1046
1047         if (status & FRAME_END_INT) {
1048                 /* Mark the frame_end as complete. */
1049                 if (!completion_done(&dc->frame_end_complete))
1050                         complete(&dc->frame_end_complete);
1051
1052                 tegra_dc_trigger_windows(dc);
1053         }
1054 }
1055 #endif
1056
1057 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1058 {
1059 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1060         struct tegra_dc *dc = ptr;
1061         unsigned long status;
1062         unsigned long underflow_mask;
1063         u32 val;
1064
1065         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1066                 WARN(1, "IRQ when DC not powered!\n");
1067                 tegra_dc_io_start(dc);
1068                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1069                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1070                 tegra_dc_io_end(dc);
1071                 return IRQ_HANDLED;
1072         }
1073
1074         /* clear all status flags except underflow, save those for the worker */
1075         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1076         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1077         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1078         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1079
1080         /*
1081          * Overlays can get thier internal state corrupted during and underflow
1082          * condition.  The only way to fix this state is to reset the DC.
1083          * if we get 4 consecutive frames with underflows, assume we're
1084          * hosed and reset.
1085          */
1086         underflow_mask = status & ALL_UF_INT;
1087
1088         /* Check underflow */
1089         if (underflow_mask) {
1090                 dc->underflow_mask |= underflow_mask;
1091                 schedule_delayed_work(&dc->underflow_work,
1092                         msecs_to_jiffies(1));
1093         }
1094
1095         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1096                 tegra_dc_one_shot_irq(dc, status);
1097         else
1098                 tegra_dc_continuous_irq(dc, status);
1099
1100         return IRQ_HANDLED;
1101 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1102         return IRQ_NONE;
1103 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1104 }
1105
1106 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1107 {
1108         u32 color_control;
1109
1110         switch (dc->out->depth) {
1111         case 3:
1112                 color_control = BASE_COLOR_SIZE111;
1113                 break;
1114
1115         case 6:
1116                 color_control = BASE_COLOR_SIZE222;
1117                 break;
1118
1119         case 8:
1120                 color_control = BASE_COLOR_SIZE332;
1121                 break;
1122
1123         case 9:
1124                 color_control = BASE_COLOR_SIZE333;
1125                 break;
1126
1127         case 12:
1128                 color_control = BASE_COLOR_SIZE444;
1129                 break;
1130
1131         case 15:
1132                 color_control = BASE_COLOR_SIZE555;
1133                 break;
1134
1135         case 16:
1136                 color_control = BASE_COLOR_SIZE565;
1137                 break;
1138
1139         case 18:
1140                 color_control = BASE_COLOR_SIZE666;
1141                 break;
1142
1143         default:
1144                 color_control = BASE_COLOR_SIZE888;
1145                 break;
1146         }
1147
1148         switch (dc->out->dither) {
1149         case TEGRA_DC_DISABLE_DITHER:
1150                 color_control |= DITHER_CONTROL_DISABLE;
1151                 break;
1152         case TEGRA_DC_ORDERED_DITHER:
1153                 color_control |= DITHER_CONTROL_ORDERED;
1154                 break;
1155         case TEGRA_DC_ERRDIFF_DITHER:
1156                 /* The line buffer for error-diffusion dither is limited
1157                  * to 1280 pixels per line. This limits the maximum
1158                  * horizontal active area size to 1280 pixels when error
1159                  * diffusion is enabled.
1160                  */
1161                 BUG_ON(dc->mode.h_active > 1280);
1162                 color_control |= DITHER_CONTROL_ERRDIFF;
1163                 break;
1164         }
1165
1166         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1167 }
1168
1169 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1170 {
1171         u32 syncpt_id;
1172
1173         switch (dc->ndev->id) {
1174         case 0:
1175                 switch (idx) {
1176                 case 0:
1177                         syncpt_id = NVSYNCPT_DISP0_A;
1178                         break;
1179                 case 1:
1180                         syncpt_id = NVSYNCPT_DISP0_B;
1181                         break;
1182                 case 2:
1183                         syncpt_id = NVSYNCPT_DISP0_C;
1184                         break;
1185                 default:
1186                         BUG();
1187                         break;
1188                 }
1189                 break;
1190         case 1:
1191                 switch (idx) {
1192                 case 0:
1193                         syncpt_id = NVSYNCPT_DISP1_A;
1194                         break;
1195                 case 1:
1196                         syncpt_id = NVSYNCPT_DISP1_B;
1197                         break;
1198                 case 2:
1199                         syncpt_id = NVSYNCPT_DISP1_C;
1200                         break;
1201                 default:
1202                         BUG();
1203                         break;
1204                 }
1205                 break;
1206         default:
1207                 BUG();
1208                 break;
1209         }
1210
1211         return syncpt_id;
1212 }
1213
1214 static int tegra_dc_init(struct tegra_dc *dc)
1215 {
1216         int i;
1217
1218         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1219         if (dc->ndev->id == 0) {
1220                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1221                                       TEGRA_MC_PRIO_MED);
1222                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1223                                       TEGRA_MC_PRIO_MED);
1224                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1225                                       TEGRA_MC_PRIO_MED);
1226                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1227                                       TEGRA_MC_PRIO_MED);
1228                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1229                                       TEGRA_MC_PRIO_HIGH);
1230         } else if (dc->ndev->id == 1) {
1231                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1232                                       TEGRA_MC_PRIO_MED);
1233                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1234                                       TEGRA_MC_PRIO_MED);
1235                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1236                                       TEGRA_MC_PRIO_MED);
1237                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1238                                       TEGRA_MC_PRIO_MED);
1239                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1240                                       TEGRA_MC_PRIO_HIGH);
1241         }
1242         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1243                         DC_CMD_CONT_SYNCPT_VSYNC);
1244         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1245         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1246         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1247         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1248 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1249         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1250 #endif
1251         /* enable interrupts for vblank, frame_end and underflows */
1252         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1253                 DC_CMD_INT_ENABLE);
1254         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1255
1256         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1257
1258         tegra_dc_set_color_control(dc);
1259         for (i = 0; i < DC_N_WINDOWS; i++) {
1260                 struct tegra_dc_win *win = &dc->windows[i];
1261                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1262                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1263                 tegra_dc_set_csc(dc, &win->csc);
1264                 tegra_dc_set_lut(dc, win);
1265                 tegra_dc_set_scaling_filter(dc);
1266         }
1267
1268
1269         for (i = 0; i < dc->n_windows; i++) {
1270                 u32 syncpt = get_syncpt(dc, i);
1271
1272                 dc->syncpt[i].id = syncpt;
1273
1274                 dc->syncpt[i].min = dc->syncpt[i].max =
1275                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1276         }
1277
1278         print_mode_info(dc, dc->mode);
1279
1280         if (dc->mode.pclk)
1281                 if (tegra_dc_program_mode(dc, &dc->mode))
1282                         return -EINVAL;
1283
1284         /* Initialize SD AFTER the modeset.
1285            nvsd_init handles the sd_settings = NULL case. */
1286         nvsd_init(dc, dc->out->sd_settings);
1287
1288         return 0;
1289 }
1290
1291 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1292 {
1293         int failed_init = 0;
1294
1295         if (dc->out->enable)
1296                 dc->out->enable();
1297
1298         tegra_dc_setup_clk(dc, dc->clk);
1299         tegra_dc_clk_enable(dc);
1300
1301         /* do not accept interrupts during initialization */
1302         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1303
1304         enable_dc_irq(dc->irq);
1305
1306         failed_init = tegra_dc_init(dc);
1307         if (failed_init) {
1308                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1309                 disable_irq(dc->irq);
1310                 tegra_dc_clear_bandwidth(dc);
1311                 tegra_dc_clk_disable(dc);
1312                 if (dc->out && dc->out->disable)
1313                         dc->out->disable();
1314                 return false;
1315         }
1316
1317         if (dc->out_ops && dc->out_ops->enable)
1318                 dc->out_ops->enable(dc);
1319
1320         /* force a full blending update */
1321         dc->blend.z[0] = -1;
1322
1323         tegra_dc_ext_enable(dc->ext);
1324
1325         trace_printk("%s:enable\n", dc->ndev->name);
1326
1327         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1328         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1329
1330         if (dc->out->postpoweron)
1331                 dc->out->postpoweron();
1332
1333         return true;
1334 }
1335
1336 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1337 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1338 {
1339         bool ret = true;
1340
1341         if (dc->out->enable)
1342                 dc->out->enable();
1343
1344         tegra_dc_setup_clk(dc, dc->clk);
1345         tegra_dc_clk_enable(dc);
1346
1347         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1348                 mutex_lock(&tegra_dcs[1]->lock);
1349                 disable_irq(tegra_dcs[1]->irq);
1350         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1351                 mutex_lock(&tegra_dcs[0]->lock);
1352                 disable_irq(tegra_dcs[0]->irq);
1353         }
1354
1355         msleep(5);
1356         tegra_periph_reset_assert(dc->clk);
1357         msleep(2);
1358 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1359         tegra_periph_reset_deassert(dc->clk);
1360         msleep(1);
1361 #endif
1362
1363         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1364                 enable_dc_irq(tegra_dcs[1]->irq);
1365                 mutex_unlock(&tegra_dcs[1]->lock);
1366         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1367                 enable_dc_irq(tegra_dcs[0]->irq);
1368                 mutex_unlock(&tegra_dcs[0]->lock);
1369         }
1370
1371         enable_dc_irq(dc->irq);
1372
1373         if (tegra_dc_init(dc)) {
1374                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1375                 ret = false;
1376         }
1377
1378         if (dc->out_ops && dc->out_ops->enable)
1379                 dc->out_ops->enable(dc);
1380
1381         if (dc->out->postpoweron)
1382                 dc->out->postpoweron();
1383
1384         /* force a full blending update */
1385         dc->blend.z[0] = -1;
1386
1387         tegra_dc_ext_enable(dc->ext);
1388
1389         if (!ret) {
1390                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1391                 _tegra_dc_controller_disable(dc);
1392         }
1393
1394         trace_printk("%s:reset enable\n", dc->ndev->name);
1395         return ret;
1396 }
1397 #endif
1398
1399 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1400 {
1401         if (dc->mode.pclk == 0) {
1402                 switch (dc->out->type) {
1403                 case TEGRA_DC_OUT_HDMI:
1404                 /* DC enable called but no videomode is loaded.
1405                      Check if HDMI is connected, then set fallback mdoe */
1406                 if (tegra_dc_hpd(dc)) {
1407                         return tegra_dc_set_fb_mode(dc,
1408                                         &tegra_dc_hdmi_fallback_mode, 0);
1409                 } else
1410                         return false;
1411
1412                 break;
1413
1414                 /* Do nothing for other outputs for now */
1415                 case TEGRA_DC_OUT_RGB:
1416
1417                 case TEGRA_DC_OUT_DSI:
1418
1419                 default:
1420                         return false;
1421                 }
1422         }
1423
1424         return false;
1425 }
1426
1427 static bool _tegra_dc_enable(struct tegra_dc *dc)
1428 {
1429         if (dc->mode.pclk == 0)
1430                 return false;
1431
1432         if (!dc->out)
1433                 return false;
1434
1435         tegra_dc_io_start(dc);
1436
1437         if (!_tegra_dc_controller_enable(dc)) {
1438                 tegra_dc_io_end(dc);
1439                 return false;
1440         }
1441         return true;
1442 }
1443
1444 void tegra_dc_enable(struct tegra_dc *dc)
1445 {
1446         mutex_lock(&dc->lock);
1447
1448         if (!dc->enabled)
1449                 dc->enabled = _tegra_dc_enable(dc);
1450
1451         mutex_unlock(&dc->lock);
1452         print_mode_info(dc, dc->mode);
1453 }
1454
1455 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1456 {
1457         unsigned i;
1458
1459         if (dc->out && dc->out->prepoweroff)
1460                 dc->out->prepoweroff();
1461
1462         if (dc->out_ops && dc->out_ops->disable)
1463                 dc->out_ops->disable(dc);
1464
1465         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1466         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1467         disable_irq(dc->irq);
1468
1469         tegra_dc_clear_bandwidth(dc);
1470         tegra_dc_clk_disable(dc);
1471
1472         if (dc->out && dc->out->disable)
1473                 dc->out->disable();
1474
1475         for (i = 0; i < dc->n_windows; i++) {
1476                 struct tegra_dc_win *w = &dc->windows[i];
1477
1478                 /* reset window bandwidth */
1479                 w->bandwidth = 0;
1480                 w->new_bandwidth = 0;
1481
1482                 /* disable windows */
1483                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1484
1485                 /* flush any pending syncpt waits */
1486                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1487                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1488                                 dc->syncpt[i].id);
1489                         dc->syncpt[i].min++;
1490                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1491                 }
1492         }
1493         trace_printk("%s:disabled\n", dc->ndev->name);
1494 }
1495
1496 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1497 {
1498 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1499         u32 val;
1500         if (dc->enabled)  {
1501                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1502                 if (enable)
1503                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1504                 else
1505                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1506                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1507         }
1508 #endif
1509 }
1510
1511 bool tegra_dc_stats_get(struct tegra_dc *dc)
1512 {
1513 #if 0 /* right now it is always enabled */
1514         u32 val;
1515         bool res;
1516
1517         if (dc->enabled)  {
1518                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1519                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1520         } else {
1521                 res = false;
1522         }
1523
1524         return res;
1525 #endif
1526         return true;
1527 }
1528
1529 /* make the screen blank by disabling all windows */
1530 void tegra_dc_blank(struct tegra_dc *dc)
1531 {
1532         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1533         unsigned i;
1534
1535         for (i = 0; i < DC_N_WINDOWS; i++) {
1536                 dcwins[i] = tegra_dc_get_window(dc, i);
1537                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1538         }
1539
1540         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1541         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1542 }
1543
1544 static void _tegra_dc_disable(struct tegra_dc *dc)
1545 {
1546         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1547                 mutex_lock(&dc->one_shot_lock);
1548                 cancel_delayed_work_sync(&dc->one_shot_work);
1549         }
1550
1551         tegra_dc_hold_dc_out(dc);
1552
1553         _tegra_dc_controller_disable(dc);
1554         tegra_dc_io_end(dc);
1555
1556         tegra_dc_release_dc_out(dc);
1557
1558         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1559                 mutex_unlock(&dc->one_shot_lock);
1560 }
1561
1562 void tegra_dc_disable(struct tegra_dc *dc)
1563 {
1564         tegra_dc_ext_disable(dc->ext);
1565
1566         /* it's important that new underflow work isn't scheduled before the
1567          * lock is acquired. */
1568         cancel_delayed_work_sync(&dc->underflow_work);
1569
1570         mutex_lock(&dc->lock);
1571
1572         if (dc->enabled) {
1573                 dc->enabled = false;
1574
1575                 if (!dc->suspended)
1576                         _tegra_dc_disable(dc);
1577         }
1578
1579 #ifdef CONFIG_SWITCH
1580         switch_set_state(&dc->modeset_switch, 0);
1581 #endif
1582
1583         mutex_unlock(&dc->lock);
1584         print_mode_info(dc, dc->mode);
1585 }
1586
1587 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1588 static void tegra_dc_reset_worker(struct work_struct *work)
1589 {
1590         struct tegra_dc *dc =
1591                 container_of(work, struct tegra_dc, reset_work);
1592
1593         unsigned long val = 0;
1594
1595         mutex_lock(&shared_lock);
1596
1597         dev_warn(&dc->ndev->dev,
1598                 "overlay stuck in underflow state.  resetting.\n");
1599
1600         tegra_dc_ext_disable(dc->ext);
1601
1602         mutex_lock(&dc->lock);
1603
1604         if (dc->enabled == false)
1605                 goto unlock;
1606
1607         dc->enabled = false;
1608
1609         /*
1610          * off host read bus
1611          */
1612         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1613         val &= ~(0x00000100);
1614         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1615
1616         /*
1617          * set DC to STOP mode
1618          */
1619         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1620
1621         msleep(10);
1622
1623         _tegra_dc_controller_disable(dc);
1624
1625         /* _tegra_dc_controller_reset_enable deasserts reset */
1626         _tegra_dc_controller_reset_enable(dc);
1627
1628         dc->enabled = true;
1629
1630         /* reopen host read bus */
1631         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1632         val &= ~(0x00000100);
1633         val |= 0x100;
1634         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1635
1636 unlock:
1637         mutex_unlock(&dc->lock);
1638         mutex_unlock(&shared_lock);
1639         trace_printk("%s:reset complete\n", dc->ndev->name);
1640 }
1641 #endif
1642
1643 static void tegra_dc_underflow_worker(struct work_struct *work)
1644 {
1645         struct tegra_dc *dc = container_of(
1646                 to_delayed_work(work), struct tegra_dc, underflow_work);
1647
1648         mutex_lock(&dc->lock);
1649         tegra_dc_hold_dc_out(dc);
1650
1651         if (dc->enabled) {
1652                 tegra_dc_underflow_handler(dc);
1653         }
1654         tegra_dc_release_dc_out(dc);
1655         mutex_unlock(&dc->lock);
1656 }
1657
1658 #ifdef CONFIG_SWITCH
1659 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1660 {
1661         struct tegra_dc *dc =
1662                 container_of(sdev, struct tegra_dc, modeset_switch);
1663
1664         if (!sdev->state)
1665                 return sprintf(buf, "offline\n");
1666
1667         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1668 }
1669 #endif
1670
1671 static int tegra_dc_probe(struct nvhost_device *ndev,
1672         struct nvhost_device_id *id_table)
1673 {
1674         struct tegra_dc *dc;
1675         struct tegra_dc_mode *mode;
1676         struct clk *clk;
1677         struct clk *emc_clk;
1678         struct resource *res;
1679         struct resource *base_res;
1680         struct resource *fb_mem = NULL;
1681         int ret = 0;
1682         void __iomem *base;
1683         int irq;
1684         int i;
1685
1686         if (!ndev->dev.platform_data) {
1687                 dev_err(&ndev->dev, "no platform data\n");
1688                 return -ENOENT;
1689         }
1690
1691         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1692         if (!dc) {
1693                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1694                 return -ENOMEM;
1695         }
1696
1697         irq = nvhost_get_irq_byname(ndev, "irq");
1698         if (irq <= 0) {
1699                 dev_err(&ndev->dev, "no irq\n");
1700                 ret = -ENOENT;
1701                 goto err_free;
1702         }
1703
1704         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1705         if (!res) {
1706                 dev_err(&ndev->dev, "no mem resource\n");
1707                 ret = -ENOENT;
1708                 goto err_free;
1709         }
1710
1711         base_res = request_mem_region(res->start, resource_size(res),
1712                 ndev->name);
1713         if (!base_res) {
1714                 dev_err(&ndev->dev, "request_mem_region failed\n");
1715                 ret = -EBUSY;
1716                 goto err_free;
1717         }
1718
1719         base = ioremap(res->start, resource_size(res));
1720         if (!base) {
1721                 dev_err(&ndev->dev, "registers can't be mapped\n");
1722                 ret = -EBUSY;
1723                 goto err_release_resource_reg;
1724         }
1725
1726         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1727
1728         clk = clk_get(&ndev->dev, NULL);
1729         if (IS_ERR_OR_NULL(clk)) {
1730                 dev_err(&ndev->dev, "can't get clock\n");
1731                 ret = -ENOENT;
1732                 goto err_iounmap_reg;
1733         }
1734
1735         emc_clk = clk_get(&ndev->dev, "emc");
1736         if (IS_ERR_OR_NULL(emc_clk)) {
1737                 dev_err(&ndev->dev, "can't get emc clock\n");
1738                 ret = -ENOENT;
1739                 goto err_put_clk;
1740         }
1741
1742         dc->clk = clk;
1743         dc->emc_clk = emc_clk;
1744         dc->shift_clk_div = 1;
1745         /* Initialize one shot work delay, it will be assigned by dsi
1746          * according to refresh rate later. */
1747         dc->one_shot_delay_ms = 40;
1748
1749         dc->base_res = base_res;
1750         dc->base = base;
1751         dc->irq = irq;
1752         dc->ndev = ndev;
1753         dc->pdata = ndev->dev.platform_data;
1754
1755         /*
1756          * The emc is a shared clock, it will be set based on
1757          * the requirements for each user on the bus.
1758          */
1759         dc->emc_clk_rate = 0;
1760
1761         mutex_init(&dc->lock);
1762         mutex_init(&dc->one_shot_lock);
1763         init_completion(&dc->frame_end_complete);
1764         init_waitqueue_head(&dc->wq);
1765 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1766         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1767 #endif
1768         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1769         dc->vblank_ref_count = 0;
1770         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
1771         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
1772
1773         tegra_dc_init_lut_defaults(&dc->fb_lut);
1774
1775         dc->n_windows = DC_N_WINDOWS;
1776         for (i = 0; i < dc->n_windows; i++) {
1777                 struct tegra_dc_win *win = &dc->windows[i];
1778                 win->idx = i;
1779                 win->dc = dc;
1780                 tegra_dc_init_csc_defaults(&win->csc);
1781                 tegra_dc_init_lut_defaults(&win->lut);
1782         }
1783
1784         ret = tegra_dc_set(dc, ndev->id);
1785         if (ret < 0) {
1786                 dev_err(&ndev->dev, "can't add dc\n");
1787                 goto err_free_irq;
1788         }
1789
1790         nvhost_set_drvdata(ndev, dc);
1791
1792 #ifdef CONFIG_SWITCH
1793         dc->modeset_switch.name = dev_name(&ndev->dev);
1794         dc->modeset_switch.state = 0;
1795         dc->modeset_switch.print_state = switch_modeset_print_mode;
1796         switch_dev_register(&dc->modeset_switch);
1797 #endif
1798
1799         tegra_dc_feature_register(dc);
1800
1801         if (dc->pdata->default_out)
1802                 tegra_dc_set_out(dc, dc->pdata->default_out);
1803         else
1804                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1805
1806         dc->vblank_syncpt = (dc->ndev->id == 0) ?
1807                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
1808
1809         dc->ext = tegra_dc_ext_register(ndev, dc);
1810         if (IS_ERR_OR_NULL(dc->ext)) {
1811                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
1812                 dc->ext = NULL;
1813         }
1814
1815         mutex_lock(&dc->lock);
1816         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
1817                 _tegra_dc_set_default_videomode(dc);
1818                 dc->enabled = _tegra_dc_enable(dc);
1819         }
1820         mutex_unlock(&dc->lock);
1821
1822         /* interrupt handler must be registered before tegra_fb_register() */
1823         if (request_irq(irq, tegra_dc_irq, 0,
1824                         dev_name(&ndev->dev), dc)) {
1825                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1826                 ret = -EBUSY;
1827                 goto err_put_emc_clk;
1828         }
1829
1830         tegra_dc_create_debugfs(dc);
1831
1832         dev_info(&ndev->dev, "probed\n");
1833
1834         if (dc->pdata->fb) {
1835                 if (dc->pdata->fb->bits_per_pixel == -1) {
1836                         unsigned long fmt;
1837                         tegra_dc_writel(dc,
1838                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1839                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1840
1841                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1842                         dc->pdata->fb->bits_per_pixel =
1843                                 tegra_dc_fmt_bpp(fmt);
1844                 }
1845
1846                 mode = tegra_dc_get_override_mode(dc);
1847                 if (mode) {
1848                         dc->pdata->fb->xres = mode->h_active;
1849                         dc->pdata->fb->yres = mode->v_active;
1850                 }
1851
1852                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1853                 if (IS_ERR_OR_NULL(dc->fb))
1854                         dc->fb = NULL;
1855         }
1856
1857         if (dc->out && dc->out->hotplug_init)
1858                 dc->out->hotplug_init();
1859
1860         if (dc->out_ops && dc->out_ops->detect)
1861                 dc->out_ops->detect(dc);
1862         else
1863                 dc->connected = true;
1864
1865         tegra_dc_create_sysfs(&dc->ndev->dev);
1866
1867         return 0;
1868
1869 err_free_irq:
1870         free_irq(irq, dc);
1871 err_put_emc_clk:
1872         clk_put(emc_clk);
1873 err_put_clk:
1874         clk_put(clk);
1875 err_iounmap_reg:
1876         iounmap(base);
1877         if (fb_mem)
1878                 release_resource(fb_mem);
1879 err_release_resource_reg:
1880         release_resource(base_res);
1881 err_free:
1882         kfree(dc);
1883
1884         return ret;
1885 }
1886
1887 static int tegra_dc_remove(struct nvhost_device *ndev)
1888 {
1889         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1890
1891         tegra_dc_remove_sysfs(&dc->ndev->dev);
1892         tegra_dc_remove_debugfs(dc);
1893
1894         if (dc->fb) {
1895                 tegra_fb_unregister(dc->fb);
1896                 if (dc->fb_mem)
1897                         release_resource(dc->fb_mem);
1898         }
1899
1900         tegra_dc_ext_disable(dc->ext);
1901
1902         if (dc->ext)
1903                 tegra_dc_ext_unregister(dc->ext);
1904
1905         if (dc->enabled)
1906                 _tegra_dc_disable(dc);
1907
1908 #ifdef CONFIG_SWITCH
1909         switch_dev_unregister(&dc->modeset_switch);
1910 #endif
1911         free_irq(dc->irq, dc);
1912         clk_put(dc->emc_clk);
1913         clk_put(dc->clk);
1914         iounmap(dc->base);
1915         if (dc->fb_mem)
1916                 release_resource(dc->base_res);
1917         kfree(dc);
1918         tegra_dc_set(NULL, ndev->id);
1919         return 0;
1920 }
1921
1922 #ifdef CONFIG_PM
1923 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
1924 {
1925         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1926
1927         trace_printk("%s:suspend\n", dc->ndev->name);
1928         dev_info(&ndev->dev, "suspend\n");
1929
1930         tegra_dc_ext_disable(dc->ext);
1931
1932         mutex_lock(&dc->lock);
1933
1934         if (dc->out_ops && dc->out_ops->suspend)
1935                 dc->out_ops->suspend(dc);
1936
1937         if (dc->enabled) {
1938                 _tegra_dc_disable(dc);
1939
1940                 dc->suspended = true;
1941         }
1942
1943         if (dc->out && dc->out->postsuspend) {
1944                 dc->out->postsuspend();
1945                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
1946                         /*
1947                          * avoid resume event due to voltage falling
1948                          */
1949                         msleep(100);
1950         }
1951
1952         mutex_unlock(&dc->lock);
1953
1954         return 0;
1955 }
1956
1957 static int tegra_dc_resume(struct nvhost_device *ndev)
1958 {
1959         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1960
1961         trace_printk("%s:resume\n", dc->ndev->name);
1962         dev_info(&ndev->dev, "resume\n");
1963
1964         mutex_lock(&dc->lock);
1965         dc->suspended = false;
1966
1967         if (dc->enabled) {
1968                 _tegra_dc_set_default_videomode(dc);
1969                 _tegra_dc_enable(dc);
1970         }
1971
1972         if (dc->out && dc->out->hotplug_init)
1973                 dc->out->hotplug_init();
1974
1975         if (dc->out_ops && dc->out_ops->resume)
1976                 dc->out_ops->resume(dc);
1977         mutex_unlock(&dc->lock);
1978
1979         return 0;
1980 }
1981
1982 #endif /* CONFIG_PM */
1983
1984 static void tegra_dc_shutdown(struct nvhost_device *ndev)
1985 {
1986         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1987
1988         if (!dc || !dc->enabled)
1989                 return;
1990
1991         tegra_dc_blank(dc);
1992         tegra_dc_disable(dc);
1993 }
1994
1995 extern int suspend_set(const char *val, struct kernel_param *kp)
1996 {
1997         if (!strcmp(val, "dump"))
1998                 dump_regs(tegra_dcs[0]);
1999 #ifdef CONFIG_PM
2000         else if (!strcmp(val, "suspend"))
2001                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2002         else if (!strcmp(val, "resume"))
2003                 tegra_dc_resume(tegra_dcs[0]->ndev);
2004 #endif
2005
2006         return 0;
2007 }
2008
2009 extern int suspend_get(char *buffer, struct kernel_param *kp)
2010 {
2011         return 0;
2012 }
2013
2014 int suspend;
2015
2016 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2017
2018 struct nvhost_driver tegra_dc_driver = {
2019         .driver = {
2020                 .name = "tegradc",
2021                 .owner = THIS_MODULE,
2022         },
2023         .probe = tegra_dc_probe,
2024         .remove = tegra_dc_remove,
2025 #ifdef CONFIG_PM
2026         .suspend = tegra_dc_suspend,
2027         .resume = tegra_dc_resume,
2028 #endif
2029         .shutdown = tegra_dc_shutdown,
2030 };
2031
2032 #ifndef MODULE
2033 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2034 {
2035         int i, params[11];
2036         char *p;
2037
2038         for (i = 0; i < ARRAY_SIZE(params); i++) {
2039                 if ((p = strsep(&options, ",")) != NULL) {
2040                         if (*p)
2041                                 params[i] = simple_strtoul(p, &p, 10);
2042                 } else
2043                         return -EINVAL;
2044         }
2045
2046         if ((mode->pclk = params[0]) == 0)
2047                 return -EINVAL;
2048
2049         mode->h_active      = params[1];
2050         mode->v_active      = params[2];
2051         mode->h_ref_to_sync = params[3];
2052         mode->v_ref_to_sync = params[4];
2053         mode->h_sync_width  = params[5];
2054         mode->v_sync_width  = params[6];
2055         mode->h_back_porch  = params[7];
2056         mode->v_back_porch  = params[8];
2057         mode->h_front_porch = params[9];
2058         mode->v_front_porch = params[10];
2059
2060         return 0;
2061 }
2062
2063 static int __init tegra_dc_mode_override(char *str)
2064 {
2065         char *p = str, *options;
2066
2067         if (!p || !*p)
2068                 return -EINVAL;
2069
2070         p = strstr(str, "hdmi:");
2071         if (p) {
2072                 p += 5;
2073                 options = strsep(&p, ";");
2074                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2075                         return -EINVAL;
2076         }
2077
2078         p = strstr(str, "rgb:");
2079         if (p) {
2080                 p += 4;
2081                 options = strsep(&p, ";");
2082                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2083                         return -EINVAL;
2084         }
2085
2086         p = strstr(str, "dsi:");
2087         if (p) {
2088                 p += 4;
2089                 options = strsep(&p, ";");
2090                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2091                         return -EINVAL;
2092         }
2093
2094         return 0;
2095 }
2096
2097 __setup("disp_params=", tegra_dc_mode_override);
2098 #endif
2099
2100 static int __init tegra_dc_module_init(void)
2101 {
2102         int ret = tegra_dc_ext_module_init();
2103         if (ret)
2104                 return ret;
2105         return nvhost_driver_register(&tegra_dc_driver);
2106 }
2107
2108 static void __exit tegra_dc_module_exit(void)
2109 {
2110         nvhost_driver_unregister(&tegra_dc_driver);
2111         tegra_dc_ext_module_exit();
2112 }
2113
2114 module_exit(tegra_dc_module_exit);
2115 module_init(tegra_dc_module_init);