HACK: handle DC IRQ when off gracefully
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/switch.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39
40 #include <mach/clk.h>
41 #include <mach/dc.h>
42 #include <mach/fb.h>
43 #include <mach/mc.h>
44 #include <linux/nvhost.h>
45 #include <mach/latency_allowance.h>
46
47 #include "dc_reg.h"
48 #include "dc_priv.h"
49 #include "overlay.h"
50 #include "nvsd.h"
51
52 #define TEGRA_CRC_LATCHED_DELAY         34
53
54 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
55 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
56 #else
57 /* ignore underflows when on simulation and fpga platform */
58 #define ALL_UF_INT (0)
59 #endif
60
61 static int no_vsync;
62
63 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
64
65 static int use_dynamic_emc = 1;
66
67 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
68
69 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
70
71 DEFINE_MUTEX(tegra_dc_lock);
72 DEFINE_MUTEX(shared_lock);
73
74 static const struct {
75         bool h;
76         bool v;
77 } can_filter[] = {
78         /* Window A has no filtering */
79         { false, false },
80         /* Window B has both H and V filtering */
81         { true,  true  },
82         /* Window C has only H filtering */
83         { false, true  },
84 };
85 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
86 {
87         return can_filter[win->idx].v &&
88                 win->h.full != dfixed_const(win->out_h);
89 }
90 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
91 {
92         return can_filter[win->idx].h &&
93                 win->w.full != dfixed_const(win->out_w);
94 }
95
96 static inline int tegra_dc_fmt_bpp(int fmt)
97 {
98         switch (fmt) {
99         case TEGRA_WIN_FMT_P1:
100                 return 1;
101
102         case TEGRA_WIN_FMT_P2:
103                 return 2;
104
105         case TEGRA_WIN_FMT_P4:
106                 return 4;
107
108         case TEGRA_WIN_FMT_P8:
109                 return 8;
110
111         case TEGRA_WIN_FMT_B4G4R4A4:
112         case TEGRA_WIN_FMT_B5G5R5A:
113         case TEGRA_WIN_FMT_B5G6R5:
114         case TEGRA_WIN_FMT_AB5G5R5:
115                 return 16;
116
117         case TEGRA_WIN_FMT_B8G8R8A8:
118         case TEGRA_WIN_FMT_R8G8B8A8:
119         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
120         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
121                 return 32;
122
123         /* for planar formats, size of the Y plane, 8bit */
124         case TEGRA_WIN_FMT_YCbCr420P:
125         case TEGRA_WIN_FMT_YUV420P:
126         case TEGRA_WIN_FMT_YCbCr422P:
127         case TEGRA_WIN_FMT_YUV422P:
128                 return 8;
129
130         case TEGRA_WIN_FMT_YCbCr422:
131         case TEGRA_WIN_FMT_YUV422:
132         case TEGRA_WIN_FMT_YCbCr422R:
133         case TEGRA_WIN_FMT_YUV422R:
134         case TEGRA_WIN_FMT_YCbCr422RA:
135         case TEGRA_WIN_FMT_YUV422RA:
136                 /* FIXME: need to know the bpp of these formats */
137                 return 0;
138         }
139         return 0;
140 }
141
142 static inline bool tegra_dc_is_yuv_planar(int fmt)
143 {
144         switch (fmt) {
145         case TEGRA_WIN_FMT_YUV420P:
146         case TEGRA_WIN_FMT_YCbCr420P:
147         case TEGRA_WIN_FMT_YCbCr422P:
148         case TEGRA_WIN_FMT_YUV422P:
149                 return true;
150         }
151         return false;
152 }
153
154 #define DUMP_REG(a) do {                        \
155         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
156                  #a, a, tegra_dc_readl(dc, a));               \
157         print(data, buff);                                    \
158         } while (0)
159
160 static void _dump_regs(struct tegra_dc *dc, void *data,
161                        void (* print)(void *data, const char *str))
162 {
163         int i;
164         char buff[256];
165
166         tegra_dc_io_start(dc);
167         clk_enable(dc->clk);
168
169         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
170         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
171         DUMP_REG(DC_CMD_SIGNAL_RAISE);
172         DUMP_REG(DC_CMD_INT_STATUS);
173         DUMP_REG(DC_CMD_INT_MASK);
174         DUMP_REG(DC_CMD_INT_ENABLE);
175         DUMP_REG(DC_CMD_INT_TYPE);
176         DUMP_REG(DC_CMD_INT_POLARITY);
177         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
178         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
179         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
180         DUMP_REG(DC_CMD_STATE_ACCESS);
181         DUMP_REG(DC_CMD_STATE_CONTROL);
182         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
183         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
184
185         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
186         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
187         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
188         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
189         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
190         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
191         DUMP_REG(DC_DISP_REF_TO_SYNC);
192         DUMP_REG(DC_DISP_SYNC_WIDTH);
193         DUMP_REG(DC_DISP_BACK_PORCH);
194         DUMP_REG(DC_DISP_DISP_ACTIVE);
195         DUMP_REG(DC_DISP_FRONT_PORCH);
196         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
197         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
198         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
199         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
200         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
201         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
202         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
203         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
204         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
205         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
206         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
211         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
212         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
213         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
214         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
215         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
216         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
217         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
218         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
219         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
220         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
221         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
223         DUMP_REG(DC_DISP_M0_CONTROL);
224         DUMP_REG(DC_DISP_M1_CONTROL);
225         DUMP_REG(DC_DISP_DI_CONTROL);
226         DUMP_REG(DC_DISP_PP_CONTROL);
227         DUMP_REG(DC_DISP_PP_SELECT_A);
228         DUMP_REG(DC_DISP_PP_SELECT_B);
229         DUMP_REG(DC_DISP_PP_SELECT_C);
230         DUMP_REG(DC_DISP_PP_SELECT_D);
231         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
232         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
233         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
234         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
235         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
236         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
237         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
238         DUMP_REG(DC_DISP_BORDER_COLOR);
239         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
240         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
241         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
242         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
243         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
244         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
245         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
246         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
247         DUMP_REG(DC_DISP_CURSOR_POSITION);
248         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
249         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
250         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
251         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
252         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
253         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
254         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
255         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
256         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
257         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
258         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
259         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
260         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
261
262
263         for (i = 0; i < 3; i++) {
264                 print(data, "\n");
265                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
266                 print(data, buff);
267
268                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
269                                 DC_CMD_DISPLAY_WINDOW_HEADER);
270                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
271                 DUMP_REG(DC_WIN_WIN_OPTIONS);
272                 DUMP_REG(DC_WIN_BYTE_SWAP);
273                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
274                 DUMP_REG(DC_WIN_COLOR_DEPTH);
275                 DUMP_REG(DC_WIN_POSITION);
276                 DUMP_REG(DC_WIN_SIZE);
277                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
278                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
279                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
280                 DUMP_REG(DC_WIN_DDA_INCREMENT);
281                 DUMP_REG(DC_WIN_LINE_STRIDE);
282                 DUMP_REG(DC_WIN_BUF_STRIDE);
283                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
284                 DUMP_REG(DC_WIN_BLEND_NOKEY);
285                 DUMP_REG(DC_WIN_BLEND_1WIN);
286                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
287                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
288                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
289                 DUMP_REG(DC_WINBUF_START_ADDR);
290                 DUMP_REG(DC_WINBUF_START_ADDR_U);
291                 DUMP_REG(DC_WINBUF_START_ADDR_V);
292                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
293                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
294                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
295                 DUMP_REG(DC_WIN_CSC_YOF);
296                 DUMP_REG(DC_WIN_CSC_KYRGB);
297                 DUMP_REG(DC_WIN_CSC_KUR);
298                 DUMP_REG(DC_WIN_CSC_KVR);
299                 DUMP_REG(DC_WIN_CSC_KUG);
300                 DUMP_REG(DC_WIN_CSC_KVG);
301                 DUMP_REG(DC_WIN_CSC_KUB);
302                 DUMP_REG(DC_WIN_CSC_KVB);
303         }
304
305         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
306         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
307         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
308         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
309         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
310         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
311         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
312         DUMP_REG(DC_DISP_M1_CONTROL);
313         DUMP_REG(DC_COM_PM1_CONTROL);
314         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
315         DUMP_REG(DC_DISP_SD_CONTROL);
316
317         clk_disable(dc->clk);
318         tegra_dc_io_end(dc);
319 }
320
321 #undef DUMP_REG
322
323 #ifdef DEBUG
324 static void dump_regs_print(void *data, const char *str)
325 {
326         struct tegra_dc *dc = data;
327         dev_dbg(&dc->ndev->dev, "%s", str);
328 }
329
330 static void dump_regs(struct tegra_dc *dc)
331 {
332         _dump_regs(dc, dc, dump_regs_print);
333 }
334 #else /* !DEBUG */
335
336 static void dump_regs(struct tegra_dc *dc) {}
337
338 #endif /* DEBUG */
339
340 #ifdef CONFIG_DEBUG_FS
341
342 static void dbg_regs_print(void *data, const char *str)
343 {
344         struct seq_file *s = data;
345
346         seq_printf(s, "%s", str);
347 }
348
349 #undef DUMP_REG
350
351 static int dbg_dc_show(struct seq_file *s, void *unused)
352 {
353         struct tegra_dc *dc = s->private;
354
355         _dump_regs(dc, s, dbg_regs_print);
356
357         return 0;
358 }
359
360
361 static int dbg_dc_open(struct inode *inode, struct file *file)
362 {
363         return single_open(file, dbg_dc_show, inode->i_private);
364 }
365
366 static const struct file_operations regs_fops = {
367         .open           = dbg_dc_open,
368         .read           = seq_read,
369         .llseek         = seq_lseek,
370         .release        = single_release,
371 };
372
373 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
374 {
375         struct tegra_dc *dc = s->private;
376         struct tegra_dc_mode *m;
377
378         mutex_lock(&dc->lock);
379         m = &dc->mode;
380         seq_printf(s,
381                 "pclk: %d\n"
382                 "h_ref_to_sync: %d\n"
383                 "v_ref_to_sync: %d\n"
384                 "h_sync_width: %d\n"
385                 "v_sync_width: %d\n"
386                 "h_back_porch: %d\n"
387                 "v_back_porch: %d\n"
388                 "h_active: %d\n"
389                 "v_active: %d\n"
390                 "h_front_porch: %d\n"
391                 "v_front_porch: %d\n"
392                 "stereo_mode: %d\n",
393                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
394                 m->h_sync_width, m->v_sync_width,
395                 m->h_back_porch, m->v_back_porch,
396                 m->h_active, m->v_active,
397                 m->h_front_porch, m->v_front_porch,
398                 m->stereo_mode);
399         mutex_unlock(&dc->lock);
400         return 0;
401 }
402
403 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
404 {
405         return single_open(file, dbg_dc_mode_show, inode->i_private);
406 }
407
408 static const struct file_operations mode_fops = {
409         .open           = dbg_dc_mode_open,
410         .read           = seq_read,
411         .llseek         = seq_lseek,
412         .release        = single_release,
413 };
414
415 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
416 {
417         struct tegra_dc *dc = s->private;
418
419         mutex_lock(&dc->lock);
420         seq_printf(s,
421                 "underflows: %llu\n"
422                 "underflows_a: %llu\n"
423                 "underflows_b: %llu\n"
424                 "underflows_c: %llu\n",
425                 dc->stats.underflows,
426                 dc->stats.underflows_a,
427                 dc->stats.underflows_b,
428                 dc->stats.underflows_c);
429         mutex_unlock(&dc->lock);
430
431         return 0;
432 }
433
434 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
435 {
436         return single_open(file, dbg_dc_stats_show, inode->i_private);
437 }
438
439 static const struct file_operations stats_fops = {
440         .open           = dbg_dc_stats_open,
441         .read           = seq_read,
442         .llseek         = seq_lseek,
443         .release        = single_release,
444 };
445
446 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
447 {
448         if (dc->debugdir)
449                 debugfs_remove_recursive(dc->debugdir);
450         dc->debugdir = NULL;
451 }
452
453 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
454 {
455         struct dentry *retval;
456
457         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
458         if (!dc->debugdir)
459                 goto remove_out;
460
461         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
462                 &regs_fops);
463         if (!retval)
464                 goto remove_out;
465
466         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
467                 &mode_fops);
468         if (!retval)
469                 goto remove_out;
470
471         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
472                 &stats_fops);
473         if (!retval)
474                 goto remove_out;
475
476         return;
477 remove_out:
478         dev_err(&dc->ndev->dev, "could not create debugfs\n");
479         tegra_dc_remove_debugfs(dc);
480 }
481
482 #else /* !CONFIG_DEBUGFS */
483 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
484 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
485 #endif /* CONFIG_DEBUGFS */
486
487 static int tegra_dc_set(struct tegra_dc *dc, int index)
488 {
489         int ret = 0;
490
491         mutex_lock(&tegra_dc_lock);
492         if (index >= TEGRA_MAX_DC) {
493                 ret = -EINVAL;
494                 goto out;
495         }
496
497         if (dc != NULL && tegra_dcs[index] != NULL) {
498                 ret = -EBUSY;
499                 goto out;
500         }
501
502         tegra_dcs[index] = dc;
503
504 out:
505         mutex_unlock(&tegra_dc_lock);
506
507         return ret;
508 }
509
510 unsigned int tegra_dc_has_multiple_dc(void)
511 {
512         unsigned int idx;
513         unsigned int cnt = 0;
514         struct tegra_dc *dc;
515
516         mutex_lock(&tegra_dc_lock);
517         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
518                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
519         mutex_unlock(&tegra_dc_lock);
520
521         return (cnt > 1);
522 }
523
524 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
525 {
526         if (idx < TEGRA_MAX_DC)
527                 return tegra_dcs[idx];
528         else
529                 return NULL;
530 }
531 EXPORT_SYMBOL(tegra_dc_get_dc);
532
533 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
534 {
535         if (win >= dc->n_windows)
536                 return NULL;
537
538         return &dc->windows[win];
539 }
540 EXPORT_SYMBOL(tegra_dc_get_window);
541
542 static int get_topmost_window(u32 *depths, unsigned long *wins)
543 {
544         int idx, best = -1;
545
546         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
547                 if (best == -1 || depths[idx] < depths[best])
548                         best = idx;
549         }
550         clear_bit(best, wins);
551         return best;
552 }
553
554 bool tegra_dc_get_connected(struct tegra_dc *dc)
555 {
556         return dc->connected;
557 }
558 EXPORT_SYMBOL(tegra_dc_get_connected);
559
560 static u32 blend_topwin(u32 flags)
561 {
562         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
563                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
564         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
565                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
566         else
567                 return BLEND(NOKEY, FIX, 0xff, 0xff);
568 }
569
570 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
571 {
572         int other;
573
574         for (other = 0; other < DC_N_WINDOWS; other++) {
575                 if (other != idx && (xy-- == 0))
576                         break;
577         }
578         if (BIT(other) & behind_mask)
579                 return blend_topwin(flags[idx]);
580         else if (flags[other])
581                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
582         else
583                 return BLEND(NOKEY, FIX, 0x00, 0x00);
584 }
585
586 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
587 {
588         unsigned long infront_mask;
589         int first;
590
591         infront_mask = ~(behind_mask | BIT(idx));
592         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
593         first = ffs(infront_mask) - 1;
594
595         if (!infront_mask)
596                 return blend_topwin(flags[idx]);
597         else if (behind_mask && first != -1 && flags[first])
598                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
599         else
600                 return BLEND(NOKEY, FIX, 0x0, 0x0);
601 }
602
603 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
604 {
605         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
606
607         while (mask) {
608                 int idx = get_topmost_window(blend->z, &mask);
609
610                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
611                                 DC_CMD_DISPLAY_WINDOW_HEADER);
612                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
613                                 DC_WIN_BLEND_NOKEY);
614                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
615                                 DC_WIN_BLEND_1WIN);
616                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
617                                 DC_WIN_BLEND_2WIN_X);
618                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
619                                 DC_WIN_BLEND_2WIN_Y);
620                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
621                                 DC_WIN_BLEND_3WIN_XY);
622         }
623 }
624
625 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
626 {
627         csc->yof   = 0x00f0;
628         csc->kyrgb = 0x012a;
629         csc->kur   = 0x0000;
630         csc->kvr   = 0x0198;
631         csc->kug   = 0x039b;
632         csc->kvg   = 0x032f;
633         csc->kub   = 0x0204;
634         csc->kvb   = 0x0000;
635 }
636
637 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
638 {
639         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
640         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
641         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
642         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
643         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
644         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
645         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
646         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
647 }
648
649 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
650 {
651         mutex_lock(&dc->lock);
652
653         if (!dc->enabled) {
654                 mutex_unlock(&dc->lock);
655                 return -EFAULT;
656         }
657
658         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
659                         DC_CMD_DISPLAY_WINDOW_HEADER);
660
661         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
662
663         mutex_unlock(&dc->lock);
664
665         return 0;
666 }
667 EXPORT_SYMBOL(tegra_dc_update_csc);
668
669 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
670 {
671         int i;
672         for (i = 0; i < 256; i++)
673                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
674 }
675
676 static int tegra_dc_loop_lut(struct tegra_dc *dc,
677                              struct tegra_dc_win *win,
678                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
679 {
680         struct tegra_dc_lut *lut = &win->lut;
681         struct tegra_dc_lut *global_lut = &dc->fb_lut;
682         int i;
683         for (i = 0; i < 256; i++) {
684
685                 u32 r = (u32)lut->r[i];
686                 u32 g = (u32)lut->g[i];
687                 u32 b = (u32)lut->b[i];
688
689                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
690                         r = (u32)global_lut->r[r];
691                         g = (u32)global_lut->g[g];
692                         b = (u32)global_lut->b[b];
693                 }
694
695                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
696                         return 0;
697         }
698         return 1;
699 }
700
701 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
702 {
703         if (rgb != (i | (i<<8) | (i<<16)))
704                 return 0;
705         return 1;
706 }
707
708 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
709 {
710         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
711         return 1;
712 }
713
714 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
715 {
716         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
717
718         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
719
720         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
721                 val |= CP_ENABLE;
722         else
723                 val &= ~CP_ENABLE;
724
725         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
726 }
727
728 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
729 {
730         struct tegra_dc_win *win = &dc->windows[win_idx];
731
732         mutex_lock(&dc->lock);
733
734         if (!dc->enabled) {
735                 mutex_unlock(&dc->lock);
736                 return -EFAULT;
737         }
738
739         if (fbovr > 0)
740                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
741         else if (fbovr == 0)
742                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
743
744         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
745                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
746         else
747                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
748
749         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
750                         DC_CMD_DISPLAY_WINDOW_HEADER);
751
752         tegra_dc_set_lut(dc, win);
753
754         mutex_unlock(&dc->lock);
755
756         return 0;
757 }
758
759 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
760 {
761         if (win_idx > -1)
762                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
763
764         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
765                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
766                 if (err)
767                         return err;
768         }
769
770         return 0;
771 }
772 EXPORT_SYMBOL(tegra_dc_update_lut);
773
774 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
775 {
776         unsigned i;
777         unsigned v0 = 128;
778         unsigned v1 = 0;
779         /* linear horizontal and vertical filters */
780         for (i = 0; i < 16; i++) {
781                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
782                                 DC_WIN_H_FILTER_P(i));
783
784                 tegra_dc_writel(dc, v0,
785                                 DC_WIN_V_FILTER_P(i));
786                 v0 -= 8;
787                 v1 += 8;
788         }
789 }
790
791 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
792         struct tegra_dc_win *w)
793 {
794         /* windows A, B, C for first and second display */
795         static const enum tegra_la_id la_id_tab[2][3] = {
796                 /* first display */
797                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
798                         TEGRA_LA_DISPLAY_0C },
799                 /* second display */
800                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
801                         TEGRA_LA_DISPLAY_0CB },
802         };
803         /* window B V-filter tap for first and second display. */
804         static const enum tegra_la_id vfilter_tab[2] = {
805                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
806         };
807         unsigned long bw;
808
809         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
810         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
811         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
812
813         bw = w->new_bandwidth;
814
815         /* tegra_dc_get_bandwidth() treats V filter windows as double
816          * bandwidth, but LA has a seperate client for V filter */
817         if (w->idx == 1 && win_use_v_filter(w))
818                 bw /= 2;
819
820         /* our bandwidth is in bytes/sec, but LA takes MBps.
821          * round up bandwidth to 1MBps */
822         bw = bw / 1000000 + 1;
823
824 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
825         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
826         /* if window B, also set the 1B client for the 2-tap V filter. */
827         if (w->idx == 1)
828                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
829 #endif
830
831         w->bandwidth = w->new_bandwidth;
832 }
833
834 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
835                                                    struct tegra_dc_win *b)
836 {
837         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
838                 return 0;
839
840         /* because memory access to load the fifo can overlap, only care
841          * if windows overlap vertically */
842         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
843                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
844 }
845
846 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
847                                                  int n)
848 {
849         unsigned i;
850         unsigned j;
851         unsigned overlap_count;
852         unsigned max_bw = 0;
853
854         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
855                          "inaccurate.\n");
856
857         /* If we had a large number of windows, we would compute adjacency
858          * graph representing 2 window overlaps, find all cliques in the graph,
859          * assign bandwidth to each clique, and then select the clique with
860          * maximum bandwidth. But because we have at most 3 windows,
861          * implementing proper Bron-Kerbosh algorithm would be an overkill,
862          * brute force will suffice.
863          *
864          * Thus: find maximum bandwidth for either single or a pair of windows
865          * and count number of window pair overlaps. If there are three
866          * pairs, all 3 window overlap.
867          */
868
869         overlap_count = 0;
870         for (i = 0; i < n; i++) {
871                 unsigned int bw1;
872
873                 if (wins[i] == NULL)
874                         continue;
875                 bw1 = wins[i]->new_bandwidth;
876                 if (bw1 > max_bw)
877                         /* Single window */
878                         max_bw = bw1;
879
880                 for (j = i + 1; j < n; j++) {
881                         if (wins[j] == NULL)
882                                 continue;
883                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
884                                 unsigned int bw2 = wins[j]->new_bandwidth;
885                                 if (bw1 + bw2 > max_bw)
886                                         /* Window pair overlaps */
887                                         max_bw = bw1 + bw2;
888                                 overlap_count++;
889                         }
890                 }
891         }
892
893         if (overlap_count == 3)
894                 /* All three windows overlap */
895                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
896                          wins[2]->new_bandwidth;
897
898         return max_bw;
899 }
900
901 /*
902  * Calculate peak EMC bandwidth for each enabled window =
903  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
904  * (windows_tiling ? 2 : 1)
905  *
906  *
907  * note:
908  * (*) We use 2 tap V filter, so need double BW if use V filter
909  * (*) Tiling mode on T30 and DDR3 requires double BW
910  */
911 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
912         struct tegra_dc_win *w)
913 {
914         unsigned long ret;
915         int tiled_windows_bw_multiplier;
916         unsigned long bpp;
917
918         if (!WIN_IS_ENABLED(w))
919                 return 0;
920
921         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
922             w->out_w == 0 || w->out_h == 0)
923                 return 0;
924
925         tiled_windows_bw_multiplier =
926                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
927
928         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
929          * but the size reported by tegra_dc_fmt_bpp for the planar version
930          * is of the luma plane's size only. */
931         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
932                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
933         /* perform calculations with most significant bits of pixel clock
934          * to prevent overflow of long. */
935         ret = (unsigned long)(dc->pixel_clk >> 16) *
936                 bpp / 8 *
937                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
938                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
939
940 /*
941  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
942  * will request 147MBps from EMC.
943  */
944         ret = ret * 2 + ret / 10;
945
946         /* if overflowed */
947         if (ret > (1UL << 31))
948                 return ULONG_MAX;
949
950         return ret << 16; /* restore the scaling we did above */
951 }
952
953 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
954 {
955         int i;
956
957         BUG_ON(n > DC_N_WINDOWS);
958
959         /* emc rate and latency allowance both need to know per window
960          * bandwidths */
961         for (i = 0; i < n; i++) {
962                 struct tegra_dc_win *w = windows[i];
963                 if (w)
964                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
965         }
966
967         return tegra_dc_find_max_bandwidth(windows, n);
968 }
969
970 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
971 {
972         unsigned i;
973
974         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
975                 dc->emc_clk_rate = dc->new_emc_clk_rate;
976                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
977         }
978
979         for (i = 0; i < DC_N_WINDOWS; i++) {
980                 struct tegra_dc_win *w = &dc->windows[i];
981                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
982                         tegra_dc_set_latency_allowance(dc, w);
983         }
984 }
985
986 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
987 {
988         unsigned long new_rate;
989         struct tegra_dc *dc;
990
991         if (!use_dynamic_emc)
992                 return 0;
993
994         dc = windows[0]->dc;
995
996         /* calculate the new rate based on this POST */
997         new_rate = tegra_dc_get_bandwidth(windows, n);
998         new_rate = EMC_BW_TO_FREQ(new_rate);
999
1000         if (tegra_dc_has_multiple_dc())
1001                 new_rate = ULONG_MAX;
1002
1003         dc->new_emc_clk_rate = new_rate;
1004
1005         return 0;
1006 }
1007
1008 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1009                                   bool v, unsigned Bpp)
1010 {
1011         /*
1012          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1013          *           (post_scaled_size_in_pixels - 1)), MAX)
1014          * Where the value of MAX is as follows:
1015          * For V_DDA_INCREMENT: 15.0 (0xF000)
1016          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1017          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1018          */
1019
1020         fixed20_12 out = dfixed_init(out_int);
1021         u32 dda_inc;
1022         int max;
1023
1024         if (v) {
1025                 max = 15;
1026         } else {
1027                 switch (Bpp) {
1028                 default:
1029                         WARN_ON_ONCE(1);
1030                         /* fallthrough */
1031                 case 4:
1032                         max = 4;
1033                         break;
1034                 case 2:
1035                         max = 8;
1036                         break;
1037                 }
1038         }
1039
1040         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1041         in.full -= dfixed_const(1);
1042
1043         dda_inc = dfixed_div(in, out);
1044
1045         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1046
1047         return dda_inc;
1048 }
1049
1050 static inline u32 compute_initial_dda(fixed20_12 in)
1051 {
1052         return dfixed_frac(in);
1053 }
1054
1055 /* does not support updating windows on multiple dcs in one call */
1056 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1057 {
1058         struct tegra_dc *dc;
1059         unsigned long update_mask = GENERAL_ACT_REQ;
1060         unsigned long val;
1061         bool update_blend = false;
1062         int i;
1063
1064         dc = windows[0]->dc;
1065
1066         mutex_lock(&dc->lock);
1067
1068         if (!dc->enabled) {
1069                 mutex_unlock(&dc->lock);
1070                 return -EFAULT;
1071         }
1072
1073         if (no_vsync)
1074                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1075         else
1076                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1077
1078         for (i = 0; i < n; i++) {
1079                 struct tegra_dc_win *win = windows[i];
1080                 unsigned h_dda;
1081                 unsigned v_dda;
1082                 fixed20_12 h_offset, v_offset;
1083                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1084                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1085                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1086                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1087                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1088                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1089                 const bool filter_h = win_use_h_filter(win);
1090                 const bool filter_v = win_use_v_filter(win);
1091
1092                 if (win->z != dc->blend.z[win->idx]) {
1093                         dc->blend.z[win->idx] = win->z;
1094                         update_blend = true;
1095                 }
1096                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1097                         dc->blend.flags[win->idx]) {
1098                         dc->blend.flags[win->idx] =
1099                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1100                         update_blend = true;
1101                 }
1102
1103                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1104                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1105
1106                 if (!no_vsync)
1107                         update_mask |= WIN_A_ACT_REQ << win->idx;
1108
1109                 if (!WIN_IS_ENABLED(win)) {
1110                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1111                         continue;
1112                 }
1113
1114                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1115                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1116
1117                 tegra_dc_writel(dc,
1118                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1119                                 DC_WIN_POSITION);
1120                 tegra_dc_writel(dc,
1121                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1122                                 DC_WIN_SIZE);
1123                 tegra_dc_writel(dc,
1124                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1125                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1126                                 DC_WIN_PRESCALED_SIZE);
1127
1128                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1129                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1130                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1131                                 DC_WIN_DDA_INCREMENT);
1132                 h_dda = compute_initial_dda(win->x);
1133                 v_dda = compute_initial_dda(win->y);
1134                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1135                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1136
1137                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1138                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1139                 tegra_dc_writel(dc,
1140                                 (unsigned long)win->phys_addr,
1141                                 DC_WINBUF_START_ADDR);
1142
1143                 if (!yuvp) {
1144                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1145                 } else {
1146                         tegra_dc_writel(dc,
1147                                         (unsigned long)win->phys_addr_u,
1148                                         DC_WINBUF_START_ADDR_U);
1149                         tegra_dc_writel(dc,
1150                                         (unsigned long)win->phys_addr_v,
1151                                         DC_WINBUF_START_ADDR_V);
1152                         tegra_dc_writel(dc,
1153                                         LINE_STRIDE(win->stride) |
1154                                         UV_LINE_STRIDE(win->stride_uv),
1155                                         DC_WIN_LINE_STRIDE);
1156                 }
1157
1158                 h_offset = win->x;
1159                 if (invert_h) {
1160                         h_offset.full += win->w.full - dfixed_const(1);
1161                 }
1162
1163                 v_offset = win->y;
1164                 if (invert_v) {
1165                         v_offset.full += win->h.full - dfixed_const(1);
1166                 }
1167
1168                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1169                                 DC_WINBUF_ADDR_H_OFFSET);
1170                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1171                                 DC_WINBUF_ADDR_V_OFFSET);
1172
1173                 if (WIN_IS_TILED(win))
1174                         tegra_dc_writel(dc,
1175                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1176                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1177                                         DC_WIN_BUFFER_ADDR_MODE);
1178                 else
1179                         tegra_dc_writel(dc,
1180                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1181                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1182                                         DC_WIN_BUFFER_ADDR_MODE);
1183
1184                 val = WIN_ENABLE;
1185                 if (yuvp)
1186                         val |= CSC_ENABLE;
1187                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1188                         val |= COLOR_EXPAND;
1189
1190                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1191                         val |= CP_ENABLE;
1192
1193                 if (filter_h)
1194                         val |= H_FILTER_ENABLE;
1195                 if (filter_v)
1196                         val |= V_FILTER_ENABLE;
1197
1198                 if (invert_h)
1199                         val |= H_DIRECTION_DECREMENT;
1200                 if (invert_v)
1201                         val |= V_DIRECTION_DECREMENT;
1202
1203                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1204
1205                 win->dirty = no_vsync ? 0 : 1;
1206
1207                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1208                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1209                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1210                         __func__, win->idx, win->z,
1211                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1212                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1213                         win->out_x, win->out_y, win->out_w, win->out_h,
1214                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1215         }
1216
1217         if (update_blend) {
1218                 tegra_dc_set_blending(dc, &dc->blend);
1219                 for (i = 0; i < DC_N_WINDOWS; i++) {
1220                         if (!no_vsync)
1221                                 dc->windows[i].dirty = 1;
1222                         update_mask |= WIN_A_ACT_REQ << i;
1223                 }
1224         }
1225
1226         tegra_dc_set_dynamic_emc(windows, n);
1227
1228         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1229
1230         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1231         if (!no_vsync) {
1232                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1233                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1234                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1235         } else {
1236                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1237                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1238                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1239         }
1240
1241         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1242
1243         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1244                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1245
1246         mutex_unlock(&dc->lock);
1247
1248         return 0;
1249 }
1250 EXPORT_SYMBOL(tegra_dc_update_windows);
1251
1252 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1253 {
1254         return dc->syncpt[i].id;
1255 }
1256 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1257
1258 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1259 {
1260         u32 max;
1261
1262         mutex_lock(&dc->lock);
1263         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1264                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1265         dc->syncpt[i].max = max;
1266         mutex_unlock(&dc->lock);
1267
1268         return max;
1269 }
1270
1271 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1272 {
1273         mutex_lock(&dc->lock);
1274         if ( dc->enabled )
1275                 while (dc->syncpt[i].min < val) {
1276                         dc->syncpt[i].min++;
1277                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1278                                         dc->syncpt[i].id);
1279                 }
1280         mutex_unlock(&dc->lock);
1281 }
1282
1283 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1284                                              int n)
1285 {
1286         int i;
1287
1288         for (i = 0; i < n; i++) {
1289                 if (windows[i]->dirty)
1290                         return false;
1291         }
1292
1293         return true;
1294 }
1295
1296 /* does not support syncing windows on multiple dcs in one call */
1297 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1298 {
1299         if (n < 1 || n > DC_N_WINDOWS)
1300                 return -EINVAL;
1301
1302         if (!windows[0]->dc->enabled)
1303                 return -EFAULT;
1304
1305 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1306         /* Don't want to timeout on simulator */
1307         return wait_event_interruptible(windows[0]->dc->wq,
1308                 tegra_dc_windows_are_clean(windows, n));
1309 #else
1310         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1311                                          tegra_dc_windows_are_clean(windows, n),
1312                                          HZ);
1313 #endif
1314 }
1315 EXPORT_SYMBOL(tegra_dc_sync_windows);
1316
1317 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1318 {
1319 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1320         return clk_get_rate(dc->clk);
1321 #else
1322         return 27000000;
1323 #endif
1324 }
1325
1326 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1327 {
1328         unsigned long rate;
1329         unsigned long div;
1330
1331         rate = tegra_dc_clk_get_rate(dc);
1332
1333         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1334
1335         if (div < 2)
1336                 return 0;
1337
1338         return rate * 2 / div;
1339 }
1340
1341 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1342 {
1343         int pclk;
1344
1345         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1346                 unsigned long rate;
1347                 struct clk *parent_clk =
1348                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1349
1350                 if (clk_get_parent(clk) != parent_clk)
1351                         clk_set_parent(clk, parent_clk);
1352
1353                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1354                         struct clk *base_clk = clk_get_parent(parent_clk);
1355
1356                         /* Assuming either pll_d or pll_d2 is used */
1357                         rate = dc->mode.pclk * 2;
1358
1359                         if (rate != clk_get_rate(base_clk))
1360                                 clk_set_rate(base_clk, rate);
1361                 }
1362         }
1363
1364         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1365                 unsigned long rate;
1366                 struct clk *parent_clk =
1367                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1368                 struct clk *base_clk = clk_get_parent(parent_clk);
1369
1370                 /* needs to match tegra_dc_hdmi_supported_modes[]
1371                 and tegra_pll_d_freq_table[] */
1372                 if (dc->mode.pclk > 70000000)
1373                         rate = 594000000;
1374                 else if (dc->mode.pclk > 25200000)
1375                         rate = 216000000;
1376                 else
1377                         rate = 504000000;
1378
1379                 if (rate != clk_get_rate(base_clk))
1380                         clk_set_rate(base_clk, rate);
1381
1382                 if (clk_get_parent(clk) != parent_clk)
1383                         clk_set_parent(clk, parent_clk);
1384         }
1385
1386         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1387                 unsigned long rate;
1388                 struct clk *parent_clk;
1389                 struct clk *base_clk;
1390
1391                 if (clk == dc->clk) {
1392                         parent_clk = clk_get_sys(NULL,
1393                                         dc->out->parent_clk ? : "pll_d_out0");
1394                         base_clk = clk_get_parent(parent_clk);
1395                         tegra_clk_cfg_ex(base_clk,
1396                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1397                 } else {
1398                         if (dc->pdata->default_out->dsi->dsi_instance) {
1399                                 parent_clk = clk_get_sys(NULL,
1400                                         dc->out->parent_clk ? : "pll_d2_out0");
1401                                 base_clk = clk_get_parent(parent_clk);
1402                                 tegra_clk_cfg_ex(base_clk,
1403                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1404                         } else {
1405                                 parent_clk = clk_get_sys(NULL,
1406                                         dc->out->parent_clk ? : "pll_d_out0");
1407                                 base_clk = clk_get_parent(parent_clk);
1408                                 tegra_clk_cfg_ex(base_clk,
1409                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1410                         }
1411                 }
1412
1413                 rate = dc->mode.pclk;
1414                 if (rate != clk_get_rate(base_clk))
1415                         clk_set_rate(base_clk, rate);
1416
1417                 if (clk_get_parent(clk) != parent_clk)
1418                         clk_set_parent(clk, parent_clk);
1419         }
1420
1421         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1422         tegra_dvfs_set_rate(clk, pclk);
1423 }
1424
1425 /* return non-zero if constraint is violated */
1426 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1427 {
1428         long a, b;
1429
1430         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1431         a = 0;
1432
1433         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1434         b = mode->h_front_porch - 1;
1435
1436         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1437         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1438                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1439         /* check Constraint 1 and 6 */
1440         if (a > b)
1441                 return 1;
1442
1443         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1444         if (mode->h_sync_width < 1)
1445                 return 4;
1446
1447         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1448         if (mode->h_active < 16)
1449                 return 7;
1450
1451         if (href) {
1452                 if (b > a && a % 2)
1453                         *href = a + 1; /* use smallest even value */
1454                 else
1455                         *href = a; /* even or only possible value */
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1462 {
1463         long a;
1464         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1465
1466         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1467         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1468                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1469
1470         /* Constraint 6 */
1471         if (mode->v_front_porch < a + 1)
1472                 a = mode->v_front_porch - 1;
1473
1474         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1475         if (mode->v_sync_width < 1)
1476                 return 4;
1477
1478         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1479         if (mode->v_active < 16)
1480                 return 7;
1481
1482         if (vref)
1483                 *vref = a;
1484         return 0;
1485 }
1486
1487 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1488 {
1489         int ret;
1490         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1491         if (ret)
1492                 return ret;
1493         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1494         if (ret)
1495                 return ret;
1496
1497         return 0;
1498 }
1499
1500 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1501 {
1502         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1503         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1504                 return false;
1505
1506         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1507         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1508                 return false;
1509
1510         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1511          * (vertical blank). */
1512         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1513                 return false;
1514
1515         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1516         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1517                 return false;
1518
1519         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1520         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1521                 return false;
1522
1523         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1524          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1525         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1526                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1527                 return false;
1528
1529         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1530         if (mode->h_active < 16 || mode->v_active < 16)
1531                 return false;
1532
1533         return true;
1534 }
1535
1536 #ifdef DEBUG
1537 /* return in 1000ths of a Hertz */
1538 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1539 {
1540         long h_total, v_total, refresh;
1541         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1542                 m->h_sync_width;
1543         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1544                 m->v_sync_width;
1545         refresh = dc->pixel_clk / h_total;
1546         refresh *= 1000;
1547         refresh /= v_total;
1548         return refresh;
1549 }
1550
1551 static void print_mode(struct tegra_dc *dc,
1552                         const struct tegra_dc_mode *mode, const char *note)
1553 {
1554         if (mode) {
1555                 int refresh = calc_refresh(dc, mode);
1556                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1557                         note ? note : "",
1558                         mode->h_active, mode->v_active,
1559                         refresh / 1000, refresh % 1000,
1560                         mode->pclk);
1561         }
1562 }
1563 #else /* !DEBUG */
1564 static inline void print_mode(struct tegra_dc *dc,
1565                         const struct tegra_dc_mode *mode, const char *note) { }
1566 #endif /* DEBUG */
1567
1568 static inline void enable_dc_irq(unsigned int irq)
1569 {
1570 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1571         enable_irq(irq);
1572 #else
1573         /* Always disable DC interrupts on FPGA. */
1574         disable_irq(irq);
1575 #endif
1576 }
1577
1578 static inline void disable_dc_irq(unsigned int irq)
1579 {
1580         disable_irq(irq);
1581 }
1582
1583 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1584 {
1585         unsigned long val;
1586         unsigned long rate;
1587         unsigned long div;
1588         unsigned long pclk;
1589
1590         print_mode(dc, mode, __func__);
1591
1592         /* use default EMC rate when switching modes */
1593         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1594         tegra_dc_program_bandwidth(dc);
1595
1596         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1597         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1598                         DC_DISP_REF_TO_SYNC);
1599         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1600                         DC_DISP_SYNC_WIDTH);
1601         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1602                         DC_DISP_BACK_PORCH);
1603         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1604                         DC_DISP_DISP_ACTIVE);
1605         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1606                         DC_DISP_FRONT_PORCH);
1607
1608         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1609                         DC_DISP_DATA_ENABLE_OPTIONS);
1610
1611         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1612         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1613                 val |= PIN1_LVS_OUTPUT;
1614         else
1615                 val &= ~PIN1_LVS_OUTPUT;
1616
1617         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1618                 val |= PIN1_LHS_OUTPUT;
1619         else
1620                 val &= ~PIN1_LHS_OUTPUT;
1621         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1622
1623         /* TODO: MIPI/CRT/HDMI clock cals */
1624
1625         val = DISP_DATA_FORMAT_DF1P1C;
1626
1627         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1628                 val |= DISP_DATA_ALIGNMENT_MSB;
1629         else
1630                 val |= DISP_DATA_ALIGNMENT_LSB;
1631
1632         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1633                 val |= DISP_DATA_ORDER_RED_BLUE;
1634         else
1635                 val |= DISP_DATA_ORDER_BLUE_RED;
1636
1637         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1638
1639         rate = tegra_dc_clk_get_rate(dc);
1640
1641         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1642         if (pclk < (mode->pclk / 100 * 99) ||
1643             pclk > (mode->pclk / 100 * 109)) {
1644                 dev_err(&dc->ndev->dev,
1645                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1646                         rate, mode->pclk,
1647                         pclk, (mode->pclk / 100 * 99),
1648                         (mode->pclk / 100 * 109));
1649                 return -EINVAL;
1650         }
1651
1652         div = (rate * 2 / pclk) - 2;
1653
1654         tegra_dc_writel(dc, 0x00010001,
1655                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1656         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1657                         DC_DISP_DISP_CLOCK_CONTROL);
1658
1659         switch_set_state(&dc->modeset_switch,
1660                          (mode->h_active << 16) | mode->v_active);
1661
1662         dc->pixel_clk = dc->mode.pclk;
1663
1664         return 0;
1665 }
1666
1667
1668 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1669 {
1670         memcpy(&dc->mode, mode, sizeof(dc->mode));
1671
1672         print_mode(dc, mode, __func__);
1673
1674         return 0;
1675 }
1676 EXPORT_SYMBOL(tegra_dc_set_mode);
1677
1678 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1679                 const struct fb_videomode *fbmode, bool stereo_mode)
1680 {
1681         struct tegra_dc_mode mode;
1682
1683         if (!fbmode->pixclock)
1684                 return -EINVAL;
1685
1686         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1687         mode.h_sync_width = fbmode->hsync_len;
1688         mode.v_sync_width = fbmode->vsync_len;
1689         mode.h_back_porch = fbmode->left_margin;
1690         mode.v_back_porch = fbmode->upper_margin;
1691         mode.h_active = fbmode->xres;
1692         mode.v_active = fbmode->yres;
1693         mode.h_front_porch = fbmode->right_margin;
1694         mode.v_front_porch = fbmode->lower_margin;
1695         mode.stereo_mode = stereo_mode;
1696         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1697                 /* HDMI controller requires h_ref=1, v_ref=1 */
1698                 mode.h_ref_to_sync = 1;
1699                 mode.v_ref_to_sync = 1;
1700         } else {
1701                 calc_ref_to_sync(&mode);
1702         }
1703         if (!check_ref_to_sync(&mode)) {
1704                 dev_err(&dc->ndev->dev,
1705                                 "Display timing doesn't meet restrictions.\n");
1706                 return -EINVAL;
1707         }
1708         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1709                 mode.h_active, mode.v_active, mode.pclk,
1710                 mode.h_ref_to_sync, mode.v_ref_to_sync
1711         );
1712
1713         if (mode.stereo_mode) {
1714                 mode.pclk *= 2;
1715                 /* total v_active = yres*2 + activespace */
1716                 mode.v_active = fbmode->yres*2 +
1717                                 fbmode->vsync_len +
1718                                 fbmode->upper_margin +
1719                                 fbmode->lower_margin;
1720         }
1721
1722         mode.flags = 0;
1723
1724         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1725                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1726
1727         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1728                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1729
1730         return tegra_dc_set_mode(dc, &mode);
1731 }
1732 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1733
1734 void
1735 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1736 {
1737         unsigned int ctrl;
1738         unsigned long out_sel;
1739         unsigned long cmd_state;
1740
1741         mutex_lock(&dc->lock);
1742         if (!dc->enabled) {
1743                 mutex_unlock(&dc->lock);
1744                 return;
1745         }
1746
1747         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1748                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1749                 cfg->clk_select);
1750
1751         /* The new value should be effected immediately */
1752         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1753         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1754
1755         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1756                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1757         else
1758                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1759
1760         switch (cfg->which_pwm) {
1761         case TEGRA_PWM_PM0:
1762                 /* Select the LM0 on PM0 */
1763                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1764                 out_sel &= ~(7 << 0);
1765                 out_sel |= (3 << 0);
1766                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1767                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1768                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1769                 break;
1770         case TEGRA_PWM_PM1:
1771                 /* Select the LM1 on PM1 */
1772                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1773                 out_sel &= ~(7 << 4);
1774                 out_sel |= (3 << 4);
1775                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1776                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1777                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1778                 break;
1779         default:
1780                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1781                 break;
1782         }
1783         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1784         mutex_unlock(&dc->lock);
1785 }
1786 EXPORT_SYMBOL(tegra_dc_config_pwm);
1787
1788 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1789                                 const struct tegra_dc_out_pin *pins,
1790                                 const unsigned int n_pins)
1791 {
1792         unsigned int i;
1793
1794         int name;
1795         int pol;
1796
1797         u32 pol1, pol3;
1798
1799         u32 set1, unset1;
1800         u32 set3, unset3;
1801
1802         set1 = set3 = unset1 = unset3 = 0;
1803
1804         for (i = 0; i < n_pins; i++) {
1805                 name = (pins + i)->name;
1806                 pol  = (pins + i)->pol;
1807
1808                 /* set polarity by name */
1809                 switch (name) {
1810                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1811                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1812                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1813                         else
1814                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1815                         break;
1816                 case TEGRA_DC_OUT_PIN_H_SYNC:
1817                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1818                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1819                         else
1820                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1821                         break;
1822                 case TEGRA_DC_OUT_PIN_V_SYNC:
1823                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1824                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1825                         else
1826                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1827                         break;
1828                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1829                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1830                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1831                         else
1832                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1833                         break;
1834                 default:
1835                         printk("Invalid argument in function %s\n",
1836                                __FUNCTION__);
1837                         break;
1838                 }
1839         }
1840
1841         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1842         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1843
1844         pol1 |= set1;
1845         pol1 &= ~unset1;
1846
1847         pol3 |= set3;
1848         pol3 &= ~unset3;
1849
1850         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1851         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1852 }
1853
1854 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1855 {
1856         dc->out = out;
1857
1858         if (out->n_modes > 0)
1859                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1860
1861         switch (out->type) {
1862         case TEGRA_DC_OUT_RGB:
1863                 dc->out_ops = &tegra_dc_rgb_ops;
1864                 break;
1865
1866         case TEGRA_DC_OUT_HDMI:
1867                 dc->out_ops = &tegra_dc_hdmi_ops;
1868                 break;
1869
1870         case TEGRA_DC_OUT_DSI:
1871                 dc->out_ops = &tegra_dc_dsi_ops;
1872                 break;
1873
1874         default:
1875                 dc->out_ops = NULL;
1876                 break;
1877         }
1878
1879         if (dc->out_ops && dc->out_ops->init)
1880                 dc->out_ops->init(dc);
1881
1882 }
1883
1884 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1885 {
1886         if (dc->out)
1887                 return dc->out->height;
1888         else
1889                 return 0;
1890 }
1891 EXPORT_SYMBOL(tegra_dc_get_out_height);
1892
1893 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1894 {
1895         if (dc->out)
1896                 return dc->out->width;
1897         else
1898                 return 0;
1899 }
1900 EXPORT_SYMBOL(tegra_dc_get_out_width);
1901
1902 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1903 {
1904         if (dc->out && dc->out->max_pixclock)
1905                 return dc->out->max_pixclock;
1906         else
1907                 return 0;
1908 }
1909 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1910
1911 void tegra_dc_enable_crc(struct tegra_dc *dc)
1912 {
1913         u32 val;
1914         tegra_dc_io_start(dc);
1915
1916         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1917                 CRC_ENABLE_ENABLE;
1918         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1919         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1920         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1921 }
1922
1923 void tegra_dc_disable_crc(struct tegra_dc *dc)
1924 {
1925         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1926         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1927         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1928
1929         tegra_dc_io_end(dc);
1930 }
1931
1932 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1933 {
1934         int crc = 0;
1935
1936         if(!dc) {
1937                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1938                 goto crc_error;
1939         }
1940
1941         /* TODO: Replace mdelay with code to sync VBlANK, since
1942          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1943         mdelay(TEGRA_CRC_LATCHED_DELAY);
1944
1945         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1946 crc_error:
1947         return crc;
1948 }
1949
1950 static void tegra_dc_vblank(struct work_struct *work)
1951 {
1952         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1953         bool nvsd_updated = false;
1954
1955         mutex_lock(&dc->lock);
1956
1957         /* update EMC clock if calculated bandwidth has changed */
1958         tegra_dc_program_bandwidth(dc);
1959
1960         /* Update the SD brightness */
1961         if (dc->enabled && dc->out->sd_settings)
1962                 nvsd_updated = nvsd_update_brightness(dc);
1963
1964         mutex_unlock(&dc->lock);
1965
1966         /* Do the actual brightness update outside of the mutex */
1967         if (nvsd_updated && dc->out->sd_settings &&
1968             dc->out->sd_settings->bl_device) {
1969
1970                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1971                 struct backlight_device *bl = platform_get_drvdata(pdev);
1972                 if (bl)
1973                         backlight_update_status(bl);
1974         }
1975 }
1976
1977 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1978 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1979 {
1980         u32 val, i;
1981
1982         /* Check for any underflow reset conditions */
1983         for (i = 0; i < DC_N_WINDOWS; i++) {
1984                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1985                         dc->windows[i].underflows++;
1986
1987 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1988                         if (dc->windows[i].underflows > 4)
1989                                 schedule_work(&dc->reset_work);
1990 #endif
1991                 } else {
1992                         dc->windows[i].underflows = 0;
1993                 }
1994         }
1995
1996         if (!dc->underflow_mask) {
1997                 /* If we have no underflow to check, go ahead
1998                    and disable the interrupt */
1999                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2000                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2001                         val &= ~FRAME_END_INT;
2002                 else
2003                         val &= ~V_BLANK_INT;
2004                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2005         }
2006
2007         /* Clear the underflow mask now that we've checked it. */
2008         dc->underflow_mask = 0;
2009 }
2010
2011 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2012 {
2013         u32 val, i;
2014         u32 completed = 0;
2015         u32 dirty = 0;
2016
2017         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2018         for (i = 0; i < DC_N_WINDOWS; i++) {
2019 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2020                 /* FIXME: this is not needed when the simulator
2021                    clears WIN_x_UPDATE bits as in HW */
2022                 dc->windows[i].dirty = 0;
2023                 completed = 1;
2024 #else
2025                 if (!(val & (WIN_A_UPDATE << i))) {
2026                         dc->windows[i].dirty = 0;
2027                         completed = 1;
2028                 } else {
2029                         dirty = 1;
2030                 }
2031 #endif
2032         }
2033
2034         if (!dirty) {
2035                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2036                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2037                         val &= ~V_BLANK_INT;
2038                 else
2039                         val &= ~FRAME_END_INT;
2040                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2041         }
2042
2043         if (completed) {
2044                 if (!dirty) {
2045                         /* With the last completed window, go ahead
2046                            and enable the vblank interrupt for nvsd. */
2047                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2048                         val |= V_BLANK_INT;
2049                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2050                 }
2051
2052                 wake_up(&dc->wq);
2053         }
2054 }
2055
2056 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2057 {
2058         if (status & V_BLANK_INT) {
2059                 /* Sync up windows. */
2060                 tegra_dc_trigger_windows(dc);
2061
2062                 /* Schedule any additional bottom-half vblank actvities. */
2063                 schedule_work(&dc->vblank_work);
2064         }
2065
2066         /* Check underflow at frame end */
2067         if (status & FRAME_END_INT) {
2068                 tegra_dc_underflow_handler(dc);
2069
2070                 /* Mark the frame_end as complete. */
2071                 if (completion_done(&dc->frame_end_complete))
2072                         complete(&dc->frame_end_complete);
2073         }
2074 }
2075
2076 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2077 {
2078         if (status & V_BLANK_INT) {
2079                 /* Check underflow */
2080                 tegra_dc_underflow_handler(dc);
2081
2082                 /* Schedule any additional bottom-half vblank actvities. */
2083                 schedule_work(&dc->vblank_work);
2084         }
2085
2086         if (status & FRAME_END_INT) {
2087                 /* Mark the frame_end as complete. */
2088                 if (completion_done(&dc->frame_end_complete))
2089                         complete(&dc->frame_end_complete);
2090
2091                 tegra_dc_trigger_windows(dc);
2092         }
2093 }
2094 #endif
2095
2096 /* return an arbitrarily large number if count overflow occurs.
2097  * make it a nice base-10 number to show up in stats output */
2098 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2099 {
2100         unsigned count = tegra_dc_readl(dc, reg);
2101         tegra_dc_writel(dc, 0, reg);
2102         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2103 }
2104
2105 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2106 {
2107 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2108         struct tegra_dc *dc = ptr;
2109         unsigned long status;
2110         unsigned long val;
2111         unsigned long underflow_mask;
2112
2113         if (!nvhost_module_powered(&dc->ndev->host->mod)) {
2114                 WARN(1, "IRQ when DC not powered!\n");
2115                 tegra_dc_io_start(dc);
2116                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2117                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2118                 tegra_dc_io_end(dc);
2119                 return IRQ_HANDLED;
2120         }
2121
2122         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2123         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2124
2125         /*
2126          * Overlays can get thier internal state corrupted during and underflow
2127          * condition.  The only way to fix this state is to reset the DC.
2128          * if we get 4 consecutive frames with underflows, assume we're
2129          * hosed and reset.
2130          */
2131         underflow_mask = status & ALL_UF_INT;
2132
2133         if (underflow_mask) {
2134                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2135                 val |= V_BLANK_INT;
2136                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2137                 dc->underflow_mask |= underflow_mask;
2138                 dc->stats.underflows++;
2139                 if (status & WIN_A_UF_INT)
2140                         dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2141                                 DC_WINBUF_AD_UFLOW_STATUS);
2142                 if (status & WIN_B_UF_INT)
2143                         dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2144                                 DC_WINBUF_BD_UFLOW_STATUS);
2145                 if (status & WIN_C_UF_INT)
2146                         dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2147                                 DC_WINBUF_CD_UFLOW_STATUS);
2148         }
2149
2150         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2151                 tegra_dc_one_shot_irq(dc, status);
2152         else
2153                 tegra_dc_continuous_irq(dc, status);
2154
2155         return IRQ_HANDLED;
2156 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2157         return IRQ_NONE;
2158 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2159 }
2160
2161 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2162 {
2163         u32 color_control;
2164
2165         switch (dc->out->depth) {
2166         case 3:
2167                 color_control = BASE_COLOR_SIZE111;
2168                 break;
2169
2170         case 6:
2171                 color_control = BASE_COLOR_SIZE222;
2172                 break;
2173
2174         case 8:
2175                 color_control = BASE_COLOR_SIZE332;
2176                 break;
2177
2178         case 9:
2179                 color_control = BASE_COLOR_SIZE333;
2180                 break;
2181
2182         case 12:
2183                 color_control = BASE_COLOR_SIZE444;
2184                 break;
2185
2186         case 15:
2187                 color_control = BASE_COLOR_SIZE555;
2188                 break;
2189
2190         case 16:
2191                 color_control = BASE_COLOR_SIZE565;
2192                 break;
2193
2194         case 18:
2195                 color_control = BASE_COLOR_SIZE666;
2196                 break;
2197
2198         default:
2199                 color_control = BASE_COLOR_SIZE888;
2200                 break;
2201         }
2202
2203         switch (dc->out->dither) {
2204         case TEGRA_DC_DISABLE_DITHER:
2205                 color_control |= DITHER_CONTROL_DISABLE;
2206                 break;
2207         case TEGRA_DC_ORDERED_DITHER:
2208                 color_control |= DITHER_CONTROL_ORDERED;
2209                 break;
2210         case TEGRA_DC_ERRDIFF_DITHER:
2211                 /* The line buffer for error-diffusion dither is limited
2212                  * to 1280 pixels per line. This limits the maximum
2213                  * horizontal active area size to 1280 pixels when error
2214                  * diffusion is enabled.
2215                  */
2216                 BUG_ON(dc->mode.h_active > 1280);
2217                 color_control |= DITHER_CONTROL_ERRDIFF;
2218                 break;
2219         }
2220
2221         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2222 }
2223
2224 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2225 {
2226         u32 syncpt_id;
2227
2228         switch (dc->ndev->id) {
2229         case 0:
2230                 switch (idx) {
2231                 case 0:
2232                         syncpt_id = NVSYNCPT_DISP0_A;
2233                         break;
2234                 case 1:
2235                         syncpt_id = NVSYNCPT_DISP0_B;
2236                         break;
2237                 case 2:
2238                         syncpt_id = NVSYNCPT_DISP0_C;
2239                         break;
2240                 default:
2241                         BUG();
2242                         break;
2243                 }
2244                 break;
2245         case 1:
2246                 switch (idx) {
2247                 case 0:
2248                         syncpt_id = NVSYNCPT_DISP1_A;
2249                         break;
2250                 case 1:
2251                         syncpt_id = NVSYNCPT_DISP1_B;
2252                         break;
2253                 case 2:
2254                         syncpt_id = NVSYNCPT_DISP1_C;
2255                         break;
2256                 default:
2257                         BUG();
2258                         break;
2259                 }
2260                 break;
2261         default:
2262                 BUG();
2263                 break;
2264         }
2265
2266         return syncpt_id;
2267 }
2268
2269 static void tegra_dc_init(struct tegra_dc *dc)
2270 {
2271         int i;
2272
2273         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2274         if (dc->ndev->id == 0) {
2275                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2276                                       TEGRA_MC_PRIO_MED);
2277                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2278                                       TEGRA_MC_PRIO_MED);
2279                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2280                                       TEGRA_MC_PRIO_MED);
2281                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2282                                       TEGRA_MC_PRIO_MED);
2283                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2284                                       TEGRA_MC_PRIO_HIGH);
2285         } else if (dc->ndev->id == 1) {
2286                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2287                                       TEGRA_MC_PRIO_MED);
2288                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2289                                       TEGRA_MC_PRIO_MED);
2290                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2291                                       TEGRA_MC_PRIO_MED);
2292                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2293                                       TEGRA_MC_PRIO_MED);
2294                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2295                                       TEGRA_MC_PRIO_HIGH);
2296         }
2297         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2298                         DC_CMD_CONT_SYNCPT_VSYNC);
2299         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2300         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2301         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2302         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2303
2304         /* enable interrupts for vblank, frame_end and underflows */
2305         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2306                 DC_CMD_INT_ENABLE);
2307         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2308
2309         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2310
2311         tegra_dc_set_color_control(dc);
2312         for (i = 0; i < DC_N_WINDOWS; i++) {
2313                 struct tegra_dc_win *win = &dc->windows[i];
2314                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2315                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2316                 tegra_dc_set_csc(dc, &win->csc);
2317                 tegra_dc_set_lut(dc, win);
2318                 tegra_dc_set_scaling_filter(dc);
2319         }
2320
2321
2322         for (i = 0; i < dc->n_windows; i++) {
2323                 u32 syncpt = get_syncpt(dc, i);
2324
2325                 dc->syncpt[i].id = syncpt;
2326
2327                 dc->syncpt[i].min = dc->syncpt[i].max =
2328                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2329         }
2330
2331         print_mode(dc, &dc->mode, __func__);
2332
2333         if (dc->mode.pclk)
2334                 tegra_dc_program_mode(dc, &dc->mode);
2335
2336         /* Initialize SD AFTER the modeset.
2337            nvsd_init handles the sd_settings = NULL case. */
2338         nvsd_init(dc, dc->out->sd_settings);
2339 }
2340
2341 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2342 {
2343         if (dc->out->enable)
2344                 dc->out->enable();
2345
2346         tegra_dc_setup_clk(dc, dc->clk);
2347         clk_enable(dc->clk);
2348         clk_enable(dc->emc_clk);
2349
2350         /* do not accept interrupts during initialization */
2351         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2352         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2353
2354         enable_dc_irq(dc->irq);
2355
2356         tegra_dc_init(dc);
2357
2358         if (dc->out_ops && dc->out_ops->enable)
2359                 dc->out_ops->enable(dc);
2360
2361         if (dc->out->out_pins)
2362                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2363                                             dc->out->n_out_pins);
2364
2365         if (dc->out->postpoweron)
2366                 dc->out->postpoweron();
2367
2368         /* force a full blending update */
2369         dc->blend.z[0] = -1;
2370
2371         tegra_dc_ext_enable(dc->ext);
2372
2373         return true;
2374 }
2375
2376 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2377 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2378 {
2379         if (dc->out->enable)
2380                 dc->out->enable();
2381
2382         tegra_dc_setup_clk(dc, dc->clk);
2383         clk_enable(dc->clk);
2384         clk_enable(dc->emc_clk);
2385
2386         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2387                 mutex_lock(&tegra_dcs[1]->lock);
2388                 disable_irq(tegra_dcs[1]->irq);
2389         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2390                 mutex_lock(&tegra_dcs[0]->lock);
2391                 disable_irq(tegra_dcs[0]->irq);
2392         }
2393
2394         msleep(5);
2395         tegra_periph_reset_assert(dc->clk);
2396         msleep(2);
2397 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2398         tegra_periph_reset_deassert(dc->clk);
2399         msleep(1);
2400 #endif
2401
2402         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2403                 enable_dc_irq(tegra_dcs[1]->irq);
2404                 mutex_unlock(&tegra_dcs[1]->lock);
2405         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2406                 enable_dc_irq(tegra_dcs[0]->irq);
2407                 mutex_unlock(&tegra_dcs[0]->lock);
2408         }
2409
2410         enable_dc_irq(dc->irq);
2411
2412         tegra_dc_init(dc);
2413
2414         if (dc->out_ops && dc->out_ops->enable)
2415                 dc->out_ops->enable(dc);
2416
2417         if (dc->out->out_pins)
2418                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2419                                             dc->out->n_out_pins);
2420
2421         if (dc->out->postpoweron)
2422                 dc->out->postpoweron();
2423
2424         /* force a full blending update */
2425         dc->blend.z[0] = -1;
2426
2427         return true;
2428 }
2429 #endif
2430
2431 static bool _tegra_dc_enable(struct tegra_dc *dc)
2432 {
2433         if (dc->mode.pclk == 0)
2434                 return false;
2435
2436         if (!dc->out)
2437                 return false;
2438
2439         tegra_dc_io_start(dc);
2440
2441         return _tegra_dc_controller_enable(dc);
2442 }
2443
2444 void tegra_dc_enable(struct tegra_dc *dc)
2445 {
2446         mutex_lock(&dc->lock);
2447
2448         if (!dc->enabled)
2449                 dc->enabled = _tegra_dc_enable(dc);
2450
2451         mutex_unlock(&dc->lock);
2452 }
2453
2454 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2455 {
2456         unsigned i;
2457
2458         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2459         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2460         disable_irq(dc->irq);
2461
2462         if (dc->out_ops && dc->out_ops->disable)
2463                 dc->out_ops->disable(dc);
2464
2465         clk_disable(dc->emc_clk);
2466         clk_disable(dc->clk);
2467         tegra_dvfs_set_rate(dc->clk, 0);
2468
2469         if (dc->out && dc->out->disable)
2470                 dc->out->disable();
2471
2472         for (i = 0; i < dc->n_windows; i++) {
2473                 struct tegra_dc_win *w = &dc->windows[i];
2474
2475                 /* reset window bandwidth */
2476                 w->bandwidth = 0;
2477                 w->new_bandwidth = 0;
2478
2479                 /* disable windows */
2480                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2481
2482                 /* flush any pending syncpt waits */
2483                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2484                         dc->syncpt[i].min++;
2485                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2486                                 dc->syncpt[i].id);
2487                 }
2488         }
2489 }
2490
2491 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2492 {
2493 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2494         u32 val;
2495         if (dc->enabled)  {
2496                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2497                 if (enable)
2498                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2499                 else
2500                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2501                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2502         }
2503 #endif
2504 }
2505
2506 bool tegra_dc_stats_get(struct tegra_dc *dc)
2507 {
2508 #if 0 /* right now it is always enabled */
2509         u32 val;
2510         bool res;
2511
2512         if (dc->enabled)  {
2513                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2514                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2515         } else {
2516                 res = false;
2517         }
2518
2519         return res;
2520 #endif
2521         return true;
2522 }
2523
2524 /* make the screen blank by disabling all windows */
2525 void tegra_dc_blank(struct tegra_dc *dc)
2526 {
2527         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2528         unsigned i;
2529
2530         for (i = 0; i < DC_N_WINDOWS; i++) {
2531                 dcwins[i] = tegra_dc_get_window(dc, i);
2532                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2533         }
2534
2535         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2536         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2537 }
2538
2539 static void _tegra_dc_disable(struct tegra_dc *dc)
2540 {
2541         _tegra_dc_controller_disable(dc);
2542         tegra_dc_io_end(dc);
2543 }
2544
2545 void tegra_dc_disable(struct tegra_dc *dc)
2546 {
2547         if (dc->overlay)
2548                 tegra_overlay_disable(dc->overlay);
2549
2550         tegra_dc_ext_disable(dc->ext);
2551
2552         mutex_lock(&dc->lock);
2553
2554         if (dc->enabled) {
2555                 dc->enabled = false;
2556
2557                 if (!dc->suspended)
2558                         _tegra_dc_disable(dc);
2559         }
2560
2561         switch_set_state(&dc->modeset_switch, 0);
2562
2563         mutex_unlock(&dc->lock);
2564 }
2565
2566 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2567 static void tegra_dc_reset_worker(struct work_struct *work)
2568 {
2569         struct tegra_dc *dc =
2570                 container_of(work, struct tegra_dc, reset_work);
2571
2572         unsigned long val = 0;
2573
2574         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2575
2576         tegra_dc_ext_disable(dc->ext);
2577
2578         mutex_lock(&shared_lock);
2579         mutex_lock(&dc->lock);
2580
2581         if (dc->enabled == false)
2582                 goto unlock;
2583
2584         dc->enabled = false;
2585
2586         /*
2587          * off host read bus
2588          */
2589         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2590         val &= ~(0x00000100);
2591         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2592
2593         /*
2594          * set DC to STOP mode
2595          */
2596         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2597
2598         msleep(10);
2599
2600         _tegra_dc_controller_disable(dc);
2601
2602         /* _tegra_dc_controller_reset_enable deasserts reset */
2603         _tegra_dc_controller_reset_enable(dc);
2604
2605         dc->enabled = true;
2606 unlock:
2607         mutex_unlock(&dc->lock);
2608         mutex_unlock(&shared_lock);
2609 }
2610 #endif
2611
2612 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2613 {
2614         struct tegra_dc *dc =
2615                 container_of(sdev, struct tegra_dc, modeset_switch);
2616
2617         if (!sdev->state)
2618                 return sprintf(buf, "offline\n");
2619
2620         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2621 }
2622
2623 static int tegra_dc_probe(struct nvhost_device *ndev)
2624 {
2625         struct tegra_dc *dc;
2626         struct clk *clk;
2627         struct clk *emc_clk;
2628         struct resource *res;
2629         struct resource *base_res;
2630         struct resource *fb_mem = NULL;
2631         int ret = 0;
2632         void __iomem *base;
2633         int irq;
2634         int i;
2635
2636         if (!ndev->dev.platform_data) {
2637                 dev_err(&ndev->dev, "no platform data\n");
2638                 return -ENOENT;
2639         }
2640
2641         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2642         if (!dc) {
2643                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2644                 return -ENOMEM;
2645         }
2646
2647         irq = nvhost_get_irq_byname(ndev, "irq");
2648         if (irq <= 0) {
2649                 dev_err(&ndev->dev, "no irq\n");
2650                 ret = -ENOENT;
2651                 goto err_free;
2652         }
2653
2654         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2655         if (!res) {
2656                 dev_err(&ndev->dev, "no mem resource\n");
2657                 ret = -ENOENT;
2658                 goto err_free;
2659         }
2660
2661         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2662         if (!base_res) {
2663                 dev_err(&ndev->dev, "request_mem_region failed\n");
2664                 ret = -EBUSY;
2665                 goto err_free;
2666         }
2667
2668         base = ioremap(res->start, resource_size(res));
2669         if (!base) {
2670                 dev_err(&ndev->dev, "registers can't be mapped\n");
2671                 ret = -EBUSY;
2672                 goto err_release_resource_reg;
2673         }
2674
2675         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2676
2677         clk = clk_get(&ndev->dev, NULL);
2678         if (IS_ERR_OR_NULL(clk)) {
2679                 dev_err(&ndev->dev, "can't get clock\n");
2680                 ret = -ENOENT;
2681                 goto err_iounmap_reg;
2682         }
2683
2684         emc_clk = clk_get(&ndev->dev, "emc");
2685         if (IS_ERR_OR_NULL(emc_clk)) {
2686                 dev_err(&ndev->dev, "can't get emc clock\n");
2687                 ret = -ENOENT;
2688                 goto err_put_clk;
2689         }
2690
2691         dc->clk = clk;
2692         dc->emc_clk = emc_clk;
2693
2694         dc->base_res = base_res;
2695         dc->base = base;
2696         dc->irq = irq;
2697         dc->ndev = ndev;
2698         dc->pdata = ndev->dev.platform_data;
2699
2700         /*
2701          * The emc is a shared clock, it will be set based on
2702          * the requirements for each user on the bus.
2703          */
2704         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2705         clk_set_rate(emc_clk, dc->emc_clk_rate);
2706
2707         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2708                 dc->enabled = true;
2709
2710         mutex_init(&dc->lock);
2711         init_completion(&dc->frame_end_complete);
2712         init_waitqueue_head(&dc->wq);
2713 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2714         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2715 #endif
2716         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2717
2718         tegra_dc_init_lut_defaults(&dc->fb_lut);
2719
2720         dc->n_windows = DC_N_WINDOWS;
2721         for (i = 0; i < dc->n_windows; i++) {
2722                 struct tegra_dc_win *win = &dc->windows[i];
2723                 win->idx = i;
2724                 win->dc = dc;
2725                 tegra_dc_init_csc_defaults(&win->csc);
2726                 tegra_dc_init_lut_defaults(&win->lut);
2727         }
2728
2729         ret = tegra_dc_set(dc, ndev->id);
2730         if (ret < 0) {
2731                 dev_err(&ndev->dev, "can't add dc\n");
2732                 goto err_free_irq;
2733         }
2734
2735         nvhost_set_drvdata(ndev, dc);
2736
2737         dc->modeset_switch.name = dev_name(&ndev->dev);
2738         dc->modeset_switch.state = 0;
2739         dc->modeset_switch.print_state = switch_modeset_print_mode;
2740         switch_dev_register(&dc->modeset_switch);
2741
2742         if (dc->pdata->default_out)
2743                 tegra_dc_set_out(dc, dc->pdata->default_out);
2744         else
2745                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2746
2747         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2748                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2749
2750         dc->ext = tegra_dc_ext_register(ndev, dc);
2751         if (IS_ERR_OR_NULL(dc->ext)) {
2752                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2753                 dc->ext = NULL;
2754         }
2755
2756         /* interrupt handler must be registered before tegra_fb_register() */
2757         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2758                         dev_name(&ndev->dev), dc)) {
2759                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2760                 ret = -EBUSY;
2761                 goto err_put_emc_clk;
2762         }
2763
2764         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2765         disable_dc_irq(dc->irq);
2766
2767         mutex_lock(&dc->lock);
2768         if (dc->enabled)
2769                 _tegra_dc_enable(dc);
2770         mutex_unlock(&dc->lock);
2771
2772         tegra_dc_create_debugfs(dc);
2773
2774         dev_info(&ndev->dev, "probed\n");
2775
2776         if (dc->pdata->fb) {
2777                 if (dc->pdata->fb->bits_per_pixel == -1) {
2778                         unsigned long fmt;
2779                         tegra_dc_writel(dc,
2780                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2781                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2782
2783                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2784                         dc->pdata->fb->bits_per_pixel =
2785                                 tegra_dc_fmt_bpp(fmt);
2786                 }
2787
2788                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2789                 if (IS_ERR_OR_NULL(dc->fb))
2790                         dc->fb = NULL;
2791         }
2792
2793         if (dc->fb) {
2794                 dc->overlay = tegra_overlay_register(ndev, dc);
2795                 if (IS_ERR_OR_NULL(dc->overlay))
2796                         dc->overlay = NULL;
2797         }
2798
2799         if (dc->out && dc->out->hotplug_init)
2800                 dc->out->hotplug_init();
2801
2802         if (dc->out_ops && dc->out_ops->detect)
2803                 dc->out_ops->detect(dc);
2804         else
2805                 dc->connected = true;
2806
2807         tegra_dc_create_sysfs(&dc->ndev->dev);
2808
2809         return 0;
2810
2811 err_free_irq:
2812         free_irq(irq, dc);
2813 err_put_emc_clk:
2814         clk_put(emc_clk);
2815 err_put_clk:
2816         clk_put(clk);
2817 err_iounmap_reg:
2818         iounmap(base);
2819         if (fb_mem)
2820                 release_resource(fb_mem);
2821 err_release_resource_reg:
2822         release_resource(base_res);
2823 err_free:
2824         kfree(dc);
2825
2826         return ret;
2827 }
2828
2829 static int tegra_dc_remove(struct nvhost_device *ndev)
2830 {
2831         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2832
2833         tegra_dc_remove_sysfs(&dc->ndev->dev);
2834         tegra_dc_remove_debugfs(dc);
2835
2836         if (dc->overlay) {
2837                 tegra_overlay_unregister(dc->overlay);
2838         }
2839
2840         if (dc->fb) {
2841                 tegra_fb_unregister(dc->fb);
2842                 if (dc->fb_mem)
2843                         release_resource(dc->fb_mem);
2844         }
2845
2846         tegra_dc_ext_disable(dc->ext);
2847
2848         if (dc->ext)
2849                 tegra_dc_ext_unregister(dc->ext);
2850
2851         if (dc->enabled)
2852                 _tegra_dc_disable(dc);
2853
2854         switch_dev_unregister(&dc->modeset_switch);
2855         free_irq(dc->irq, dc);
2856         clk_put(dc->emc_clk);
2857         clk_put(dc->clk);
2858         iounmap(dc->base);
2859         if (dc->fb_mem)
2860                 release_resource(dc->base_res);
2861         kfree(dc);
2862         tegra_dc_set(NULL, ndev->id);
2863         return 0;
2864 }
2865
2866 #ifdef CONFIG_PM
2867 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2868 {
2869         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2870
2871         dev_info(&ndev->dev, "suspend\n");
2872
2873         if (dc->overlay)
2874                 tegra_overlay_disable(dc->overlay);
2875
2876         tegra_dc_ext_disable(dc->ext);
2877
2878         mutex_lock(&dc->lock);
2879
2880         if (dc->out_ops && dc->out_ops->suspend)
2881                 dc->out_ops->suspend(dc);
2882
2883         if (dc->enabled) {
2884                 _tegra_dc_disable(dc);
2885
2886                 dc->suspended = true;
2887         }
2888
2889         if (dc->out && dc->out->postsuspend) {
2890                 dc->out->postsuspend();
2891                 msleep(100); /* avoid resume event due to voltage falling */
2892         }
2893
2894         mutex_unlock(&dc->lock);
2895
2896         return 0;
2897 }
2898
2899 static int tegra_dc_resume(struct nvhost_device *ndev)
2900 {
2901         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2902
2903         dev_info(&ndev->dev, "resume\n");
2904
2905         mutex_lock(&dc->lock);
2906         dc->suspended = false;
2907
2908         if (dc->enabled)
2909                 _tegra_dc_enable(dc);
2910
2911         if (dc->out && dc->out->hotplug_init)
2912                 dc->out->hotplug_init();
2913
2914         if (dc->out_ops && dc->out_ops->resume)
2915                 dc->out_ops->resume(dc);
2916         mutex_unlock(&dc->lock);
2917
2918         return 0;
2919 }
2920
2921 #endif /* CONFIG_PM */
2922
2923 extern int suspend_set(const char *val, struct kernel_param *kp)
2924 {
2925         if (!strcmp(val, "dump"))
2926                 dump_regs(tegra_dcs[0]);
2927 #ifdef CONFIG_PM
2928         else if (!strcmp(val, "suspend"))
2929                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2930         else if (!strcmp(val, "resume"))
2931                 tegra_dc_resume(tegra_dcs[0]->ndev);
2932 #endif
2933
2934         return 0;
2935 }
2936
2937 extern int suspend_get(char *buffer, struct kernel_param *kp)
2938 {
2939         return 0;
2940 }
2941
2942 int suspend;
2943
2944 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2945
2946 struct nvhost_driver tegra_dc_driver = {
2947         .driver = {
2948                 .name = "tegradc",
2949                 .owner = THIS_MODULE,
2950         },
2951         .probe = tegra_dc_probe,
2952         .remove = tegra_dc_remove,
2953 #ifdef CONFIG_PM
2954         .suspend = tegra_dc_suspend,
2955         .resume = tegra_dc_resume,
2956 #endif
2957 };
2958
2959 static int __init tegra_dc_module_init(void)
2960 {
2961         int ret = tegra_dc_ext_module_init();
2962         if (ret)
2963                 return ret;
2964         return nvhost_driver_register(&tegra_dc_driver);
2965 }
2966
2967 static void __exit tegra_dc_module_exit(void)
2968 {
2969         nvhost_driver_unregister(&tegra_dc_driver);
2970         tegra_dc_ext_module_exit();
2971 }
2972
2973 module_exit(tegra_dc_module_exit);
2974 module_init(tegra_dc_module_init);