video: tegra: dc: split dc.c into smaller files
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
62         .refresh = 60,
63         .xres = 640,
64         .yres = 480,
65         .pixclock = KHZ2PICOS(25200),
66         .hsync_len = 96,        /* h_sync_width */
67         .vsync_len = 2,         /* v_sync_width */
68         .left_margin = 48,      /* h_back_porch */
69         .upper_margin = 33,     /* v_back_porch */
70         .right_margin = 16,     /* h_front_porch */
71         .lower_margin = 10,     /* v_front_porch */
72         .vmode = 0,
73         .sync = 0,
74 };
75
76 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
77
78 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
79
80 DEFINE_MUTEX(tegra_dc_lock);
81 DEFINE_MUTEX(shared_lock);
82
83 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
84 {
85         if (!tegra_is_clk_enabled(dc->clk)) {
86                 clk_enable(dc->clk);
87                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
88         }
89 }
90
91 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
92 {
93         if (tegra_is_clk_enabled(dc->clk)) {
94                 clk_disable(dc->clk);
95                 tegra_dvfs_set_rate(dc->clk, 0);
96         }
97 }
98
99 #define DUMP_REG(a) do {                        \
100         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
101                  #a, a, tegra_dc_readl(dc, a));               \
102         print(data, buff);                                    \
103         } while (0)
104
105 #define print_underflow_info(dc) do {                 \
106         trace_printk("%s:Underflow stats: underflows : %llu, "      \
107                         "undeflows_a : %llu, "                          \
108                         "underflows_b : %llu, "                         \
109                         "underflows_c : %llu\n",                        \
110                         dc->ndev->name,                                 \
111                         dc->stats.underflows,                           \
112                         dc->stats.underflows_a, dc->stats.underflows_b, \
113                         dc->stats.underflows_c);                        \
114         } while (0)
115
116 static void _dump_regs(struct tegra_dc *dc, void *data,
117                        void (* print)(void *data, const char *str))
118 {
119         int i;
120         char buff[256];
121
122         tegra_dc_io_start(dc);
123         tegra_dc_clk_enable(dc);
124
125         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
126         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
127         DUMP_REG(DC_CMD_SIGNAL_RAISE);
128         DUMP_REG(DC_CMD_INT_STATUS);
129         DUMP_REG(DC_CMD_INT_MASK);
130         DUMP_REG(DC_CMD_INT_ENABLE);
131         DUMP_REG(DC_CMD_INT_TYPE);
132         DUMP_REG(DC_CMD_INT_POLARITY);
133         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
134         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
135         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
136         DUMP_REG(DC_CMD_STATE_ACCESS);
137         DUMP_REG(DC_CMD_STATE_CONTROL);
138         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
139         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
140
141         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
142         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
143         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
144         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
145         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
146         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
147         DUMP_REG(DC_DISP_REF_TO_SYNC);
148         DUMP_REG(DC_DISP_SYNC_WIDTH);
149         DUMP_REG(DC_DISP_BACK_PORCH);
150         DUMP_REG(DC_DISP_DISP_ACTIVE);
151         DUMP_REG(DC_DISP_FRONT_PORCH);
152         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
153         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
154         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
155         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
156         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
157         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
158         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
159         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
160         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
161         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
162         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
163         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
164         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
165         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
166         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
167         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
168         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
169         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
170         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
171         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
172         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
173         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
174         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
175         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
176         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
177         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
178         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
179         DUMP_REG(DC_DISP_M0_CONTROL);
180         DUMP_REG(DC_DISP_M1_CONTROL);
181         DUMP_REG(DC_DISP_DI_CONTROL);
182         DUMP_REG(DC_DISP_PP_CONTROL);
183         DUMP_REG(DC_DISP_PP_SELECT_A);
184         DUMP_REG(DC_DISP_PP_SELECT_B);
185         DUMP_REG(DC_DISP_PP_SELECT_C);
186         DUMP_REG(DC_DISP_PP_SELECT_D);
187         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
188         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
189         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
190         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
191         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
192         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
193         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
194         DUMP_REG(DC_DISP_BORDER_COLOR);
195         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
196         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
197         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
198         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
199         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
200         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
201         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
202         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
203         DUMP_REG(DC_DISP_CURSOR_POSITION);
204         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
205         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
206         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
207         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
208         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
209         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
210         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
211         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
212         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
213         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
214         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
215         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
216         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
217
218
219         for (i = 0; i < 3; i++) {
220                 print(data, "\n");
221                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
222                 print(data, buff);
223
224                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
225                                 DC_CMD_DISPLAY_WINDOW_HEADER);
226                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
227                 DUMP_REG(DC_WIN_WIN_OPTIONS);
228                 DUMP_REG(DC_WIN_BYTE_SWAP);
229                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
230                 DUMP_REG(DC_WIN_COLOR_DEPTH);
231                 DUMP_REG(DC_WIN_POSITION);
232                 DUMP_REG(DC_WIN_SIZE);
233                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
234                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
235                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
236                 DUMP_REG(DC_WIN_DDA_INCREMENT);
237                 DUMP_REG(DC_WIN_LINE_STRIDE);
238                 DUMP_REG(DC_WIN_BUF_STRIDE);
239                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
240                 DUMP_REG(DC_WIN_BLEND_NOKEY);
241                 DUMP_REG(DC_WIN_BLEND_1WIN);
242                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
243                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
244                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
245                 DUMP_REG(DC_WINBUF_START_ADDR);
246                 DUMP_REG(DC_WINBUF_START_ADDR_U);
247                 DUMP_REG(DC_WINBUF_START_ADDR_V);
248                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
249                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
250                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
251                 DUMP_REG(DC_WIN_CSC_YOF);
252                 DUMP_REG(DC_WIN_CSC_KYRGB);
253                 DUMP_REG(DC_WIN_CSC_KUR);
254                 DUMP_REG(DC_WIN_CSC_KVR);
255                 DUMP_REG(DC_WIN_CSC_KUG);
256                 DUMP_REG(DC_WIN_CSC_KVG);
257                 DUMP_REG(DC_WIN_CSC_KUB);
258                 DUMP_REG(DC_WIN_CSC_KVB);
259         }
260
261         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
262         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
263         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
264         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
265         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
266         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
267         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
268         DUMP_REG(DC_DISP_M1_CONTROL);
269         DUMP_REG(DC_COM_PM1_CONTROL);
270         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
271         DUMP_REG(DC_DISP_SD_CONTROL);
272
273         tegra_dc_clk_disable(dc);
274         tegra_dc_io_end(dc);
275 }
276
277 #undef DUMP_REG
278
279 #ifdef DEBUG
280 static void dump_regs_print(void *data, const char *str)
281 {
282         struct tegra_dc *dc = data;
283         dev_dbg(&dc->ndev->dev, "%s", str);
284 }
285
286 static void dump_regs(struct tegra_dc *dc)
287 {
288         _dump_regs(dc, dc, dump_regs_print);
289 }
290 #else /* !DEBUG */
291
292 static void dump_regs(struct tegra_dc *dc) {}
293
294 #endif /* DEBUG */
295
296 #ifdef CONFIG_DEBUG_FS
297
298 static void dbg_regs_print(void *data, const char *str)
299 {
300         struct seq_file *s = data;
301
302         seq_printf(s, "%s", str);
303 }
304
305 #undef DUMP_REG
306
307 static int dbg_dc_show(struct seq_file *s, void *unused)
308 {
309         struct tegra_dc *dc = s->private;
310
311         _dump_regs(dc, s, dbg_regs_print);
312
313         return 0;
314 }
315
316
317 static int dbg_dc_open(struct inode *inode, struct file *file)
318 {
319         return single_open(file, dbg_dc_show, inode->i_private);
320 }
321
322 static const struct file_operations regs_fops = {
323         .open           = dbg_dc_open,
324         .read           = seq_read,
325         .llseek         = seq_lseek,
326         .release        = single_release,
327 };
328
329 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
330 {
331         struct tegra_dc *dc = s->private;
332         struct tegra_dc_mode *m;
333
334         mutex_lock(&dc->lock);
335         m = &dc->mode;
336         seq_printf(s,
337                 "pclk: %d\n"
338                 "h_ref_to_sync: %d\n"
339                 "v_ref_to_sync: %d\n"
340                 "h_sync_width: %d\n"
341                 "v_sync_width: %d\n"
342                 "h_back_porch: %d\n"
343                 "v_back_porch: %d\n"
344                 "h_active: %d\n"
345                 "v_active: %d\n"
346                 "h_front_porch: %d\n"
347                 "v_front_porch: %d\n"
348                 "stereo_mode: %d\n",
349                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
350                 m->h_sync_width, m->v_sync_width,
351                 m->h_back_porch, m->v_back_porch,
352                 m->h_active, m->v_active,
353                 m->h_front_porch, m->v_front_porch,
354                 m->stereo_mode);
355         mutex_unlock(&dc->lock);
356         return 0;
357 }
358
359 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
360 {
361         return single_open(file, dbg_dc_mode_show, inode->i_private);
362 }
363
364 static const struct file_operations mode_fops = {
365         .open           = dbg_dc_mode_open,
366         .read           = seq_read,
367         .llseek         = seq_lseek,
368         .release        = single_release,
369 };
370
371 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
372 {
373         struct tegra_dc *dc = s->private;
374
375         mutex_lock(&dc->lock);
376         seq_printf(s,
377                 "underflows: %llu\n"
378                 "underflows_a: %llu\n"
379                 "underflows_b: %llu\n"
380                 "underflows_c: %llu\n",
381                 dc->stats.underflows,
382                 dc->stats.underflows_a,
383                 dc->stats.underflows_b,
384                 dc->stats.underflows_c);
385         mutex_unlock(&dc->lock);
386
387         return 0;
388 }
389
390 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
391 {
392         return single_open(file, dbg_dc_stats_show, inode->i_private);
393 }
394
395 static const struct file_operations stats_fops = {
396         .open           = dbg_dc_stats_open,
397         .read           = seq_read,
398         .llseek         = seq_lseek,
399         .release        = single_release,
400 };
401
402 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
403 {
404         if (dc->debugdir)
405                 debugfs_remove_recursive(dc->debugdir);
406         dc->debugdir = NULL;
407 }
408
409 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
410 {
411         struct dentry *retval;
412
413         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
414         if (!dc->debugdir)
415                 goto remove_out;
416
417         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
418                 &regs_fops);
419         if (!retval)
420                 goto remove_out;
421
422         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
423                 &mode_fops);
424         if (!retval)
425                 goto remove_out;
426
427         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
428                 &stats_fops);
429         if (!retval)
430                 goto remove_out;
431
432         return;
433 remove_out:
434         dev_err(&dc->ndev->dev, "could not create debugfs\n");
435         tegra_dc_remove_debugfs(dc);
436 }
437
438 #else /* !CONFIG_DEBUGFS */
439 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
440 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
441 #endif /* CONFIG_DEBUGFS */
442
443 static int tegra_dc_set(struct tegra_dc *dc, int index)
444 {
445         int ret = 0;
446
447         mutex_lock(&tegra_dc_lock);
448         if (index >= TEGRA_MAX_DC) {
449                 ret = -EINVAL;
450                 goto out;
451         }
452
453         if (dc != NULL && tegra_dcs[index] != NULL) {
454                 ret = -EBUSY;
455                 goto out;
456         }
457
458         tegra_dcs[index] = dc;
459
460 out:
461         mutex_unlock(&tegra_dc_lock);
462
463         return ret;
464 }
465
466 unsigned int tegra_dc_has_multiple_dc(void)
467 {
468         unsigned int idx;
469         unsigned int cnt = 0;
470         struct tegra_dc *dc;
471
472         mutex_lock(&tegra_dc_lock);
473         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
474                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
475         mutex_unlock(&tegra_dc_lock);
476
477         return (cnt > 1);
478 }
479
480 /* get the stride size of a window.
481  * return: stride size in bytes for window win. or 0 if unavailble. */
482 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
483 {
484         u32 stride;
485
486         if (!dc->enabled)
487                 return 0;
488         BUG_ON(win > DC_N_WINDOWS);
489         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
490                 DC_CMD_DISPLAY_WINDOW_HEADER);
491         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
492         return GET_LINE_STRIDE(stride);
493 }
494 EXPORT_SYMBOL(tegra_dc_get_stride);
495
496 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
497 {
498         if (idx < TEGRA_MAX_DC)
499                 return tegra_dcs[idx];
500         else
501                 return NULL;
502 }
503 EXPORT_SYMBOL(tegra_dc_get_dc);
504
505 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
506 {
507         if (win >= dc->n_windows)
508                 return NULL;
509
510         return &dc->windows[win];
511 }
512 EXPORT_SYMBOL(tegra_dc_get_window);
513
514 bool tegra_dc_get_connected(struct tegra_dc *dc)
515 {
516         return dc->connected;
517 }
518 EXPORT_SYMBOL(tegra_dc_get_connected);
519
520 bool tegra_dc_hpd(struct tegra_dc *dc)
521 {
522         int sense;
523         int level;
524
525         level = gpio_get_value(dc->out->hotplug_gpio);
526
527         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
528
529         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
530                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
531 }
532 EXPORT_SYMBOL(tegra_dc_hpd);
533
534 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
535 {
536         unsigned i;
537         unsigned v0 = 128;
538         unsigned v1 = 0;
539         /* linear horizontal and vertical filters */
540         for (i = 0; i < 16; i++) {
541                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
542                                 DC_WIN_H_FILTER_P(i));
543
544                 tegra_dc_writel(dc, v0,
545                                 DC_WIN_V_FILTER_P(i));
546                 v0 -= 8;
547                 v1 += 8;
548         }
549 }
550
551 void tegra_dc_host_suspend(struct tegra_dc *dc)
552 {
553         tegra_dsi_host_suspend(dc);
554         tegra_dc_clk_disable(dc);
555 }
556
557 void tegra_dc_host_resume(struct tegra_dc *dc) {
558         tegra_dc_clk_enable(dc);
559         tegra_dsi_host_resume(dc);
560 }
561
562 static inline void disable_dc_irq(unsigned int irq)
563 {
564         disable_irq(irq);
565 }
566
567 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
568 {
569         return dc->syncpt[i].id;
570 }
571 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
572
573 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
574 {
575         u32 max;
576
577         mutex_lock(&dc->lock);
578         max = nvhost_syncpt_incr_max_ext(dc->ndev,
579                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
580         dc->syncpt[i].max = max;
581         mutex_unlock(&dc->lock);
582
583         return max;
584 }
585
586 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
587 {
588         mutex_lock(&dc->lock);
589         if ( dc->enabled )
590                 while (dc->syncpt[i].min < val) {
591                         dc->syncpt[i].min++;
592                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
593                 }
594         mutex_unlock(&dc->lock);
595 }
596
597 void
598 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
599 {
600         unsigned int ctrl;
601         unsigned long out_sel;
602         unsigned long cmd_state;
603
604         mutex_lock(&dc->lock);
605         if (!dc->enabled) {
606                 mutex_unlock(&dc->lock);
607                 return;
608         }
609
610         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
611                 tegra_dc_host_resume(dc);
612
613         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
614                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
615                 cfg->clk_select);
616
617         /* The new value should be effected immediately */
618         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
619         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
620
621         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
622                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
623         else
624                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
625
626         switch (cfg->which_pwm) {
627         case TEGRA_PWM_PM0:
628                 /* Select the LM0 on PM0 */
629                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
630                 out_sel &= ~(7 << 0);
631                 out_sel |= (3 << 0);
632                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
633                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
634                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
635                 break;
636         case TEGRA_PWM_PM1:
637                 /* Select the LM1 on PM1 */
638                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
639                 out_sel &= ~(7 << 4);
640                 out_sel |= (3 << 4);
641                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
642                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
643                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
644                 break;
645         default:
646                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
647                 break;
648         }
649         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
650         mutex_unlock(&dc->lock);
651 }
652 EXPORT_SYMBOL(tegra_dc_config_pwm);
653
654 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
655                                 const struct tegra_dc_out_pin *pins,
656                                 const unsigned int n_pins)
657 {
658         unsigned int i;
659
660         int name;
661         int pol;
662
663         u32 pol1, pol3;
664
665         u32 set1, unset1;
666         u32 set3, unset3;
667
668         set1 = set3 = unset1 = unset3 = 0;
669
670         for (i = 0; i < n_pins; i++) {
671                 name = (pins + i)->name;
672                 pol  = (pins + i)->pol;
673
674                 /* set polarity by name */
675                 switch (name) {
676                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
677                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
678                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
679                         else
680                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
681                         break;
682                 case TEGRA_DC_OUT_PIN_H_SYNC:
683                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
684                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
685                         else
686                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
687                         break;
688                 case TEGRA_DC_OUT_PIN_V_SYNC:
689                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
690                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
691                         else
692                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
693                         break;
694                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
695                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
696                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
697                         else
698                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
699                         break;
700                 default:
701                         printk("Invalid argument in function %s\n",
702                                __FUNCTION__);
703                         break;
704                 }
705         }
706
707         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
708         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
709
710         pol1 |= set1;
711         pol1 &= ~unset1;
712
713         pol3 |= set3;
714         pol3 &= ~unset3;
715
716         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
717         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
718 }
719
720 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
721 {
722         dc->out = out;
723
724         if (out->n_modes > 0)
725                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
726
727         switch (out->type) {
728         case TEGRA_DC_OUT_RGB:
729                 dc->out_ops = &tegra_dc_rgb_ops;
730                 break;
731
732         case TEGRA_DC_OUT_HDMI:
733                 dc->out_ops = &tegra_dc_hdmi_ops;
734                 break;
735
736         case TEGRA_DC_OUT_DSI:
737                 dc->out_ops = &tegra_dc_dsi_ops;
738                 break;
739
740         default:
741                 dc->out_ops = NULL;
742                 break;
743         }
744
745         if (dc->out_ops && dc->out_ops->init)
746                 dc->out_ops->init(dc);
747
748 }
749
750 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
751 {
752         if (dc->out)
753                 return dc->out->height;
754         else
755                 return 0;
756 }
757 EXPORT_SYMBOL(tegra_dc_get_out_height);
758
759 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
760 {
761         if (dc->out)
762                 return dc->out->width;
763         else
764                 return 0;
765 }
766 EXPORT_SYMBOL(tegra_dc_get_out_width);
767
768 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
769 {
770         if (dc->out && dc->out->max_pixclock)
771                 return dc->out->max_pixclock;
772         else
773                 return 0;
774 }
775 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
776
777 void tegra_dc_enable_crc(struct tegra_dc *dc)
778 {
779         u32 val;
780         tegra_dc_io_start(dc);
781
782         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
783                 CRC_ENABLE_ENABLE;
784         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
785         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
786         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
787 }
788
789 void tegra_dc_disable_crc(struct tegra_dc *dc)
790 {
791         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
792         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
793         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
794
795         tegra_dc_io_end(dc);
796 }
797
798 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
799 {
800         int crc = 0;
801
802         if (!dc) {
803                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
804                 goto crc_error;
805         }
806
807         /* TODO: Replace mdelay with code to sync VBlANK, since
808          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
809         mdelay(TEGRA_CRC_LATCHED_DELAY);
810
811         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
812 crc_error:
813         return crc;
814 }
815
816 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
817 {
818 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
819         u32 val;
820
821         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
822         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
823             return true;
824 #endif
825         return false;
826 }
827
828 static inline void enable_dc_irq(unsigned int irq)
829 {
830 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
831         enable_irq(irq);
832 #else
833         /* Always disable DC interrupts on FPGA. */
834         disable_irq(irq);
835 #endif
836 }
837
838 static void tegra_dc_vblank(struct work_struct *work)
839 {
840         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
841         bool nvsd_updated = false;
842
843         mutex_lock(&dc->lock);
844
845         if (!dc->enabled) {
846                 mutex_unlock(&dc->lock);
847                 return;
848         }
849
850         /* use the new frame's bandwidth setting instead of max(current, new),
851          * skip this if we're using tegra_dc_one_shot_worker() */
852         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
853                 tegra_dc_program_bandwidth(dc, true);
854
855         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
856         if (!tegra_dc_windows_are_dirty(dc))
857                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
858
859         /* Update the SD brightness */
860         if (dc->enabled && dc->out->sd_settings) {
861                 nvsd_updated = nvsd_update_brightness(dc);
862                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
863                  * V_BLANK_NVSD bit of vblank ref-count. */
864                 if (nvsd_updated) {
865                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
866                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
867                 } else {
868                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
869                 }
870         }
871
872         /* Mask vblank interrupt if ref-count is zero. */
873         if (!dc->vblank_ref_count)
874                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
875
876         mutex_unlock(&dc->lock);
877
878         /* Do the actual brightness update outside of the mutex */
879         if (nvsd_updated && dc->out->sd_settings &&
880             dc->out->sd_settings->bl_device) {
881
882                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
883                 struct backlight_device *bl = platform_get_drvdata(pdev);
884                 if (bl)
885                         backlight_update_status(bl);
886         }
887 }
888
889 static void tegra_dc_one_shot_worker(struct work_struct *work)
890 {
891         struct tegra_dc *dc = container_of(
892                 to_delayed_work(work), struct tegra_dc, one_shot_work);
893         mutex_lock(&dc->lock);
894
895         /* memory client has gone idle */
896         tegra_dc_clear_bandwidth(dc);
897
898         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
899                 tegra_dc_host_suspend(dc);
900
901         mutex_unlock(&dc->lock);
902 }
903
904 /* return an arbitrarily large number if count overflow occurs.
905  * make it a nice base-10 number to show up in stats output */
906 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
907 {
908         unsigned count = tegra_dc_readl(dc, reg);
909         tegra_dc_writel(dc, 0, reg);
910         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
911 }
912
913 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
914 {
915         u32 val;
916         int i;
917
918         dc->stats.underflows++;
919         if (dc->underflow_mask & WIN_A_UF_INT) {
920                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
921                         DC_WINBUF_AD_UFLOW_STATUS);
922                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
923         }
924         if (dc->underflow_mask & WIN_B_UF_INT) {
925                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
926                         DC_WINBUF_BD_UFLOW_STATUS);
927                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
928         }
929         if (dc->underflow_mask & WIN_C_UF_INT) {
930                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
931                         DC_WINBUF_CD_UFLOW_STATUS);
932                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
933         }
934
935         /* Check for any underflow reset conditions */
936         for (i = 0; i < DC_N_WINDOWS; i++) {
937                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
938                         dc->windows[i].underflows++;
939
940 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
941                         if (dc->windows[i].underflows > 4) {
942                                 schedule_work(&dc->reset_work);
943                                 /* reset counter */
944                                 dc->windows[i].underflows = 0;
945                                 trace_printk("%s:Reset work scheduled for "
946                                                 "window %c\n",
947                                                 dc->ndev->name, (65 + i));
948                         }
949 #endif
950 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
951                         if (dc->windows[i].underflows > 4) {
952                                 printk("%s:dc in underflow state."
953                                         " enable UF_LINE_FLUSH to clear up\n",
954                                         __func__);
955                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
956                                                 DC_DISP_DISP_MISC_CONTROL);
957                                 tegra_dc_writel(dc, GENERAL_UPDATE,
958                                                 DC_CMD_STATE_CONTROL);
959                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
960                                                 DC_CMD_STATE_CONTROL);
961
962                                 tegra_dc_writel(dc, 0,
963                                                 DC_DISP_DISP_MISC_CONTROL);
964                                 tegra_dc_writel(dc, GENERAL_UPDATE,
965                                                 DC_CMD_STATE_CONTROL);
966                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
967                                                 DC_CMD_STATE_CONTROL);
968                         }
969 #endif
970                 } else {
971                         dc->windows[i].underflows = 0;
972                 }
973         }
974
975         /* Clear the underflow mask now that we've checked it. */
976         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
977         dc->underflow_mask = 0;
978         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
979         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
980         print_underflow_info(dc);
981 }
982
983 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
984 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
985 {
986         if (status & V_BLANK_INT) {
987                 /* Sync up windows. */
988                 tegra_dc_trigger_windows(dc);
989
990                 /* Schedule any additional bottom-half vblank actvities. */
991                 schedule_work(&dc->vblank_work);
992         }
993
994         if (status & FRAME_END_INT) {
995                 /* Mark the frame_end as complete. */
996                 if (!completion_done(&dc->frame_end_complete))
997                         complete(&dc->frame_end_complete);
998         }
999 }
1000
1001 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1002 {
1003         /* Schedule any additional bottom-half vblank actvities. */
1004         if (status & V_BLANK_INT)
1005                 schedule_work(&dc->vblank_work);
1006
1007         if (status & FRAME_END_INT) {
1008                 /* Mark the frame_end as complete. */
1009                 if (!completion_done(&dc->frame_end_complete))
1010                         complete(&dc->frame_end_complete);
1011
1012                 tegra_dc_trigger_windows(dc);
1013         }
1014 }
1015 #endif
1016
1017 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1018 {
1019 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1020         struct tegra_dc *dc = ptr;
1021         unsigned long status;
1022         unsigned long underflow_mask;
1023         u32 val;
1024
1025         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1026                 WARN(1, "IRQ when DC not powered!\n");
1027                 tegra_dc_io_start(dc);
1028                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1029                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1030                 tegra_dc_io_end(dc);
1031                 return IRQ_HANDLED;
1032         }
1033
1034         /* clear all status flags except underflow, save those for the worker */
1035         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1036         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1037         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1038         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1039
1040         /*
1041          * Overlays can get thier internal state corrupted during and underflow
1042          * condition.  The only way to fix this state is to reset the DC.
1043          * if we get 4 consecutive frames with underflows, assume we're
1044          * hosed and reset.
1045          */
1046         underflow_mask = status & ALL_UF_INT;
1047
1048         /* Check underflow */
1049         if (underflow_mask) {
1050                 dc->underflow_mask |= underflow_mask;
1051                 schedule_delayed_work(&dc->underflow_work,
1052                         msecs_to_jiffies(1));
1053         }
1054
1055         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1056                 tegra_dc_one_shot_irq(dc, status);
1057         else
1058                 tegra_dc_continuous_irq(dc, status);
1059
1060         return IRQ_HANDLED;
1061 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1062         return IRQ_NONE;
1063 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1064 }
1065
1066 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1067 {
1068         u32 color_control;
1069
1070         switch (dc->out->depth) {
1071         case 3:
1072                 color_control = BASE_COLOR_SIZE111;
1073                 break;
1074
1075         case 6:
1076                 color_control = BASE_COLOR_SIZE222;
1077                 break;
1078
1079         case 8:
1080                 color_control = BASE_COLOR_SIZE332;
1081                 break;
1082
1083         case 9:
1084                 color_control = BASE_COLOR_SIZE333;
1085                 break;
1086
1087         case 12:
1088                 color_control = BASE_COLOR_SIZE444;
1089                 break;
1090
1091         case 15:
1092                 color_control = BASE_COLOR_SIZE555;
1093                 break;
1094
1095         case 16:
1096                 color_control = BASE_COLOR_SIZE565;
1097                 break;
1098
1099         case 18:
1100                 color_control = BASE_COLOR_SIZE666;
1101                 break;
1102
1103         default:
1104                 color_control = BASE_COLOR_SIZE888;
1105                 break;
1106         }
1107
1108         switch (dc->out->dither) {
1109         case TEGRA_DC_DISABLE_DITHER:
1110                 color_control |= DITHER_CONTROL_DISABLE;
1111                 break;
1112         case TEGRA_DC_ORDERED_DITHER:
1113                 color_control |= DITHER_CONTROL_ORDERED;
1114                 break;
1115         case TEGRA_DC_ERRDIFF_DITHER:
1116                 /* The line buffer for error-diffusion dither is limited
1117                  * to 1280 pixels per line. This limits the maximum
1118                  * horizontal active area size to 1280 pixels when error
1119                  * diffusion is enabled.
1120                  */
1121                 BUG_ON(dc->mode.h_active > 1280);
1122                 color_control |= DITHER_CONTROL_ERRDIFF;
1123                 break;
1124         }
1125
1126         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1127 }
1128
1129 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1130 {
1131         u32 syncpt_id;
1132
1133         switch (dc->ndev->id) {
1134         case 0:
1135                 switch (idx) {
1136                 case 0:
1137                         syncpt_id = NVSYNCPT_DISP0_A;
1138                         break;
1139                 case 1:
1140                         syncpt_id = NVSYNCPT_DISP0_B;
1141                         break;
1142                 case 2:
1143                         syncpt_id = NVSYNCPT_DISP0_C;
1144                         break;
1145                 default:
1146                         BUG();
1147                         break;
1148                 }
1149                 break;
1150         case 1:
1151                 switch (idx) {
1152                 case 0:
1153                         syncpt_id = NVSYNCPT_DISP1_A;
1154                         break;
1155                 case 1:
1156                         syncpt_id = NVSYNCPT_DISP1_B;
1157                         break;
1158                 case 2:
1159                         syncpt_id = NVSYNCPT_DISP1_C;
1160                         break;
1161                 default:
1162                         BUG();
1163                         break;
1164                 }
1165                 break;
1166         default:
1167                 BUG();
1168                 break;
1169         }
1170
1171         return syncpt_id;
1172 }
1173
1174 static int tegra_dc_init(struct tegra_dc *dc)
1175 {
1176         int i;
1177
1178         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1179         if (dc->ndev->id == 0) {
1180                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1181                                       TEGRA_MC_PRIO_MED);
1182                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1183                                       TEGRA_MC_PRIO_MED);
1184                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1185                                       TEGRA_MC_PRIO_MED);
1186                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1187                                       TEGRA_MC_PRIO_MED);
1188                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1189                                       TEGRA_MC_PRIO_HIGH);
1190         } else if (dc->ndev->id == 1) {
1191                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1192                                       TEGRA_MC_PRIO_MED);
1193                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1194                                       TEGRA_MC_PRIO_MED);
1195                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1196                                       TEGRA_MC_PRIO_MED);
1197                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1198                                       TEGRA_MC_PRIO_MED);
1199                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1200                                       TEGRA_MC_PRIO_HIGH);
1201         }
1202         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1203                         DC_CMD_CONT_SYNCPT_VSYNC);
1204         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1205         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1206         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1207         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1208 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1209         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1210 #endif
1211         /* enable interrupts for vblank, frame_end and underflows */
1212         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1213                 DC_CMD_INT_ENABLE);
1214         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1215
1216         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1217
1218         tegra_dc_set_color_control(dc);
1219         for (i = 0; i < DC_N_WINDOWS; i++) {
1220                 struct tegra_dc_win *win = &dc->windows[i];
1221                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1222                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1223                 tegra_dc_set_csc(dc, &win->csc);
1224                 tegra_dc_set_lut(dc, win);
1225                 tegra_dc_set_scaling_filter(dc);
1226         }
1227
1228
1229         for (i = 0; i < dc->n_windows; i++) {
1230                 u32 syncpt = get_syncpt(dc, i);
1231
1232                 dc->syncpt[i].id = syncpt;
1233
1234                 dc->syncpt[i].min = dc->syncpt[i].max =
1235                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1236         }
1237
1238         print_mode_info(dc, dc->mode);
1239
1240         if (dc->mode.pclk)
1241                 if (tegra_dc_program_mode(dc, &dc->mode))
1242                         return -EINVAL;
1243
1244         /* Initialize SD AFTER the modeset.
1245            nvsd_init handles the sd_settings = NULL case. */
1246         nvsd_init(dc, dc->out->sd_settings);
1247
1248         return 0;
1249 }
1250
1251 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1252 {
1253         int failed_init = 0;
1254
1255         if (dc->out->enable)
1256                 dc->out->enable();
1257
1258         tegra_dc_setup_clk(dc, dc->clk);
1259         tegra_dc_clk_enable(dc);
1260
1261         /* do not accept interrupts during initialization */
1262         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1263         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1264
1265         enable_dc_irq(dc->irq);
1266
1267         failed_init = tegra_dc_init(dc);
1268         if (failed_init) {
1269                 _tegra_dc_controller_disable(dc);
1270                 return false;
1271         }
1272
1273         if (dc->out_ops && dc->out_ops->enable)
1274                 dc->out_ops->enable(dc);
1275
1276         if (dc->out->postpoweron)
1277                 dc->out->postpoweron();
1278
1279         /* force a full blending update */
1280         dc->blend.z[0] = -1;
1281
1282         tegra_dc_ext_enable(dc->ext);
1283
1284         trace_printk("%s:enable\n", dc->ndev->name);
1285         return true;
1286 }
1287
1288 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1289 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1290 {
1291         bool ret = true;
1292
1293         if (dc->out->enable)
1294                 dc->out->enable();
1295
1296         tegra_dc_setup_clk(dc, dc->clk);
1297         tegra_dc_clk_enable(dc);
1298
1299         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1300                 mutex_lock(&tegra_dcs[1]->lock);
1301                 disable_irq(tegra_dcs[1]->irq);
1302         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1303                 mutex_lock(&tegra_dcs[0]->lock);
1304                 disable_irq(tegra_dcs[0]->irq);
1305         }
1306
1307         msleep(5);
1308         tegra_periph_reset_assert(dc->clk);
1309         msleep(2);
1310 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1311         tegra_periph_reset_deassert(dc->clk);
1312         msleep(1);
1313 #endif
1314
1315         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1316                 enable_dc_irq(tegra_dcs[1]->irq);
1317                 mutex_unlock(&tegra_dcs[1]->lock);
1318         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1319                 enable_dc_irq(tegra_dcs[0]->irq);
1320                 mutex_unlock(&tegra_dcs[0]->lock);
1321         }
1322
1323         enable_dc_irq(dc->irq);
1324
1325         if (tegra_dc_init(dc)) {
1326                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1327                 ret = false;
1328         }
1329
1330         if (dc->out_ops && dc->out_ops->enable)
1331                 dc->out_ops->enable(dc);
1332
1333         if (dc->out->postpoweron)
1334                 dc->out->postpoweron();
1335
1336         /* force a full blending update */
1337         dc->blend.z[0] = -1;
1338
1339         tegra_dc_ext_enable(dc->ext);
1340
1341         if (!ret) {
1342                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1343                 _tegra_dc_controller_disable(dc);
1344         }
1345
1346         trace_printk("%s:reset enable\n", dc->ndev->name);
1347         return ret;
1348 }
1349 #endif
1350
1351 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1352 {
1353         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1354 }
1355
1356 static bool _tegra_dc_enable(struct tegra_dc *dc)
1357 {
1358         if (dc->mode.pclk == 0) {
1359                 switch (dc->out->type) {
1360                 case TEGRA_DC_OUT_HDMI:
1361                 /* DC enable called but no videomode is loaded.
1362                      Check if HDMI is connected, then set fallback mdoe */
1363                 if (tegra_dc_hpd(dc)) {
1364                         if (_tegra_dc_set_default_videomode(dc))
1365                                 return false;
1366                 } else
1367                         return false;
1368
1369                 break;
1370
1371                 /* Do nothing for other outputs for now */
1372                 case TEGRA_DC_OUT_RGB:
1373
1374                 case TEGRA_DC_OUT_DSI:
1375
1376                 default:
1377                         return false;
1378                 }
1379         }
1380
1381         if (!dc->out)
1382                 return false;
1383
1384         tegra_dc_io_start(dc);
1385
1386         return _tegra_dc_controller_enable(dc);
1387 }
1388
1389 void tegra_dc_enable(struct tegra_dc *dc)
1390 {
1391         mutex_lock(&dc->lock);
1392
1393         if (!dc->enabled)
1394                 dc->enabled = _tegra_dc_enable(dc);
1395
1396         mutex_unlock(&dc->lock);
1397         print_mode_info(dc, dc->mode);
1398 }
1399
1400 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1401 {
1402         unsigned i;
1403
1404         if (dc->out && dc->out->prepoweroff)
1405                 dc->out->prepoweroff();
1406
1407         if (dc->out_ops && dc->out_ops->disable)
1408                 dc->out_ops->disable(dc);
1409
1410         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1411         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1412         disable_irq(dc->irq);
1413
1414         tegra_dc_clear_bandwidth(dc);
1415         tegra_dc_clk_disable(dc);
1416
1417         if (dc->out && dc->out->disable)
1418                 dc->out->disable();
1419
1420         for (i = 0; i < dc->n_windows; i++) {
1421                 struct tegra_dc_win *w = &dc->windows[i];
1422
1423                 /* reset window bandwidth */
1424                 w->bandwidth = 0;
1425                 w->new_bandwidth = 0;
1426
1427                 /* disable windows */
1428                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1429
1430                 /* flush any pending syncpt waits */
1431                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1432                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1433                                 dc->syncpt[i].id);
1434                         dc->syncpt[i].min++;
1435                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1436                 }
1437         }
1438         trace_printk("%s:disabled\n", dc->ndev->name);
1439 }
1440
1441 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1442 {
1443 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1444         u32 val;
1445         if (dc->enabled)  {
1446                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1447                 if (enable)
1448                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1449                 else
1450                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1451                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1452         }
1453 #endif
1454 }
1455
1456 bool tegra_dc_stats_get(struct tegra_dc *dc)
1457 {
1458 #if 0 /* right now it is always enabled */
1459         u32 val;
1460         bool res;
1461
1462         if (dc->enabled)  {
1463                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1464                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1465         } else {
1466                 res = false;
1467         }
1468
1469         return res;
1470 #endif
1471         return true;
1472 }
1473
1474 /* make the screen blank by disabling all windows */
1475 void tegra_dc_blank(struct tegra_dc *dc)
1476 {
1477         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1478         unsigned i;
1479
1480         for (i = 0; i < DC_N_WINDOWS; i++) {
1481                 dcwins[i] = tegra_dc_get_window(dc, i);
1482                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1483         }
1484
1485         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1486         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1487 }
1488
1489 static void _tegra_dc_disable(struct tegra_dc *dc)
1490 {
1491         _tegra_dc_controller_disable(dc);
1492         tegra_dc_io_end(dc);
1493 }
1494
1495 void tegra_dc_disable(struct tegra_dc *dc)
1496 {
1497         tegra_dc_ext_disable(dc->ext);
1498
1499         /* it's important that new underflow work isn't scheduled before the
1500          * lock is acquired. */
1501         cancel_delayed_work_sync(&dc->underflow_work);
1502         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1503                 mutex_lock(&dc->one_shot_lock);
1504                 cancel_delayed_work_sync(&dc->one_shot_work);
1505         }
1506
1507         mutex_lock(&dc->lock);
1508
1509         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1510                 tegra_dc_host_resume(dc);
1511
1512         if (dc->enabled) {
1513                 dc->enabled = false;
1514
1515                 if (!dc->suspended)
1516                         _tegra_dc_disable(dc);
1517         }
1518
1519 #ifdef CONFIG_SWITCH
1520         switch_set_state(&dc->modeset_switch, 0);
1521 #endif
1522
1523         mutex_unlock(&dc->lock);
1524         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1525                 mutex_unlock(&dc->one_shot_lock);
1526         print_mode_info(dc, dc->mode);
1527 }
1528
1529 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1530 static void tegra_dc_reset_worker(struct work_struct *work)
1531 {
1532         struct tegra_dc *dc =
1533                 container_of(work, struct tegra_dc, reset_work);
1534
1535         unsigned long val = 0;
1536
1537         mutex_lock(&shared_lock);
1538
1539         dev_warn(&dc->ndev->dev,
1540                 "overlay stuck in underflow state.  resetting.\n");
1541
1542         tegra_dc_ext_disable(dc->ext);
1543
1544         mutex_lock(&dc->lock);
1545
1546         if (dc->enabled == false)
1547                 goto unlock;
1548
1549         dc->enabled = false;
1550
1551         /*
1552          * off host read bus
1553          */
1554         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1555         val &= ~(0x00000100);
1556         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1557
1558         /*
1559          * set DC to STOP mode
1560          */
1561         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1562
1563         msleep(10);
1564
1565         _tegra_dc_controller_disable(dc);
1566
1567         /* _tegra_dc_controller_reset_enable deasserts reset */
1568         _tegra_dc_controller_reset_enable(dc);
1569
1570         dc->enabled = true;
1571
1572         /* reopen host read bus */
1573         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1574         val &= ~(0x00000100);
1575         val |= 0x100;
1576         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1577
1578 unlock:
1579         mutex_unlock(&dc->lock);
1580         mutex_unlock(&shared_lock);
1581         trace_printk("%s:reset complete\n", dc->ndev->name);
1582 }
1583 #endif
1584
1585 static void tegra_dc_underflow_worker(struct work_struct *work)
1586 {
1587         struct tegra_dc *dc = container_of(
1588                 to_delayed_work(work), struct tegra_dc, underflow_work);
1589
1590         mutex_lock(&dc->lock);
1591         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1592                 tegra_dc_host_resume(dc);
1593
1594         if (dc->enabled) {
1595                 tegra_dc_underflow_handler(dc);
1596         }
1597         mutex_unlock(&dc->lock);
1598 }
1599
1600 #ifdef CONFIG_SWITCH
1601 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1602 {
1603         struct tegra_dc *dc =
1604                 container_of(sdev, struct tegra_dc, modeset_switch);
1605
1606         if (!sdev->state)
1607                 return sprintf(buf, "offline\n");
1608
1609         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1610 }
1611 #endif
1612
1613 static int tegra_dc_probe(struct nvhost_device *ndev,
1614         struct nvhost_device_id *id_table)
1615 {
1616         struct tegra_dc *dc;
1617         struct clk *clk;
1618         struct clk *emc_clk;
1619         struct resource *res;
1620         struct resource *base_res;
1621         struct resource *fb_mem = NULL;
1622         int ret = 0;
1623         void __iomem *base;
1624         int irq;
1625         int i;
1626
1627         if (!ndev->dev.platform_data) {
1628                 dev_err(&ndev->dev, "no platform data\n");
1629                 return -ENOENT;
1630         }
1631
1632         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1633         if (!dc) {
1634                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1635                 return -ENOMEM;
1636         }
1637
1638         irq = nvhost_get_irq_byname(ndev, "irq");
1639         if (irq <= 0) {
1640                 dev_err(&ndev->dev, "no irq\n");
1641                 ret = -ENOENT;
1642                 goto err_free;
1643         }
1644
1645         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1646         if (!res) {
1647                 dev_err(&ndev->dev, "no mem resource\n");
1648                 ret = -ENOENT;
1649                 goto err_free;
1650         }
1651
1652         base_res = request_mem_region(res->start, resource_size(res),
1653                 ndev->name);
1654         if (!base_res) {
1655                 dev_err(&ndev->dev, "request_mem_region failed\n");
1656                 ret = -EBUSY;
1657                 goto err_free;
1658         }
1659
1660         base = ioremap(res->start, resource_size(res));
1661         if (!base) {
1662                 dev_err(&ndev->dev, "registers can't be mapped\n");
1663                 ret = -EBUSY;
1664                 goto err_release_resource_reg;
1665         }
1666
1667         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1668
1669         clk = clk_get(&ndev->dev, NULL);
1670         if (IS_ERR_OR_NULL(clk)) {
1671                 dev_err(&ndev->dev, "can't get clock\n");
1672                 ret = -ENOENT;
1673                 goto err_iounmap_reg;
1674         }
1675
1676         emc_clk = clk_get(&ndev->dev, "emc");
1677         if (IS_ERR_OR_NULL(emc_clk)) {
1678                 dev_err(&ndev->dev, "can't get emc clock\n");
1679                 ret = -ENOENT;
1680                 goto err_put_clk;
1681         }
1682
1683         dc->clk = clk;
1684         dc->emc_clk = emc_clk;
1685         dc->shift_clk_div = 1;
1686         /* Initialize one shot work delay, it will be assigned by dsi
1687          * according to refresh rate later. */
1688         dc->one_shot_delay_ms = 40;
1689
1690         dc->base_res = base_res;
1691         dc->base = base;
1692         dc->irq = irq;
1693         dc->ndev = ndev;
1694         dc->pdata = ndev->dev.platform_data;
1695
1696         /*
1697          * The emc is a shared clock, it will be set based on
1698          * the requirements for each user on the bus.
1699          */
1700         dc->emc_clk_rate = 0;
1701
1702         mutex_init(&dc->lock);
1703         mutex_init(&dc->one_shot_lock);
1704         init_completion(&dc->frame_end_complete);
1705         init_waitqueue_head(&dc->wq);
1706 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1707         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1708 #endif
1709         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1710         dc->vblank_ref_count = 0;
1711         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
1712         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
1713
1714         tegra_dc_init_lut_defaults(&dc->fb_lut);
1715
1716         dc->n_windows = DC_N_WINDOWS;
1717         for (i = 0; i < dc->n_windows; i++) {
1718                 struct tegra_dc_win *win = &dc->windows[i];
1719                 win->idx = i;
1720                 win->dc = dc;
1721                 tegra_dc_init_csc_defaults(&win->csc);
1722                 tegra_dc_init_lut_defaults(&win->lut);
1723         }
1724
1725         ret = tegra_dc_set(dc, ndev->id);
1726         if (ret < 0) {
1727                 dev_err(&ndev->dev, "can't add dc\n");
1728                 goto err_free_irq;
1729         }
1730
1731         nvhost_set_drvdata(ndev, dc);
1732
1733 #ifdef CONFIG_SWITCH
1734         dc->modeset_switch.name = dev_name(&ndev->dev);
1735         dc->modeset_switch.state = 0;
1736         dc->modeset_switch.print_state = switch_modeset_print_mode;
1737         switch_dev_register(&dc->modeset_switch);
1738 #endif
1739
1740         tegra_dc_feature_register(dc);
1741
1742         if (dc->pdata->default_out)
1743                 tegra_dc_set_out(dc, dc->pdata->default_out);
1744         else
1745                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1746
1747         dc->vblank_syncpt = (dc->ndev->id == 0) ?
1748                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
1749
1750         dc->ext = tegra_dc_ext_register(ndev, dc);
1751         if (IS_ERR_OR_NULL(dc->ext)) {
1752                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
1753                 dc->ext = NULL;
1754         }
1755
1756         mutex_lock(&dc->lock);
1757         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
1758                 dc->enabled = _tegra_dc_enable(dc);
1759         mutex_unlock(&dc->lock);
1760
1761         /* interrupt handler must be registered before tegra_fb_register() */
1762         if (request_irq(irq, tegra_dc_irq, 0,
1763                         dev_name(&ndev->dev), dc)) {
1764                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1765                 ret = -EBUSY;
1766                 goto err_put_emc_clk;
1767         }
1768
1769         tegra_dc_create_debugfs(dc);
1770
1771         dev_info(&ndev->dev, "probed\n");
1772
1773         if (dc->pdata->fb) {
1774                 if (dc->pdata->fb->bits_per_pixel == -1) {
1775                         unsigned long fmt;
1776                         tegra_dc_writel(dc,
1777                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1778                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1779
1780                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1781                         dc->pdata->fb->bits_per_pixel =
1782                                 tegra_dc_fmt_bpp(fmt);
1783                 }
1784
1785                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1786                 if (IS_ERR_OR_NULL(dc->fb))
1787                         dc->fb = NULL;
1788         }
1789
1790         if (dc->out && dc->out->hotplug_init)
1791                 dc->out->hotplug_init();
1792
1793         if (dc->out_ops && dc->out_ops->detect)
1794                 dc->out_ops->detect(dc);
1795         else
1796                 dc->connected = true;
1797
1798         tegra_dc_create_sysfs(&dc->ndev->dev);
1799
1800         return 0;
1801
1802 err_free_irq:
1803         free_irq(irq, dc);
1804 err_put_emc_clk:
1805         clk_put(emc_clk);
1806 err_put_clk:
1807         clk_put(clk);
1808 err_iounmap_reg:
1809         iounmap(base);
1810         if (fb_mem)
1811                 release_resource(fb_mem);
1812 err_release_resource_reg:
1813         release_resource(base_res);
1814 err_free:
1815         kfree(dc);
1816
1817         return ret;
1818 }
1819
1820 static int tegra_dc_remove(struct nvhost_device *ndev)
1821 {
1822         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1823
1824         tegra_dc_remove_sysfs(&dc->ndev->dev);
1825         tegra_dc_remove_debugfs(dc);
1826
1827         if (dc->fb) {
1828                 tegra_fb_unregister(dc->fb);
1829                 if (dc->fb_mem)
1830                         release_resource(dc->fb_mem);
1831         }
1832
1833         tegra_dc_ext_disable(dc->ext);
1834
1835         if (dc->ext)
1836                 tegra_dc_ext_unregister(dc->ext);
1837
1838         if (dc->enabled)
1839                 _tegra_dc_disable(dc);
1840
1841 #ifdef CONFIG_SWITCH
1842         switch_dev_unregister(&dc->modeset_switch);
1843 #endif
1844         free_irq(dc->irq, dc);
1845         clk_put(dc->emc_clk);
1846         clk_put(dc->clk);
1847         iounmap(dc->base);
1848         if (dc->fb_mem)
1849                 release_resource(dc->base_res);
1850         kfree(dc);
1851         tegra_dc_set(NULL, ndev->id);
1852         return 0;
1853 }
1854
1855 #ifdef CONFIG_PM
1856 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
1857 {
1858         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1859
1860         trace_printk("%s:suspend\n", dc->ndev->name);
1861         dev_info(&ndev->dev, "suspend\n");
1862
1863         tegra_dc_ext_disable(dc->ext);
1864
1865         mutex_lock(&dc->lock);
1866
1867         if (dc->out_ops && dc->out_ops->suspend)
1868                 dc->out_ops->suspend(dc);
1869
1870         if (dc->enabled) {
1871                 _tegra_dc_disable(dc);
1872
1873                 dc->suspended = true;
1874         }
1875
1876         if (dc->out && dc->out->postsuspend) {
1877                 dc->out->postsuspend();
1878                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
1879                         /*
1880                          * avoid resume event due to voltage falling
1881                          */
1882                         msleep(100);
1883         }
1884
1885         mutex_unlock(&dc->lock);
1886
1887         return 0;
1888 }
1889
1890 static int tegra_dc_resume(struct nvhost_device *ndev)
1891 {
1892         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1893
1894         trace_printk("%s:resume\n", dc->ndev->name);
1895         dev_info(&ndev->dev, "resume\n");
1896
1897         mutex_lock(&dc->lock);
1898         dc->suspended = false;
1899
1900         if (dc->enabled)
1901                 _tegra_dc_enable(dc);
1902
1903         if (dc->out && dc->out->hotplug_init)
1904                 dc->out->hotplug_init();
1905
1906         if (dc->out_ops && dc->out_ops->resume)
1907                 dc->out_ops->resume(dc);
1908         mutex_unlock(&dc->lock);
1909
1910         return 0;
1911 }
1912
1913 #endif /* CONFIG_PM */
1914
1915 static void tegra_dc_shutdown(struct nvhost_device *ndev)
1916 {
1917         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1918
1919         if (!dc || !dc->enabled)
1920                 return;
1921
1922         tegra_dc_blank(dc);
1923         tegra_dc_disable(dc);
1924 }
1925
1926 extern int suspend_set(const char *val, struct kernel_param *kp)
1927 {
1928         if (!strcmp(val, "dump"))
1929                 dump_regs(tegra_dcs[0]);
1930 #ifdef CONFIG_PM
1931         else if (!strcmp(val, "suspend"))
1932                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
1933         else if (!strcmp(val, "resume"))
1934                 tegra_dc_resume(tegra_dcs[0]->ndev);
1935 #endif
1936
1937         return 0;
1938 }
1939
1940 extern int suspend_get(char *buffer, struct kernel_param *kp)
1941 {
1942         return 0;
1943 }
1944
1945 int suspend;
1946
1947 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
1948
1949 struct nvhost_driver tegra_dc_driver = {
1950         .driver = {
1951                 .name = "tegradc",
1952                 .owner = THIS_MODULE,
1953         },
1954         .probe = tegra_dc_probe,
1955         .remove = tegra_dc_remove,
1956 #ifdef CONFIG_PM
1957         .suspend = tegra_dc_suspend,
1958         .resume = tegra_dc_resume,
1959 #endif
1960         .shutdown = tegra_dc_shutdown,
1961 };
1962
1963 static int __init tegra_dc_module_init(void)
1964 {
1965         int ret = tegra_dc_ext_module_init();
1966         if (ret)
1967                 return ret;
1968         return nvhost_driver_register(&tegra_dc_driver);
1969 }
1970
1971 static void __exit tegra_dc_module_exit(void)
1972 {
1973         nvhost_driver_unregister(&tegra_dc_driver);
1974         tegra_dc_ext_module_exit();
1975 }
1976
1977 module_exit(tegra_dc_module_exit);
1978 module_init(tegra_dc_module_init);