tegra: dc: Make data output along with pixel clock.
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
62         .refresh = 60,
63         .xres = 640,
64         .yres = 480,
65         .pixclock = KHZ2PICOS(25200),
66         .hsync_len = 96,        /* h_sync_width */
67         .vsync_len = 2,         /* v_sync_width */
68         .left_margin = 48,      /* h_back_porch */
69         .upper_margin = 33,     /* v_back_porch */
70         .right_margin = 16,     /* h_front_porch */
71         .lower_margin = 10,     /* v_front_porch */
72         .vmode = 0,
73         .sync = 0,
74 };
75
76 static struct tegra_dc_mode override_disp_mode[3];
77
78 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
79
80 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
81
82 DEFINE_MUTEX(tegra_dc_lock);
83 DEFINE_MUTEX(shared_lock);
84
85 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
86 {
87         if (!tegra_is_clk_enabled(dc->clk)) {
88                 clk_enable(dc->clk);
89                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
90         }
91 }
92
93 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
94 {
95         if (tegra_is_clk_enabled(dc->clk)) {
96                 clk_disable(dc->clk);
97                 tegra_dvfs_set_rate(dc->clk, 0);
98         }
99 }
100
101 #define DUMP_REG(a) do {                        \
102         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
103                  #a, a, tegra_dc_readl(dc, a));               \
104         print(data, buff);                                    \
105         } while (0)
106
107 #define print_underflow_info(dc) do {                 \
108         trace_printk("%s:Underflow stats: underflows : %llu, "      \
109                         "undeflows_a : %llu, "                          \
110                         "underflows_b : %llu, "                         \
111                         "underflows_c : %llu\n",                        \
112                         dc->ndev->name,                                 \
113                         dc->stats.underflows,                           \
114                         dc->stats.underflows_a, dc->stats.underflows_b, \
115                         dc->stats.underflows_c);                        \
116         } while (0)
117
118 static void _dump_regs(struct tegra_dc *dc, void *data,
119                        void (* print)(void *data, const char *str))
120 {
121         int i;
122         char buff[256];
123
124         tegra_dc_io_start(dc);
125         tegra_dc_clk_enable(dc);
126
127         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
128         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
129         DUMP_REG(DC_CMD_SIGNAL_RAISE);
130         DUMP_REG(DC_CMD_INT_STATUS);
131         DUMP_REG(DC_CMD_INT_MASK);
132         DUMP_REG(DC_CMD_INT_ENABLE);
133         DUMP_REG(DC_CMD_INT_TYPE);
134         DUMP_REG(DC_CMD_INT_POLARITY);
135         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
136         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
137         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
138         DUMP_REG(DC_CMD_STATE_ACCESS);
139         DUMP_REG(DC_CMD_STATE_CONTROL);
140         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
141         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
142
143         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
144         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
145         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
146         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
147         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
148         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
149         DUMP_REG(DC_DISP_REF_TO_SYNC);
150         DUMP_REG(DC_DISP_SYNC_WIDTH);
151         DUMP_REG(DC_DISP_BACK_PORCH);
152         DUMP_REG(DC_DISP_DISP_ACTIVE);
153         DUMP_REG(DC_DISP_FRONT_PORCH);
154         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
155         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
156         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
157         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
158         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
159         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
160         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
161         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
162         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
163         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
164         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
165         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
166         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
167         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
168         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
169         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
170         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
171         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
172         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
173         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
174         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
175         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
176         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
177         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
178         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
179         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
180         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
181         DUMP_REG(DC_DISP_M0_CONTROL);
182         DUMP_REG(DC_DISP_M1_CONTROL);
183         DUMP_REG(DC_DISP_DI_CONTROL);
184         DUMP_REG(DC_DISP_PP_CONTROL);
185         DUMP_REG(DC_DISP_PP_SELECT_A);
186         DUMP_REG(DC_DISP_PP_SELECT_B);
187         DUMP_REG(DC_DISP_PP_SELECT_C);
188         DUMP_REG(DC_DISP_PP_SELECT_D);
189         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
190         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
191         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
192         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
193         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
194         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
195         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
196         DUMP_REG(DC_DISP_BORDER_COLOR);
197         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
198         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
199         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
200         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
201         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
202         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
203         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
204         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
205         DUMP_REG(DC_DISP_CURSOR_POSITION);
206         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
207         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
208         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
209         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
210         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
211         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
212         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
213         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
214         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
215         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
216         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
217         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
218         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
219
220
221         for (i = 0; i < 3; i++) {
222                 print(data, "\n");
223                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
224                 print(data, buff);
225
226                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
227                                 DC_CMD_DISPLAY_WINDOW_HEADER);
228                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
229                 DUMP_REG(DC_WIN_WIN_OPTIONS);
230                 DUMP_REG(DC_WIN_BYTE_SWAP);
231                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
232                 DUMP_REG(DC_WIN_COLOR_DEPTH);
233                 DUMP_REG(DC_WIN_POSITION);
234                 DUMP_REG(DC_WIN_SIZE);
235                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
236                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
237                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
238                 DUMP_REG(DC_WIN_DDA_INCREMENT);
239                 DUMP_REG(DC_WIN_LINE_STRIDE);
240                 DUMP_REG(DC_WIN_BUF_STRIDE);
241                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
242                 DUMP_REG(DC_WIN_BLEND_NOKEY);
243                 DUMP_REG(DC_WIN_BLEND_1WIN);
244                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
245                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
246                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
247                 DUMP_REG(DC_WINBUF_START_ADDR);
248                 DUMP_REG(DC_WINBUF_START_ADDR_U);
249                 DUMP_REG(DC_WINBUF_START_ADDR_V);
250                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
251                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
252                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
253                 DUMP_REG(DC_WIN_CSC_YOF);
254                 DUMP_REG(DC_WIN_CSC_KYRGB);
255                 DUMP_REG(DC_WIN_CSC_KUR);
256                 DUMP_REG(DC_WIN_CSC_KVR);
257                 DUMP_REG(DC_WIN_CSC_KUG);
258                 DUMP_REG(DC_WIN_CSC_KVG);
259                 DUMP_REG(DC_WIN_CSC_KUB);
260                 DUMP_REG(DC_WIN_CSC_KVB);
261         }
262
263         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
264         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
265         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
266         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
267         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
268         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
269         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
270         DUMP_REG(DC_DISP_M1_CONTROL);
271         DUMP_REG(DC_COM_PM1_CONTROL);
272         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
273         DUMP_REG(DC_DISP_SD_CONTROL);
274
275         tegra_dc_clk_disable(dc);
276         tegra_dc_io_end(dc);
277 }
278
279 #undef DUMP_REG
280
281 #ifdef DEBUG
282 static void dump_regs_print(void *data, const char *str)
283 {
284         struct tegra_dc *dc = data;
285         dev_dbg(&dc->ndev->dev, "%s", str);
286 }
287
288 static void dump_regs(struct tegra_dc *dc)
289 {
290         _dump_regs(dc, dc, dump_regs_print);
291 }
292 #else /* !DEBUG */
293
294 static void dump_regs(struct tegra_dc *dc) {}
295
296 #endif /* DEBUG */
297
298 #ifdef CONFIG_DEBUG_FS
299
300 static void dbg_regs_print(void *data, const char *str)
301 {
302         struct seq_file *s = data;
303
304         seq_printf(s, "%s", str);
305 }
306
307 #undef DUMP_REG
308
309 static int dbg_dc_show(struct seq_file *s, void *unused)
310 {
311         struct tegra_dc *dc = s->private;
312
313         _dump_regs(dc, s, dbg_regs_print);
314
315         return 0;
316 }
317
318
319 static int dbg_dc_open(struct inode *inode, struct file *file)
320 {
321         return single_open(file, dbg_dc_show, inode->i_private);
322 }
323
324 static const struct file_operations regs_fops = {
325         .open           = dbg_dc_open,
326         .read           = seq_read,
327         .llseek         = seq_lseek,
328         .release        = single_release,
329 };
330
331 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
332 {
333         struct tegra_dc *dc = s->private;
334         struct tegra_dc_mode *m;
335
336         mutex_lock(&dc->lock);
337         m = &dc->mode;
338         seq_printf(s,
339                 "pclk: %d\n"
340                 "h_ref_to_sync: %d\n"
341                 "v_ref_to_sync: %d\n"
342                 "h_sync_width: %d\n"
343                 "v_sync_width: %d\n"
344                 "h_back_porch: %d\n"
345                 "v_back_porch: %d\n"
346                 "h_active: %d\n"
347                 "v_active: %d\n"
348                 "h_front_porch: %d\n"
349                 "v_front_porch: %d\n"
350                 "stereo_mode: %d\n",
351                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
352                 m->h_sync_width, m->v_sync_width,
353                 m->h_back_porch, m->v_back_porch,
354                 m->h_active, m->v_active,
355                 m->h_front_porch, m->v_front_porch,
356                 m->stereo_mode);
357         mutex_unlock(&dc->lock);
358         return 0;
359 }
360
361 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
362 {
363         return single_open(file, dbg_dc_mode_show, inode->i_private);
364 }
365
366 static const struct file_operations mode_fops = {
367         .open           = dbg_dc_mode_open,
368         .read           = seq_read,
369         .llseek         = seq_lseek,
370         .release        = single_release,
371 };
372
373 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
374 {
375         struct tegra_dc *dc = s->private;
376
377         mutex_lock(&dc->lock);
378         seq_printf(s,
379                 "underflows: %llu\n"
380                 "underflows_a: %llu\n"
381                 "underflows_b: %llu\n"
382                 "underflows_c: %llu\n",
383                 dc->stats.underflows,
384                 dc->stats.underflows_a,
385                 dc->stats.underflows_b,
386                 dc->stats.underflows_c);
387         mutex_unlock(&dc->lock);
388
389         return 0;
390 }
391
392 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
393 {
394         return single_open(file, dbg_dc_stats_show, inode->i_private);
395 }
396
397 static const struct file_operations stats_fops = {
398         .open           = dbg_dc_stats_open,
399         .read           = seq_read,
400         .llseek         = seq_lseek,
401         .release        = single_release,
402 };
403
404 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
405 {
406         if (dc->debugdir)
407                 debugfs_remove_recursive(dc->debugdir);
408         dc->debugdir = NULL;
409 }
410
411 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
412 {
413         struct dentry *retval;
414
415         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
416         if (!dc->debugdir)
417                 goto remove_out;
418
419         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
420                 &regs_fops);
421         if (!retval)
422                 goto remove_out;
423
424         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
425                 &mode_fops);
426         if (!retval)
427                 goto remove_out;
428
429         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
430                 &stats_fops);
431         if (!retval)
432                 goto remove_out;
433
434         return;
435 remove_out:
436         dev_err(&dc->ndev->dev, "could not create debugfs\n");
437         tegra_dc_remove_debugfs(dc);
438 }
439
440 #else /* !CONFIG_DEBUGFS */
441 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
442 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
443 #endif /* CONFIG_DEBUGFS */
444
445 static int tegra_dc_set(struct tegra_dc *dc, int index)
446 {
447         int ret = 0;
448
449         mutex_lock(&tegra_dc_lock);
450         if (index >= TEGRA_MAX_DC) {
451                 ret = -EINVAL;
452                 goto out;
453         }
454
455         if (dc != NULL && tegra_dcs[index] != NULL) {
456                 ret = -EBUSY;
457                 goto out;
458         }
459
460         tegra_dcs[index] = dc;
461
462 out:
463         mutex_unlock(&tegra_dc_lock);
464
465         return ret;
466 }
467
468 unsigned int tegra_dc_has_multiple_dc(void)
469 {
470         unsigned int idx;
471         unsigned int cnt = 0;
472         struct tegra_dc *dc;
473
474         mutex_lock(&tegra_dc_lock);
475         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
476                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
477         mutex_unlock(&tegra_dc_lock);
478
479         return (cnt > 1);
480 }
481
482 /* get the stride size of a window.
483  * return: stride size in bytes for window win. or 0 if unavailble. */
484 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
485 {
486         u32 stride;
487
488         if (!dc->enabled)
489                 return 0;
490         BUG_ON(win > DC_N_WINDOWS);
491         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
492                 DC_CMD_DISPLAY_WINDOW_HEADER);
493         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
494         return GET_LINE_STRIDE(stride);
495 }
496 EXPORT_SYMBOL(tegra_dc_get_stride);
497
498 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
499 {
500         if (idx < TEGRA_MAX_DC)
501                 return tegra_dcs[idx];
502         else
503                 return NULL;
504 }
505 EXPORT_SYMBOL(tegra_dc_get_dc);
506
507 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
508 {
509         if (win >= dc->n_windows)
510                 return NULL;
511
512         return &dc->windows[win];
513 }
514 EXPORT_SYMBOL(tegra_dc_get_window);
515
516 bool tegra_dc_get_connected(struct tegra_dc *dc)
517 {
518         return dc->connected;
519 }
520 EXPORT_SYMBOL(tegra_dc_get_connected);
521
522 bool tegra_dc_hpd(struct tegra_dc *dc)
523 {
524         int sense;
525         int level;
526
527         level = gpio_get_value(dc->out->hotplug_gpio);
528
529         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
530
531         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
532                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
533 }
534 EXPORT_SYMBOL(tegra_dc_hpd);
535
536 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
537 {
538         unsigned i;
539         unsigned v0 = 128;
540         unsigned v1 = 0;
541         /* linear horizontal and vertical filters */
542         for (i = 0; i < 16; i++) {
543                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
544                                 DC_WIN_H_FILTER_P(i));
545
546                 tegra_dc_writel(dc, v0,
547                                 DC_WIN_V_FILTER_P(i));
548                 v0 -= 8;
549                 v1 += 8;
550         }
551 }
552
553 void tegra_dc_host_suspend(struct tegra_dc *dc)
554 {
555         tegra_dsi_host_suspend(dc);
556         tegra_dc_clk_disable(dc);
557 }
558
559 void tegra_dc_host_resume(struct tegra_dc *dc) {
560         tegra_dc_clk_enable(dc);
561         tegra_dsi_host_resume(dc);
562 }
563
564 static inline void disable_dc_irq(unsigned int irq)
565 {
566         disable_irq(irq);
567 }
568
569 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
570 {
571         return dc->syncpt[i].id;
572 }
573 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
574
575 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
576 {
577         u32 max;
578
579         mutex_lock(&dc->lock);
580         max = nvhost_syncpt_incr_max_ext(dc->ndev,
581                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
582         dc->syncpt[i].max = max;
583         mutex_unlock(&dc->lock);
584
585         return max;
586 }
587
588 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
589 {
590         mutex_lock(&dc->lock);
591         if ( dc->enabled )
592                 while (dc->syncpt[i].min < val) {
593                         dc->syncpt[i].min++;
594                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
595                 }
596         mutex_unlock(&dc->lock);
597 }
598
599 void
600 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
601 {
602         unsigned int ctrl;
603         unsigned long out_sel;
604         unsigned long cmd_state;
605
606         mutex_lock(&dc->lock);
607         if (!dc->enabled) {
608                 mutex_unlock(&dc->lock);
609                 return;
610         }
611
612         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
613                 tegra_dc_host_resume(dc);
614
615         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
616                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
617                 cfg->clk_select);
618
619         /* The new value should be effected immediately */
620         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
621         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
622
623         switch (cfg->which_pwm) {
624         case TEGRA_PWM_PM0:
625                 /* Select the LM0 on PM0 */
626                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
627                 out_sel &= ~(7 << 0);
628                 out_sel |= (3 << 0);
629                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
630                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
631                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
632                 break;
633         case TEGRA_PWM_PM1:
634                 /* Select the LM1 on PM1 */
635                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
636                 out_sel &= ~(7 << 4);
637                 out_sel |= (3 << 4);
638                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
639                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
640                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
641                 break;
642         default:
643                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
644                 break;
645         }
646         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
647         mutex_unlock(&dc->lock);
648 }
649 EXPORT_SYMBOL(tegra_dc_config_pwm);
650
651 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
652                                 const struct tegra_dc_out_pin *pins,
653                                 const unsigned int n_pins)
654 {
655         unsigned int i;
656
657         int name;
658         int pol;
659
660         u32 pol1, pol3;
661
662         u32 set1, unset1;
663         u32 set3, unset3;
664
665         set1 = set3 = unset1 = unset3 = 0;
666
667         for (i = 0; i < n_pins; i++) {
668                 name = (pins + i)->name;
669                 pol  = (pins + i)->pol;
670
671                 /* set polarity by name */
672                 switch (name) {
673                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
674                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
675                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
676                         else
677                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
678                         break;
679                 case TEGRA_DC_OUT_PIN_H_SYNC:
680                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
681                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
682                         else
683                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
684                         break;
685                 case TEGRA_DC_OUT_PIN_V_SYNC:
686                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
687                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
688                         else
689                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
690                         break;
691                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
692                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
693                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
694                         else
695                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
696                         break;
697                 default:
698                         printk("Invalid argument in function %s\n",
699                                __FUNCTION__);
700                         break;
701                 }
702         }
703
704         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
705         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
706
707         pol1 |= set1;
708         pol1 &= ~unset1;
709
710         pol3 |= set3;
711         pol3 &= ~unset3;
712
713         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
714         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
715 }
716
717 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
718 {
719         if (dc->out->type == TEGRA_DC_OUT_RGB ||
720                 dc->out->type == TEGRA_DC_OUT_HDMI ||
721                 dc->out->type == TEGRA_DC_OUT_DSI)
722                 return override_disp_mode[dc->out->type].pclk ?
723                         &override_disp_mode[dc->out->type] : NULL;
724         else
725                 return NULL;
726 }
727
728 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
729 {
730         struct tegra_dc_mode *mode;
731
732         dc->out = out;
733         mode = tegra_dc_get_override_mode(dc);
734
735         if (mode)
736                 tegra_dc_set_mode(dc, mode);
737         else if (out->n_modes > 0)
738                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
739
740         switch (out->type) {
741         case TEGRA_DC_OUT_RGB:
742                 dc->out_ops = &tegra_dc_rgb_ops;
743                 break;
744
745         case TEGRA_DC_OUT_HDMI:
746                 dc->out_ops = &tegra_dc_hdmi_ops;
747                 break;
748
749         case TEGRA_DC_OUT_DSI:
750                 dc->out_ops = &tegra_dc_dsi_ops;
751                 break;
752
753         default:
754                 dc->out_ops = NULL;
755                 break;
756         }
757
758         if (dc->out_ops && dc->out_ops->init)
759                 dc->out_ops->init(dc);
760
761 }
762
763 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
764 {
765         if (dc->out)
766                 return dc->out->height;
767         else
768                 return 0;
769 }
770 EXPORT_SYMBOL(tegra_dc_get_out_height);
771
772 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
773 {
774         if (dc->out)
775                 return dc->out->width;
776         else
777                 return 0;
778 }
779 EXPORT_SYMBOL(tegra_dc_get_out_width);
780
781 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
782 {
783         if (dc->out && dc->out->max_pixclock)
784                 return dc->out->max_pixclock;
785         else
786                 return 0;
787 }
788 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
789
790 void tegra_dc_enable_crc(struct tegra_dc *dc)
791 {
792         u32 val;
793         tegra_dc_io_start(dc);
794
795         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
796                 CRC_ENABLE_ENABLE;
797         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
798         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
799         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
800 }
801
802 void tegra_dc_disable_crc(struct tegra_dc *dc)
803 {
804         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
805         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
806         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
807
808         tegra_dc_io_end(dc);
809 }
810
811 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
812 {
813         int crc = 0;
814
815         if (!dc) {
816                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
817                 goto crc_error;
818         }
819
820         /* TODO: Replace mdelay with code to sync VBlANK, since
821          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
822         mdelay(TEGRA_CRC_LATCHED_DELAY);
823
824         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
825 crc_error:
826         return crc;
827 }
828
829 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
830 {
831 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
832         u32 val;
833
834         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
835         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
836             return true;
837 #endif
838         return false;
839 }
840
841 static inline void enable_dc_irq(unsigned int irq)
842 {
843 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
844         enable_irq(irq);
845 #else
846         /* Always disable DC interrupts on FPGA. */
847         disable_irq(irq);
848 #endif
849 }
850
851 static void tegra_dc_vblank(struct work_struct *work)
852 {
853         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
854         bool nvsd_updated = false;
855
856         mutex_lock(&dc->lock);
857
858         if (!dc->enabled) {
859                 mutex_unlock(&dc->lock);
860                 return;
861         }
862
863         /* use the new frame's bandwidth setting instead of max(current, new),
864          * skip this if we're using tegra_dc_one_shot_worker() */
865         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
866                 tegra_dc_program_bandwidth(dc, true);
867
868         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
869         if (!tegra_dc_windows_are_dirty(dc))
870                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
871
872         /* Update the SD brightness */
873         if (dc->enabled && dc->out->sd_settings) {
874                 nvsd_updated = nvsd_update_brightness(dc);
875                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
876                  * V_BLANK_NVSD bit of vblank ref-count. */
877                 if (nvsd_updated) {
878                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
879                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
880                 } else {
881                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
882                 }
883         }
884
885         /* Mask vblank interrupt if ref-count is zero. */
886         if (!dc->vblank_ref_count)
887                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
888
889         mutex_unlock(&dc->lock);
890
891         /* Do the actual brightness update outside of the mutex */
892         if (nvsd_updated && dc->out->sd_settings &&
893             dc->out->sd_settings->bl_device) {
894
895                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
896                 struct backlight_device *bl = platform_get_drvdata(pdev);
897                 if (bl)
898                         backlight_update_status(bl);
899         }
900 }
901
902 static void tegra_dc_one_shot_worker(struct work_struct *work)
903 {
904         struct tegra_dc *dc = container_of(
905                 to_delayed_work(work), struct tegra_dc, one_shot_work);
906         mutex_lock(&dc->lock);
907
908         /* memory client has gone idle */
909         tegra_dc_clear_bandwidth(dc);
910
911         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
912                 tegra_dc_host_suspend(dc);
913
914         mutex_unlock(&dc->lock);
915 }
916
917 /* return an arbitrarily large number if count overflow occurs.
918  * make it a nice base-10 number to show up in stats output */
919 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
920 {
921         unsigned count = tegra_dc_readl(dc, reg);
922         tegra_dc_writel(dc, 0, reg);
923         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
924 }
925
926 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
927 {
928         u32 val;
929         int i;
930
931         dc->stats.underflows++;
932         if (dc->underflow_mask & WIN_A_UF_INT) {
933                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
934                         DC_WINBUF_AD_UFLOW_STATUS);
935                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
936         }
937         if (dc->underflow_mask & WIN_B_UF_INT) {
938                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
939                         DC_WINBUF_BD_UFLOW_STATUS);
940                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
941         }
942         if (dc->underflow_mask & WIN_C_UF_INT) {
943                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
944                         DC_WINBUF_CD_UFLOW_STATUS);
945                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
946         }
947
948         /* Check for any underflow reset conditions */
949         for (i = 0; i < DC_N_WINDOWS; i++) {
950                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
951                         dc->windows[i].underflows++;
952
953 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
954                         if (dc->windows[i].underflows > 4) {
955                                 schedule_work(&dc->reset_work);
956                                 /* reset counter */
957                                 dc->windows[i].underflows = 0;
958                                 trace_printk("%s:Reset work scheduled for "
959                                                 "window %c\n",
960                                                 dc->ndev->name, (65 + i));
961                         }
962 #endif
963 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
964                         if (dc->windows[i].underflows > 4) {
965                                 printk("%s:dc in underflow state."
966                                         " enable UF_LINE_FLUSH to clear up\n",
967                                         __func__);
968                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
969                                                 DC_DISP_DISP_MISC_CONTROL);
970                                 tegra_dc_writel(dc, GENERAL_UPDATE,
971                                                 DC_CMD_STATE_CONTROL);
972                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
973                                                 DC_CMD_STATE_CONTROL);
974
975                                 tegra_dc_writel(dc, 0,
976                                                 DC_DISP_DISP_MISC_CONTROL);
977                                 tegra_dc_writel(dc, GENERAL_UPDATE,
978                                                 DC_CMD_STATE_CONTROL);
979                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
980                                                 DC_CMD_STATE_CONTROL);
981                         }
982 #endif
983                 } else {
984                         dc->windows[i].underflows = 0;
985                 }
986         }
987
988         /* Clear the underflow mask now that we've checked it. */
989         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
990         dc->underflow_mask = 0;
991         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
992         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
993         print_underflow_info(dc);
994 }
995
996 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
997 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
998 {
999         if (status & V_BLANK_INT) {
1000                 /* Sync up windows. */
1001                 tegra_dc_trigger_windows(dc);
1002
1003                 /* Schedule any additional bottom-half vblank actvities. */
1004                 queue_work(system_freezable_wq, &dc->vblank_work);
1005         }
1006
1007         if (status & FRAME_END_INT) {
1008                 /* Mark the frame_end as complete. */
1009                 if (!completion_done(&dc->frame_end_complete))
1010                         complete(&dc->frame_end_complete);
1011         }
1012 }
1013
1014 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1015 {
1016         /* Schedule any additional bottom-half vblank actvities. */
1017         if (status & V_BLANK_INT)
1018                 queue_work(system_freezable_wq, &dc->vblank_work);
1019
1020         if (status & FRAME_END_INT) {
1021                 /* Mark the frame_end as complete. */
1022                 if (!completion_done(&dc->frame_end_complete))
1023                         complete(&dc->frame_end_complete);
1024
1025                 tegra_dc_trigger_windows(dc);
1026         }
1027 }
1028 #endif
1029
1030 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1031 {
1032 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1033         struct tegra_dc *dc = ptr;
1034         unsigned long status;
1035         unsigned long underflow_mask;
1036         u32 val;
1037
1038         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1039                 WARN(1, "IRQ when DC not powered!\n");
1040                 tegra_dc_io_start(dc);
1041                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1042                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1043                 tegra_dc_io_end(dc);
1044                 return IRQ_HANDLED;
1045         }
1046
1047         /* clear all status flags except underflow, save those for the worker */
1048         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1049         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1050         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1051         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1052
1053         /*
1054          * Overlays can get thier internal state corrupted during and underflow
1055          * condition.  The only way to fix this state is to reset the DC.
1056          * if we get 4 consecutive frames with underflows, assume we're
1057          * hosed and reset.
1058          */
1059         underflow_mask = status & ALL_UF_INT;
1060
1061         /* Check underflow */
1062         if (underflow_mask) {
1063                 dc->underflow_mask |= underflow_mask;
1064                 schedule_delayed_work(&dc->underflow_work,
1065                         msecs_to_jiffies(1));
1066         }
1067
1068         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1069                 tegra_dc_one_shot_irq(dc, status);
1070         else
1071                 tegra_dc_continuous_irq(dc, status);
1072
1073         return IRQ_HANDLED;
1074 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1075         return IRQ_NONE;
1076 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1077 }
1078
1079 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1080 {
1081         u32 color_control;
1082
1083         switch (dc->out->depth) {
1084         case 3:
1085                 color_control = BASE_COLOR_SIZE111;
1086                 break;
1087
1088         case 6:
1089                 color_control = BASE_COLOR_SIZE222;
1090                 break;
1091
1092         case 8:
1093                 color_control = BASE_COLOR_SIZE332;
1094                 break;
1095
1096         case 9:
1097                 color_control = BASE_COLOR_SIZE333;
1098                 break;
1099
1100         case 12:
1101                 color_control = BASE_COLOR_SIZE444;
1102                 break;
1103
1104         case 15:
1105                 color_control = BASE_COLOR_SIZE555;
1106                 break;
1107
1108         case 16:
1109                 color_control = BASE_COLOR_SIZE565;
1110                 break;
1111
1112         case 18:
1113                 color_control = BASE_COLOR_SIZE666;
1114                 break;
1115
1116         default:
1117                 color_control = BASE_COLOR_SIZE888;
1118                 break;
1119         }
1120
1121         switch (dc->out->dither) {
1122         case TEGRA_DC_DISABLE_DITHER:
1123                 color_control |= DITHER_CONTROL_DISABLE;
1124                 break;
1125         case TEGRA_DC_ORDERED_DITHER:
1126                 color_control |= DITHER_CONTROL_ORDERED;
1127                 break;
1128         case TEGRA_DC_ERRDIFF_DITHER:
1129                 /* The line buffer for error-diffusion dither is limited
1130                  * to 1280 pixels per line. This limits the maximum
1131                  * horizontal active area size to 1280 pixels when error
1132                  * diffusion is enabled.
1133                  */
1134                 BUG_ON(dc->mode.h_active > 1280);
1135                 color_control |= DITHER_CONTROL_ERRDIFF;
1136                 break;
1137         }
1138
1139         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1140 }
1141
1142 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1143 {
1144         u32 syncpt_id;
1145
1146         switch (dc->ndev->id) {
1147         case 0:
1148                 switch (idx) {
1149                 case 0:
1150                         syncpt_id = NVSYNCPT_DISP0_A;
1151                         break;
1152                 case 1:
1153                         syncpt_id = NVSYNCPT_DISP0_B;
1154                         break;
1155                 case 2:
1156                         syncpt_id = NVSYNCPT_DISP0_C;
1157                         break;
1158                 default:
1159                         BUG();
1160                         break;
1161                 }
1162                 break;
1163         case 1:
1164                 switch (idx) {
1165                 case 0:
1166                         syncpt_id = NVSYNCPT_DISP1_A;
1167                         break;
1168                 case 1:
1169                         syncpt_id = NVSYNCPT_DISP1_B;
1170                         break;
1171                 case 2:
1172                         syncpt_id = NVSYNCPT_DISP1_C;
1173                         break;
1174                 default:
1175                         BUG();
1176                         break;
1177                 }
1178                 break;
1179         default:
1180                 BUG();
1181                 break;
1182         }
1183
1184         return syncpt_id;
1185 }
1186
1187 static int tegra_dc_init(struct tegra_dc *dc)
1188 {
1189         int i;
1190
1191         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1192         if (dc->ndev->id == 0) {
1193                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1194                                       TEGRA_MC_PRIO_MED);
1195                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1196                                       TEGRA_MC_PRIO_MED);
1197                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1198                                       TEGRA_MC_PRIO_MED);
1199                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1200                                       TEGRA_MC_PRIO_MED);
1201                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1202                                       TEGRA_MC_PRIO_HIGH);
1203         } else if (dc->ndev->id == 1) {
1204                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1205                                       TEGRA_MC_PRIO_MED);
1206                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1207                                       TEGRA_MC_PRIO_MED);
1208                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1209                                       TEGRA_MC_PRIO_MED);
1210                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1211                                       TEGRA_MC_PRIO_MED);
1212                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1213                                       TEGRA_MC_PRIO_HIGH);
1214         }
1215         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1216                         DC_CMD_CONT_SYNCPT_VSYNC);
1217         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1218         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1219         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1220         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1221 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1222         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1223 #endif
1224         /* enable interrupts for vblank, frame_end and underflows */
1225         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1226                 DC_CMD_INT_ENABLE);
1227         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1228
1229         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1230
1231         tegra_dc_set_color_control(dc);
1232         for (i = 0; i < DC_N_WINDOWS; i++) {
1233                 struct tegra_dc_win *win = &dc->windows[i];
1234                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1235                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1236                 tegra_dc_set_csc(dc, &win->csc);
1237                 tegra_dc_set_lut(dc, win);
1238                 tegra_dc_set_scaling_filter(dc);
1239         }
1240
1241
1242         for (i = 0; i < dc->n_windows; i++) {
1243                 u32 syncpt = get_syncpt(dc, i);
1244
1245                 dc->syncpt[i].id = syncpt;
1246
1247                 dc->syncpt[i].min = dc->syncpt[i].max =
1248                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1249         }
1250
1251         print_mode_info(dc, dc->mode);
1252
1253         if (dc->mode.pclk)
1254                 if (tegra_dc_program_mode(dc, &dc->mode))
1255                         return -EINVAL;
1256
1257         /* Initialize SD AFTER the modeset.
1258            nvsd_init handles the sd_settings = NULL case. */
1259         nvsd_init(dc, dc->out->sd_settings);
1260
1261         return 0;
1262 }
1263
1264 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1265 {
1266         int failed_init = 0;
1267
1268         if (dc->out->enable)
1269                 dc->out->enable();
1270
1271         tegra_dc_setup_clk(dc, dc->clk);
1272         tegra_dc_clk_enable(dc);
1273
1274         /* do not accept interrupts during initialization */
1275         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1276         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1277
1278         enable_dc_irq(dc->irq);
1279
1280         failed_init = tegra_dc_init(dc);
1281         if (failed_init) {
1282                 _tegra_dc_controller_disable(dc);
1283                 return false;
1284         }
1285
1286         if (dc->out_ops && dc->out_ops->enable)
1287                 dc->out_ops->enable(dc);
1288
1289         /* force a full blending update */
1290         dc->blend.z[0] = -1;
1291
1292         tegra_dc_ext_enable(dc->ext);
1293
1294         trace_printk("%s:enable\n", dc->ndev->name);
1295
1296         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1297         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1298
1299         if (dc->out->postpoweron)
1300                 dc->out->postpoweron();
1301
1302         return true;
1303 }
1304
1305 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1306 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1307 {
1308         bool ret = true;
1309
1310         if (dc->out->enable)
1311                 dc->out->enable();
1312
1313         tegra_dc_setup_clk(dc, dc->clk);
1314         tegra_dc_clk_enable(dc);
1315
1316         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1317                 mutex_lock(&tegra_dcs[1]->lock);
1318                 disable_irq(tegra_dcs[1]->irq);
1319         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1320                 mutex_lock(&tegra_dcs[0]->lock);
1321                 disable_irq(tegra_dcs[0]->irq);
1322         }
1323
1324         msleep(5);
1325         tegra_periph_reset_assert(dc->clk);
1326         msleep(2);
1327 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1328         tegra_periph_reset_deassert(dc->clk);
1329         msleep(1);
1330 #endif
1331
1332         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1333                 enable_dc_irq(tegra_dcs[1]->irq);
1334                 mutex_unlock(&tegra_dcs[1]->lock);
1335         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1336                 enable_dc_irq(tegra_dcs[0]->irq);
1337                 mutex_unlock(&tegra_dcs[0]->lock);
1338         }
1339
1340         enable_dc_irq(dc->irq);
1341
1342         if (tegra_dc_init(dc)) {
1343                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1344                 ret = false;
1345         }
1346
1347         if (dc->out_ops && dc->out_ops->enable)
1348                 dc->out_ops->enable(dc);
1349
1350         if (dc->out->postpoweron)
1351                 dc->out->postpoweron();
1352
1353         /* force a full blending update */
1354         dc->blend.z[0] = -1;
1355
1356         tegra_dc_ext_enable(dc->ext);
1357
1358         if (!ret) {
1359                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1360                 _tegra_dc_controller_disable(dc);
1361         }
1362
1363         trace_printk("%s:reset enable\n", dc->ndev->name);
1364         return ret;
1365 }
1366 #endif
1367
1368 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1369 {
1370         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1371 }
1372
1373 static bool _tegra_dc_enable(struct tegra_dc *dc)
1374 {
1375         if (dc->mode.pclk == 0) {
1376                 switch (dc->out->type) {
1377                 case TEGRA_DC_OUT_HDMI:
1378                 /* DC enable called but no videomode is loaded.
1379                      Check if HDMI is connected, then set fallback mdoe */
1380                 if (tegra_dc_hpd(dc)) {
1381                         if (_tegra_dc_set_default_videomode(dc))
1382                                 return false;
1383                 } else
1384                         return false;
1385
1386                 break;
1387
1388                 /* Do nothing for other outputs for now */
1389                 case TEGRA_DC_OUT_RGB:
1390
1391                 case TEGRA_DC_OUT_DSI:
1392
1393                 default:
1394                         return false;
1395                 }
1396         }
1397
1398         if (!dc->out)
1399                 return false;
1400
1401         tegra_dc_io_start(dc);
1402
1403         return _tegra_dc_controller_enable(dc);
1404 }
1405
1406 void tegra_dc_enable(struct tegra_dc *dc)
1407 {
1408         mutex_lock(&dc->lock);
1409
1410         if (!dc->enabled)
1411                 dc->enabled = _tegra_dc_enable(dc);
1412
1413         mutex_unlock(&dc->lock);
1414         print_mode_info(dc, dc->mode);
1415 }
1416
1417 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1418 {
1419         unsigned i;
1420
1421         if (dc->out && dc->out->prepoweroff)
1422                 dc->out->prepoweroff();
1423
1424         if (dc->out_ops && dc->out_ops->disable)
1425                 dc->out_ops->disable(dc);
1426
1427         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1428         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1429         disable_irq(dc->irq);
1430
1431         tegra_dc_clear_bandwidth(dc);
1432         tegra_dc_clk_disable(dc);
1433
1434         if (dc->out && dc->out->disable)
1435                 dc->out->disable();
1436
1437         for (i = 0; i < dc->n_windows; i++) {
1438                 struct tegra_dc_win *w = &dc->windows[i];
1439
1440                 /* reset window bandwidth */
1441                 w->bandwidth = 0;
1442                 w->new_bandwidth = 0;
1443
1444                 /* disable windows */
1445                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1446
1447                 /* flush any pending syncpt waits */
1448                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1449                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1450                                 dc->syncpt[i].id);
1451                         dc->syncpt[i].min++;
1452                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1453                 }
1454         }
1455         trace_printk("%s:disabled\n", dc->ndev->name);
1456 }
1457
1458 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1459 {
1460 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1461         u32 val;
1462         if (dc->enabled)  {
1463                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1464                 if (enable)
1465                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1466                 else
1467                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1468                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1469         }
1470 #endif
1471 }
1472
1473 bool tegra_dc_stats_get(struct tegra_dc *dc)
1474 {
1475 #if 0 /* right now it is always enabled */
1476         u32 val;
1477         bool res;
1478
1479         if (dc->enabled)  {
1480                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1481                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1482         } else {
1483                 res = false;
1484         }
1485
1486         return res;
1487 #endif
1488         return true;
1489 }
1490
1491 /* make the screen blank by disabling all windows */
1492 void tegra_dc_blank(struct tegra_dc *dc)
1493 {
1494         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1495         unsigned i;
1496
1497         for (i = 0; i < DC_N_WINDOWS; i++) {
1498                 dcwins[i] = tegra_dc_get_window(dc, i);
1499                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1500         }
1501
1502         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1503         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1504 }
1505
1506 static void _tegra_dc_disable(struct tegra_dc *dc)
1507 {
1508         _tegra_dc_controller_disable(dc);
1509         tegra_dc_io_end(dc);
1510 }
1511
1512 void tegra_dc_disable(struct tegra_dc *dc)
1513 {
1514         tegra_dc_ext_disable(dc->ext);
1515
1516         /* it's important that new underflow work isn't scheduled before the
1517          * lock is acquired. */
1518         cancel_delayed_work_sync(&dc->underflow_work);
1519         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1520                 mutex_lock(&dc->one_shot_lock);
1521                 cancel_delayed_work_sync(&dc->one_shot_work);
1522         }
1523
1524         mutex_lock(&dc->lock);
1525
1526         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1527                 tegra_dc_host_resume(dc);
1528
1529         if (dc->enabled) {
1530                 dc->enabled = false;
1531
1532                 if (!dc->suspended)
1533                         _tegra_dc_disable(dc);
1534         }
1535
1536 #ifdef CONFIG_SWITCH
1537         switch_set_state(&dc->modeset_switch, 0);
1538 #endif
1539
1540         mutex_unlock(&dc->lock);
1541         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1542                 mutex_unlock(&dc->one_shot_lock);
1543         print_mode_info(dc, dc->mode);
1544 }
1545
1546 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1547 static void tegra_dc_reset_worker(struct work_struct *work)
1548 {
1549         struct tegra_dc *dc =
1550                 container_of(work, struct tegra_dc, reset_work);
1551
1552         unsigned long val = 0;
1553
1554         mutex_lock(&shared_lock);
1555
1556         dev_warn(&dc->ndev->dev,
1557                 "overlay stuck in underflow state.  resetting.\n");
1558
1559         tegra_dc_ext_disable(dc->ext);
1560
1561         mutex_lock(&dc->lock);
1562
1563         if (dc->enabled == false)
1564                 goto unlock;
1565
1566         dc->enabled = false;
1567
1568         /*
1569          * off host read bus
1570          */
1571         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1572         val &= ~(0x00000100);
1573         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1574
1575         /*
1576          * set DC to STOP mode
1577          */
1578         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1579
1580         msleep(10);
1581
1582         _tegra_dc_controller_disable(dc);
1583
1584         /* _tegra_dc_controller_reset_enable deasserts reset */
1585         _tegra_dc_controller_reset_enable(dc);
1586
1587         dc->enabled = true;
1588
1589         /* reopen host read bus */
1590         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1591         val &= ~(0x00000100);
1592         val |= 0x100;
1593         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1594
1595 unlock:
1596         mutex_unlock(&dc->lock);
1597         mutex_unlock(&shared_lock);
1598         trace_printk("%s:reset complete\n", dc->ndev->name);
1599 }
1600 #endif
1601
1602 static void tegra_dc_underflow_worker(struct work_struct *work)
1603 {
1604         struct tegra_dc *dc = container_of(
1605                 to_delayed_work(work), struct tegra_dc, underflow_work);
1606
1607         mutex_lock(&dc->lock);
1608         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1609                 tegra_dc_host_resume(dc);
1610
1611         if (dc->enabled) {
1612                 tegra_dc_underflow_handler(dc);
1613         }
1614         mutex_unlock(&dc->lock);
1615 }
1616
1617 #ifdef CONFIG_SWITCH
1618 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1619 {
1620         struct tegra_dc *dc =
1621                 container_of(sdev, struct tegra_dc, modeset_switch);
1622
1623         if (!sdev->state)
1624                 return sprintf(buf, "offline\n");
1625
1626         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1627 }
1628 #endif
1629
1630 static int tegra_dc_probe(struct nvhost_device *ndev,
1631         struct nvhost_device_id *id_table)
1632 {
1633         struct tegra_dc *dc;
1634         struct tegra_dc_mode *mode;
1635         struct clk *clk;
1636         struct clk *emc_clk;
1637         struct resource *res;
1638         struct resource *base_res;
1639         struct resource *fb_mem = NULL;
1640         int ret = 0;
1641         void __iomem *base;
1642         int irq;
1643         int i;
1644
1645         if (!ndev->dev.platform_data) {
1646                 dev_err(&ndev->dev, "no platform data\n");
1647                 return -ENOENT;
1648         }
1649
1650         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1651         if (!dc) {
1652                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1653                 return -ENOMEM;
1654         }
1655
1656         irq = nvhost_get_irq_byname(ndev, "irq");
1657         if (irq <= 0) {
1658                 dev_err(&ndev->dev, "no irq\n");
1659                 ret = -ENOENT;
1660                 goto err_free;
1661         }
1662
1663         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1664         if (!res) {
1665                 dev_err(&ndev->dev, "no mem resource\n");
1666                 ret = -ENOENT;
1667                 goto err_free;
1668         }
1669
1670         base_res = request_mem_region(res->start, resource_size(res),
1671                 ndev->name);
1672         if (!base_res) {
1673                 dev_err(&ndev->dev, "request_mem_region failed\n");
1674                 ret = -EBUSY;
1675                 goto err_free;
1676         }
1677
1678         base = ioremap(res->start, resource_size(res));
1679         if (!base) {
1680                 dev_err(&ndev->dev, "registers can't be mapped\n");
1681                 ret = -EBUSY;
1682                 goto err_release_resource_reg;
1683         }
1684
1685         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1686
1687         clk = clk_get(&ndev->dev, NULL);
1688         if (IS_ERR_OR_NULL(clk)) {
1689                 dev_err(&ndev->dev, "can't get clock\n");
1690                 ret = -ENOENT;
1691                 goto err_iounmap_reg;
1692         }
1693
1694         emc_clk = clk_get(&ndev->dev, "emc");
1695         if (IS_ERR_OR_NULL(emc_clk)) {
1696                 dev_err(&ndev->dev, "can't get emc clock\n");
1697                 ret = -ENOENT;
1698                 goto err_put_clk;
1699         }
1700
1701         dc->clk = clk;
1702         dc->emc_clk = emc_clk;
1703         dc->shift_clk_div = 1;
1704         /* Initialize one shot work delay, it will be assigned by dsi
1705          * according to refresh rate later. */
1706         dc->one_shot_delay_ms = 40;
1707
1708         dc->base_res = base_res;
1709         dc->base = base;
1710         dc->irq = irq;
1711         dc->ndev = ndev;
1712         dc->pdata = ndev->dev.platform_data;
1713
1714         /*
1715          * The emc is a shared clock, it will be set based on
1716          * the requirements for each user on the bus.
1717          */
1718         dc->emc_clk_rate = 0;
1719
1720         mutex_init(&dc->lock);
1721         mutex_init(&dc->one_shot_lock);
1722         init_completion(&dc->frame_end_complete);
1723         init_waitqueue_head(&dc->wq);
1724 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1725         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1726 #endif
1727         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1728         dc->vblank_ref_count = 0;
1729         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
1730         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
1731
1732         tegra_dc_init_lut_defaults(&dc->fb_lut);
1733
1734         dc->n_windows = DC_N_WINDOWS;
1735         for (i = 0; i < dc->n_windows; i++) {
1736                 struct tegra_dc_win *win = &dc->windows[i];
1737                 win->idx = i;
1738                 win->dc = dc;
1739                 tegra_dc_init_csc_defaults(&win->csc);
1740                 tegra_dc_init_lut_defaults(&win->lut);
1741         }
1742
1743         ret = tegra_dc_set(dc, ndev->id);
1744         if (ret < 0) {
1745                 dev_err(&ndev->dev, "can't add dc\n");
1746                 goto err_free_irq;
1747         }
1748
1749         nvhost_set_drvdata(ndev, dc);
1750
1751 #ifdef CONFIG_SWITCH
1752         dc->modeset_switch.name = dev_name(&ndev->dev);
1753         dc->modeset_switch.state = 0;
1754         dc->modeset_switch.print_state = switch_modeset_print_mode;
1755         switch_dev_register(&dc->modeset_switch);
1756 #endif
1757
1758         tegra_dc_feature_register(dc);
1759
1760         if (dc->pdata->default_out)
1761                 tegra_dc_set_out(dc, dc->pdata->default_out);
1762         else
1763                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1764
1765         dc->vblank_syncpt = (dc->ndev->id == 0) ?
1766                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
1767
1768         dc->ext = tegra_dc_ext_register(ndev, dc);
1769         if (IS_ERR_OR_NULL(dc->ext)) {
1770                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
1771                 dc->ext = NULL;
1772         }
1773
1774         mutex_lock(&dc->lock);
1775         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
1776                 dc->enabled = _tegra_dc_enable(dc);
1777         mutex_unlock(&dc->lock);
1778
1779         /* interrupt handler must be registered before tegra_fb_register() */
1780         if (request_irq(irq, tegra_dc_irq, 0,
1781                         dev_name(&ndev->dev), dc)) {
1782                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1783                 ret = -EBUSY;
1784                 goto err_put_emc_clk;
1785         }
1786
1787         tegra_dc_create_debugfs(dc);
1788
1789         dev_info(&ndev->dev, "probed\n");
1790
1791         if (dc->pdata->fb) {
1792                 if (dc->pdata->fb->bits_per_pixel == -1) {
1793                         unsigned long fmt;
1794                         tegra_dc_writel(dc,
1795                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1796                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1797
1798                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1799                         dc->pdata->fb->bits_per_pixel =
1800                                 tegra_dc_fmt_bpp(fmt);
1801                 }
1802
1803                 mode = tegra_dc_get_override_mode(dc);
1804                 if (mode) {
1805                         dc->pdata->fb->xres = mode->h_active;
1806                         dc->pdata->fb->yres = mode->v_active;
1807                 }
1808
1809                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1810                 if (IS_ERR_OR_NULL(dc->fb))
1811                         dc->fb = NULL;
1812         }
1813
1814         if (dc->out && dc->out->hotplug_init)
1815                 dc->out->hotplug_init();
1816
1817         if (dc->out_ops && dc->out_ops->detect)
1818                 dc->out_ops->detect(dc);
1819         else
1820                 dc->connected = true;
1821
1822         tegra_dc_create_sysfs(&dc->ndev->dev);
1823
1824         return 0;
1825
1826 err_free_irq:
1827         free_irq(irq, dc);
1828 err_put_emc_clk:
1829         clk_put(emc_clk);
1830 err_put_clk:
1831         clk_put(clk);
1832 err_iounmap_reg:
1833         iounmap(base);
1834         if (fb_mem)
1835                 release_resource(fb_mem);
1836 err_release_resource_reg:
1837         release_resource(base_res);
1838 err_free:
1839         kfree(dc);
1840
1841         return ret;
1842 }
1843
1844 static int tegra_dc_remove(struct nvhost_device *ndev)
1845 {
1846         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1847
1848         tegra_dc_remove_sysfs(&dc->ndev->dev);
1849         tegra_dc_remove_debugfs(dc);
1850
1851         if (dc->fb) {
1852                 tegra_fb_unregister(dc->fb);
1853                 if (dc->fb_mem)
1854                         release_resource(dc->fb_mem);
1855         }
1856
1857         tegra_dc_ext_disable(dc->ext);
1858
1859         if (dc->ext)
1860                 tegra_dc_ext_unregister(dc->ext);
1861
1862         if (dc->enabled)
1863                 _tegra_dc_disable(dc);
1864
1865 #ifdef CONFIG_SWITCH
1866         switch_dev_unregister(&dc->modeset_switch);
1867 #endif
1868         free_irq(dc->irq, dc);
1869         clk_put(dc->emc_clk);
1870         clk_put(dc->clk);
1871         iounmap(dc->base);
1872         if (dc->fb_mem)
1873                 release_resource(dc->base_res);
1874         kfree(dc);
1875         tegra_dc_set(NULL, ndev->id);
1876         return 0;
1877 }
1878
1879 #ifdef CONFIG_PM
1880 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
1881 {
1882         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1883
1884         trace_printk("%s:suspend\n", dc->ndev->name);
1885         dev_info(&ndev->dev, "suspend\n");
1886
1887         tegra_dc_ext_disable(dc->ext);
1888
1889         mutex_lock(&dc->lock);
1890
1891         if (dc->out_ops && dc->out_ops->suspend)
1892                 dc->out_ops->suspend(dc);
1893
1894         if (dc->enabled) {
1895                 _tegra_dc_disable(dc);
1896
1897                 dc->suspended = true;
1898         }
1899
1900         if (dc->out && dc->out->postsuspend) {
1901                 dc->out->postsuspend();
1902                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
1903                         /*
1904                          * avoid resume event due to voltage falling
1905                          */
1906                         msleep(100);
1907         }
1908
1909         mutex_unlock(&dc->lock);
1910
1911         return 0;
1912 }
1913
1914 static int tegra_dc_resume(struct nvhost_device *ndev)
1915 {
1916         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1917
1918         trace_printk("%s:resume\n", dc->ndev->name);
1919         dev_info(&ndev->dev, "resume\n");
1920
1921         mutex_lock(&dc->lock);
1922         dc->suspended = false;
1923
1924         if (dc->enabled)
1925                 _tegra_dc_enable(dc);
1926
1927         if (dc->out && dc->out->hotplug_init)
1928                 dc->out->hotplug_init();
1929
1930         if (dc->out_ops && dc->out_ops->resume)
1931                 dc->out_ops->resume(dc);
1932         mutex_unlock(&dc->lock);
1933
1934         return 0;
1935 }
1936
1937 #endif /* CONFIG_PM */
1938
1939 static void tegra_dc_shutdown(struct nvhost_device *ndev)
1940 {
1941         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1942
1943         if (!dc || !dc->enabled)
1944                 return;
1945
1946         tegra_dc_blank(dc);
1947         tegra_dc_disable(dc);
1948 }
1949
1950 extern int suspend_set(const char *val, struct kernel_param *kp)
1951 {
1952         if (!strcmp(val, "dump"))
1953                 dump_regs(tegra_dcs[0]);
1954 #ifdef CONFIG_PM
1955         else if (!strcmp(val, "suspend"))
1956                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
1957         else if (!strcmp(val, "resume"))
1958                 tegra_dc_resume(tegra_dcs[0]->ndev);
1959 #endif
1960
1961         return 0;
1962 }
1963
1964 extern int suspend_get(char *buffer, struct kernel_param *kp)
1965 {
1966         return 0;
1967 }
1968
1969 int suspend;
1970
1971 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
1972
1973 struct nvhost_driver tegra_dc_driver = {
1974         .driver = {
1975                 .name = "tegradc",
1976                 .owner = THIS_MODULE,
1977         },
1978         .probe = tegra_dc_probe,
1979         .remove = tegra_dc_remove,
1980 #ifdef CONFIG_PM
1981         .suspend = tegra_dc_suspend,
1982         .resume = tegra_dc_resume,
1983 #endif
1984         .shutdown = tegra_dc_shutdown,
1985 };
1986
1987 #ifndef MODULE
1988 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
1989 {
1990         int i, params[11];
1991         char *p;
1992
1993         for (i = 0; i < ARRAY_SIZE(params); i++) {
1994                 if ((p = strsep(&options, ",")) != NULL) {
1995                         if (*p)
1996                                 params[i] = simple_strtoul(p, &p, 10);
1997                 } else
1998                         return -EINVAL;
1999         }
2000
2001         if ((mode->pclk = params[0]) == 0)
2002                 return -EINVAL;
2003
2004         mode->h_active      = params[1];
2005         mode->v_active      = params[2];
2006         mode->h_ref_to_sync = params[3];
2007         mode->v_ref_to_sync = params[4];
2008         mode->h_sync_width  = params[5];
2009         mode->v_sync_width  = params[6];
2010         mode->h_back_porch  = params[7];
2011         mode->v_back_porch  = params[8];
2012         mode->h_front_porch = params[9];
2013         mode->v_front_porch = params[10];
2014
2015         return 0;
2016 }
2017
2018 static int __init tegra_dc_mode_override(char *str)
2019 {
2020         char *p = str, *options;
2021
2022         if (!p || !*p)
2023                 return -EINVAL;
2024
2025         p = strstr(str, "hdmi:");
2026         if (p) {
2027                 p += 5;
2028                 options = strsep(&p, ";");
2029                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2030                         return -EINVAL;
2031         }
2032
2033         p = strstr(str, "rgb:");
2034         if (p) {
2035                 p += 4;
2036                 options = strsep(&p, ";");
2037                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2038                         return -EINVAL;
2039         }
2040
2041         p = strstr(str, "dsi:");
2042         if (p) {
2043                 p += 4;
2044                 options = strsep(&p, ";");
2045                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2046                         return -EINVAL;
2047         }
2048
2049         return 0;
2050 }
2051
2052 __setup("disp_params=", tegra_dc_mode_override);
2053 #endif
2054
2055 static int __init tegra_dc_module_init(void)
2056 {
2057         int ret = tegra_dc_ext_module_init();
2058         if (ret)
2059                 return ret;
2060         return nvhost_driver_register(&tegra_dc_driver);
2061 }
2062
2063 static void __exit tegra_dc_module_exit(void)
2064 {
2065         nvhost_driver_unregister(&tegra_dc_driver);
2066         tegra_dc_ext_module_exit();
2067 }
2068
2069 module_exit(tegra_dc_module_exit);
2070 module_init(tegra_dc_module_init);