video: tegra: dc: new file for bandwidth calc
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39 #ifdef CONFIG_SWITCH
40 #include <linux/switch.h>
41 #endif
42
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
62 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
63 #else
64 /* ignore underflows when on simulation and fpga platform */
65 #define ALL_UF_INT (0)
66 #endif
67
68 static int no_vsync;
69 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
70         .refresh = 60,
71         .xres = 640,
72         .yres = 480,
73         .pixclock = KHZ2PICOS(25200),
74         .hsync_len = 96,        /* h_sync_width */
75         .vsync_len = 2,         /* v_sync_width */
76         .left_margin = 48,      /* h_back_porch */
77         .upper_margin = 33,     /* v_back_porch */
78         .right_margin = 16,     /* h_front_porch */
79         .lower_margin = 10,     /* v_front_porch */
80         .vmode = 0,
81         .sync = 0,
82 };
83
84 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
85
86 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
87
88 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
89
90 DEFINE_MUTEX(tegra_dc_lock);
91 DEFINE_MUTEX(shared_lock);
92
93 #define DUMP_REG(a) do {                        \
94         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
95                  #a, a, tegra_dc_readl(dc, a));               \
96         print(data, buff);                                    \
97         } while (0)
98
99 #define print_mode_info(dc, mode) do {                        \
100         trace_printk("%s:Mode settings: "                              \
101                         "ref_to_sync: H = %d V = %d, "                  \
102                         "sync_width: H = %d V = %d, "                   \
103                         "back_porch: H = %d V = %d, "                   \
104                         "active: H = %d V = %d, "                       \
105                         "front_porch: H = %d V = %d, "                  \
106                         "pclk = %d, stereo mode = %d\n",                \
107                         dc->ndev->name,                                 \
108                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
109                         mode.h_sync_width, mode.v_sync_width,           \
110                         mode.h_back_porch, mode.v_back_porch,           \
111                         mode.h_active, mode.v_active,                   \
112                         mode.h_front_porch, mode.v_front_porch,         \
113                         mode.pclk, mode.stereo_mode);                   \
114         } while (0)
115
116 #define print_underflow_info(dc) do {                 \
117         trace_printk("%s:Underflow stats: underflows : %llu, "      \
118                         "undeflows_a : %llu, "                          \
119                         "underflows_b : %llu, "                         \
120                         "underflows_c : %llu\n",                        \
121                         dc->ndev->name,                                 \
122                         dc->stats.underflows,                           \
123                         dc->stats.underflows_a, dc->stats.underflows_b, \
124                         dc->stats.underflows_c);                        \
125         } while (0)
126
127 static void _dump_regs(struct tegra_dc *dc, void *data,
128                        void (* print)(void *data, const char *str))
129 {
130         int i;
131         char buff[256];
132
133         tegra_dc_io_start(dc);
134         clk_enable(dc->clk);
135
136         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
137         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
138         DUMP_REG(DC_CMD_SIGNAL_RAISE);
139         DUMP_REG(DC_CMD_INT_STATUS);
140         DUMP_REG(DC_CMD_INT_MASK);
141         DUMP_REG(DC_CMD_INT_ENABLE);
142         DUMP_REG(DC_CMD_INT_TYPE);
143         DUMP_REG(DC_CMD_INT_POLARITY);
144         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
145         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
146         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
147         DUMP_REG(DC_CMD_STATE_ACCESS);
148         DUMP_REG(DC_CMD_STATE_CONTROL);
149         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
150         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
151
152         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
153         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
154         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
155         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
156         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
157         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
158         DUMP_REG(DC_DISP_REF_TO_SYNC);
159         DUMP_REG(DC_DISP_SYNC_WIDTH);
160         DUMP_REG(DC_DISP_BACK_PORCH);
161         DUMP_REG(DC_DISP_DISP_ACTIVE);
162         DUMP_REG(DC_DISP_FRONT_PORCH);
163         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
164         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
165         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
166         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
167         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
168         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
169         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
170         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
171         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
172         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
173         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
174         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
175         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
176         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
177         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
178         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
179         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
180         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
181         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
182         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
183         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
184         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
185         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
186         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
187         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
188         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
189         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
190         DUMP_REG(DC_DISP_M0_CONTROL);
191         DUMP_REG(DC_DISP_M1_CONTROL);
192         DUMP_REG(DC_DISP_DI_CONTROL);
193         DUMP_REG(DC_DISP_PP_CONTROL);
194         DUMP_REG(DC_DISP_PP_SELECT_A);
195         DUMP_REG(DC_DISP_PP_SELECT_B);
196         DUMP_REG(DC_DISP_PP_SELECT_C);
197         DUMP_REG(DC_DISP_PP_SELECT_D);
198         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
199         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
200         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
201         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
202         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
203         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
204         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
205         DUMP_REG(DC_DISP_BORDER_COLOR);
206         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
207         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
208         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
209         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
210         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
211         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
212         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
213         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
214         DUMP_REG(DC_DISP_CURSOR_POSITION);
215         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
216         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
217         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
218         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
219         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
220         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
221         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
222         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
223         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
224         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
225         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
226         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
227         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
228
229
230         for (i = 0; i < 3; i++) {
231                 print(data, "\n");
232                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
233                 print(data, buff);
234
235                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
236                                 DC_CMD_DISPLAY_WINDOW_HEADER);
237                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
238                 DUMP_REG(DC_WIN_WIN_OPTIONS);
239                 DUMP_REG(DC_WIN_BYTE_SWAP);
240                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
241                 DUMP_REG(DC_WIN_COLOR_DEPTH);
242                 DUMP_REG(DC_WIN_POSITION);
243                 DUMP_REG(DC_WIN_SIZE);
244                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
245                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
246                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
247                 DUMP_REG(DC_WIN_DDA_INCREMENT);
248                 DUMP_REG(DC_WIN_LINE_STRIDE);
249                 DUMP_REG(DC_WIN_BUF_STRIDE);
250                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
251                 DUMP_REG(DC_WIN_BLEND_NOKEY);
252                 DUMP_REG(DC_WIN_BLEND_1WIN);
253                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
254                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
255                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
256                 DUMP_REG(DC_WINBUF_START_ADDR);
257                 DUMP_REG(DC_WINBUF_START_ADDR_U);
258                 DUMP_REG(DC_WINBUF_START_ADDR_V);
259                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
260                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
261                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
262                 DUMP_REG(DC_WIN_CSC_YOF);
263                 DUMP_REG(DC_WIN_CSC_KYRGB);
264                 DUMP_REG(DC_WIN_CSC_KUR);
265                 DUMP_REG(DC_WIN_CSC_KVR);
266                 DUMP_REG(DC_WIN_CSC_KUG);
267                 DUMP_REG(DC_WIN_CSC_KVG);
268                 DUMP_REG(DC_WIN_CSC_KUB);
269                 DUMP_REG(DC_WIN_CSC_KVB);
270         }
271
272         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
273         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
274         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
275         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
276         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
277         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
278         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
279         DUMP_REG(DC_DISP_M1_CONTROL);
280         DUMP_REG(DC_COM_PM1_CONTROL);
281         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
282         DUMP_REG(DC_DISP_SD_CONTROL);
283
284         clk_disable(dc->clk);
285         tegra_dc_io_end(dc);
286 }
287
288 #undef DUMP_REG
289
290 #ifdef DEBUG
291 static void dump_regs_print(void *data, const char *str)
292 {
293         struct tegra_dc *dc = data;
294         dev_dbg(&dc->ndev->dev, "%s", str);
295 }
296
297 static void dump_regs(struct tegra_dc *dc)
298 {
299         _dump_regs(dc, dc, dump_regs_print);
300 }
301 #else /* !DEBUG */
302
303 static void dump_regs(struct tegra_dc *dc) {}
304
305 #endif /* DEBUG */
306
307 #ifdef CONFIG_DEBUG_FS
308
309 static void dbg_regs_print(void *data, const char *str)
310 {
311         struct seq_file *s = data;
312
313         seq_printf(s, "%s", str);
314 }
315
316 #undef DUMP_REG
317
318 static int dbg_dc_show(struct seq_file *s, void *unused)
319 {
320         struct tegra_dc *dc = s->private;
321
322         _dump_regs(dc, s, dbg_regs_print);
323
324         return 0;
325 }
326
327
328 static int dbg_dc_open(struct inode *inode, struct file *file)
329 {
330         return single_open(file, dbg_dc_show, inode->i_private);
331 }
332
333 static const struct file_operations regs_fops = {
334         .open           = dbg_dc_open,
335         .read           = seq_read,
336         .llseek         = seq_lseek,
337         .release        = single_release,
338 };
339
340 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
341 {
342         struct tegra_dc *dc = s->private;
343         struct tegra_dc_mode *m;
344
345         mutex_lock(&dc->lock);
346         m = &dc->mode;
347         seq_printf(s,
348                 "pclk: %d\n"
349                 "h_ref_to_sync: %d\n"
350                 "v_ref_to_sync: %d\n"
351                 "h_sync_width: %d\n"
352                 "v_sync_width: %d\n"
353                 "h_back_porch: %d\n"
354                 "v_back_porch: %d\n"
355                 "h_active: %d\n"
356                 "v_active: %d\n"
357                 "h_front_porch: %d\n"
358                 "v_front_porch: %d\n"
359                 "stereo_mode: %d\n",
360                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
361                 m->h_sync_width, m->v_sync_width,
362                 m->h_back_porch, m->v_back_porch,
363                 m->h_active, m->v_active,
364                 m->h_front_porch, m->v_front_porch,
365                 m->stereo_mode);
366         mutex_unlock(&dc->lock);
367         return 0;
368 }
369
370 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
371 {
372         return single_open(file, dbg_dc_mode_show, inode->i_private);
373 }
374
375 static const struct file_operations mode_fops = {
376         .open           = dbg_dc_mode_open,
377         .read           = seq_read,
378         .llseek         = seq_lseek,
379         .release        = single_release,
380 };
381
382 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
383 {
384         struct tegra_dc *dc = s->private;
385
386         mutex_lock(&dc->lock);
387         seq_printf(s,
388                 "underflows: %llu\n"
389                 "underflows_a: %llu\n"
390                 "underflows_b: %llu\n"
391                 "underflows_c: %llu\n",
392                 dc->stats.underflows,
393                 dc->stats.underflows_a,
394                 dc->stats.underflows_b,
395                 dc->stats.underflows_c);
396         mutex_unlock(&dc->lock);
397
398         return 0;
399 }
400
401 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
402 {
403         return single_open(file, dbg_dc_stats_show, inode->i_private);
404 }
405
406 static const struct file_operations stats_fops = {
407         .open           = dbg_dc_stats_open,
408         .read           = seq_read,
409         .llseek         = seq_lseek,
410         .release        = single_release,
411 };
412
413 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
414 {
415         if (dc->debugdir)
416                 debugfs_remove_recursive(dc->debugdir);
417         dc->debugdir = NULL;
418 }
419
420 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
421 {
422         struct dentry *retval;
423
424         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
425         if (!dc->debugdir)
426                 goto remove_out;
427
428         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
429                 &regs_fops);
430         if (!retval)
431                 goto remove_out;
432
433         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
434                 &mode_fops);
435         if (!retval)
436                 goto remove_out;
437
438         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
439                 &stats_fops);
440         if (!retval)
441                 goto remove_out;
442
443         return;
444 remove_out:
445         dev_err(&dc->ndev->dev, "could not create debugfs\n");
446         tegra_dc_remove_debugfs(dc);
447 }
448
449 #else /* !CONFIG_DEBUGFS */
450 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
451 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
452 #endif /* CONFIG_DEBUGFS */
453
454 static int tegra_dc_set(struct tegra_dc *dc, int index)
455 {
456         int ret = 0;
457
458         mutex_lock(&tegra_dc_lock);
459         if (index >= TEGRA_MAX_DC) {
460                 ret = -EINVAL;
461                 goto out;
462         }
463
464         if (dc != NULL && tegra_dcs[index] != NULL) {
465                 ret = -EBUSY;
466                 goto out;
467         }
468
469         tegra_dcs[index] = dc;
470
471 out:
472         mutex_unlock(&tegra_dc_lock);
473
474         return ret;
475 }
476
477 unsigned int tegra_dc_has_multiple_dc(void)
478 {
479         unsigned int idx;
480         unsigned int cnt = 0;
481         struct tegra_dc *dc;
482
483         mutex_lock(&tegra_dc_lock);
484         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
485                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
486         mutex_unlock(&tegra_dc_lock);
487
488         return (cnt > 1);
489 }
490
491 /* get the stride size of a window.
492  * return: stride size in bytes for window win. or 0 if unavailble. */
493 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
494 {
495         u32 stride;
496
497         if (!dc->enabled)
498                 return 0;
499         BUG_ON(win > DC_N_WINDOWS);
500         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
501                 DC_CMD_DISPLAY_WINDOW_HEADER);
502         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
503         return GET_LINE_STRIDE(stride);
504 }
505 EXPORT_SYMBOL(tegra_dc_get_stride);
506
507 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
508 {
509         if (idx < TEGRA_MAX_DC)
510                 return tegra_dcs[idx];
511         else
512                 return NULL;
513 }
514 EXPORT_SYMBOL(tegra_dc_get_dc);
515
516 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
517 {
518         if (win >= dc->n_windows)
519                 return NULL;
520
521         return &dc->windows[win];
522 }
523 EXPORT_SYMBOL(tegra_dc_get_window);
524
525 static int get_topmost_window(u32 *depths, unsigned long *wins)
526 {
527         int idx, best = -1;
528
529         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
530                 if (best == -1 || depths[idx] < depths[best])
531                         best = idx;
532         }
533         clear_bit(best, wins);
534         return best;
535 }
536
537 bool tegra_dc_get_connected(struct tegra_dc *dc)
538 {
539         return dc->connected;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_connected);
542
543 bool tegra_dc_hpd(struct tegra_dc *dc)
544 {
545         int sense;
546         int level;
547
548         level = gpio_get_value(dc->out->hotplug_gpio);
549
550         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
551
552         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
553                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
554 }
555 EXPORT_SYMBOL(tegra_dc_hpd);
556
557 static u32 blend_topwin(u32 flags)
558 {
559         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
560                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
561         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
562                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
563         else
564                 return BLEND(NOKEY, FIX, 0xff, 0xff);
565 }
566
567 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
568 {
569         int other;
570
571         for (other = 0; other < DC_N_WINDOWS; other++) {
572                 if (other != idx && (xy-- == 0))
573                         break;
574         }
575         if (BIT(other) & behind_mask)
576                 return blend_topwin(flags[idx]);
577         else if (flags[other])
578                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
579         else
580                 return BLEND(NOKEY, FIX, 0x00, 0x00);
581 }
582
583 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
584 {
585         unsigned long infront_mask;
586         int first;
587
588         infront_mask = ~(behind_mask | BIT(idx));
589         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
590         first = ffs(infront_mask) - 1;
591
592         if (!infront_mask)
593                 return blend_topwin(flags[idx]);
594         else if (behind_mask && first != -1 && flags[first])
595                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
596         else
597                 return BLEND(NOKEY, FIX, 0x0, 0x0);
598 }
599
600 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
601 {
602         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
603
604         while (mask) {
605                 int idx = get_topmost_window(blend->z, &mask);
606
607                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
608                                 DC_CMD_DISPLAY_WINDOW_HEADER);
609                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
610                                 DC_WIN_BLEND_NOKEY);
611                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
612                                 DC_WIN_BLEND_1WIN);
613                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
614                                 DC_WIN_BLEND_2WIN_X);
615                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
616                                 DC_WIN_BLEND_2WIN_Y);
617                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
618                                 DC_WIN_BLEND_3WIN_XY);
619         }
620 }
621
622 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
623 {
624         csc->yof   = 0x00f0;
625         csc->kyrgb = 0x012a;
626         csc->kur   = 0x0000;
627         csc->kvr   = 0x0198;
628         csc->kug   = 0x039b;
629         csc->kvg   = 0x032f;
630         csc->kub   = 0x0204;
631         csc->kvb   = 0x0000;
632 }
633
634 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
635 {
636         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
637         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
638         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
639         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
640         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
641         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
642         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
643         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
644 }
645
646 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
647 {
648         mutex_lock(&dc->lock);
649
650         if (!dc->enabled) {
651                 mutex_unlock(&dc->lock);
652                 return -EFAULT;
653         }
654
655         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
656                         DC_CMD_DISPLAY_WINDOW_HEADER);
657
658         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
659
660         mutex_unlock(&dc->lock);
661
662         return 0;
663 }
664 EXPORT_SYMBOL(tegra_dc_update_csc);
665
666 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
667 {
668         int i;
669         for (i = 0; i < 256; i++)
670                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
671 }
672
673 static int tegra_dc_loop_lut(struct tegra_dc *dc,
674                              struct tegra_dc_win *win,
675                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
676 {
677         struct tegra_dc_lut *lut = &win->lut;
678         struct tegra_dc_lut *global_lut = &dc->fb_lut;
679         int i;
680         for (i = 0; i < 256; i++) {
681
682                 u32 r = (u32)lut->r[i];
683                 u32 g = (u32)lut->g[i];
684                 u32 b = (u32)lut->b[i];
685
686                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
687                         r = (u32)global_lut->r[r];
688                         g = (u32)global_lut->g[g];
689                         b = (u32)global_lut->b[b];
690                 }
691
692                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
693                         return 0;
694         }
695         return 1;
696 }
697
698 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
699 {
700         if (rgb != (i | (i<<8) | (i<<16)))
701                 return 0;
702         return 1;
703 }
704
705 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
706 {
707         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
708         return 1;
709 }
710
711 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
712 {
713         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
714
715         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
716
717         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
718                 val |= CP_ENABLE;
719         else
720                 val &= ~CP_ENABLE;
721
722         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
723 }
724
725 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
726 {
727         struct tegra_dc_win *win = &dc->windows[win_idx];
728
729         mutex_lock(&dc->lock);
730
731         if (!dc->enabled) {
732                 mutex_unlock(&dc->lock);
733                 return -EFAULT;
734         }
735
736         if (fbovr > 0)
737                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
738         else if (fbovr == 0)
739                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
740
741         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
742                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
743         else
744                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
745
746         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
747                         DC_CMD_DISPLAY_WINDOW_HEADER);
748
749         tegra_dc_set_lut(dc, win);
750
751         mutex_unlock(&dc->lock);
752
753         tegra_dc_update_windows(&win, 1);
754
755         return 0;
756 }
757
758 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
759 {
760         if (win_idx > -1)
761                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
762
763         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
764                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
765                 if (err)
766                         return err;
767         }
768
769         return 0;
770 }
771 EXPORT_SYMBOL(tegra_dc_update_lut);
772
773 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
774 {
775         unsigned i;
776         unsigned v0 = 128;
777         unsigned v1 = 0;
778         /* linear horizontal and vertical filters */
779         for (i = 0; i < 16; i++) {
780                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
781                                 DC_WIN_H_FILTER_P(i));
782
783                 tegra_dc_writel(dc, v0,
784                                 DC_WIN_V_FILTER_P(i));
785                 v0 -= 8;
786                 v1 += 8;
787         }
788 }
789
790 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
791                                   bool v, unsigned Bpp)
792 {
793         /*
794          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
795          *           (post_scaled_size_in_pixels - 1)), MAX)
796          * Where the value of MAX is as follows:
797          * For V_DDA_INCREMENT: 15.0 (0xF000)
798          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
799          *                       8.0 (0x8000) for 2 Bytes/pix formats.
800          */
801
802         fixed20_12 out = dfixed_init(out_int);
803         u32 dda_inc;
804         int max;
805
806         if (v) {
807                 max = 15;
808         } else {
809                 switch (Bpp) {
810                 default:
811                         WARN_ON_ONCE(1);
812                         /* fallthrough */
813                 case 4:
814                         max = 4;
815                         break;
816                 case 2:
817                         max = 8;
818                         break;
819                 }
820         }
821
822         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
823         in.full -= dfixed_const(1);
824
825         dda_inc = dfixed_div(in, out);
826
827         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
828
829         return dda_inc;
830 }
831
832 static inline u32 compute_initial_dda(fixed20_12 in)
833 {
834         return dfixed_frac(in);
835 }
836
837 /* does not support updating windows on multiple dcs in one call */
838 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
839 {
840         struct tegra_dc *dc;
841         unsigned long update_mask = GENERAL_ACT_REQ;
842         unsigned long val;
843         bool update_blend = false;
844         int i;
845
846         dc = windows[0]->dc;
847
848         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
849                 /* Acquire one_shot_lock to avoid race condition between
850                  * cancellation of old delayed work and schedule of new
851                  * delayed work. */
852                 mutex_lock(&dc->one_shot_lock);
853                 cancel_delayed_work_sync(&dc->one_shot_work);
854         }
855         mutex_lock(&dc->lock);
856
857         if (!dc->enabled) {
858                 mutex_unlock(&dc->lock);
859                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
860                         mutex_unlock(&dc->one_shot_lock);
861                 return -EFAULT;
862         }
863
864         if (no_vsync)
865                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
866         else
867                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
868
869         for (i = 0; i < n; i++) {
870                 struct tegra_dc_win *win = windows[i];
871                 unsigned h_dda;
872                 unsigned v_dda;
873                 fixed20_12 h_offset, v_offset;
874                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
875                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
876                 bool yuv = tegra_dc_is_yuv(win->fmt);
877                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
878                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
879                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
880                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
881                 const bool filter_h = win_use_h_filter(dc, win);
882                 const bool filter_v = win_use_v_filter(dc, win);
883
884                 if (win->z != dc->blend.z[win->idx]) {
885                         dc->blend.z[win->idx] = win->z;
886                         update_blend = true;
887                 }
888                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
889                         dc->blend.flags[win->idx]) {
890                         dc->blend.flags[win->idx] =
891                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
892                         update_blend = true;
893                 }
894
895                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
896                                 DC_CMD_DISPLAY_WINDOW_HEADER);
897
898                 if (!no_vsync)
899                         update_mask |= WIN_A_ACT_REQ << win->idx;
900
901                 if (!WIN_IS_ENABLED(win)) {
902                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
903                         continue;
904                 }
905
906                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
907                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
908
909                 tegra_dc_writel(dc,
910                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
911                                 DC_WIN_POSITION);
912                 tegra_dc_writel(dc,
913                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
914                                 DC_WIN_SIZE);
915
916                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
917                         tegra_dc_writel(dc,
918                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
919                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
920                                         DC_WIN_PRESCALED_SIZE);
921
922                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
923                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
924                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
925                                         DC_WIN_DDA_INCREMENT);
926                         h_dda = compute_initial_dda(win->x);
927                         v_dda = compute_initial_dda(win->y);
928                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
929                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
930                 }
931
932                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
933                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
934                 tegra_dc_writel(dc,
935                                 (unsigned long)win->phys_addr,
936                                 DC_WINBUF_START_ADDR);
937
938                 if (!yuvp) {
939                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
940                 } else {
941                         tegra_dc_writel(dc,
942                                         (unsigned long)win->phys_addr_u,
943                                         DC_WINBUF_START_ADDR_U);
944                         tegra_dc_writel(dc,
945                                         (unsigned long)win->phys_addr_v,
946                                         DC_WINBUF_START_ADDR_V);
947                         tegra_dc_writel(dc,
948                                         LINE_STRIDE(win->stride) |
949                                         UV_LINE_STRIDE(win->stride_uv),
950                                         DC_WIN_LINE_STRIDE);
951                 }
952
953                 h_offset = win->x;
954                 if (invert_h) {
955                         h_offset.full += win->w.full - dfixed_const(1);
956                 }
957
958                 v_offset = win->y;
959                 if (invert_v) {
960                         v_offset.full += win->h.full - dfixed_const(1);
961                 }
962
963                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
964                                 DC_WINBUF_ADDR_H_OFFSET);
965                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
966                                 DC_WINBUF_ADDR_V_OFFSET);
967
968                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
969                         if (WIN_IS_TILED(win))
970                                 tegra_dc_writel(dc,
971                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
972                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
973                                                 DC_WIN_BUFFER_ADDR_MODE);
974                         else
975                                 tegra_dc_writel(dc,
976                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
977                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
978                                                 DC_WIN_BUFFER_ADDR_MODE);
979                 }
980
981                 val = WIN_ENABLE;
982                 if (yuv)
983                         val |= CSC_ENABLE;
984                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
985                         val |= COLOR_EXPAND;
986
987                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
988                         val |= CP_ENABLE;
989
990                 if (filter_h)
991                         val |= H_FILTER_ENABLE;
992                 if (filter_v)
993                         val |= V_FILTER_ENABLE;
994
995                 if (invert_h)
996                         val |= H_DIRECTION_DECREMENT;
997                 if (invert_v)
998                         val |= V_DIRECTION_DECREMENT;
999
1000                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1001
1002 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1003                 if (win->global_alpha == 255)
1004                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1005                 else
1006                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1007                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1008 #endif
1009
1010                 win->dirty = no_vsync ? 0 : 1;
1011
1012                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1013                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1014                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1015                         __func__, win->idx, win->z,
1016                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1017                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1018                         win->out_x, win->out_y, win->out_w, win->out_h,
1019                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1020                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1021                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1022                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1023         }
1024
1025         if (update_blend) {
1026                 tegra_dc_set_blending(dc, &dc->blend);
1027                 for (i = 0; i < DC_N_WINDOWS; i++) {
1028                         if (!no_vsync)
1029                                 dc->windows[i].dirty = 1;
1030                         update_mask |= WIN_A_ACT_REQ << i;
1031                 }
1032         }
1033
1034         tegra_dc_set_dynamic_emc(windows, n);
1035
1036         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1037
1038         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1039         if (!no_vsync) {
1040                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1041                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1042                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1043         } else {
1044                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1045                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1046                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1047         }
1048
1049         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1050                 schedule_delayed_work(&dc->one_shot_work,
1051                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1052
1053         /* update EMC clock if calculated bandwidth has changed */
1054         tegra_dc_program_bandwidth(dc);
1055
1056         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1057                 update_mask |= NC_HOST_TRIG;
1058
1059         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1060         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1061
1062         mutex_unlock(&dc->lock);
1063         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1064                 mutex_unlock(&dc->one_shot_lock);
1065
1066         return 0;
1067 }
1068 EXPORT_SYMBOL(tegra_dc_update_windows);
1069
1070 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1071 {
1072         return dc->syncpt[i].id;
1073 }
1074 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1075
1076 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1077 {
1078         u32 max;
1079
1080         mutex_lock(&dc->lock);
1081         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1082                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1083         dc->syncpt[i].max = max;
1084         mutex_unlock(&dc->lock);
1085
1086         return max;
1087 }
1088
1089 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1090 {
1091         mutex_lock(&dc->lock);
1092         if ( dc->enabled )
1093                 while (dc->syncpt[i].min < val) {
1094                         dc->syncpt[i].min++;
1095                         nvhost_syncpt_cpu_incr(
1096                                         &nvhost_get_host(dc->ndev)->syncpt,
1097                                         dc->syncpt[i].id);
1098                 }
1099         mutex_unlock(&dc->lock);
1100 }
1101
1102 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1103                                              int n)
1104 {
1105         int i;
1106
1107         for (i = 0; i < n; i++) {
1108                 if (windows[i]->dirty)
1109                         return false;
1110         }
1111
1112         return true;
1113 }
1114
1115 /* does not support syncing windows on multiple dcs in one call */
1116 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1117 {
1118         int ret;
1119         if (n < 1 || n > DC_N_WINDOWS)
1120                 return -EINVAL;
1121
1122         if (!windows[0]->dc->enabled)
1123                 return -EFAULT;
1124
1125 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1126         /* Don't want to timeout on simulator */
1127         ret = wait_event_interruptible(windows[0]->dc->wq,
1128                 tegra_dc_windows_are_clean(windows, n));
1129 #else
1130         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1131                         windows[0]->dc->ndev->name);
1132         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1133                                          tegra_dc_windows_are_clean(windows, n),
1134                                          HZ);
1135         trace_printk("%s:After wait_event_interruptible_timeout\n",
1136                         windows[0]->dc->ndev->name);
1137 #endif
1138         return ret;
1139 }
1140 EXPORT_SYMBOL(tegra_dc_sync_windows);
1141
1142 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1143 {
1144 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1145         return clk_get_rate(dc->clk);
1146 #else
1147         return 27000000;
1148 #endif
1149 }
1150
1151 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1152 {
1153         unsigned long rate;
1154         unsigned long div;
1155
1156         rate = tegra_dc_clk_get_rate(dc);
1157
1158         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1159
1160         if (div < 2)
1161                 return 0;
1162
1163         return rate * 2 / div;
1164 }
1165
1166 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1167 {
1168         unsigned long rate;
1169         unsigned long div;
1170
1171         rate = clk_get_rate(parent);
1172
1173         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1174
1175         if (div < 2)
1176                 return 0;
1177
1178         return rate * 2 / div;
1179 }
1180
1181 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1182 {
1183         int pclk;
1184
1185         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1186                 unsigned long rate;
1187                 struct clk *parent_clk =
1188                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1189
1190                 if (dc->out->parent_clk_backup &&
1191                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1192                         rate = tegra_dc_pclk_predict_rate(
1193                                 parent_clk, dc->mode.pclk);
1194                         /* use pll_d as last resort */
1195                         if (rate < (dc->mode.pclk / 100 * 99) ||
1196                             rate > (dc->mode.pclk / 100 * 109))
1197                                 parent_clk = clk_get_sys(
1198                                         NULL, dc->out->parent_clk_backup);
1199                 }
1200
1201                 if (clk_get_parent(clk) != parent_clk)
1202                         clk_set_parent(clk, parent_clk);
1203
1204                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1205                         struct clk *base_clk = clk_get_parent(parent_clk);
1206
1207                         /* Assuming either pll_d or pll_d2 is used */
1208                         rate = dc->mode.pclk * 2;
1209
1210                         if (rate != clk_get_rate(base_clk))
1211                                 clk_set_rate(base_clk, rate);
1212                 }
1213         }
1214
1215         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1216                 unsigned long rate;
1217                 struct clk *parent_clk =
1218                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1219                 struct clk *base_clk = clk_get_parent(parent_clk);
1220
1221                 /*
1222                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1223                  * The required rate needs to be setup at 4x multiplier,
1224                  * as out0 is 1/2 of the actual PLL output.
1225                  */
1226
1227                 rate = dc->mode.pclk * 4;
1228                 if (rate != clk_get_rate(base_clk))
1229                         clk_set_rate(base_clk, rate);
1230
1231                 if (clk_get_parent(clk) != parent_clk)
1232                         clk_set_parent(clk, parent_clk);
1233         }
1234
1235         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1236                 unsigned long rate;
1237                 struct clk *parent_clk;
1238                 struct clk *base_clk;
1239
1240                 if (clk == dc->clk) {
1241                         parent_clk = clk_get_sys(NULL,
1242                                         dc->out->parent_clk ? : "pll_d_out0");
1243                         base_clk = clk_get_parent(parent_clk);
1244                         tegra_clk_cfg_ex(base_clk,
1245                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1246                 } else {
1247                         if (dc->pdata->default_out->dsi->dsi_instance) {
1248                                 parent_clk = clk_get_sys(NULL,
1249                                         dc->out->parent_clk ? : "pll_d2_out0");
1250                                 base_clk = clk_get_parent(parent_clk);
1251                                 tegra_clk_cfg_ex(base_clk,
1252                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1253                         } else {
1254                                 parent_clk = clk_get_sys(NULL,
1255                                         dc->out->parent_clk ? : "pll_d_out0");
1256                                 base_clk = clk_get_parent(parent_clk);
1257                                 tegra_clk_cfg_ex(base_clk,
1258                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1259                         }
1260                 }
1261
1262                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1263                 if (rate != clk_get_rate(base_clk))
1264                         clk_set_rate(base_clk, rate);
1265
1266                 if (clk_get_parent(clk) != parent_clk)
1267                         clk_set_parent(clk, parent_clk);
1268         }
1269
1270         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1271         tegra_dvfs_set_rate(clk, pclk);
1272 }
1273
1274 /* return non-zero if constraint is violated */
1275 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1276 {
1277         long a, b;
1278
1279         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1280         a = 0;
1281
1282         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1283         b = mode->h_front_porch - 1;
1284
1285         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1286         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1287                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1288         /* check Constraint 1 and 6 */
1289         if (a > b)
1290                 return 1;
1291
1292         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1293         if (mode->h_sync_width < 1)
1294                 return 4;
1295
1296         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1297         if (mode->h_active < 16)
1298                 return 7;
1299
1300         if (href) {
1301                 if (b > a && a % 2)
1302                         *href = a + 1; /* use smallest even value */
1303                 else
1304                         *href = a; /* even or only possible value */
1305         }
1306
1307         return 0;
1308 }
1309
1310 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1311 {
1312         long a;
1313         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1314
1315         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1316         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1317                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1318
1319         /* Constraint 6 */
1320         if (mode->v_front_porch < a + 1)
1321                 a = mode->v_front_porch - 1;
1322
1323         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1324         if (mode->v_sync_width < 1)
1325                 return 4;
1326
1327         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1328         if (mode->v_active < 16)
1329                 return 7;
1330
1331         if (vref)
1332                 *vref = a;
1333         return 0;
1334 }
1335
1336 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1337 {
1338         int ret;
1339         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1340         if (ret)
1341                 return ret;
1342         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1343         if (ret)
1344                 return ret;
1345
1346         return 0;
1347 }
1348
1349 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1350 {
1351         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1352         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1353                 return false;
1354
1355         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1356         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1357                 return false;
1358
1359         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1360          * (vertical blank). */
1361         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1362                 return false;
1363
1364         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1365         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1366                 return false;
1367
1368         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1369         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1370                 return false;
1371
1372         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1373          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1374         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1375                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1376                 return false;
1377
1378         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1379         if (mode->h_active < 16 || mode->v_active < 16)
1380                 return false;
1381
1382         return true;
1383 }
1384
1385 #ifdef DEBUG
1386 /* return in 1000ths of a Hertz */
1387 static int calc_refresh(const struct tegra_dc_mode *m)
1388 {
1389         long h_total, v_total, refresh;
1390         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1391                 m->h_sync_width;
1392         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1393                 m->v_sync_width;
1394         refresh = m->pclk / h_total;
1395         refresh *= 1000;
1396         refresh /= v_total;
1397         return refresh;
1398 }
1399
1400 static void print_mode(struct tegra_dc *dc,
1401                         const struct tegra_dc_mode *mode, const char *note)
1402 {
1403         if (mode) {
1404                 int refresh = calc_refresh(dc, mode);
1405                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1406                         note ? note : "",
1407                         mode->h_active, mode->v_active,
1408                         refresh / 1000, refresh % 1000,
1409                         mode->pclk);
1410         }
1411 }
1412 #else /* !DEBUG */
1413 static inline void print_mode(struct tegra_dc *dc,
1414                         const struct tegra_dc_mode *mode, const char *note) { }
1415 #endif /* DEBUG */
1416
1417 static inline void enable_dc_irq(unsigned int irq)
1418 {
1419 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1420         enable_irq(irq);
1421 #else
1422         /* Always disable DC interrupts on FPGA. */
1423         disable_irq(irq);
1424 #endif
1425 }
1426
1427 static inline void disable_dc_irq(unsigned int irq)
1428 {
1429         disable_irq(irq);
1430 }
1431
1432 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1433 {
1434         unsigned long val;
1435         unsigned long rate;
1436         unsigned long div;
1437         unsigned long pclk;
1438
1439         print_mode(dc, mode, __func__);
1440
1441         /* use default EMC rate when switching modes */
1442         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1443         tegra_dc_program_bandwidth(dc);
1444
1445         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1446         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1447                         DC_DISP_REF_TO_SYNC);
1448         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1449                         DC_DISP_SYNC_WIDTH);
1450         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1451                         DC_DISP_BACK_PORCH);
1452         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1453                         DC_DISP_DISP_ACTIVE);
1454         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1455                         DC_DISP_FRONT_PORCH);
1456
1457         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1458                         DC_DISP_DATA_ENABLE_OPTIONS);
1459
1460         /* TODO: MIPI/CRT/HDMI clock cals */
1461
1462         val = DISP_DATA_FORMAT_DF1P1C;
1463
1464         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1465                 val |= DISP_DATA_ALIGNMENT_MSB;
1466         else
1467                 val |= DISP_DATA_ALIGNMENT_LSB;
1468
1469         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1470                 val |= DISP_DATA_ORDER_RED_BLUE;
1471         else
1472                 val |= DISP_DATA_ORDER_BLUE_RED;
1473
1474         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1475
1476         rate = tegra_dc_clk_get_rate(dc);
1477
1478         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1479         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1480         if (pclk < (mode->pclk / 100 * 99) ||
1481             pclk > (mode->pclk / 100 * 109)) {
1482                 dev_err(&dc->ndev->dev,
1483                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1484                         rate, mode->pclk,
1485                         pclk, (mode->pclk / 100 * 99),
1486                         (mode->pclk / 100 * 109));
1487                 return -EINVAL;
1488         }
1489
1490         div = (rate * 2 / pclk) - 2;
1491         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1492
1493         tegra_dc_writel(dc, 0x00010001,
1494                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1495         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1496                         DC_DISP_DISP_CLOCK_CONTROL);
1497
1498 #ifdef CONFIG_SWITCH
1499         switch_set_state(&dc->modeset_switch,
1500                          (mode->h_active << 16) | mode->v_active);
1501 #endif
1502
1503         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1504         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1505
1506         print_mode_info(dc, dc->mode);
1507         return 0;
1508 }
1509
1510
1511 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1512 {
1513         memcpy(&dc->mode, mode, sizeof(dc->mode));
1514
1515         print_mode(dc, mode, __func__);
1516
1517         return 0;
1518 }
1519 EXPORT_SYMBOL(tegra_dc_set_mode);
1520
1521 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1522                 const struct fb_videomode *fbmode, bool stereo_mode)
1523 {
1524         struct tegra_dc_mode mode;
1525
1526         if (!fbmode->pixclock)
1527                 return -EINVAL;
1528
1529         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1530         mode.h_sync_width = fbmode->hsync_len;
1531         mode.v_sync_width = fbmode->vsync_len;
1532         mode.h_back_porch = fbmode->left_margin;
1533         mode.v_back_porch = fbmode->upper_margin;
1534         mode.h_active = fbmode->xres;
1535         mode.v_active = fbmode->yres;
1536         mode.h_front_porch = fbmode->right_margin;
1537         mode.v_front_porch = fbmode->lower_margin;
1538         mode.stereo_mode = stereo_mode;
1539         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1540                 /* HDMI controller requires h_ref=1, v_ref=1 */
1541                 mode.h_ref_to_sync = 1;
1542                 mode.v_ref_to_sync = 1;
1543         } else {
1544                 calc_ref_to_sync(&mode);
1545         }
1546         if (!check_ref_to_sync(&mode)) {
1547                 dev_err(&dc->ndev->dev,
1548                                 "Display timing doesn't meet restrictions.\n");
1549                 return -EINVAL;
1550         }
1551         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1552                 mode.h_active, mode.v_active, mode.pclk,
1553                 mode.h_ref_to_sync, mode.v_ref_to_sync
1554         );
1555
1556 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1557         /* Double the pixel clock and update v_active only for frame packed mode */
1558         if (mode.stereo_mode) {
1559                 mode.pclk *= 2;
1560                 /* total v_active = yres*2 + activespace */
1561                 mode.v_active = fbmode->yres*2 +
1562                                 fbmode->vsync_len +
1563                                 fbmode->upper_margin +
1564                                 fbmode->lower_margin;
1565         }
1566 #endif
1567
1568         mode.flags = 0;
1569
1570         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1571                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1572
1573         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1574                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1575
1576         return tegra_dc_set_mode(dc, &mode);
1577 }
1578 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1579
1580 void
1581 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1582 {
1583         unsigned int ctrl;
1584         unsigned long out_sel;
1585         unsigned long cmd_state;
1586
1587         mutex_lock(&dc->lock);
1588         if (!dc->enabled) {
1589                 mutex_unlock(&dc->lock);
1590                 return;
1591         }
1592
1593         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1594                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1595                 cfg->clk_select);
1596
1597         /* The new value should be effected immediately */
1598         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1599         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1600
1601         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1602                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1603         else
1604                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1605
1606         switch (cfg->which_pwm) {
1607         case TEGRA_PWM_PM0:
1608                 /* Select the LM0 on PM0 */
1609                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1610                 out_sel &= ~(7 << 0);
1611                 out_sel |= (3 << 0);
1612                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1613                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1614                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1615                 break;
1616         case TEGRA_PWM_PM1:
1617                 /* Select the LM1 on PM1 */
1618                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1619                 out_sel &= ~(7 << 4);
1620                 out_sel |= (3 << 4);
1621                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1622                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1623                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1624                 break;
1625         default:
1626                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1627                 break;
1628         }
1629         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1630         mutex_unlock(&dc->lock);
1631 }
1632 EXPORT_SYMBOL(tegra_dc_config_pwm);
1633
1634 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1635                                 const struct tegra_dc_out_pin *pins,
1636                                 const unsigned int n_pins)
1637 {
1638         unsigned int i;
1639
1640         int name;
1641         int pol;
1642
1643         u32 pol1, pol3;
1644
1645         u32 set1, unset1;
1646         u32 set3, unset3;
1647
1648         set1 = set3 = unset1 = unset3 = 0;
1649
1650         for (i = 0; i < n_pins; i++) {
1651                 name = (pins + i)->name;
1652                 pol  = (pins + i)->pol;
1653
1654                 /* set polarity by name */
1655                 switch (name) {
1656                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1657                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1658                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1659                         else
1660                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1661                         break;
1662                 case TEGRA_DC_OUT_PIN_H_SYNC:
1663                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1664                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1665                         else
1666                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1667                         break;
1668                 case TEGRA_DC_OUT_PIN_V_SYNC:
1669                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1670                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1671                         else
1672                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1673                         break;
1674                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1675                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1676                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1677                         else
1678                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1679                         break;
1680                 default:
1681                         printk("Invalid argument in function %s\n",
1682                                __FUNCTION__);
1683                         break;
1684                 }
1685         }
1686
1687         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1688         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1689
1690         pol1 |= set1;
1691         pol1 &= ~unset1;
1692
1693         pol3 |= set3;
1694         pol3 &= ~unset3;
1695
1696         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1697         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1698 }
1699
1700 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1701 {
1702         dc->out = out;
1703
1704         if (out->n_modes > 0)
1705                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1706
1707         switch (out->type) {
1708         case TEGRA_DC_OUT_RGB:
1709                 dc->out_ops = &tegra_dc_rgb_ops;
1710                 break;
1711
1712         case TEGRA_DC_OUT_HDMI:
1713                 dc->out_ops = &tegra_dc_hdmi_ops;
1714                 break;
1715
1716         case TEGRA_DC_OUT_DSI:
1717                 dc->out_ops = &tegra_dc_dsi_ops;
1718                 break;
1719
1720         default:
1721                 dc->out_ops = NULL;
1722                 break;
1723         }
1724
1725         if (dc->out_ops && dc->out_ops->init)
1726                 dc->out_ops->init(dc);
1727
1728 }
1729
1730 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1731 {
1732         if (dc->out)
1733                 return dc->out->height;
1734         else
1735                 return 0;
1736 }
1737 EXPORT_SYMBOL(tegra_dc_get_out_height);
1738
1739 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1740 {
1741         if (dc->out)
1742                 return dc->out->width;
1743         else
1744                 return 0;
1745 }
1746 EXPORT_SYMBOL(tegra_dc_get_out_width);
1747
1748 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1749 {
1750         if (dc->out && dc->out->max_pixclock)
1751                 return dc->out->max_pixclock;
1752         else
1753                 return 0;
1754 }
1755 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1756
1757 void tegra_dc_enable_crc(struct tegra_dc *dc)
1758 {
1759         u32 val;
1760         tegra_dc_io_start(dc);
1761
1762         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1763                 CRC_ENABLE_ENABLE;
1764         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1765         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1766         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1767 }
1768
1769 void tegra_dc_disable_crc(struct tegra_dc *dc)
1770 {
1771         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1772         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1773         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1774
1775         tegra_dc_io_end(dc);
1776 }
1777
1778 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1779 {
1780         int crc = 0;
1781
1782         if (!dc) {
1783                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1784                 goto crc_error;
1785         }
1786
1787         /* TODO: Replace mdelay with code to sync VBlANK, since
1788          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1789         mdelay(TEGRA_CRC_LATCHED_DELAY);
1790
1791         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1792 crc_error:
1793         return crc;
1794 }
1795
1796 static void tegra_dc_vblank(struct work_struct *work)
1797 {
1798         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1799         bool nvsd_updated = false;
1800
1801         mutex_lock(&dc->lock);
1802         /* use the new frame's bandwidth setting instead of max(current, new),
1803          * skip this if we're using tegra_dc_one_shot_worker() */
1804         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1805                 tegra_dc_program_bandwidth(dc);
1806
1807         /* Update the SD brightness */
1808         if (dc->enabled && dc->out->sd_settings)
1809                 nvsd_updated = nvsd_update_brightness(dc);
1810
1811         mutex_unlock(&dc->lock);
1812
1813         /* Do the actual brightness update outside of the mutex */
1814         if (nvsd_updated && dc->out->sd_settings &&
1815             dc->out->sd_settings->bl_device) {
1816
1817                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1818                 struct backlight_device *bl = platform_get_drvdata(pdev);
1819                 if (bl)
1820                         backlight_update_status(bl);
1821         }
1822 }
1823
1824 static void tegra_dc_one_shot_worker(struct work_struct *work)
1825 {
1826         struct tegra_dc *dc = container_of(
1827                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1828         mutex_lock(&dc->lock);
1829         /* memory client has gone idle */
1830         tegra_dc_clear_bandwidth(dc);
1831         mutex_unlock(&dc->lock);
1832 }
1833
1834 /* return an arbitrarily large number if count overflow occurs.
1835  * make it a nice base-10 number to show up in stats output */
1836 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1837 {
1838         unsigned count = tegra_dc_readl(dc, reg);
1839         tegra_dc_writel(dc, 0, reg);
1840         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1841 }
1842
1843 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1844 {
1845         u32 val;
1846         int i;
1847
1848         dc->stats.underflows++;
1849         if (dc->underflow_mask & WIN_A_UF_INT) {
1850                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1851                         DC_WINBUF_AD_UFLOW_STATUS);
1852                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1853         }
1854         if (dc->underflow_mask & WIN_B_UF_INT) {
1855                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1856                         DC_WINBUF_BD_UFLOW_STATUS);
1857                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1858         }
1859         if (dc->underflow_mask & WIN_C_UF_INT) {
1860                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1861                         DC_WINBUF_CD_UFLOW_STATUS);
1862                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1863         }
1864
1865         /* Check for any underflow reset conditions */
1866         for (i = 0; i < DC_N_WINDOWS; i++) {
1867                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1868                         dc->windows[i].underflows++;
1869
1870 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1871                         if (dc->windows[i].underflows > 4) {
1872                                 schedule_work(&dc->reset_work);
1873                                 /* reset counter */
1874                                 dc->windows[i].underflows = 0;
1875                                 trace_printk("%s:Reset work scheduled for "
1876                                                 "window %c\n",
1877                                                 dc->ndev->name, (65 + i));
1878                         }
1879 #endif
1880                 } else {
1881                         dc->windows[i].underflows = 0;
1882                 }
1883         }
1884
1885         /* Clear the underflow mask now that we've checked it. */
1886         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1887         dc->underflow_mask = 0;
1888         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1889         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1890         print_underflow_info(dc);
1891 }
1892
1893 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1894 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1895 {
1896 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1897         u32 val;
1898
1899         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1900         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
1901             return true;
1902 #endif
1903         return false;
1904 }
1905
1906 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
1907 {
1908         u32 val, i;
1909         u32 completed = 0;
1910         u32 dirty = 0;
1911
1912         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1913         for (i = 0; i < DC_N_WINDOWS; i++) {
1914 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1915                 /* FIXME: this is not needed when the simulator
1916                    clears WIN_x_UPDATE bits as in HW */
1917                 dc->windows[i].dirty = 0;
1918                 completed = 1;
1919 #else
1920                 if (!(val & (WIN_A_UPDATE << i))) {
1921                         dc->windows[i].dirty = 0;
1922                         completed = 1;
1923                 } else {
1924                         dirty = 1;
1925                 }
1926 #endif
1927         }
1928
1929         if (!dirty) {
1930                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1931                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1932                         val &= ~V_BLANK_INT;
1933                 else
1934                         val &= ~FRAME_END_INT;
1935                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1936         }
1937
1938         if (completed) {
1939                 if (!dirty) {
1940                         /* With the last completed window, go ahead
1941                            and enable the vblank interrupt for nvsd. */
1942                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1943                         val |= V_BLANK_INT;
1944                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1945                 }
1946
1947                 wake_up(&dc->wq);
1948         }
1949 }
1950
1951 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1952 {
1953         if (status & V_BLANK_INT) {
1954                 /* Sync up windows. */
1955                 tegra_dc_trigger_windows(dc);
1956
1957                 /* Schedule any additional bottom-half vblank actvities. */
1958                 schedule_work(&dc->vblank_work);
1959         }
1960
1961         if (status & FRAME_END_INT) {
1962                 /* Mark the frame_end as complete. */
1963                 if (!completion_done(&dc->frame_end_complete))
1964                         complete(&dc->frame_end_complete);
1965         }
1966 }
1967
1968 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1969 {
1970         if (status & V_BLANK_INT) {
1971                 /* Schedule any additional bottom-half vblank actvities. */
1972                 schedule_work(&dc->vblank_work);
1973
1974                 /* All windows updated. Mask subsequent V_BLANK interrupts */
1975                 if (!tegra_dc_windows_are_dirty(dc)) {
1976                         u32 val;
1977
1978                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1979                         val &= ~V_BLANK_INT;
1980                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1981                 }
1982         }
1983
1984         if (status & FRAME_END_INT) {
1985                 /* Mark the frame_end as complete. */
1986                 if (!completion_done(&dc->frame_end_complete))
1987                         complete(&dc->frame_end_complete);
1988
1989                 tegra_dc_trigger_windows(dc);
1990         }
1991 }
1992 #endif
1993
1994 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1995 {
1996 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1997         struct tegra_dc *dc = ptr;
1998         unsigned long status;
1999         unsigned long underflow_mask;
2000         u32 val;
2001
2002         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2003                 WARN(1, "IRQ when DC not powered!\n");
2004                 tegra_dc_io_start(dc);
2005                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2006                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2007                 tegra_dc_io_end(dc);
2008                 return IRQ_HANDLED;
2009         }
2010
2011         /* clear all status flags except underflow, save those for the worker */
2012         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2013         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2014         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2015         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2016
2017         /*
2018          * Overlays can get thier internal state corrupted during and underflow
2019          * condition.  The only way to fix this state is to reset the DC.
2020          * if we get 4 consecutive frames with underflows, assume we're
2021          * hosed and reset.
2022          */
2023         underflow_mask = status & ALL_UF_INT;
2024
2025         /* Check underflow */
2026         if (underflow_mask) {
2027                 dc->underflow_mask |= underflow_mask;
2028                 schedule_delayed_work(&dc->underflow_work,
2029                         msecs_to_jiffies(1));
2030         }
2031
2032         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2033                 tegra_dc_one_shot_irq(dc, status);
2034         else
2035                 tegra_dc_continuous_irq(dc, status);
2036
2037         return IRQ_HANDLED;
2038 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2039         return IRQ_NONE;
2040 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2041 }
2042
2043 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2044 {
2045         u32 color_control;
2046
2047         switch (dc->out->depth) {
2048         case 3:
2049                 color_control = BASE_COLOR_SIZE111;
2050                 break;
2051
2052         case 6:
2053                 color_control = BASE_COLOR_SIZE222;
2054                 break;
2055
2056         case 8:
2057                 color_control = BASE_COLOR_SIZE332;
2058                 break;
2059
2060         case 9:
2061                 color_control = BASE_COLOR_SIZE333;
2062                 break;
2063
2064         case 12:
2065                 color_control = BASE_COLOR_SIZE444;
2066                 break;
2067
2068         case 15:
2069                 color_control = BASE_COLOR_SIZE555;
2070                 break;
2071
2072         case 16:
2073                 color_control = BASE_COLOR_SIZE565;
2074                 break;
2075
2076         case 18:
2077                 color_control = BASE_COLOR_SIZE666;
2078                 break;
2079
2080         default:
2081                 color_control = BASE_COLOR_SIZE888;
2082                 break;
2083         }
2084
2085         switch (dc->out->dither) {
2086         case TEGRA_DC_DISABLE_DITHER:
2087                 color_control |= DITHER_CONTROL_DISABLE;
2088                 break;
2089         case TEGRA_DC_ORDERED_DITHER:
2090                 color_control |= DITHER_CONTROL_ORDERED;
2091                 break;
2092         case TEGRA_DC_ERRDIFF_DITHER:
2093                 /* The line buffer for error-diffusion dither is limited
2094                  * to 1280 pixels per line. This limits the maximum
2095                  * horizontal active area size to 1280 pixels when error
2096                  * diffusion is enabled.
2097                  */
2098                 BUG_ON(dc->mode.h_active > 1280);
2099                 color_control |= DITHER_CONTROL_ERRDIFF;
2100                 break;
2101         }
2102
2103         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2104 }
2105
2106 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2107 {
2108         u32 syncpt_id;
2109
2110         switch (dc->ndev->id) {
2111         case 0:
2112                 switch (idx) {
2113                 case 0:
2114                         syncpt_id = NVSYNCPT_DISP0_A;
2115                         break;
2116                 case 1:
2117                         syncpt_id = NVSYNCPT_DISP0_B;
2118                         break;
2119                 case 2:
2120                         syncpt_id = NVSYNCPT_DISP0_C;
2121                         break;
2122                 default:
2123                         BUG();
2124                         break;
2125                 }
2126                 break;
2127         case 1:
2128                 switch (idx) {
2129                 case 0:
2130                         syncpt_id = NVSYNCPT_DISP1_A;
2131                         break;
2132                 case 1:
2133                         syncpt_id = NVSYNCPT_DISP1_B;
2134                         break;
2135                 case 2:
2136                         syncpt_id = NVSYNCPT_DISP1_C;
2137                         break;
2138                 default:
2139                         BUG();
2140                         break;
2141                 }
2142                 break;
2143         default:
2144                 BUG();
2145                 break;
2146         }
2147
2148         return syncpt_id;
2149 }
2150
2151 static int tegra_dc_init(struct tegra_dc *dc)
2152 {
2153         int i;
2154
2155         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2156         if (dc->ndev->id == 0) {
2157                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2158                                       TEGRA_MC_PRIO_MED);
2159                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2160                                       TEGRA_MC_PRIO_MED);
2161                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2162                                       TEGRA_MC_PRIO_MED);
2163                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2164                                       TEGRA_MC_PRIO_MED);
2165                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2166                                       TEGRA_MC_PRIO_HIGH);
2167         } else if (dc->ndev->id == 1) {
2168                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2169                                       TEGRA_MC_PRIO_MED);
2170                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2171                                       TEGRA_MC_PRIO_MED);
2172                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2173                                       TEGRA_MC_PRIO_MED);
2174                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2175                                       TEGRA_MC_PRIO_MED);
2176                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2177                                       TEGRA_MC_PRIO_HIGH);
2178         }
2179         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2180                         DC_CMD_CONT_SYNCPT_VSYNC);
2181         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2182         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2183         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2184         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2185
2186         /* enable interrupts for vblank, frame_end and underflows */
2187         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2188                 DC_CMD_INT_ENABLE);
2189         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2190
2191         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2192
2193         tegra_dc_set_color_control(dc);
2194         for (i = 0; i < DC_N_WINDOWS; i++) {
2195                 struct tegra_dc_win *win = &dc->windows[i];
2196                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2197                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2198                 tegra_dc_set_csc(dc, &win->csc);
2199                 tegra_dc_set_lut(dc, win);
2200                 tegra_dc_set_scaling_filter(dc);
2201         }
2202
2203
2204         for (i = 0; i < dc->n_windows; i++) {
2205                 u32 syncpt = get_syncpt(dc, i);
2206
2207                 dc->syncpt[i].id = syncpt;
2208
2209                 dc->syncpt[i].min = dc->syncpt[i].max =
2210                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2211                                         syncpt);
2212         }
2213
2214         print_mode(dc, &dc->mode, __func__);
2215
2216         if (dc->mode.pclk)
2217                 if (tegra_dc_program_mode(dc, &dc->mode))
2218                         return -EINVAL;
2219
2220         /* Initialize SD AFTER the modeset.
2221            nvsd_init handles the sd_settings = NULL case. */
2222         nvsd_init(dc, dc->out->sd_settings);
2223
2224         return 0;
2225 }
2226
2227 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2228 {
2229         int failed_init = 0;
2230
2231         if (dc->out->enable)
2232                 dc->out->enable();
2233
2234         tegra_dc_setup_clk(dc, dc->clk);
2235         clk_enable(dc->clk);
2236
2237         /* do not accept interrupts during initialization */
2238         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2239         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2240
2241         enable_dc_irq(dc->irq);
2242
2243         failed_init = tegra_dc_init(dc);
2244         if (failed_init) {
2245                 _tegra_dc_controller_disable(dc);
2246                 return false;
2247         }
2248
2249         if (dc->out_ops && dc->out_ops->enable)
2250                 dc->out_ops->enable(dc);
2251
2252         if (dc->out->postpoweron)
2253                 dc->out->postpoweron();
2254
2255         /* force a full blending update */
2256         dc->blend.z[0] = -1;
2257
2258         tegra_dc_ext_enable(dc->ext);
2259
2260         trace_printk("%s:enable\n", dc->ndev->name);
2261         return true;
2262 }
2263
2264 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2265 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2266 {
2267         bool ret = true;
2268
2269         if (dc->out->enable)
2270                 dc->out->enable();
2271
2272         tegra_dc_setup_clk(dc, dc->clk);
2273         clk_enable(dc->clk);
2274
2275         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2276                 mutex_lock(&tegra_dcs[1]->lock);
2277                 disable_irq(tegra_dcs[1]->irq);
2278         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2279                 mutex_lock(&tegra_dcs[0]->lock);
2280                 disable_irq(tegra_dcs[0]->irq);
2281         }
2282
2283         msleep(5);
2284         tegra_periph_reset_assert(dc->clk);
2285         msleep(2);
2286 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2287         tegra_periph_reset_deassert(dc->clk);
2288         msleep(1);
2289 #endif
2290
2291         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2292                 enable_dc_irq(tegra_dcs[1]->irq);
2293                 mutex_unlock(&tegra_dcs[1]->lock);
2294         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2295                 enable_dc_irq(tegra_dcs[0]->irq);
2296                 mutex_unlock(&tegra_dcs[0]->lock);
2297         }
2298
2299         enable_dc_irq(dc->irq);
2300
2301         if (tegra_dc_init(dc)) {
2302                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2303                 ret = false;
2304         }
2305
2306         if (dc->out_ops && dc->out_ops->enable)
2307                 dc->out_ops->enable(dc);
2308
2309         if (dc->out->postpoweron)
2310                 dc->out->postpoweron();
2311
2312         /* force a full blending update */
2313         dc->blend.z[0] = -1;
2314
2315         tegra_dc_ext_enable(dc->ext);
2316
2317         if (!ret) {
2318                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2319                 _tegra_dc_controller_disable(dc);
2320         }
2321
2322         trace_printk("%s:reset enable\n", dc->ndev->name);
2323         return ret;
2324 }
2325 #endif
2326
2327 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2328 {
2329         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2330 }
2331
2332 static bool _tegra_dc_enable(struct tegra_dc *dc)
2333 {
2334         if (dc->mode.pclk == 0) {
2335                 switch (dc->out->type) {
2336                 case TEGRA_DC_OUT_HDMI:
2337                 /* DC enable called but no videomode is loaded.
2338                      Check if HDMI is connected, then set fallback mdoe */
2339                 if (tegra_dc_hpd(dc)) {
2340                         if (_tegra_dc_set_default_videomode(dc))
2341                                 return false;
2342                 } else
2343                         return false;
2344
2345                 break;
2346
2347                 /* Do nothing for other outputs for now */
2348                 case TEGRA_DC_OUT_RGB:
2349
2350                 case TEGRA_DC_OUT_DSI:
2351
2352                 default:
2353                         return false;
2354                 }
2355         }
2356
2357         if (!dc->out)
2358                 return false;
2359
2360         tegra_dc_io_start(dc);
2361
2362         return _tegra_dc_controller_enable(dc);
2363 }
2364
2365 void tegra_dc_enable(struct tegra_dc *dc)
2366 {
2367         mutex_lock(&dc->lock);
2368
2369         if (!dc->enabled)
2370                 dc->enabled = _tegra_dc_enable(dc);
2371
2372         mutex_unlock(&dc->lock);
2373         print_mode_info(dc, dc->mode);
2374 }
2375
2376 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2377 {
2378         unsigned i;
2379
2380         if (dc->out_ops && dc->out_ops->disable)
2381                 dc->out_ops->disable(dc);
2382
2383         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2384         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2385         disable_irq(dc->irq);
2386
2387         tegra_dc_clear_bandwidth(dc);
2388         clk_disable(dc->clk);
2389         tegra_dvfs_set_rate(dc->clk, 0);
2390
2391         if (dc->out && dc->out->disable)
2392                 dc->out->disable();
2393
2394         for (i = 0; i < dc->n_windows; i++) {
2395                 struct tegra_dc_win *w = &dc->windows[i];
2396
2397                 /* reset window bandwidth */
2398                 w->bandwidth = 0;
2399                 w->new_bandwidth = 0;
2400
2401                 /* disable windows */
2402                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2403
2404                 /* flush any pending syncpt waits */
2405                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2406                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2407                                 dc->syncpt[i].id);
2408                         dc->syncpt[i].min++;
2409                         nvhost_syncpt_cpu_incr(
2410                                 &nvhost_get_host(dc->ndev)->syncpt,
2411                                 dc->syncpt[i].id);
2412                 }
2413         }
2414         trace_printk("%s:disabled\n", dc->ndev->name);
2415 }
2416
2417 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2418 {
2419 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2420         u32 val;
2421         if (dc->enabled)  {
2422                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2423                 if (enable)
2424                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2425                 else
2426                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2427                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2428         }
2429 #endif
2430 }
2431
2432 bool tegra_dc_stats_get(struct tegra_dc *dc)
2433 {
2434 #if 0 /* right now it is always enabled */
2435         u32 val;
2436         bool res;
2437
2438         if (dc->enabled)  {
2439                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2440                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2441         } else {
2442                 res = false;
2443         }
2444
2445         return res;
2446 #endif
2447         return true;
2448 }
2449
2450 /* make the screen blank by disabling all windows */
2451 void tegra_dc_blank(struct tegra_dc *dc)
2452 {
2453         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2454         unsigned i;
2455
2456         for (i = 0; i < DC_N_WINDOWS; i++) {
2457                 dcwins[i] = tegra_dc_get_window(dc, i);
2458                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2459         }
2460
2461         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2462         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2463 }
2464
2465 static void _tegra_dc_disable(struct tegra_dc *dc)
2466 {
2467         _tegra_dc_controller_disable(dc);
2468         tegra_dc_io_end(dc);
2469 }
2470
2471 void tegra_dc_disable(struct tegra_dc *dc)
2472 {
2473         tegra_dc_ext_disable(dc->ext);
2474
2475         /* it's important that new underflow work isn't scheduled before the
2476          * lock is acquired. */
2477         cancel_delayed_work_sync(&dc->underflow_work);
2478         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2479                 mutex_lock(&dc->one_shot_lock);
2480                 cancel_delayed_work_sync(&dc->one_shot_work);
2481         }
2482
2483         mutex_lock(&dc->lock);
2484
2485         if (dc->enabled) {
2486                 dc->enabled = false;
2487
2488                 if (!dc->suspended)
2489                         _tegra_dc_disable(dc);
2490         }
2491
2492 #ifdef CONFIG_SWITCH
2493         switch_set_state(&dc->modeset_switch, 0);
2494 #endif
2495
2496         mutex_unlock(&dc->lock);
2497         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2498                 mutex_unlock(&dc->one_shot_lock);
2499         print_mode_info(dc, dc->mode);
2500 }
2501
2502 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2503 static void tegra_dc_reset_worker(struct work_struct *work)
2504 {
2505         struct tegra_dc *dc =
2506                 container_of(work, struct tegra_dc, reset_work);
2507
2508         unsigned long val = 0;
2509
2510         mutex_lock(&shared_lock);
2511
2512         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2513
2514         tegra_dc_ext_disable(dc->ext);
2515
2516         mutex_lock(&dc->lock);
2517
2518         if (dc->enabled == false)
2519                 goto unlock;
2520
2521         dc->enabled = false;
2522
2523         /*
2524          * off host read bus
2525          */
2526         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2527         val &= ~(0x00000100);
2528         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2529
2530         /*
2531          * set DC to STOP mode
2532          */
2533         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2534
2535         msleep(10);
2536
2537         _tegra_dc_controller_disable(dc);
2538
2539         /* _tegra_dc_controller_reset_enable deasserts reset */
2540         _tegra_dc_controller_reset_enable(dc);
2541
2542         dc->enabled = true;
2543
2544         /* reopen host read bus */
2545         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2546         val &= ~(0x00000100);
2547         val |= 0x100;
2548         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2549
2550 unlock:
2551         mutex_unlock(&dc->lock);
2552         mutex_unlock(&shared_lock);
2553         trace_printk("%s:reset complete\n", dc->ndev->name);
2554 }
2555 #endif
2556
2557 static void tegra_dc_underflow_worker(struct work_struct *work)
2558 {
2559         struct tegra_dc *dc = container_of(
2560                 to_delayed_work(work), struct tegra_dc, underflow_work);
2561
2562         mutex_lock(&dc->lock);
2563         if (dc->enabled) {
2564                 tegra_dc_underflow_handler(dc);
2565         }
2566         mutex_unlock(&dc->lock);
2567 }
2568
2569 #ifdef CONFIG_SWITCH
2570 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2571 {
2572         struct tegra_dc *dc =
2573                 container_of(sdev, struct tegra_dc, modeset_switch);
2574
2575         if (!sdev->state)
2576                 return sprintf(buf, "offline\n");
2577
2578         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2579 }
2580 #endif
2581
2582 static int tegra_dc_probe(struct nvhost_device *ndev,
2583         struct nvhost_device_id *id_table)
2584 {
2585         struct tegra_dc *dc;
2586         struct clk *clk;
2587         struct clk *emc_clk;
2588         struct resource *res;
2589         struct resource *base_res;
2590         struct resource *fb_mem = NULL;
2591         int ret = 0;
2592         void __iomem *base;
2593         int irq;
2594         int i;
2595
2596         if (!ndev->dev.platform_data) {
2597                 dev_err(&ndev->dev, "no platform data\n");
2598                 return -ENOENT;
2599         }
2600
2601         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2602         if (!dc) {
2603                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2604                 return -ENOMEM;
2605         }
2606
2607         irq = nvhost_get_irq_byname(ndev, "irq");
2608         if (irq <= 0) {
2609                 dev_err(&ndev->dev, "no irq\n");
2610                 ret = -ENOENT;
2611                 goto err_free;
2612         }
2613
2614         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2615         if (!res) {
2616                 dev_err(&ndev->dev, "no mem resource\n");
2617                 ret = -ENOENT;
2618                 goto err_free;
2619         }
2620
2621         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2622         if (!base_res) {
2623                 dev_err(&ndev->dev, "request_mem_region failed\n");
2624                 ret = -EBUSY;
2625                 goto err_free;
2626         }
2627
2628         base = ioremap(res->start, resource_size(res));
2629         if (!base) {
2630                 dev_err(&ndev->dev, "registers can't be mapped\n");
2631                 ret = -EBUSY;
2632                 goto err_release_resource_reg;
2633         }
2634
2635         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2636
2637         clk = clk_get(&ndev->dev, NULL);
2638         if (IS_ERR_OR_NULL(clk)) {
2639                 dev_err(&ndev->dev, "can't get clock\n");
2640                 ret = -ENOENT;
2641                 goto err_iounmap_reg;
2642         }
2643
2644         emc_clk = clk_get(&ndev->dev, "emc");
2645         if (IS_ERR_OR_NULL(emc_clk)) {
2646                 dev_err(&ndev->dev, "can't get emc clock\n");
2647                 ret = -ENOENT;
2648                 goto err_put_clk;
2649         }
2650
2651         dc->clk = clk;
2652         dc->emc_clk = emc_clk;
2653         dc->shift_clk_div = 1;
2654         /* Initialize one shot work delay, it will be assigned by dsi
2655          * according to refresh rate later. */
2656         dc->one_shot_delay_ms = 40;
2657
2658         dc->base_res = base_res;
2659         dc->base = base;
2660         dc->irq = irq;
2661         dc->ndev = ndev;
2662         dc->pdata = ndev->dev.platform_data;
2663
2664         /*
2665          * The emc is a shared clock, it will be set based on
2666          * the requirements for each user on the bus.
2667          */
2668         dc->emc_clk_rate = 0;
2669
2670         mutex_init(&dc->lock);
2671         mutex_init(&dc->one_shot_lock);
2672         init_completion(&dc->frame_end_complete);
2673         init_waitqueue_head(&dc->wq);
2674 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2675         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2676 #endif
2677         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2678         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2679         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2680
2681         tegra_dc_init_lut_defaults(&dc->fb_lut);
2682
2683         dc->n_windows = DC_N_WINDOWS;
2684         for (i = 0; i < dc->n_windows; i++) {
2685                 struct tegra_dc_win *win = &dc->windows[i];
2686                 win->idx = i;
2687                 win->dc = dc;
2688                 tegra_dc_init_csc_defaults(&win->csc);
2689                 tegra_dc_init_lut_defaults(&win->lut);
2690         }
2691
2692         ret = tegra_dc_set(dc, ndev->id);
2693         if (ret < 0) {
2694                 dev_err(&ndev->dev, "can't add dc\n");
2695                 goto err_free_irq;
2696         }
2697
2698         nvhost_set_drvdata(ndev, dc);
2699
2700 #ifdef CONFIG_SWITCH
2701         dc->modeset_switch.name = dev_name(&ndev->dev);
2702         dc->modeset_switch.state = 0;
2703         dc->modeset_switch.print_state = switch_modeset_print_mode;
2704         switch_dev_register(&dc->modeset_switch);
2705 #endif
2706
2707         tegra_dc_feature_register(dc);
2708
2709         if (dc->pdata->default_out)
2710                 tegra_dc_set_out(dc, dc->pdata->default_out);
2711         else
2712                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2713
2714         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2715                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2716
2717         dc->ext = tegra_dc_ext_register(ndev, dc);
2718         if (IS_ERR_OR_NULL(dc->ext)) {
2719                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2720                 dc->ext = NULL;
2721         }
2722
2723         mutex_lock(&dc->lock);
2724         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2725                 dc->enabled = _tegra_dc_enable(dc);
2726         mutex_unlock(&dc->lock);
2727
2728         /* interrupt handler must be registered before tegra_fb_register() */
2729         if (request_irq(irq, tegra_dc_irq, 0,
2730                         dev_name(&ndev->dev), dc)) {
2731                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2732                 ret = -EBUSY;
2733                 goto err_put_emc_clk;
2734         }
2735
2736         tegra_dc_create_debugfs(dc);
2737
2738         dev_info(&ndev->dev, "probed\n");
2739
2740         if (dc->pdata->fb) {
2741                 if (dc->pdata->fb->bits_per_pixel == -1) {
2742                         unsigned long fmt;
2743                         tegra_dc_writel(dc,
2744                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2745                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2746
2747                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2748                         dc->pdata->fb->bits_per_pixel =
2749                                 tegra_dc_fmt_bpp(fmt);
2750                 }
2751
2752                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2753                 if (IS_ERR_OR_NULL(dc->fb))
2754                         dc->fb = NULL;
2755         }
2756
2757         if (dc->out && dc->out->hotplug_init)
2758                 dc->out->hotplug_init();
2759
2760         if (dc->out_ops && dc->out_ops->detect)
2761                 dc->out_ops->detect(dc);
2762         else
2763                 dc->connected = true;
2764
2765         tegra_dc_create_sysfs(&dc->ndev->dev);
2766
2767         return 0;
2768
2769 err_free_irq:
2770         free_irq(irq, dc);
2771 err_put_emc_clk:
2772         clk_put(emc_clk);
2773 err_put_clk:
2774         clk_put(clk);
2775 err_iounmap_reg:
2776         iounmap(base);
2777         if (fb_mem)
2778                 release_resource(fb_mem);
2779 err_release_resource_reg:
2780         release_resource(base_res);
2781 err_free:
2782         kfree(dc);
2783
2784         return ret;
2785 }
2786
2787 static int tegra_dc_remove(struct nvhost_device *ndev)
2788 {
2789         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2790
2791         tegra_dc_remove_sysfs(&dc->ndev->dev);
2792         tegra_dc_remove_debugfs(dc);
2793
2794         if (dc->fb) {
2795                 tegra_fb_unregister(dc->fb);
2796                 if (dc->fb_mem)
2797                         release_resource(dc->fb_mem);
2798         }
2799
2800         tegra_dc_ext_disable(dc->ext);
2801
2802         if (dc->ext)
2803                 tegra_dc_ext_unregister(dc->ext);
2804
2805         if (dc->enabled)
2806                 _tegra_dc_disable(dc);
2807
2808 #ifdef CONFIG_SWITCH
2809         switch_dev_unregister(&dc->modeset_switch);
2810 #endif
2811         free_irq(dc->irq, dc);
2812         clk_put(dc->emc_clk);
2813         clk_put(dc->clk);
2814         iounmap(dc->base);
2815         if (dc->fb_mem)
2816                 release_resource(dc->base_res);
2817         kfree(dc);
2818         tegra_dc_set(NULL, ndev->id);
2819         return 0;
2820 }
2821
2822 #ifdef CONFIG_PM
2823 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2824 {
2825         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2826
2827         trace_printk("%s:suspend\n", dc->ndev->name);
2828         dev_info(&ndev->dev, "suspend\n");
2829
2830         tegra_dc_ext_disable(dc->ext);
2831
2832         mutex_lock(&dc->lock);
2833
2834         if (dc->out_ops && dc->out_ops->suspend)
2835                 dc->out_ops->suspend(dc);
2836
2837         if (dc->enabled) {
2838                 _tegra_dc_disable(dc);
2839
2840                 dc->suspended = true;
2841         }
2842
2843         if (dc->out && dc->out->postsuspend) {
2844                 dc->out->postsuspend();
2845                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2846                         /*
2847                          * avoid resume event due to voltage falling
2848                          */
2849                         msleep(100);
2850         }
2851
2852         mutex_unlock(&dc->lock);
2853
2854         return 0;
2855 }
2856
2857 static int tegra_dc_resume(struct nvhost_device *ndev)
2858 {
2859         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2860
2861         trace_printk("%s:resume\n", dc->ndev->name);
2862         dev_info(&ndev->dev, "resume\n");
2863
2864         mutex_lock(&dc->lock);
2865         dc->suspended = false;
2866
2867         if (dc->enabled)
2868                 _tegra_dc_enable(dc);
2869
2870         if (dc->out && dc->out->hotplug_init)
2871                 dc->out->hotplug_init();
2872
2873         if (dc->out_ops && dc->out_ops->resume)
2874                 dc->out_ops->resume(dc);
2875         mutex_unlock(&dc->lock);
2876
2877         return 0;
2878 }
2879
2880 #endif /* CONFIG_PM */
2881
2882 extern int suspend_set(const char *val, struct kernel_param *kp)
2883 {
2884         if (!strcmp(val, "dump"))
2885                 dump_regs(tegra_dcs[0]);
2886 #ifdef CONFIG_PM
2887         else if (!strcmp(val, "suspend"))
2888                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2889         else if (!strcmp(val, "resume"))
2890                 tegra_dc_resume(tegra_dcs[0]->ndev);
2891 #endif
2892
2893         return 0;
2894 }
2895
2896 extern int suspend_get(char *buffer, struct kernel_param *kp)
2897 {
2898         return 0;
2899 }
2900
2901 int suspend;
2902
2903 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2904
2905 struct nvhost_driver tegra_dc_driver = {
2906         .driver = {
2907                 .name = "tegradc",
2908                 .owner = THIS_MODULE,
2909         },
2910         .probe = tegra_dc_probe,
2911         .remove = tegra_dc_remove,
2912 #ifdef CONFIG_PM
2913         .suspend = tegra_dc_suspend,
2914         .resume = tegra_dc_resume,
2915 #endif
2916 };
2917
2918 static int __init tegra_dc_module_init(void)
2919 {
2920         int ret = tegra_dc_ext_module_init();
2921         if (ret)
2922                 return ret;
2923         return nvhost_driver_register(&tegra_dc_driver);
2924 }
2925
2926 static void __exit tegra_dc_module_exit(void)
2927 {
2928         nvhost_driver_unregister(&tegra_dc_driver);
2929         tegra_dc_ext_module_exit();
2930 }
2931
2932 module_exit(tegra_dc_module_exit);
2933 module_init(tegra_dc_module_init);