video: tegra: dc: Use ref-count to mask vblank interrupt.
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39 #ifdef CONFIG_SWITCH
40 #include <linux/switch.h>
41 #endif
42
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
62 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
63 #else
64 /* ignore underflows when on simulation and fpga platform */
65 #define ALL_UF_INT (0)
66 #endif
67
68 static int no_vsync;
69 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
70         .refresh = 60,
71         .xres = 640,
72         .yres = 480,
73         .pixclock = KHZ2PICOS(25200),
74         .hsync_len = 96,        /* h_sync_width */
75         .vsync_len = 2,         /* v_sync_width */
76         .left_margin = 48,      /* h_back_porch */
77         .upper_margin = 33,     /* v_back_porch */
78         .right_margin = 16,     /* h_front_porch */
79         .lower_margin = 10,     /* v_front_porch */
80         .vmode = 0,
81         .sync = 0,
82 };
83
84 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
85
86 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
87
88 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
89
90 DEFINE_MUTEX(tegra_dc_lock);
91 DEFINE_MUTEX(shared_lock);
92
93 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
94 {
95         if (!tegra_is_clk_enabled(dc->clk)) {
96                 clk_enable(dc->clk);
97                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
98         }
99 }
100
101 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
102 {
103         if (tegra_is_clk_enabled(dc->clk)) {
104                 clk_disable(dc->clk);
105                 tegra_dvfs_set_rate(dc->clk, 0);
106         }
107 }
108
109 #define DUMP_REG(a) do {                        \
110         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
111                  #a, a, tegra_dc_readl(dc, a));               \
112         print(data, buff);                                    \
113         } while (0)
114
115 #define print_mode_info(dc, mode) do {                        \
116         trace_printk("%s:Mode settings: "                              \
117                         "ref_to_sync: H = %d V = %d, "                  \
118                         "sync_width: H = %d V = %d, "                   \
119                         "back_porch: H = %d V = %d, "                   \
120                         "active: H = %d V = %d, "                       \
121                         "front_porch: H = %d V = %d, "                  \
122                         "pclk = %d, stereo mode = %d\n",                \
123                         dc->ndev->name,                                 \
124                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
125                         mode.h_sync_width, mode.v_sync_width,           \
126                         mode.h_back_porch, mode.v_back_porch,           \
127                         mode.h_active, mode.v_active,                   \
128                         mode.h_front_porch, mode.v_front_porch,         \
129                         mode.pclk, mode.stereo_mode);                   \
130         } while (0)
131
132 #define print_underflow_info(dc) do {                 \
133         trace_printk("%s:Underflow stats: underflows : %llu, "      \
134                         "undeflows_a : %llu, "                          \
135                         "underflows_b : %llu, "                         \
136                         "underflows_c : %llu\n",                        \
137                         dc->ndev->name,                                 \
138                         dc->stats.underflows,                           \
139                         dc->stats.underflows_a, dc->stats.underflows_b, \
140                         dc->stats.underflows_c);                        \
141         } while (0)
142
143 static void _dump_regs(struct tegra_dc *dc, void *data,
144                        void (* print)(void *data, const char *str))
145 {
146         int i;
147         char buff[256];
148
149         tegra_dc_io_start(dc);
150         tegra_dc_clk_enable(dc);
151
152         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
153         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
154         DUMP_REG(DC_CMD_SIGNAL_RAISE);
155         DUMP_REG(DC_CMD_INT_STATUS);
156         DUMP_REG(DC_CMD_INT_MASK);
157         DUMP_REG(DC_CMD_INT_ENABLE);
158         DUMP_REG(DC_CMD_INT_TYPE);
159         DUMP_REG(DC_CMD_INT_POLARITY);
160         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
161         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
162         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
163         DUMP_REG(DC_CMD_STATE_ACCESS);
164         DUMP_REG(DC_CMD_STATE_CONTROL);
165         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
166         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
167
168         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
169         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
170         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
171         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
172         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
173         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
174         DUMP_REG(DC_DISP_REF_TO_SYNC);
175         DUMP_REG(DC_DISP_SYNC_WIDTH);
176         DUMP_REG(DC_DISP_BACK_PORCH);
177         DUMP_REG(DC_DISP_DISP_ACTIVE);
178         DUMP_REG(DC_DISP_FRONT_PORCH);
179         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
180         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
181         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
182         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
183         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
184         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
185         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
186         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
187         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
188         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
189         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
190         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
191         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
192         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
193         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
194         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
195         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
196         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
197         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
198         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
199         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
200         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
201         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
202         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
203         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
204         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
205         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
206         DUMP_REG(DC_DISP_M0_CONTROL);
207         DUMP_REG(DC_DISP_M1_CONTROL);
208         DUMP_REG(DC_DISP_DI_CONTROL);
209         DUMP_REG(DC_DISP_PP_CONTROL);
210         DUMP_REG(DC_DISP_PP_SELECT_A);
211         DUMP_REG(DC_DISP_PP_SELECT_B);
212         DUMP_REG(DC_DISP_PP_SELECT_C);
213         DUMP_REG(DC_DISP_PP_SELECT_D);
214         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
215         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
216         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
217         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
218         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
219         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
220         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
221         DUMP_REG(DC_DISP_BORDER_COLOR);
222         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
223         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
224         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
225         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
226         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
227         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
228         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
229         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
230         DUMP_REG(DC_DISP_CURSOR_POSITION);
231         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
232         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
233         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
234         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
235         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
236         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
237         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
238         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
239         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
240         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
241         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
242         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
243         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
244
245
246         for (i = 0; i < 3; i++) {
247                 print(data, "\n");
248                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
249                 print(data, buff);
250
251                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
252                                 DC_CMD_DISPLAY_WINDOW_HEADER);
253                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
254                 DUMP_REG(DC_WIN_WIN_OPTIONS);
255                 DUMP_REG(DC_WIN_BYTE_SWAP);
256                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
257                 DUMP_REG(DC_WIN_COLOR_DEPTH);
258                 DUMP_REG(DC_WIN_POSITION);
259                 DUMP_REG(DC_WIN_SIZE);
260                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
261                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
262                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
263                 DUMP_REG(DC_WIN_DDA_INCREMENT);
264                 DUMP_REG(DC_WIN_LINE_STRIDE);
265                 DUMP_REG(DC_WIN_BUF_STRIDE);
266                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
267                 DUMP_REG(DC_WIN_BLEND_NOKEY);
268                 DUMP_REG(DC_WIN_BLEND_1WIN);
269                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
270                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
271                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
272                 DUMP_REG(DC_WINBUF_START_ADDR);
273                 DUMP_REG(DC_WINBUF_START_ADDR_U);
274                 DUMP_REG(DC_WINBUF_START_ADDR_V);
275                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
276                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
277                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
278                 DUMP_REG(DC_WIN_CSC_YOF);
279                 DUMP_REG(DC_WIN_CSC_KYRGB);
280                 DUMP_REG(DC_WIN_CSC_KUR);
281                 DUMP_REG(DC_WIN_CSC_KVR);
282                 DUMP_REG(DC_WIN_CSC_KUG);
283                 DUMP_REG(DC_WIN_CSC_KVG);
284                 DUMP_REG(DC_WIN_CSC_KUB);
285                 DUMP_REG(DC_WIN_CSC_KVB);
286         }
287
288         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
289         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
290         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
291         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
292         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
293         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
294         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
295         DUMP_REG(DC_DISP_M1_CONTROL);
296         DUMP_REG(DC_COM_PM1_CONTROL);
297         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
298         DUMP_REG(DC_DISP_SD_CONTROL);
299
300         tegra_dc_clk_disable(dc->clk);
301         tegra_dc_io_end(dc);
302 }
303
304 #undef DUMP_REG
305
306 #ifdef DEBUG
307 static void dump_regs_print(void *data, const char *str)
308 {
309         struct tegra_dc *dc = data;
310         dev_dbg(&dc->ndev->dev, "%s", str);
311 }
312
313 static void dump_regs(struct tegra_dc *dc)
314 {
315         _dump_regs(dc, dc, dump_regs_print);
316 }
317 #else /* !DEBUG */
318
319 static void dump_regs(struct tegra_dc *dc) {}
320
321 #endif /* DEBUG */
322
323 #ifdef CONFIG_DEBUG_FS
324
325 static void dbg_regs_print(void *data, const char *str)
326 {
327         struct seq_file *s = data;
328
329         seq_printf(s, "%s", str);
330 }
331
332 #undef DUMP_REG
333
334 static int dbg_dc_show(struct seq_file *s, void *unused)
335 {
336         struct tegra_dc *dc = s->private;
337
338         _dump_regs(dc, s, dbg_regs_print);
339
340         return 0;
341 }
342
343
344 static int dbg_dc_open(struct inode *inode, struct file *file)
345 {
346         return single_open(file, dbg_dc_show, inode->i_private);
347 }
348
349 static const struct file_operations regs_fops = {
350         .open           = dbg_dc_open,
351         .read           = seq_read,
352         .llseek         = seq_lseek,
353         .release        = single_release,
354 };
355
356 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
357 {
358         struct tegra_dc *dc = s->private;
359         struct tegra_dc_mode *m;
360
361         mutex_lock(&dc->lock);
362         m = &dc->mode;
363         seq_printf(s,
364                 "pclk: %d\n"
365                 "h_ref_to_sync: %d\n"
366                 "v_ref_to_sync: %d\n"
367                 "h_sync_width: %d\n"
368                 "v_sync_width: %d\n"
369                 "h_back_porch: %d\n"
370                 "v_back_porch: %d\n"
371                 "h_active: %d\n"
372                 "v_active: %d\n"
373                 "h_front_porch: %d\n"
374                 "v_front_porch: %d\n"
375                 "stereo_mode: %d\n",
376                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
377                 m->h_sync_width, m->v_sync_width,
378                 m->h_back_porch, m->v_back_porch,
379                 m->h_active, m->v_active,
380                 m->h_front_porch, m->v_front_porch,
381                 m->stereo_mode);
382         mutex_unlock(&dc->lock);
383         return 0;
384 }
385
386 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
387 {
388         return single_open(file, dbg_dc_mode_show, inode->i_private);
389 }
390
391 static const struct file_operations mode_fops = {
392         .open           = dbg_dc_mode_open,
393         .read           = seq_read,
394         .llseek         = seq_lseek,
395         .release        = single_release,
396 };
397
398 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
399 {
400         struct tegra_dc *dc = s->private;
401
402         mutex_lock(&dc->lock);
403         seq_printf(s,
404                 "underflows: %llu\n"
405                 "underflows_a: %llu\n"
406                 "underflows_b: %llu\n"
407                 "underflows_c: %llu\n",
408                 dc->stats.underflows,
409                 dc->stats.underflows_a,
410                 dc->stats.underflows_b,
411                 dc->stats.underflows_c);
412         mutex_unlock(&dc->lock);
413
414         return 0;
415 }
416
417 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
418 {
419         return single_open(file, dbg_dc_stats_show, inode->i_private);
420 }
421
422 static const struct file_operations stats_fops = {
423         .open           = dbg_dc_stats_open,
424         .read           = seq_read,
425         .llseek         = seq_lseek,
426         .release        = single_release,
427 };
428
429 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
430 {
431         if (dc->debugdir)
432                 debugfs_remove_recursive(dc->debugdir);
433         dc->debugdir = NULL;
434 }
435
436 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
437 {
438         struct dentry *retval;
439
440         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
441         if (!dc->debugdir)
442                 goto remove_out;
443
444         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
445                 &regs_fops);
446         if (!retval)
447                 goto remove_out;
448
449         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
450                 &mode_fops);
451         if (!retval)
452                 goto remove_out;
453
454         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
455                 &stats_fops);
456         if (!retval)
457                 goto remove_out;
458
459         return;
460 remove_out:
461         dev_err(&dc->ndev->dev, "could not create debugfs\n");
462         tegra_dc_remove_debugfs(dc);
463 }
464
465 #else /* !CONFIG_DEBUGFS */
466 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
467 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
468 #endif /* CONFIG_DEBUGFS */
469
470 static int tegra_dc_set(struct tegra_dc *dc, int index)
471 {
472         int ret = 0;
473
474         mutex_lock(&tegra_dc_lock);
475         if (index >= TEGRA_MAX_DC) {
476                 ret = -EINVAL;
477                 goto out;
478         }
479
480         if (dc != NULL && tegra_dcs[index] != NULL) {
481                 ret = -EBUSY;
482                 goto out;
483         }
484
485         tegra_dcs[index] = dc;
486
487 out:
488         mutex_unlock(&tegra_dc_lock);
489
490         return ret;
491 }
492
493 unsigned int tegra_dc_has_multiple_dc(void)
494 {
495         unsigned int idx;
496         unsigned int cnt = 0;
497         struct tegra_dc *dc;
498
499         mutex_lock(&tegra_dc_lock);
500         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
501                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
502         mutex_unlock(&tegra_dc_lock);
503
504         return (cnt > 1);
505 }
506
507 /* get the stride size of a window.
508  * return: stride size in bytes for window win. or 0 if unavailble. */
509 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
510 {
511         u32 stride;
512
513         if (!dc->enabled)
514                 return 0;
515         BUG_ON(win > DC_N_WINDOWS);
516         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
517                 DC_CMD_DISPLAY_WINDOW_HEADER);
518         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
519         return GET_LINE_STRIDE(stride);
520 }
521 EXPORT_SYMBOL(tegra_dc_get_stride);
522
523 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
524 {
525         if (idx < TEGRA_MAX_DC)
526                 return tegra_dcs[idx];
527         else
528                 return NULL;
529 }
530 EXPORT_SYMBOL(tegra_dc_get_dc);
531
532 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
533 {
534         if (win >= dc->n_windows)
535                 return NULL;
536
537         return &dc->windows[win];
538 }
539 EXPORT_SYMBOL(tegra_dc_get_window);
540
541 static int get_topmost_window(u32 *depths, unsigned long *wins)
542 {
543         int idx, best = -1;
544
545         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
546                 if (best == -1 || depths[idx] < depths[best])
547                         best = idx;
548         }
549         clear_bit(best, wins);
550         return best;
551 }
552
553 bool tegra_dc_get_connected(struct tegra_dc *dc)
554 {
555         return dc->connected;
556 }
557 EXPORT_SYMBOL(tegra_dc_get_connected);
558
559 bool tegra_dc_hpd(struct tegra_dc *dc)
560 {
561         int sense;
562         int level;
563
564         level = gpio_get_value(dc->out->hotplug_gpio);
565
566         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
567
568         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
569                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
570 }
571 EXPORT_SYMBOL(tegra_dc_hpd);
572
573 static u32 blend_topwin(u32 flags)
574 {
575         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
576                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
577         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
578                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
579         else
580                 return BLEND(NOKEY, FIX, 0xff, 0xff);
581 }
582
583 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
584 {
585         int other;
586
587         for (other = 0; other < DC_N_WINDOWS; other++) {
588                 if (other != idx && (xy-- == 0))
589                         break;
590         }
591         if (BIT(other) & behind_mask)
592                 return blend_topwin(flags[idx]);
593         else if (flags[other])
594                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
595         else
596                 return BLEND(NOKEY, FIX, 0x00, 0x00);
597 }
598
599 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
600 {
601         unsigned long infront_mask;
602         int first;
603
604         infront_mask = ~(behind_mask | BIT(idx));
605         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
606         first = ffs(infront_mask) - 1;
607
608         if (!infront_mask)
609                 return blend_topwin(flags[idx]);
610         else if (behind_mask && first != -1 && flags[first])
611                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
612         else
613                 return BLEND(NOKEY, FIX, 0x0, 0x0);
614 }
615
616 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
617 {
618         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
619
620         while (mask) {
621                 int idx = get_topmost_window(blend->z, &mask);
622
623                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
624                                 DC_CMD_DISPLAY_WINDOW_HEADER);
625                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
626                                 DC_WIN_BLEND_NOKEY);
627                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
628                                 DC_WIN_BLEND_1WIN);
629                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
630                                 DC_WIN_BLEND_2WIN_X);
631                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
632                                 DC_WIN_BLEND_2WIN_Y);
633                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
634                                 DC_WIN_BLEND_3WIN_XY);
635         }
636 }
637
638 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
639 {
640         csc->yof   = 0x00f0;
641         csc->kyrgb = 0x012a;
642         csc->kur   = 0x0000;
643         csc->kvr   = 0x0198;
644         csc->kug   = 0x039b;
645         csc->kvg   = 0x032f;
646         csc->kub   = 0x0204;
647         csc->kvb   = 0x0000;
648 }
649
650 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
651 {
652         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
653         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
654         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
655         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
656         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
657         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
658         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
659         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
660 }
661
662 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
663 {
664         mutex_lock(&dc->lock);
665
666         if (!dc->enabled) {
667                 mutex_unlock(&dc->lock);
668                 return -EFAULT;
669         }
670
671         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
672                         DC_CMD_DISPLAY_WINDOW_HEADER);
673
674         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
675
676         mutex_unlock(&dc->lock);
677
678         return 0;
679 }
680 EXPORT_SYMBOL(tegra_dc_update_csc);
681
682 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
683 {
684         int i;
685         for (i = 0; i < 256; i++)
686                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
687 }
688
689 static int tegra_dc_loop_lut(struct tegra_dc *dc,
690                              struct tegra_dc_win *win,
691                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
692 {
693         struct tegra_dc_lut *lut = &win->lut;
694         struct tegra_dc_lut *global_lut = &dc->fb_lut;
695         int i;
696         for (i = 0; i < 256; i++) {
697
698                 u32 r = (u32)lut->r[i];
699                 u32 g = (u32)lut->g[i];
700                 u32 b = (u32)lut->b[i];
701
702                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
703                         r = (u32)global_lut->r[r];
704                         g = (u32)global_lut->g[g];
705                         b = (u32)global_lut->b[b];
706                 }
707
708                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
709                         return 0;
710         }
711         return 1;
712 }
713
714 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
715 {
716         if (rgb != (i | (i<<8) | (i<<16)))
717                 return 0;
718         return 1;
719 }
720
721 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
722 {
723         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
724         return 1;
725 }
726
727 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
728 {
729         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
730
731         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
732
733         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
734                 val |= CP_ENABLE;
735         else
736                 val &= ~CP_ENABLE;
737
738         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
739 }
740
741 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
742 {
743         struct tegra_dc_win *win = &dc->windows[win_idx];
744
745         mutex_lock(&dc->lock);
746
747         if (!dc->enabled) {
748                 mutex_unlock(&dc->lock);
749                 return -EFAULT;
750         }
751
752         if (fbovr > 0)
753                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
754         else if (fbovr == 0)
755                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
756
757         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
758                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
759         else
760                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
761
762         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
763                         DC_CMD_DISPLAY_WINDOW_HEADER);
764
765         tegra_dc_set_lut(dc, win);
766
767         mutex_unlock(&dc->lock);
768
769         tegra_dc_update_windows(&win, 1);
770
771         return 0;
772 }
773
774 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
775 {
776         if (win_idx > -1)
777                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
778
779         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
780                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
781                 if (err)
782                         return err;
783         }
784
785         return 0;
786 }
787 EXPORT_SYMBOL(tegra_dc_update_lut);
788
789 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
790 {
791         unsigned i;
792         unsigned v0 = 128;
793         unsigned v1 = 0;
794         /* linear horizontal and vertical filters */
795         for (i = 0; i < 16; i++) {
796                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
797                                 DC_WIN_H_FILTER_P(i));
798
799                 tegra_dc_writel(dc, v0,
800                                 DC_WIN_V_FILTER_P(i));
801                 v0 -= 8;
802                 v1 += 8;
803         }
804 }
805
806 void tegra_dc_host_suspend(struct tegra_dc *dc)
807 {
808         tegra_dsi_host_suspend(dc);
809         tegra_dc_clk_disable(dc);
810 }
811
812 void tegra_dc_host_resume(struct tegra_dc *dc) {
813         tegra_dc_clk_enable(dc);
814         tegra_dsi_host_resume(dc);
815 }
816
817 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
818                                   bool v, unsigned Bpp)
819 {
820         /*
821          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
822          *           (post_scaled_size_in_pixels - 1)), MAX)
823          * Where the value of MAX is as follows:
824          * For V_DDA_INCREMENT: 15.0 (0xF000)
825          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
826          *                       8.0 (0x8000) for 2 Bytes/pix formats.
827          */
828
829         fixed20_12 out = dfixed_init(out_int);
830         u32 dda_inc;
831         int max;
832
833         if (v) {
834                 max = 15;
835         } else {
836                 switch (Bpp) {
837                 default:
838                         WARN_ON_ONCE(1);
839                         /* fallthrough */
840                 case 4:
841                         max = 4;
842                         break;
843                 case 2:
844                         max = 8;
845                         break;
846                 }
847         }
848
849         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
850         in.full -= dfixed_const(1);
851
852         dda_inc = dfixed_div(in, out);
853
854         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
855
856         return dda_inc;
857 }
858
859 static inline u32 compute_initial_dda(fixed20_12 in)
860 {
861         return dfixed_frac(in);
862 }
863
864 /* does not support updating windows on multiple dcs in one call */
865 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
866 {
867         struct tegra_dc *dc;
868         unsigned long update_mask = GENERAL_ACT_REQ;
869         unsigned long val;
870         bool update_blend = false;
871         int i;
872
873         dc = windows[0]->dc;
874
875         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
876                 /* Acquire one_shot_lock to avoid race condition between
877                  * cancellation of old delayed work and schedule of new
878                  * delayed work. */
879                 mutex_lock(&dc->one_shot_lock);
880                 cancel_delayed_work_sync(&dc->one_shot_work);
881         }
882         mutex_lock(&dc->lock);
883
884         if (!dc->enabled) {
885                 mutex_unlock(&dc->lock);
886                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
887                         mutex_unlock(&dc->one_shot_lock);
888                 return -EFAULT;
889         }
890
891         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
892                 tegra_dc_host_resume(dc);
893
894         if (no_vsync)
895                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
896         else
897                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
898
899         for (i = 0; i < n; i++) {
900                 struct tegra_dc_win *win = windows[i];
901                 unsigned h_dda;
902                 unsigned v_dda;
903                 fixed20_12 h_offset, v_offset;
904                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
905                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
906                 bool yuv = tegra_dc_is_yuv(win->fmt);
907                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
908                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
909                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
910                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
911                 const bool filter_h = win_use_h_filter(dc, win);
912                 const bool filter_v = win_use_v_filter(dc, win);
913
914                 if (win->z != dc->blend.z[win->idx]) {
915                         dc->blend.z[win->idx] = win->z;
916                         update_blend = true;
917                 }
918                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
919                         dc->blend.flags[win->idx]) {
920                         dc->blend.flags[win->idx] =
921                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
922                         update_blend = true;
923                 }
924
925                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
926                                 DC_CMD_DISPLAY_WINDOW_HEADER);
927
928                 if (!no_vsync)
929                         update_mask |= WIN_A_ACT_REQ << win->idx;
930
931                 if (!WIN_IS_ENABLED(win)) {
932                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
933                         continue;
934                 }
935
936                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
937                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
938
939                 tegra_dc_writel(dc,
940                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
941                                 DC_WIN_POSITION);
942                 tegra_dc_writel(dc,
943                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
944                                 DC_WIN_SIZE);
945
946                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
947                         tegra_dc_writel(dc,
948                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
949                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
950                                         DC_WIN_PRESCALED_SIZE);
951
952                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
953                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
954                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
955                                         DC_WIN_DDA_INCREMENT);
956                         h_dda = compute_initial_dda(win->x);
957                         v_dda = compute_initial_dda(win->y);
958                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
959                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
960                 }
961
962                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
963                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
964                 tegra_dc_writel(dc,
965                                 (unsigned long)win->phys_addr,
966                                 DC_WINBUF_START_ADDR);
967
968                 if (!yuvp) {
969                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
970                 } else {
971                         tegra_dc_writel(dc,
972                                         (unsigned long)win->phys_addr_u,
973                                         DC_WINBUF_START_ADDR_U);
974                         tegra_dc_writel(dc,
975                                         (unsigned long)win->phys_addr_v,
976                                         DC_WINBUF_START_ADDR_V);
977                         tegra_dc_writel(dc,
978                                         LINE_STRIDE(win->stride) |
979                                         UV_LINE_STRIDE(win->stride_uv),
980                                         DC_WIN_LINE_STRIDE);
981                 }
982
983                 h_offset = win->x;
984                 if (invert_h) {
985                         h_offset.full += win->w.full - dfixed_const(1);
986                 }
987
988                 v_offset = win->y;
989                 if (invert_v) {
990                         v_offset.full += win->h.full - dfixed_const(1);
991                 }
992
993                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
994                                 DC_WINBUF_ADDR_H_OFFSET);
995                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
996                                 DC_WINBUF_ADDR_V_OFFSET);
997
998                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
999                         if (WIN_IS_TILED(win))
1000                                 tegra_dc_writel(dc,
1001                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1002                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1003                                                 DC_WIN_BUFFER_ADDR_MODE);
1004                         else
1005                                 tegra_dc_writel(dc,
1006                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1007                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1008                                                 DC_WIN_BUFFER_ADDR_MODE);
1009                 }
1010
1011                 val = WIN_ENABLE;
1012                 if (yuv)
1013                         val |= CSC_ENABLE;
1014                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1015                         val |= COLOR_EXPAND;
1016
1017                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1018                         val |= CP_ENABLE;
1019
1020                 if (filter_h)
1021                         val |= H_FILTER_ENABLE;
1022                 if (filter_v)
1023                         val |= V_FILTER_ENABLE;
1024
1025                 if (invert_h)
1026                         val |= H_DIRECTION_DECREMENT;
1027                 if (invert_v)
1028                         val |= V_DIRECTION_DECREMENT;
1029
1030                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1031
1032 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1033                 if (win->global_alpha == 255)
1034                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1035                 else
1036                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1037                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1038 #endif
1039
1040                 win->dirty = no_vsync ? 0 : 1;
1041
1042                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1043                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1044                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1045                         __func__, win->idx, win->z,
1046                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1047                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1048                         win->out_x, win->out_y, win->out_w, win->out_h,
1049                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1050                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1051                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1052                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1053         }
1054
1055         if (update_blend) {
1056                 tegra_dc_set_blending(dc, &dc->blend);
1057                 for (i = 0; i < DC_N_WINDOWS; i++) {
1058                         if (!no_vsync)
1059                                 dc->windows[i].dirty = 1;
1060                         update_mask |= WIN_A_ACT_REQ << i;
1061                 }
1062         }
1063
1064         tegra_dc_set_dynamic_emc(windows, n);
1065
1066         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1067
1068         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1069         if (!no_vsync) {
1070                 set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1071                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1072         } else {
1073                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1074                 tegra_dc_mask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1075         }
1076
1077         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1078                 schedule_delayed_work(&dc->one_shot_work,
1079                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1080
1081         /* update EMC clock if calculated bandwidth has changed */
1082         tegra_dc_program_bandwidth(dc);
1083
1084         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1085                 update_mask |= NC_HOST_TRIG;
1086
1087         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1088         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1089
1090         mutex_unlock(&dc->lock);
1091         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1092                 mutex_unlock(&dc->one_shot_lock);
1093
1094         return 0;
1095 }
1096 EXPORT_SYMBOL(tegra_dc_update_windows);
1097
1098 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1099 {
1100         return dc->syncpt[i].id;
1101 }
1102 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1103
1104 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1105 {
1106         u32 max;
1107
1108         mutex_lock(&dc->lock);
1109         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1110                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1111         dc->syncpt[i].max = max;
1112         mutex_unlock(&dc->lock);
1113
1114         return max;
1115 }
1116
1117 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1118 {
1119         mutex_lock(&dc->lock);
1120         if ( dc->enabled )
1121                 while (dc->syncpt[i].min < val) {
1122                         dc->syncpt[i].min++;
1123                         nvhost_syncpt_cpu_incr(
1124                                         &nvhost_get_host(dc->ndev)->syncpt,
1125                                         dc->syncpt[i].id);
1126                 }
1127         mutex_unlock(&dc->lock);
1128 }
1129
1130 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1131                                              int n)
1132 {
1133         int i;
1134
1135         for (i = 0; i < n; i++) {
1136                 if (windows[i]->dirty)
1137                         return false;
1138         }
1139
1140         return true;
1141 }
1142
1143 /* does not support syncing windows on multiple dcs in one call */
1144 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1145 {
1146         int ret;
1147         if (n < 1 || n > DC_N_WINDOWS)
1148                 return -EINVAL;
1149
1150         if (!windows[0]->dc->enabled)
1151                 return -EFAULT;
1152
1153 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1154         /* Don't want to timeout on simulator */
1155         ret = wait_event_interruptible(windows[0]->dc->wq,
1156                 tegra_dc_windows_are_clean(windows, n));
1157 #else
1158         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1159                         windows[0]->dc->ndev->name);
1160         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1161                                          tegra_dc_windows_are_clean(windows, n),
1162                                          HZ);
1163         trace_printk("%s:After wait_event_interruptible_timeout\n",
1164                         windows[0]->dc->ndev->name);
1165 #endif
1166         return ret;
1167 }
1168 EXPORT_SYMBOL(tegra_dc_sync_windows);
1169
1170 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1171 {
1172 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1173         return clk_get_rate(dc->clk);
1174 #else
1175         return 27000000;
1176 #endif
1177 }
1178
1179 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1180 {
1181         unsigned long rate;
1182         unsigned long div;
1183
1184         rate = tegra_dc_clk_get_rate(dc);
1185
1186         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1187
1188         if (div < 2)
1189                 return 0;
1190
1191         return rate * 2 / div;
1192 }
1193
1194 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1195 {
1196         unsigned long rate;
1197         unsigned long div;
1198
1199         rate = clk_get_rate(parent);
1200
1201         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1202
1203         if (div < 2)
1204                 return 0;
1205
1206         return rate * 2 / div;
1207 }
1208
1209 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1210 {
1211         int pclk;
1212
1213         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1214                 unsigned long rate;
1215                 struct clk *parent_clk =
1216                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1217
1218                 if (dc->out->parent_clk_backup &&
1219                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1220                         rate = tegra_dc_pclk_predict_rate(
1221                                 parent_clk, dc->mode.pclk);
1222                         /* use pll_d as last resort */
1223                         if (rate < (dc->mode.pclk / 100 * 99) ||
1224                             rate > (dc->mode.pclk / 100 * 109))
1225                                 parent_clk = clk_get_sys(
1226                                         NULL, dc->out->parent_clk_backup);
1227                 }
1228
1229                 if (clk_get_parent(clk) != parent_clk)
1230                         clk_set_parent(clk, parent_clk);
1231
1232                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1233                         struct clk *base_clk = clk_get_parent(parent_clk);
1234
1235                         /* Assuming either pll_d or pll_d2 is used */
1236                         rate = dc->mode.pclk * 2;
1237
1238                         if (rate != clk_get_rate(base_clk))
1239                                 clk_set_rate(base_clk, rate);
1240                 }
1241         }
1242
1243         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1244                 unsigned long rate;
1245                 struct clk *parent_clk =
1246                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1247                 struct clk *base_clk = clk_get_parent(parent_clk);
1248
1249                 /*
1250                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1251                  * The required rate needs to be setup at 4x multiplier,
1252                  * as out0 is 1/2 of the actual PLL output.
1253                  */
1254
1255                 rate = dc->mode.pclk * 4;
1256                 if (rate != clk_get_rate(base_clk))
1257                         clk_set_rate(base_clk, rate);
1258
1259                 if (clk_get_parent(clk) != parent_clk)
1260                         clk_set_parent(clk, parent_clk);
1261         }
1262
1263         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1264                 unsigned long rate;
1265                 struct clk *parent_clk;
1266                 struct clk *base_clk;
1267
1268                 if (clk == dc->clk) {
1269                         parent_clk = clk_get_sys(NULL,
1270                                         dc->out->parent_clk ? : "pll_d_out0");
1271                         base_clk = clk_get_parent(parent_clk);
1272                         tegra_clk_cfg_ex(base_clk,
1273                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1274                 } else {
1275                         if (dc->pdata->default_out->dsi->dsi_instance) {
1276                                 parent_clk = clk_get_sys(NULL,
1277                                         dc->out->parent_clk ? : "pll_d2_out0");
1278                                 base_clk = clk_get_parent(parent_clk);
1279                                 tegra_clk_cfg_ex(base_clk,
1280                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1281                         } else {
1282                                 parent_clk = clk_get_sys(NULL,
1283                                         dc->out->parent_clk ? : "pll_d_out0");
1284                                 base_clk = clk_get_parent(parent_clk);
1285                                 tegra_clk_cfg_ex(base_clk,
1286                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1287                         }
1288                 }
1289
1290                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1291                 if (rate != clk_get_rate(base_clk))
1292                         clk_set_rate(base_clk, rate);
1293
1294                 if (clk_get_parent(clk) != parent_clk)
1295                         clk_set_parent(clk, parent_clk);
1296         }
1297
1298         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1299         tegra_dvfs_set_rate(clk, pclk);
1300 }
1301
1302 /* return non-zero if constraint is violated */
1303 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1304 {
1305         long a, b;
1306
1307         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1308         a = 0;
1309
1310         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1311         b = mode->h_front_porch - 1;
1312
1313         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1314         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1315                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1316         /* check Constraint 1 and 6 */
1317         if (a > b)
1318                 return 1;
1319
1320         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1321         if (mode->h_sync_width < 1)
1322                 return 4;
1323
1324         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1325         if (mode->h_active < 16)
1326                 return 7;
1327
1328         if (href) {
1329                 if (b > a && a % 2)
1330                         *href = a + 1; /* use smallest even value */
1331                 else
1332                         *href = a; /* even or only possible value */
1333         }
1334
1335         return 0;
1336 }
1337
1338 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1339 {
1340         long a;
1341         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1342
1343         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1344         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1345                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1346
1347         /* Constraint 6 */
1348         if (mode->v_front_porch < a + 1)
1349                 a = mode->v_front_porch - 1;
1350
1351         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1352         if (mode->v_sync_width < 1)
1353                 return 4;
1354
1355         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1356         if (mode->v_active < 16)
1357                 return 7;
1358
1359         if (vref)
1360                 *vref = a;
1361         return 0;
1362 }
1363
1364 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1365 {
1366         int ret;
1367         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1368         if (ret)
1369                 return ret;
1370         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1371         if (ret)
1372                 return ret;
1373
1374         return 0;
1375 }
1376
1377 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1378 {
1379         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1380         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1381                 return false;
1382
1383         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1384         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1385                 return false;
1386
1387         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1388          * (vertical blank). */
1389         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1390                 return false;
1391
1392         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1393         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1394                 return false;
1395
1396         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1397         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1398                 return false;
1399
1400         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1401          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1402         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1403                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1404                 return false;
1405
1406         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1407         if (mode->h_active < 16 || mode->v_active < 16)
1408                 return false;
1409
1410         return true;
1411 }
1412
1413 #ifdef DEBUG
1414 /* return in 1000ths of a Hertz */
1415 static int calc_refresh(const struct tegra_dc_mode *m)
1416 {
1417         long h_total, v_total, refresh;
1418         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1419                 m->h_sync_width;
1420         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1421                 m->v_sync_width;
1422         refresh = m->pclk / h_total;
1423         refresh *= 1000;
1424         refresh /= v_total;
1425         return refresh;
1426 }
1427
1428 static void print_mode(struct tegra_dc *dc,
1429                         const struct tegra_dc_mode *mode, const char *note)
1430 {
1431         if (mode) {
1432                 int refresh = calc_refresh(dc, mode);
1433                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1434                         note ? note : "",
1435                         mode->h_active, mode->v_active,
1436                         refresh / 1000, refresh % 1000,
1437                         mode->pclk);
1438         }
1439 }
1440 #else /* !DEBUG */
1441 static inline void print_mode(struct tegra_dc *dc,
1442                         const struct tegra_dc_mode *mode, const char *note) { }
1443 #endif /* DEBUG */
1444
1445 static inline void enable_dc_irq(unsigned int irq)
1446 {
1447 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1448         enable_irq(irq);
1449 #else
1450         /* Always disable DC interrupts on FPGA. */
1451         disable_irq(irq);
1452 #endif
1453 }
1454
1455 static inline void disable_dc_irq(unsigned int irq)
1456 {
1457         disable_irq(irq);
1458 }
1459
1460 static inline void tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
1461 {
1462         u32 val;
1463
1464         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1465         val |= int_val;
1466         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1467 }
1468
1469 static inline void tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
1470 {
1471         u32 val;
1472
1473         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1474         val &= ~int_val;
1475         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1476 }
1477
1478 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1479 {
1480         unsigned long val;
1481         unsigned long rate;
1482         unsigned long div;
1483         unsigned long pclk;
1484
1485         print_mode(dc, mode, __func__);
1486
1487         /* use default EMC rate when switching modes */
1488         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1489         tegra_dc_program_bandwidth(dc);
1490
1491         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1492         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1493                         DC_DISP_REF_TO_SYNC);
1494         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1495                         DC_DISP_SYNC_WIDTH);
1496         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1497                         DC_DISP_BACK_PORCH);
1498         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1499                         DC_DISP_DISP_ACTIVE);
1500         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1501                         DC_DISP_FRONT_PORCH);
1502
1503         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1504                         DC_DISP_DATA_ENABLE_OPTIONS);
1505
1506         /* TODO: MIPI/CRT/HDMI clock cals */
1507
1508         val = DISP_DATA_FORMAT_DF1P1C;
1509
1510         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1511                 val |= DISP_DATA_ALIGNMENT_MSB;
1512         else
1513                 val |= DISP_DATA_ALIGNMENT_LSB;
1514
1515         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1516                 val |= DISP_DATA_ORDER_RED_BLUE;
1517         else
1518                 val |= DISP_DATA_ORDER_BLUE_RED;
1519
1520         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1521
1522         rate = tegra_dc_clk_get_rate(dc);
1523
1524         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1525         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1526         if (pclk < (mode->pclk / 100 * 99) ||
1527             pclk > (mode->pclk / 100 * 109)) {
1528                 dev_err(&dc->ndev->dev,
1529                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1530                         rate, mode->pclk,
1531                         pclk, (mode->pclk / 100 * 99),
1532                         (mode->pclk / 100 * 109));
1533                 return -EINVAL;
1534         }
1535
1536         div = (rate * 2 / pclk) - 2;
1537         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1538
1539         tegra_dc_writel(dc, 0x00010001,
1540                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1541         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1542                         DC_DISP_DISP_CLOCK_CONTROL);
1543
1544 #ifdef CONFIG_SWITCH
1545         switch_set_state(&dc->modeset_switch,
1546                          (mode->h_active << 16) | mode->v_active);
1547 #endif
1548
1549         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1550         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1551
1552         print_mode_info(dc, dc->mode);
1553         return 0;
1554 }
1555
1556
1557 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1558 {
1559         memcpy(&dc->mode, mode, sizeof(dc->mode));
1560
1561         print_mode(dc, mode, __func__);
1562
1563         return 0;
1564 }
1565 EXPORT_SYMBOL(tegra_dc_set_mode);
1566
1567 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1568                 const struct fb_videomode *fbmode, bool stereo_mode)
1569 {
1570         struct tegra_dc_mode mode;
1571
1572         if (!fbmode->pixclock)
1573                 return -EINVAL;
1574
1575         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1576         mode.h_sync_width = fbmode->hsync_len;
1577         mode.v_sync_width = fbmode->vsync_len;
1578         mode.h_back_porch = fbmode->left_margin;
1579         mode.v_back_porch = fbmode->upper_margin;
1580         mode.h_active = fbmode->xres;
1581         mode.v_active = fbmode->yres;
1582         mode.h_front_porch = fbmode->right_margin;
1583         mode.v_front_porch = fbmode->lower_margin;
1584         mode.stereo_mode = stereo_mode;
1585         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1586                 /* HDMI controller requires h_ref=1, v_ref=1 */
1587                 mode.h_ref_to_sync = 1;
1588                 mode.v_ref_to_sync = 1;
1589         } else {
1590                 calc_ref_to_sync(&mode);
1591         }
1592         if (!check_ref_to_sync(&mode)) {
1593                 dev_err(&dc->ndev->dev,
1594                                 "Display timing doesn't meet restrictions.\n");
1595                 return -EINVAL;
1596         }
1597         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1598                 mode.h_active, mode.v_active, mode.pclk,
1599                 mode.h_ref_to_sync, mode.v_ref_to_sync
1600         );
1601
1602 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1603         /* Double the pixel clock and update v_active only for frame packed mode */
1604         if (mode.stereo_mode) {
1605                 mode.pclk *= 2;
1606                 /* total v_active = yres*2 + activespace */
1607                 mode.v_active = fbmode->yres*2 +
1608                                 fbmode->vsync_len +
1609                                 fbmode->upper_margin +
1610                                 fbmode->lower_margin;
1611         }
1612 #endif
1613
1614         mode.flags = 0;
1615
1616         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1617                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1618
1619         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1620                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1621
1622         return tegra_dc_set_mode(dc, &mode);
1623 }
1624 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1625
1626 void
1627 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1628 {
1629         unsigned int ctrl;
1630         unsigned long out_sel;
1631         unsigned long cmd_state;
1632
1633         mutex_lock(&dc->lock);
1634         if (!dc->enabled) {
1635                 mutex_unlock(&dc->lock);
1636                 return;
1637         }
1638
1639         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1640                 tegra_dc_host_resume(dc);
1641
1642         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1643                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1644                 cfg->clk_select);
1645
1646         /* The new value should be effected immediately */
1647         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1648         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1649
1650         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1651                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1652         else
1653                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1654
1655         switch (cfg->which_pwm) {
1656         case TEGRA_PWM_PM0:
1657                 /* Select the LM0 on PM0 */
1658                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1659                 out_sel &= ~(7 << 0);
1660                 out_sel |= (3 << 0);
1661                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1662                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1663                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1664                 break;
1665         case TEGRA_PWM_PM1:
1666                 /* Select the LM1 on PM1 */
1667                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1668                 out_sel &= ~(7 << 4);
1669                 out_sel |= (3 << 4);
1670                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1671                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1672                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1673                 break;
1674         default:
1675                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1676                 break;
1677         }
1678         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1679         mutex_unlock(&dc->lock);
1680 }
1681 EXPORT_SYMBOL(tegra_dc_config_pwm);
1682
1683 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1684                                 const struct tegra_dc_out_pin *pins,
1685                                 const unsigned int n_pins)
1686 {
1687         unsigned int i;
1688
1689         int name;
1690         int pol;
1691
1692         u32 pol1, pol3;
1693
1694         u32 set1, unset1;
1695         u32 set3, unset3;
1696
1697         set1 = set3 = unset1 = unset3 = 0;
1698
1699         for (i = 0; i < n_pins; i++) {
1700                 name = (pins + i)->name;
1701                 pol  = (pins + i)->pol;
1702
1703                 /* set polarity by name */
1704                 switch (name) {
1705                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1706                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1707                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1708                         else
1709                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1710                         break;
1711                 case TEGRA_DC_OUT_PIN_H_SYNC:
1712                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1713                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1714                         else
1715                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1716                         break;
1717                 case TEGRA_DC_OUT_PIN_V_SYNC:
1718                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1719                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1720                         else
1721                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1722                         break;
1723                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1724                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1725                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1726                         else
1727                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1728                         break;
1729                 default:
1730                         printk("Invalid argument in function %s\n",
1731                                __FUNCTION__);
1732                         break;
1733                 }
1734         }
1735
1736         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1737         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1738
1739         pol1 |= set1;
1740         pol1 &= ~unset1;
1741
1742         pol3 |= set3;
1743         pol3 &= ~unset3;
1744
1745         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1746         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1747 }
1748
1749 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1750 {
1751         dc->out = out;
1752
1753         if (out->n_modes > 0)
1754                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1755
1756         switch (out->type) {
1757         case TEGRA_DC_OUT_RGB:
1758                 dc->out_ops = &tegra_dc_rgb_ops;
1759                 break;
1760
1761         case TEGRA_DC_OUT_HDMI:
1762                 dc->out_ops = &tegra_dc_hdmi_ops;
1763                 break;
1764
1765         case TEGRA_DC_OUT_DSI:
1766                 dc->out_ops = &tegra_dc_dsi_ops;
1767                 break;
1768
1769         default:
1770                 dc->out_ops = NULL;
1771                 break;
1772         }
1773
1774         if (dc->out_ops && dc->out_ops->init)
1775                 dc->out_ops->init(dc);
1776
1777 }
1778
1779 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1780 {
1781         if (dc->out)
1782                 return dc->out->height;
1783         else
1784                 return 0;
1785 }
1786 EXPORT_SYMBOL(tegra_dc_get_out_height);
1787
1788 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1789 {
1790         if (dc->out)
1791                 return dc->out->width;
1792         else
1793                 return 0;
1794 }
1795 EXPORT_SYMBOL(tegra_dc_get_out_width);
1796
1797 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1798 {
1799         if (dc->out && dc->out->max_pixclock)
1800                 return dc->out->max_pixclock;
1801         else
1802                 return 0;
1803 }
1804 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1805
1806 void tegra_dc_enable_crc(struct tegra_dc *dc)
1807 {
1808         u32 val;
1809         tegra_dc_io_start(dc);
1810
1811         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1812                 CRC_ENABLE_ENABLE;
1813         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1814         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1815         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1816 }
1817
1818 void tegra_dc_disable_crc(struct tegra_dc *dc)
1819 {
1820         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1821         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1822         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1823
1824         tegra_dc_io_end(dc);
1825 }
1826
1827 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1828 {
1829         int crc = 0;
1830
1831         if (!dc) {
1832                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1833                 goto crc_error;
1834         }
1835
1836         /* TODO: Replace mdelay with code to sync VBlANK, since
1837          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1838         mdelay(TEGRA_CRC_LATCHED_DELAY);
1839
1840         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1841 crc_error:
1842         return crc;
1843 }
1844
1845 static void tegra_dc_vblank(struct work_struct *work)
1846 {
1847         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1848         bool nvsd_updated = false;
1849
1850         mutex_lock(&dc->lock);
1851
1852         /* use the new frame's bandwidth setting instead of max(current, new),
1853          * skip this if we're using tegra_dc_one_shot_worker() */
1854         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1855                 tegra_dc_program_bandwidth(dc);
1856
1857         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1858         if (!tegra_dc_windows_are_dirty(dc))
1859                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1860
1861         /* Update the SD brightness */
1862         if (dc->enabled && dc->out->sd_settings) {
1863                 nvsd_updated = nvsd_update_brightness(dc);
1864                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1865                  * V_BLANK_NVSD bit of vblank ref-count. */
1866                 if (nvsd_updated) {
1867                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1868                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1869                 } else {
1870                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1871                 }
1872         }
1873
1874         /* Mask vblank interrupt if ref-count is zero. */
1875         if (!dc->vblank_ref_count)
1876                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1877
1878         mutex_unlock(&dc->lock);
1879
1880         /* Do the actual brightness update outside of the mutex */
1881         if (nvsd_updated && dc->out->sd_settings &&
1882             dc->out->sd_settings->bl_device) {
1883
1884                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1885                 struct backlight_device *bl = platform_get_drvdata(pdev);
1886                 if (bl)
1887                         backlight_update_status(bl);
1888         }
1889 }
1890
1891 static void tegra_dc_one_shot_worker(struct work_struct *work)
1892 {
1893         struct tegra_dc *dc = container_of(
1894                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1895         mutex_lock(&dc->lock);
1896
1897         /* memory client has gone idle */
1898         tegra_dc_clear_bandwidth(dc);
1899
1900         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1901                 tegra_dc_host_suspend(dc);
1902
1903         mutex_unlock(&dc->lock);
1904 }
1905
1906 /* return an arbitrarily large number if count overflow occurs.
1907  * make it a nice base-10 number to show up in stats output */
1908 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1909 {
1910         unsigned count = tegra_dc_readl(dc, reg);
1911         tegra_dc_writel(dc, 0, reg);
1912         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1913 }
1914
1915 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1916 {
1917         u32 val;
1918         int i;
1919
1920         dc->stats.underflows++;
1921         if (dc->underflow_mask & WIN_A_UF_INT) {
1922                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1923                         DC_WINBUF_AD_UFLOW_STATUS);
1924                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1925         }
1926         if (dc->underflow_mask & WIN_B_UF_INT) {
1927                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1928                         DC_WINBUF_BD_UFLOW_STATUS);
1929                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1930         }
1931         if (dc->underflow_mask & WIN_C_UF_INT) {
1932                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1933                         DC_WINBUF_CD_UFLOW_STATUS);
1934                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1935         }
1936
1937         /* Check for any underflow reset conditions */
1938         for (i = 0; i < DC_N_WINDOWS; i++) {
1939                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1940                         dc->windows[i].underflows++;
1941
1942 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1943                         if (dc->windows[i].underflows > 4) {
1944                                 schedule_work(&dc->reset_work);
1945                                 /* reset counter */
1946                                 dc->windows[i].underflows = 0;
1947                                 trace_printk("%s:Reset work scheduled for "
1948                                                 "window %c\n",
1949                                                 dc->ndev->name, (65 + i));
1950                         }
1951 #endif
1952 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1953                         if (dc->windows[i].underflows > 4) {
1954                                 printk("%s:dc in underflow state."
1955                                         " enable UF_LINE_FLUSH to clear up\n",
1956                                         __func__);
1957                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1958                                                 DC_DISP_DISP_MISC_CONTROL);
1959                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1960                                                 DC_CMD_STATE_CONTROL);
1961                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1962                                                 DC_CMD_STATE_CONTROL);
1963
1964                                 tegra_dc_writel(dc, 0,
1965                                                 DC_DISP_DISP_MISC_CONTROL);
1966                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1967                                                 DC_CMD_STATE_CONTROL);
1968                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1969                                                 DC_CMD_STATE_CONTROL);
1970                         }
1971 #endif
1972                 } else {
1973                         dc->windows[i].underflows = 0;
1974                 }
1975         }
1976
1977         /* Clear the underflow mask now that we've checked it. */
1978         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1979         dc->underflow_mask = 0;
1980         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1981         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1982         print_underflow_info(dc);
1983 }
1984
1985 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1986 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1987 {
1988 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1989         u32 val;
1990
1991         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1992         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
1993             return true;
1994 #endif
1995         return false;
1996 }
1997
1998 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
1999 {
2000         u32 val, i;
2001         u32 completed = 0;
2002         u32 dirty = 0;
2003
2004         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2005         for (i = 0; i < DC_N_WINDOWS; i++) {
2006 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2007                 /* FIXME: this is not needed when the simulator
2008                    clears WIN_x_UPDATE bits as in HW */
2009                 dc->windows[i].dirty = 0;
2010                 completed = 1;
2011 #else
2012                 if (!(val & (WIN_A_UPDATE << i))) {
2013                         dc->windows[i].dirty = 0;
2014                         completed = 1;
2015                 } else {
2016                         dirty = 1;
2017                 }
2018 #endif
2019         }
2020
2021         if (!dirty) {
2022                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2023                         tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2024         }
2025
2026         if (completed)
2027                 wake_up(&dc->wq);
2028 }
2029
2030 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2031 {
2032         if (status & V_BLANK_INT) {
2033                 /* Sync up windows. */
2034                 tegra_dc_trigger_windows(dc);
2035
2036                 /* Schedule any additional bottom-half vblank actvities. */
2037                 schedule_work(&dc->vblank_work);
2038         }
2039
2040         if (status & FRAME_END_INT) {
2041                 /* Mark the frame_end as complete. */
2042                 if (!completion_done(&dc->frame_end_complete))
2043                         complete(&dc->frame_end_complete);
2044         }
2045 }
2046
2047 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2048 {
2049         /* Schedule any additional bottom-half vblank actvities. */
2050         if (status & V_BLANK_INT)
2051                 schedule_work(&dc->vblank_work);
2052
2053         if (status & FRAME_END_INT) {
2054                 /* Mark the frame_end as complete. */
2055                 if (!completion_done(&dc->frame_end_complete))
2056                         complete(&dc->frame_end_complete);
2057
2058                 tegra_dc_trigger_windows(dc);
2059         }
2060 }
2061 #endif
2062
2063 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2064 {
2065 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2066         struct tegra_dc *dc = ptr;
2067         unsigned long status;
2068         unsigned long underflow_mask;
2069         u32 val;
2070
2071         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2072                 WARN(1, "IRQ when DC not powered!\n");
2073                 tegra_dc_io_start(dc);
2074                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2075                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2076                 tegra_dc_io_end(dc);
2077                 return IRQ_HANDLED;
2078         }
2079
2080         /* clear all status flags except underflow, save those for the worker */
2081         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2082         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2083         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2084         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2085
2086         /*
2087          * Overlays can get thier internal state corrupted during and underflow
2088          * condition.  The only way to fix this state is to reset the DC.
2089          * if we get 4 consecutive frames with underflows, assume we're
2090          * hosed and reset.
2091          */
2092         underflow_mask = status & ALL_UF_INT;
2093
2094         /* Check underflow */
2095         if (underflow_mask) {
2096                 dc->underflow_mask |= underflow_mask;
2097                 schedule_delayed_work(&dc->underflow_work,
2098                         msecs_to_jiffies(1));
2099         }
2100
2101         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2102                 tegra_dc_one_shot_irq(dc, status);
2103         else
2104                 tegra_dc_continuous_irq(dc, status);
2105
2106         return IRQ_HANDLED;
2107 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2108         return IRQ_NONE;
2109 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2110 }
2111
2112 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2113 {
2114         u32 color_control;
2115
2116         switch (dc->out->depth) {
2117         case 3:
2118                 color_control = BASE_COLOR_SIZE111;
2119                 break;
2120
2121         case 6:
2122                 color_control = BASE_COLOR_SIZE222;
2123                 break;
2124
2125         case 8:
2126                 color_control = BASE_COLOR_SIZE332;
2127                 break;
2128
2129         case 9:
2130                 color_control = BASE_COLOR_SIZE333;
2131                 break;
2132
2133         case 12:
2134                 color_control = BASE_COLOR_SIZE444;
2135                 break;
2136
2137         case 15:
2138                 color_control = BASE_COLOR_SIZE555;
2139                 break;
2140
2141         case 16:
2142                 color_control = BASE_COLOR_SIZE565;
2143                 break;
2144
2145         case 18:
2146                 color_control = BASE_COLOR_SIZE666;
2147                 break;
2148
2149         default:
2150                 color_control = BASE_COLOR_SIZE888;
2151                 break;
2152         }
2153
2154         switch (dc->out->dither) {
2155         case TEGRA_DC_DISABLE_DITHER:
2156                 color_control |= DITHER_CONTROL_DISABLE;
2157                 break;
2158         case TEGRA_DC_ORDERED_DITHER:
2159                 color_control |= DITHER_CONTROL_ORDERED;
2160                 break;
2161         case TEGRA_DC_ERRDIFF_DITHER:
2162                 /* The line buffer for error-diffusion dither is limited
2163                  * to 1280 pixels per line. This limits the maximum
2164                  * horizontal active area size to 1280 pixels when error
2165                  * diffusion is enabled.
2166                  */
2167                 BUG_ON(dc->mode.h_active > 1280);
2168                 color_control |= DITHER_CONTROL_ERRDIFF;
2169                 break;
2170         }
2171
2172         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2173 }
2174
2175 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2176 {
2177         u32 syncpt_id;
2178
2179         switch (dc->ndev->id) {
2180         case 0:
2181                 switch (idx) {
2182                 case 0:
2183                         syncpt_id = NVSYNCPT_DISP0_A;
2184                         break;
2185                 case 1:
2186                         syncpt_id = NVSYNCPT_DISP0_B;
2187                         break;
2188                 case 2:
2189                         syncpt_id = NVSYNCPT_DISP0_C;
2190                         break;
2191                 default:
2192                         BUG();
2193                         break;
2194                 }
2195                 break;
2196         case 1:
2197                 switch (idx) {
2198                 case 0:
2199                         syncpt_id = NVSYNCPT_DISP1_A;
2200                         break;
2201                 case 1:
2202                         syncpt_id = NVSYNCPT_DISP1_B;
2203                         break;
2204                 case 2:
2205                         syncpt_id = NVSYNCPT_DISP1_C;
2206                         break;
2207                 default:
2208                         BUG();
2209                         break;
2210                 }
2211                 break;
2212         default:
2213                 BUG();
2214                 break;
2215         }
2216
2217         return syncpt_id;
2218 }
2219
2220 static int tegra_dc_init(struct tegra_dc *dc)
2221 {
2222         int i;
2223
2224         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2225         if (dc->ndev->id == 0) {
2226                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2227                                       TEGRA_MC_PRIO_MED);
2228                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2229                                       TEGRA_MC_PRIO_MED);
2230                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2231                                       TEGRA_MC_PRIO_MED);
2232                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2233                                       TEGRA_MC_PRIO_MED);
2234                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2235                                       TEGRA_MC_PRIO_HIGH);
2236         } else if (dc->ndev->id == 1) {
2237                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2238                                       TEGRA_MC_PRIO_MED);
2239                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2240                                       TEGRA_MC_PRIO_MED);
2241                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2242                                       TEGRA_MC_PRIO_MED);
2243                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2244                                       TEGRA_MC_PRIO_MED);
2245                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2246                                       TEGRA_MC_PRIO_HIGH);
2247         }
2248         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2249                         DC_CMD_CONT_SYNCPT_VSYNC);
2250         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2251         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2252         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2253         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2254 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2255         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2256 #endif
2257         /* enable interrupts for vblank, frame_end and underflows */
2258         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2259                 DC_CMD_INT_ENABLE);
2260         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2261
2262         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2263
2264         tegra_dc_set_color_control(dc);
2265         for (i = 0; i < DC_N_WINDOWS; i++) {
2266                 struct tegra_dc_win *win = &dc->windows[i];
2267                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2268                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2269                 tegra_dc_set_csc(dc, &win->csc);
2270                 tegra_dc_set_lut(dc, win);
2271                 tegra_dc_set_scaling_filter(dc);
2272         }
2273
2274
2275         for (i = 0; i < dc->n_windows; i++) {
2276                 u32 syncpt = get_syncpt(dc, i);
2277
2278                 dc->syncpt[i].id = syncpt;
2279
2280                 dc->syncpt[i].min = dc->syncpt[i].max =
2281                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2282                                         syncpt);
2283         }
2284
2285         print_mode(dc, &dc->mode, __func__);
2286
2287         if (dc->mode.pclk)
2288                 if (tegra_dc_program_mode(dc, &dc->mode))
2289                         return -EINVAL;
2290
2291         /* Initialize SD AFTER the modeset.
2292            nvsd_init handles the sd_settings = NULL case. */
2293         nvsd_init(dc, dc->out->sd_settings);
2294
2295         return 0;
2296 }
2297
2298 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2299 {
2300         int failed_init = 0;
2301
2302         if (dc->out->enable)
2303                 dc->out->enable();
2304
2305         tegra_dc_setup_clk(dc, dc->clk);
2306         tegra_dc_clk_enable(dc);
2307
2308         /* do not accept interrupts during initialization */
2309         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2310         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2311
2312         enable_dc_irq(dc->irq);
2313
2314         failed_init = tegra_dc_init(dc);
2315         if (failed_init) {
2316                 _tegra_dc_controller_disable(dc);
2317                 return false;
2318         }
2319
2320         if (dc->out_ops && dc->out_ops->enable)
2321                 dc->out_ops->enable(dc);
2322
2323         if (dc->out->postpoweron)
2324                 dc->out->postpoweron();
2325
2326         /* force a full blending update */
2327         dc->blend.z[0] = -1;
2328
2329         tegra_dc_ext_enable(dc->ext);
2330
2331         trace_printk("%s:enable\n", dc->ndev->name);
2332         return true;
2333 }
2334
2335 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2336 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2337 {
2338         bool ret = true;
2339
2340         if (dc->out->enable)
2341                 dc->out->enable();
2342
2343         tegra_dc_setup_clk(dc, dc->clk);
2344         tegra_dc_clk_enable(dc);
2345
2346         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2347                 mutex_lock(&tegra_dcs[1]->lock);
2348                 disable_irq(tegra_dcs[1]->irq);
2349         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2350                 mutex_lock(&tegra_dcs[0]->lock);
2351                 disable_irq(tegra_dcs[0]->irq);
2352         }
2353
2354         msleep(5);
2355         tegra_periph_reset_assert(dc->clk);
2356         msleep(2);
2357 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2358         tegra_periph_reset_deassert(dc->clk);
2359         msleep(1);
2360 #endif
2361
2362         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2363                 enable_dc_irq(tegra_dcs[1]->irq);
2364                 mutex_unlock(&tegra_dcs[1]->lock);
2365         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2366                 enable_dc_irq(tegra_dcs[0]->irq);
2367                 mutex_unlock(&tegra_dcs[0]->lock);
2368         }
2369
2370         enable_dc_irq(dc->irq);
2371
2372         if (tegra_dc_init(dc)) {
2373                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2374                 ret = false;
2375         }
2376
2377         if (dc->out_ops && dc->out_ops->enable)
2378                 dc->out_ops->enable(dc);
2379
2380         if (dc->out->postpoweron)
2381                 dc->out->postpoweron();
2382
2383         /* force a full blending update */
2384         dc->blend.z[0] = -1;
2385
2386         tegra_dc_ext_enable(dc->ext);
2387
2388         if (!ret) {
2389                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2390                 _tegra_dc_controller_disable(dc);
2391         }
2392
2393         trace_printk("%s:reset enable\n", dc->ndev->name);
2394         return ret;
2395 }
2396 #endif
2397
2398 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2399 {
2400         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2401 }
2402
2403 static bool _tegra_dc_enable(struct tegra_dc *dc)
2404 {
2405         if (dc->mode.pclk == 0) {
2406                 switch (dc->out->type) {
2407                 case TEGRA_DC_OUT_HDMI:
2408                 /* DC enable called but no videomode is loaded.
2409                      Check if HDMI is connected, then set fallback mdoe */
2410                 if (tegra_dc_hpd(dc)) {
2411                         if (_tegra_dc_set_default_videomode(dc))
2412                                 return false;
2413                 } else
2414                         return false;
2415
2416                 break;
2417
2418                 /* Do nothing for other outputs for now */
2419                 case TEGRA_DC_OUT_RGB:
2420
2421                 case TEGRA_DC_OUT_DSI:
2422
2423                 default:
2424                         return false;
2425                 }
2426         }
2427
2428         if (!dc->out)
2429                 return false;
2430
2431         tegra_dc_io_start(dc);
2432
2433         return _tegra_dc_controller_enable(dc);
2434 }
2435
2436 void tegra_dc_enable(struct tegra_dc *dc)
2437 {
2438         mutex_lock(&dc->lock);
2439
2440         if (!dc->enabled)
2441                 dc->enabled = _tegra_dc_enable(dc);
2442
2443         mutex_unlock(&dc->lock);
2444         print_mode_info(dc, dc->mode);
2445 }
2446
2447 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2448 {
2449         unsigned i;
2450
2451         if (dc->out_ops && dc->out_ops->disable)
2452                 dc->out_ops->disable(dc);
2453
2454         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2455         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2456         disable_irq(dc->irq);
2457
2458         tegra_dc_clear_bandwidth(dc);
2459         tegra_dc_clk_disable(dc);
2460
2461         if (dc->out && dc->out->disable)
2462                 dc->out->disable();
2463
2464         for (i = 0; i < dc->n_windows; i++) {
2465                 struct tegra_dc_win *w = &dc->windows[i];
2466
2467                 /* reset window bandwidth */
2468                 w->bandwidth = 0;
2469                 w->new_bandwidth = 0;
2470
2471                 /* disable windows */
2472                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2473
2474                 /* flush any pending syncpt waits */
2475                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2476                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2477                                 dc->syncpt[i].id);
2478                         dc->syncpt[i].min++;
2479                         nvhost_syncpt_cpu_incr(
2480                                 &nvhost_get_host(dc->ndev)->syncpt,
2481                                 dc->syncpt[i].id);
2482                 }
2483         }
2484         trace_printk("%s:disabled\n", dc->ndev->name);
2485 }
2486
2487 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2488 {
2489 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2490         u32 val;
2491         if (dc->enabled)  {
2492                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2493                 if (enable)
2494                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2495                 else
2496                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2497                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2498         }
2499 #endif
2500 }
2501
2502 bool tegra_dc_stats_get(struct tegra_dc *dc)
2503 {
2504 #if 0 /* right now it is always enabled */
2505         u32 val;
2506         bool res;
2507
2508         if (dc->enabled)  {
2509                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2510                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2511         } else {
2512                 res = false;
2513         }
2514
2515         return res;
2516 #endif
2517         return true;
2518 }
2519
2520 /* make the screen blank by disabling all windows */
2521 void tegra_dc_blank(struct tegra_dc *dc)
2522 {
2523         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2524         unsigned i;
2525
2526         for (i = 0; i < DC_N_WINDOWS; i++) {
2527                 dcwins[i] = tegra_dc_get_window(dc, i);
2528                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2529         }
2530
2531         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2532         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2533 }
2534
2535 static void _tegra_dc_disable(struct tegra_dc *dc)
2536 {
2537         _tegra_dc_controller_disable(dc);
2538         tegra_dc_io_end(dc);
2539 }
2540
2541 void tegra_dc_disable(struct tegra_dc *dc)
2542 {
2543         tegra_dc_ext_disable(dc->ext);
2544
2545         /* it's important that new underflow work isn't scheduled before the
2546          * lock is acquired. */
2547         cancel_delayed_work_sync(&dc->underflow_work);
2548         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2549                 mutex_lock(&dc->one_shot_lock);
2550                 cancel_delayed_work_sync(&dc->one_shot_work);
2551         }
2552
2553         mutex_lock(&dc->lock);
2554
2555         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2556                 tegra_dc_host_resume(dc);
2557
2558         if (dc->enabled) {
2559                 dc->enabled = false;
2560
2561                 if (!dc->suspended)
2562                         _tegra_dc_disable(dc);
2563         }
2564
2565 #ifdef CONFIG_SWITCH
2566         switch_set_state(&dc->modeset_switch, 0);
2567 #endif
2568
2569         mutex_unlock(&dc->lock);
2570         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2571                 mutex_unlock(&dc->one_shot_lock);
2572         print_mode_info(dc, dc->mode);
2573 }
2574
2575 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2576 static void tegra_dc_reset_worker(struct work_struct *work)
2577 {
2578         struct tegra_dc *dc =
2579                 container_of(work, struct tegra_dc, reset_work);
2580
2581         unsigned long val = 0;
2582
2583         mutex_lock(&shared_lock);
2584
2585         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2586
2587         tegra_dc_ext_disable(dc->ext);
2588
2589         mutex_lock(&dc->lock);
2590
2591         if (dc->enabled == false)
2592                 goto unlock;
2593
2594         dc->enabled = false;
2595
2596         /*
2597          * off host read bus
2598          */
2599         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2600         val &= ~(0x00000100);
2601         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2602
2603         /*
2604          * set DC to STOP mode
2605          */
2606         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2607
2608         msleep(10);
2609
2610         _tegra_dc_controller_disable(dc);
2611
2612         /* _tegra_dc_controller_reset_enable deasserts reset */
2613         _tegra_dc_controller_reset_enable(dc);
2614
2615         dc->enabled = true;
2616
2617         /* reopen host read bus */
2618         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2619         val &= ~(0x00000100);
2620         val |= 0x100;
2621         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2622
2623 unlock:
2624         mutex_unlock(&dc->lock);
2625         mutex_unlock(&shared_lock);
2626         trace_printk("%s:reset complete\n", dc->ndev->name);
2627 }
2628 #endif
2629
2630 static void tegra_dc_underflow_worker(struct work_struct *work)
2631 {
2632         struct tegra_dc *dc = container_of(
2633                 to_delayed_work(work), struct tegra_dc, underflow_work);
2634
2635         mutex_lock(&dc->lock);
2636         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2637                 tegra_dc_host_resume(dc);
2638
2639         if (dc->enabled) {
2640                 tegra_dc_underflow_handler(dc);
2641         }
2642         mutex_unlock(&dc->lock);
2643 }
2644
2645 #ifdef CONFIG_SWITCH
2646 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2647 {
2648         struct tegra_dc *dc =
2649                 container_of(sdev, struct tegra_dc, modeset_switch);
2650
2651         if (!sdev->state)
2652                 return sprintf(buf, "offline\n");
2653
2654         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2655 }
2656 #endif
2657
2658 static int tegra_dc_probe(struct nvhost_device *ndev,
2659         struct nvhost_device_id *id_table)
2660 {
2661         struct tegra_dc *dc;
2662         struct clk *clk;
2663         struct clk *emc_clk;
2664         struct resource *res;
2665         struct resource *base_res;
2666         struct resource *fb_mem = NULL;
2667         int ret = 0;
2668         void __iomem *base;
2669         int irq;
2670         int i;
2671
2672         if (!ndev->dev.platform_data) {
2673                 dev_err(&ndev->dev, "no platform data\n");
2674                 return -ENOENT;
2675         }
2676
2677         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2678         if (!dc) {
2679                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2680                 return -ENOMEM;
2681         }
2682
2683         irq = nvhost_get_irq_byname(ndev, "irq");
2684         if (irq <= 0) {
2685                 dev_err(&ndev->dev, "no irq\n");
2686                 ret = -ENOENT;
2687                 goto err_free;
2688         }
2689
2690         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2691         if (!res) {
2692                 dev_err(&ndev->dev, "no mem resource\n");
2693                 ret = -ENOENT;
2694                 goto err_free;
2695         }
2696
2697         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2698         if (!base_res) {
2699                 dev_err(&ndev->dev, "request_mem_region failed\n");
2700                 ret = -EBUSY;
2701                 goto err_free;
2702         }
2703
2704         base = ioremap(res->start, resource_size(res));
2705         if (!base) {
2706                 dev_err(&ndev->dev, "registers can't be mapped\n");
2707                 ret = -EBUSY;
2708                 goto err_release_resource_reg;
2709         }
2710
2711         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2712
2713         clk = clk_get(&ndev->dev, NULL);
2714         if (IS_ERR_OR_NULL(clk)) {
2715                 dev_err(&ndev->dev, "can't get clock\n");
2716                 ret = -ENOENT;
2717                 goto err_iounmap_reg;
2718         }
2719
2720         emc_clk = clk_get(&ndev->dev, "emc");
2721         if (IS_ERR_OR_NULL(emc_clk)) {
2722                 dev_err(&ndev->dev, "can't get emc clock\n");
2723                 ret = -ENOENT;
2724                 goto err_put_clk;
2725         }
2726
2727         dc->clk = clk;
2728         dc->emc_clk = emc_clk;
2729         dc->shift_clk_div = 1;
2730         /* Initialize one shot work delay, it will be assigned by dsi
2731          * according to refresh rate later. */
2732         dc->one_shot_delay_ms = 40;
2733
2734         dc->base_res = base_res;
2735         dc->base = base;
2736         dc->irq = irq;
2737         dc->ndev = ndev;
2738         dc->pdata = ndev->dev.platform_data;
2739
2740         /*
2741          * The emc is a shared clock, it will be set based on
2742          * the requirements for each user on the bus.
2743          */
2744         dc->emc_clk_rate = 0;
2745
2746         mutex_init(&dc->lock);
2747         mutex_init(&dc->one_shot_lock);
2748         init_completion(&dc->frame_end_complete);
2749         init_waitqueue_head(&dc->wq);
2750 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2751         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2752 #endif
2753         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2754         dc->vblank_ref_count = 0;
2755         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2756         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2757
2758         tegra_dc_init_lut_defaults(&dc->fb_lut);
2759
2760         dc->n_windows = DC_N_WINDOWS;
2761         for (i = 0; i < dc->n_windows; i++) {
2762                 struct tegra_dc_win *win = &dc->windows[i];
2763                 win->idx = i;
2764                 win->dc = dc;
2765                 tegra_dc_init_csc_defaults(&win->csc);
2766                 tegra_dc_init_lut_defaults(&win->lut);
2767         }
2768
2769         ret = tegra_dc_set(dc, ndev->id);
2770         if (ret < 0) {
2771                 dev_err(&ndev->dev, "can't add dc\n");
2772                 goto err_free_irq;
2773         }
2774
2775         nvhost_set_drvdata(ndev, dc);
2776
2777 #ifdef CONFIG_SWITCH
2778         dc->modeset_switch.name = dev_name(&ndev->dev);
2779         dc->modeset_switch.state = 0;
2780         dc->modeset_switch.print_state = switch_modeset_print_mode;
2781         switch_dev_register(&dc->modeset_switch);
2782 #endif
2783
2784         tegra_dc_feature_register(dc);
2785
2786         if (dc->pdata->default_out)
2787                 tegra_dc_set_out(dc, dc->pdata->default_out);
2788         else
2789                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2790
2791         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2792                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2793
2794         dc->ext = tegra_dc_ext_register(ndev, dc);
2795         if (IS_ERR_OR_NULL(dc->ext)) {
2796                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2797                 dc->ext = NULL;
2798         }
2799
2800         mutex_lock(&dc->lock);
2801         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2802                 dc->enabled = _tegra_dc_enable(dc);
2803         mutex_unlock(&dc->lock);
2804
2805         /* interrupt handler must be registered before tegra_fb_register() */
2806         if (request_irq(irq, tegra_dc_irq, 0,
2807                         dev_name(&ndev->dev), dc)) {
2808                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2809                 ret = -EBUSY;
2810                 goto err_put_emc_clk;
2811         }
2812
2813         tegra_dc_create_debugfs(dc);
2814
2815         dev_info(&ndev->dev, "probed\n");
2816
2817         if (dc->pdata->fb) {
2818                 if (dc->pdata->fb->bits_per_pixel == -1) {
2819                         unsigned long fmt;
2820                         tegra_dc_writel(dc,
2821                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2822                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2823
2824                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2825                         dc->pdata->fb->bits_per_pixel =
2826                                 tegra_dc_fmt_bpp(fmt);
2827                 }
2828
2829                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2830                 if (IS_ERR_OR_NULL(dc->fb))
2831                         dc->fb = NULL;
2832         }
2833
2834         if (dc->out && dc->out->hotplug_init)
2835                 dc->out->hotplug_init();
2836
2837         if (dc->out_ops && dc->out_ops->detect)
2838                 dc->out_ops->detect(dc);
2839         else
2840                 dc->connected = true;
2841
2842         tegra_dc_create_sysfs(&dc->ndev->dev);
2843
2844         return 0;
2845
2846 err_free_irq:
2847         free_irq(irq, dc);
2848 err_put_emc_clk:
2849         clk_put(emc_clk);
2850 err_put_clk:
2851         clk_put(clk);
2852 err_iounmap_reg:
2853         iounmap(base);
2854         if (fb_mem)
2855                 release_resource(fb_mem);
2856 err_release_resource_reg:
2857         release_resource(base_res);
2858 err_free:
2859         kfree(dc);
2860
2861         return ret;
2862 }
2863
2864 static int tegra_dc_remove(struct nvhost_device *ndev)
2865 {
2866         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2867
2868         tegra_dc_remove_sysfs(&dc->ndev->dev);
2869         tegra_dc_remove_debugfs(dc);
2870
2871         if (dc->fb) {
2872                 tegra_fb_unregister(dc->fb);
2873                 if (dc->fb_mem)
2874                         release_resource(dc->fb_mem);
2875         }
2876
2877         tegra_dc_ext_disable(dc->ext);
2878
2879         if (dc->ext)
2880                 tegra_dc_ext_unregister(dc->ext);
2881
2882         if (dc->enabled)
2883                 _tegra_dc_disable(dc);
2884
2885 #ifdef CONFIG_SWITCH
2886         switch_dev_unregister(&dc->modeset_switch);
2887 #endif
2888         free_irq(dc->irq, dc);
2889         clk_put(dc->emc_clk);
2890         clk_put(dc->clk);
2891         iounmap(dc->base);
2892         if (dc->fb_mem)
2893                 release_resource(dc->base_res);
2894         kfree(dc);
2895         tegra_dc_set(NULL, ndev->id);
2896         return 0;
2897 }
2898
2899 #ifdef CONFIG_PM
2900 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2901 {
2902         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2903
2904         trace_printk("%s:suspend\n", dc->ndev->name);
2905         dev_info(&ndev->dev, "suspend\n");
2906
2907         tegra_dc_ext_disable(dc->ext);
2908
2909         mutex_lock(&dc->lock);
2910
2911         if (dc->out_ops && dc->out_ops->suspend)
2912                 dc->out_ops->suspend(dc);
2913
2914         if (dc->enabled) {
2915                 _tegra_dc_disable(dc);
2916
2917                 dc->suspended = true;
2918         }
2919
2920         if (dc->out && dc->out->postsuspend) {
2921                 dc->out->postsuspend();
2922                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2923                         /*
2924                          * avoid resume event due to voltage falling
2925                          */
2926                         msleep(100);
2927         }
2928
2929         mutex_unlock(&dc->lock);
2930
2931         return 0;
2932 }
2933
2934 static int tegra_dc_resume(struct nvhost_device *ndev)
2935 {
2936         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2937
2938         trace_printk("%s:resume\n", dc->ndev->name);
2939         dev_info(&ndev->dev, "resume\n");
2940
2941         mutex_lock(&dc->lock);
2942         dc->suspended = false;
2943
2944         if (dc->enabled)
2945                 _tegra_dc_enable(dc);
2946
2947         if (dc->out && dc->out->hotplug_init)
2948                 dc->out->hotplug_init();
2949
2950         if (dc->out_ops && dc->out_ops->resume)
2951                 dc->out_ops->resume(dc);
2952         mutex_unlock(&dc->lock);
2953
2954         return 0;
2955 }
2956
2957 #endif /* CONFIG_PM */
2958
2959 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2960 {
2961         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2962
2963         if (!dc || !dc->enabled)
2964                 return;
2965
2966         tegra_dc_blank(dc);
2967         tegra_dc_disable(dc);
2968 }
2969
2970 extern int suspend_set(const char *val, struct kernel_param *kp)
2971 {
2972         if (!strcmp(val, "dump"))
2973                 dump_regs(tegra_dcs[0]);
2974 #ifdef CONFIG_PM
2975         else if (!strcmp(val, "suspend"))
2976                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2977         else if (!strcmp(val, "resume"))
2978                 tegra_dc_resume(tegra_dcs[0]->ndev);
2979 #endif
2980
2981         return 0;
2982 }
2983
2984 extern int suspend_get(char *buffer, struct kernel_param *kp)
2985 {
2986         return 0;
2987 }
2988
2989 int suspend;
2990
2991 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2992
2993 struct nvhost_driver tegra_dc_driver = {
2994         .driver = {
2995                 .name = "tegradc",
2996                 .owner = THIS_MODULE,
2997         },
2998         .probe = tegra_dc_probe,
2999         .remove = tegra_dc_remove,
3000 #ifdef CONFIG_PM
3001         .suspend = tegra_dc_suspend,
3002         .resume = tegra_dc_resume,
3003 #endif
3004         .shutdown = tegra_dc_shutdown,
3005 };
3006
3007 static int __init tegra_dc_module_init(void)
3008 {
3009         int ret = tegra_dc_ext_module_init();
3010         if (ret)
3011                 return ret;
3012         return nvhost_driver_register(&tegra_dc_driver);
3013 }
3014
3015 static void __exit tegra_dc_module_exit(void)
3016 {
3017         nvhost_driver_unregister(&tegra_dc_driver);
3018         tegra_dc_ext_module_exit();
3019 }
3020
3021 module_exit(tegra_dc_module_exit);
3022 module_init(tegra_dc_module_init);