video: tegra3: dc: remove hard coded HDMI rates
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
70
71 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
72
73 static int use_dynamic_emc = 1;
74
75 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
76
77 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
78
79 DEFINE_MUTEX(tegra_dc_lock);
80 DEFINE_MUTEX(shared_lock);
81
82 static const struct {
83         bool h;
84         bool v;
85 } can_filter[] = {
86         /* Window A has no filtering */
87         { false, false },
88         /* Window B has both H and V filtering */
89         { true,  true  },
90         /* Window C has only H filtering */
91         { false, true  },
92 };
93 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
94 {
95         return can_filter[win->idx].v &&
96                 win->h.full != dfixed_const(win->out_h);
97 }
98 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
99 {
100         return can_filter[win->idx].h &&
101                 win->w.full != dfixed_const(win->out_w);
102 }
103
104 static inline int tegra_dc_fmt_bpp(int fmt)
105 {
106         switch (fmt) {
107         case TEGRA_WIN_FMT_P1:
108                 return 1;
109
110         case TEGRA_WIN_FMT_P2:
111                 return 2;
112
113         case TEGRA_WIN_FMT_P4:
114                 return 4;
115
116         case TEGRA_WIN_FMT_P8:
117                 return 8;
118
119         case TEGRA_WIN_FMT_B4G4R4A4:
120         case TEGRA_WIN_FMT_B5G5R5A:
121         case TEGRA_WIN_FMT_B5G6R5:
122         case TEGRA_WIN_FMT_AB5G5R5:
123                 return 16;
124
125         case TEGRA_WIN_FMT_B8G8R8A8:
126         case TEGRA_WIN_FMT_R8G8B8A8:
127         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
128         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
129                 return 32;
130
131         /* for planar formats, size of the Y plane, 8bit */
132         case TEGRA_WIN_FMT_YCbCr420P:
133         case TEGRA_WIN_FMT_YUV420P:
134         case TEGRA_WIN_FMT_YCbCr422P:
135         case TEGRA_WIN_FMT_YUV422P:
136         case TEGRA_WIN_FMT_YCbCr422R:
137         case TEGRA_WIN_FMT_YUV422R:
138         case TEGRA_WIN_FMT_YCbCr422RA:
139         case TEGRA_WIN_FMT_YUV422RA:
140                 return 8;
141
142         case TEGRA_WIN_FMT_YCbCr422:
143         case TEGRA_WIN_FMT_YUV422:
144                 /* FIXME: need to know the bpp of these formats */
145                 return 0;
146         }
147         return 0;
148 }
149
150 static inline bool tegra_dc_is_yuv_planar(int fmt)
151 {
152         switch (fmt) {
153         case TEGRA_WIN_FMT_YUV420P:
154         case TEGRA_WIN_FMT_YCbCr420P:
155         case TEGRA_WIN_FMT_YCbCr422P:
156         case TEGRA_WIN_FMT_YUV422P:
157         case TEGRA_WIN_FMT_YCbCr422R:
158         case TEGRA_WIN_FMT_YUV422R:
159         case TEGRA_WIN_FMT_YCbCr422RA:
160         case TEGRA_WIN_FMT_YUV422RA:
161                 return true;
162         }
163         return false;
164 }
165
166 #define DUMP_REG(a) do {                        \
167         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
168                  #a, a, tegra_dc_readl(dc, a));               \
169         print(data, buff);                                    \
170         } while (0)
171
172 static void _dump_regs(struct tegra_dc *dc, void *data,
173                        void (* print)(void *data, const char *str))
174 {
175         int i;
176         char buff[256];
177
178         tegra_dc_io_start(dc);
179         clk_enable(dc->clk);
180
181         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
182         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
183         DUMP_REG(DC_CMD_SIGNAL_RAISE);
184         DUMP_REG(DC_CMD_INT_STATUS);
185         DUMP_REG(DC_CMD_INT_MASK);
186         DUMP_REG(DC_CMD_INT_ENABLE);
187         DUMP_REG(DC_CMD_INT_TYPE);
188         DUMP_REG(DC_CMD_INT_POLARITY);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
190         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
191         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
192         DUMP_REG(DC_CMD_STATE_ACCESS);
193         DUMP_REG(DC_CMD_STATE_CONTROL);
194         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
195         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
196
197         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
198         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
199         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
200         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
201         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
202         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
203         DUMP_REG(DC_DISP_REF_TO_SYNC);
204         DUMP_REG(DC_DISP_SYNC_WIDTH);
205         DUMP_REG(DC_DISP_BACK_PORCH);
206         DUMP_REG(DC_DISP_DISP_ACTIVE);
207         DUMP_REG(DC_DISP_FRONT_PORCH);
208         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
211         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
212         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
213         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
216         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
217         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
218         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
221         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
222         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
223         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
225         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
226         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
227         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
229         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
230         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
231         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
233         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
234         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
235         DUMP_REG(DC_DISP_M0_CONTROL);
236         DUMP_REG(DC_DISP_M1_CONTROL);
237         DUMP_REG(DC_DISP_DI_CONTROL);
238         DUMP_REG(DC_DISP_PP_CONTROL);
239         DUMP_REG(DC_DISP_PP_SELECT_A);
240         DUMP_REG(DC_DISP_PP_SELECT_B);
241         DUMP_REG(DC_DISP_PP_SELECT_C);
242         DUMP_REG(DC_DISP_PP_SELECT_D);
243         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
244         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
245         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
246         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
247         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
248         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
249         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
250         DUMP_REG(DC_DISP_BORDER_COLOR);
251         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
253         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
254         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
255         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
256         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
257         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
258         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
259         DUMP_REG(DC_DISP_CURSOR_POSITION);
260         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
261         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
264         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
265         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
266         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
269         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
270         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
271         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
272         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
273
274
275         for (i = 0; i < 3; i++) {
276                 print(data, "\n");
277                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
278                 print(data, buff);
279
280                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
281                                 DC_CMD_DISPLAY_WINDOW_HEADER);
282                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
283                 DUMP_REG(DC_WIN_WIN_OPTIONS);
284                 DUMP_REG(DC_WIN_BYTE_SWAP);
285                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
286                 DUMP_REG(DC_WIN_COLOR_DEPTH);
287                 DUMP_REG(DC_WIN_POSITION);
288                 DUMP_REG(DC_WIN_SIZE);
289                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
290                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
291                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
292                 DUMP_REG(DC_WIN_DDA_INCREMENT);
293                 DUMP_REG(DC_WIN_LINE_STRIDE);
294                 DUMP_REG(DC_WIN_BUF_STRIDE);
295                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
296                 DUMP_REG(DC_WIN_BLEND_NOKEY);
297                 DUMP_REG(DC_WIN_BLEND_1WIN);
298                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
299                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
300                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
301                 DUMP_REG(DC_WINBUF_START_ADDR);
302                 DUMP_REG(DC_WINBUF_START_ADDR_U);
303                 DUMP_REG(DC_WINBUF_START_ADDR_V);
304                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
305                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
306                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
307                 DUMP_REG(DC_WIN_CSC_YOF);
308                 DUMP_REG(DC_WIN_CSC_KYRGB);
309                 DUMP_REG(DC_WIN_CSC_KUR);
310                 DUMP_REG(DC_WIN_CSC_KVR);
311                 DUMP_REG(DC_WIN_CSC_KUG);
312                 DUMP_REG(DC_WIN_CSC_KVG);
313                 DUMP_REG(DC_WIN_CSC_KUB);
314                 DUMP_REG(DC_WIN_CSC_KVB);
315         }
316
317         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
318         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
319         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
321         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
322         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
323         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
324         DUMP_REG(DC_DISP_M1_CONTROL);
325         DUMP_REG(DC_COM_PM1_CONTROL);
326         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
327         DUMP_REG(DC_DISP_SD_CONTROL);
328
329         clk_disable(dc->clk);
330         tegra_dc_io_end(dc);
331 }
332
333 #undef DUMP_REG
334
335 #ifdef DEBUG
336 static void dump_regs_print(void *data, const char *str)
337 {
338         struct tegra_dc *dc = data;
339         dev_dbg(&dc->ndev->dev, "%s", str);
340 }
341
342 static void dump_regs(struct tegra_dc *dc)
343 {
344         _dump_regs(dc, dc, dump_regs_print);
345 }
346 #else /* !DEBUG */
347
348 static void dump_regs(struct tegra_dc *dc) {}
349
350 #endif /* DEBUG */
351
352 #ifdef CONFIG_DEBUG_FS
353
354 static void dbg_regs_print(void *data, const char *str)
355 {
356         struct seq_file *s = data;
357
358         seq_printf(s, "%s", str);
359 }
360
361 #undef DUMP_REG
362
363 static int dbg_dc_show(struct seq_file *s, void *unused)
364 {
365         struct tegra_dc *dc = s->private;
366
367         _dump_regs(dc, s, dbg_regs_print);
368
369         return 0;
370 }
371
372
373 static int dbg_dc_open(struct inode *inode, struct file *file)
374 {
375         return single_open(file, dbg_dc_show, inode->i_private);
376 }
377
378 static const struct file_operations regs_fops = {
379         .open           = dbg_dc_open,
380         .read           = seq_read,
381         .llseek         = seq_lseek,
382         .release        = single_release,
383 };
384
385 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
386 {
387         struct tegra_dc *dc = s->private;
388         struct tegra_dc_mode *m;
389
390         mutex_lock(&dc->lock);
391         m = &dc->mode;
392         seq_printf(s,
393                 "pclk: %d\n"
394                 "h_ref_to_sync: %d\n"
395                 "v_ref_to_sync: %d\n"
396                 "h_sync_width: %d\n"
397                 "v_sync_width: %d\n"
398                 "h_back_porch: %d\n"
399                 "v_back_porch: %d\n"
400                 "h_active: %d\n"
401                 "v_active: %d\n"
402                 "h_front_porch: %d\n"
403                 "v_front_porch: %d\n"
404                 "stereo_mode: %d\n",
405                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
406                 m->h_sync_width, m->v_sync_width,
407                 m->h_back_porch, m->v_back_porch,
408                 m->h_active, m->v_active,
409                 m->h_front_porch, m->v_front_porch,
410                 m->stereo_mode);
411         mutex_unlock(&dc->lock);
412         return 0;
413 }
414
415 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
416 {
417         return single_open(file, dbg_dc_mode_show, inode->i_private);
418 }
419
420 static const struct file_operations mode_fops = {
421         .open           = dbg_dc_mode_open,
422         .read           = seq_read,
423         .llseek         = seq_lseek,
424         .release        = single_release,
425 };
426
427 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
428 {
429         struct tegra_dc *dc = s->private;
430
431         mutex_lock(&dc->lock);
432         seq_printf(s,
433                 "underflows: %llu\n"
434                 "underflows_a: %llu\n"
435                 "underflows_b: %llu\n"
436                 "underflows_c: %llu\n",
437                 dc->stats.underflows,
438                 dc->stats.underflows_a,
439                 dc->stats.underflows_b,
440                 dc->stats.underflows_c);
441         mutex_unlock(&dc->lock);
442
443         return 0;
444 }
445
446 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
447 {
448         return single_open(file, dbg_dc_stats_show, inode->i_private);
449 }
450
451 static const struct file_operations stats_fops = {
452         .open           = dbg_dc_stats_open,
453         .read           = seq_read,
454         .llseek         = seq_lseek,
455         .release        = single_release,
456 };
457
458 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
459 {
460         if (dc->debugdir)
461                 debugfs_remove_recursive(dc->debugdir);
462         dc->debugdir = NULL;
463 }
464
465 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
466 {
467         struct dentry *retval;
468
469         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
470         if (!dc->debugdir)
471                 goto remove_out;
472
473         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
474                 &regs_fops);
475         if (!retval)
476                 goto remove_out;
477
478         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
479                 &mode_fops);
480         if (!retval)
481                 goto remove_out;
482
483         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
484                 &stats_fops);
485         if (!retval)
486                 goto remove_out;
487
488         return;
489 remove_out:
490         dev_err(&dc->ndev->dev, "could not create debugfs\n");
491         tegra_dc_remove_debugfs(dc);
492 }
493
494 #else /* !CONFIG_DEBUGFS */
495 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
496 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
497 #endif /* CONFIG_DEBUGFS */
498
499 static int tegra_dc_set(struct tegra_dc *dc, int index)
500 {
501         int ret = 0;
502
503         mutex_lock(&tegra_dc_lock);
504         if (index >= TEGRA_MAX_DC) {
505                 ret = -EINVAL;
506                 goto out;
507         }
508
509         if (dc != NULL && tegra_dcs[index] != NULL) {
510                 ret = -EBUSY;
511                 goto out;
512         }
513
514         tegra_dcs[index] = dc;
515
516 out:
517         mutex_unlock(&tegra_dc_lock);
518
519         return ret;
520 }
521
522 unsigned int tegra_dc_has_multiple_dc(void)
523 {
524         unsigned int idx;
525         unsigned int cnt = 0;
526         struct tegra_dc *dc;
527
528         mutex_lock(&tegra_dc_lock);
529         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
530                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
531         mutex_unlock(&tegra_dc_lock);
532
533         return (cnt > 1);
534 }
535
536 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
537 {
538         if (idx < TEGRA_MAX_DC)
539                 return tegra_dcs[idx];
540         else
541                 return NULL;
542 }
543 EXPORT_SYMBOL(tegra_dc_get_dc);
544
545 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
546 {
547         if (win >= dc->n_windows)
548                 return NULL;
549
550         return &dc->windows[win];
551 }
552 EXPORT_SYMBOL(tegra_dc_get_window);
553
554 static int get_topmost_window(u32 *depths, unsigned long *wins)
555 {
556         int idx, best = -1;
557
558         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
559                 if (best == -1 || depths[idx] < depths[best])
560                         best = idx;
561         }
562         clear_bit(best, wins);
563         return best;
564 }
565
566 bool tegra_dc_get_connected(struct tegra_dc *dc)
567 {
568         return dc->connected;
569 }
570 EXPORT_SYMBOL(tegra_dc_get_connected);
571
572 static u32 blend_topwin(u32 flags)
573 {
574         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
575                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
576         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
577                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
578         else
579                 return BLEND(NOKEY, FIX, 0xff, 0xff);
580 }
581
582 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
583 {
584         int other;
585
586         for (other = 0; other < DC_N_WINDOWS; other++) {
587                 if (other != idx && (xy-- == 0))
588                         break;
589         }
590         if (BIT(other) & behind_mask)
591                 return blend_topwin(flags[idx]);
592         else if (flags[other])
593                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
594         else
595                 return BLEND(NOKEY, FIX, 0x00, 0x00);
596 }
597
598 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
599 {
600         unsigned long infront_mask;
601         int first;
602
603         infront_mask = ~(behind_mask | BIT(idx));
604         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
605         first = ffs(infront_mask) - 1;
606
607         if (!infront_mask)
608                 return blend_topwin(flags[idx]);
609         else if (behind_mask && first != -1 && flags[first])
610                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
611         else
612                 return BLEND(NOKEY, FIX, 0x0, 0x0);
613 }
614
615 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
616 {
617         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
618
619         while (mask) {
620                 int idx = get_topmost_window(blend->z, &mask);
621
622                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
623                                 DC_CMD_DISPLAY_WINDOW_HEADER);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_NOKEY);
626                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
627                                 DC_WIN_BLEND_1WIN);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
629                                 DC_WIN_BLEND_2WIN_X);
630                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
631                                 DC_WIN_BLEND_2WIN_Y);
632                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
633                                 DC_WIN_BLEND_3WIN_XY);
634         }
635 }
636
637 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
638 {
639         csc->yof   = 0x00f0;
640         csc->kyrgb = 0x012a;
641         csc->kur   = 0x0000;
642         csc->kvr   = 0x0198;
643         csc->kug   = 0x039b;
644         csc->kvg   = 0x032f;
645         csc->kub   = 0x0204;
646         csc->kvb   = 0x0000;
647 }
648
649 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
650 {
651         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
652         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
653         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
654         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
655         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
656         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
657         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
658         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
659 }
660
661 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
662 {
663         mutex_lock(&dc->lock);
664
665         if (!dc->enabled) {
666                 mutex_unlock(&dc->lock);
667                 return -EFAULT;
668         }
669
670         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
671                         DC_CMD_DISPLAY_WINDOW_HEADER);
672
673         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
674
675         mutex_unlock(&dc->lock);
676
677         return 0;
678 }
679 EXPORT_SYMBOL(tegra_dc_update_csc);
680
681 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
682 {
683         int i;
684         for (i = 0; i < 256; i++)
685                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
686 }
687
688 static int tegra_dc_loop_lut(struct tegra_dc *dc,
689                              struct tegra_dc_win *win,
690                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
691 {
692         struct tegra_dc_lut *lut = &win->lut;
693         struct tegra_dc_lut *global_lut = &dc->fb_lut;
694         int i;
695         for (i = 0; i < 256; i++) {
696
697                 u32 r = (u32)lut->r[i];
698                 u32 g = (u32)lut->g[i];
699                 u32 b = (u32)lut->b[i];
700
701                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
702                         r = (u32)global_lut->r[r];
703                         g = (u32)global_lut->g[g];
704                         b = (u32)global_lut->b[b];
705                 }
706
707                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
708                         return 0;
709         }
710         return 1;
711 }
712
713 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
714 {
715         if (rgb != (i | (i<<8) | (i<<16)))
716                 return 0;
717         return 1;
718 }
719
720 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
721 {
722         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
723         return 1;
724 }
725
726 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
727 {
728         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
729
730         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
731
732         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
733                 val |= CP_ENABLE;
734         else
735                 val &= ~CP_ENABLE;
736
737         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
738 }
739
740 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
741 {
742         struct tegra_dc_win *win = &dc->windows[win_idx];
743
744         mutex_lock(&dc->lock);
745
746         if (!dc->enabled) {
747                 mutex_unlock(&dc->lock);
748                 return -EFAULT;
749         }
750
751         if (fbovr > 0)
752                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753         else if (fbovr == 0)
754                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
755
756         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
757                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
758         else
759                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
760
761         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
762                         DC_CMD_DISPLAY_WINDOW_HEADER);
763
764         tegra_dc_set_lut(dc, win);
765
766         mutex_unlock(&dc->lock);
767
768         return 0;
769 }
770
771 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
772 {
773         if (win_idx > -1)
774                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
775
776         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
777                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
778                 if (err)
779                         return err;
780         }
781
782         return 0;
783 }
784 EXPORT_SYMBOL(tegra_dc_update_lut);
785
786 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
787 {
788         unsigned i;
789         unsigned v0 = 128;
790         unsigned v1 = 0;
791         /* linear horizontal and vertical filters */
792         for (i = 0; i < 16; i++) {
793                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
794                                 DC_WIN_H_FILTER_P(i));
795
796                 tegra_dc_writel(dc, v0,
797                                 DC_WIN_V_FILTER_P(i));
798                 v0 -= 8;
799                 v1 += 8;
800         }
801 }
802
803 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
804         struct tegra_dc_win *w)
805 {
806         /* windows A, B, C for first and second display */
807         static const enum tegra_la_id la_id_tab[2][3] = {
808                 /* first display */
809                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
810                         TEGRA_LA_DISPLAY_0C },
811                 /* second display */
812                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
813                         TEGRA_LA_DISPLAY_0CB },
814         };
815         /* window B V-filter tap for first and second display. */
816         static const enum tegra_la_id vfilter_tab[2] = {
817                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
818         };
819         unsigned long bw;
820
821         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
822         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
823         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
824
825         bw = w->new_bandwidth;
826
827         /* tegra_dc_get_bandwidth() treats V filter windows as double
828          * bandwidth, but LA has a seperate client for V filter */
829         if (w->idx == 1 && win_use_v_filter(w))
830                 bw /= 2;
831
832         /* our bandwidth is in bytes/sec, but LA takes MBps.
833          * round up bandwidth to 1MBps */
834         bw = bw / 1000000 + 1;
835
836 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
837         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
838         /* if window B, also set the 1B client for the 2-tap V filter. */
839         if (w->idx == 1)
840                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
841 #endif
842
843         w->bandwidth = w->new_bandwidth;
844 }
845
846 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
847                                                    struct tegra_dc_win *b)
848 {
849         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
850                 return 0;
851
852         /* because memory access to load the fifo can overlap, only care
853          * if windows overlap vertically */
854         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
855                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
856 }
857
858 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
859                                                  int n)
860 {
861         unsigned i;
862         unsigned j;
863         unsigned overlap_count;
864         unsigned max_bw = 0;
865
866         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
867                          "inaccurate.\n");
868
869         /* If we had a large number of windows, we would compute adjacency
870          * graph representing 2 window overlaps, find all cliques in the graph,
871          * assign bandwidth to each clique, and then select the clique with
872          * maximum bandwidth. But because we have at most 3 windows,
873          * implementing proper Bron-Kerbosh algorithm would be an overkill,
874          * brute force will suffice.
875          *
876          * Thus: find maximum bandwidth for either single or a pair of windows
877          * and count number of window pair overlaps. If there are three
878          * pairs, all 3 window overlap.
879          */
880
881         overlap_count = 0;
882         for (i = 0; i < n; i++) {
883                 unsigned int bw1;
884
885                 if (wins[i] == NULL)
886                         continue;
887                 bw1 = wins[i]->new_bandwidth;
888                 if (bw1 > max_bw)
889                         /* Single window */
890                         max_bw = bw1;
891
892                 for (j = i + 1; j < n; j++) {
893                         if (wins[j] == NULL)
894                                 continue;
895                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
896                                 unsigned int bw2 = wins[j]->new_bandwidth;
897                                 if (bw1 + bw2 > max_bw)
898                                         /* Window pair overlaps */
899                                         max_bw = bw1 + bw2;
900                                 overlap_count++;
901                         }
902                 }
903         }
904
905         if (overlap_count == 3)
906                 /* All three windows overlap */
907                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
908                          wins[2]->new_bandwidth;
909
910         return max_bw;
911 }
912
913 /*
914  * Calculate peak EMC bandwidth for each enabled window =
915  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
916  * (windows_tiling ? 2 : 1)
917  *
918  *
919  * note:
920  * (*) We use 2 tap V filter, so need double BW if use V filter
921  * (*) Tiling mode on T30 and DDR3 requires double BW
922  */
923 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
924         struct tegra_dc_win *w)
925 {
926         unsigned long ret;
927         int tiled_windows_bw_multiplier;
928         unsigned long bpp;
929
930         if (!WIN_IS_ENABLED(w))
931                 return 0;
932
933         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
934             w->out_w == 0 || w->out_h == 0)
935                 return 0;
936
937         tiled_windows_bw_multiplier =
938                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
939
940         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
941          * but the size reported by tegra_dc_fmt_bpp for the planar version
942          * is of the luma plane's size only. */
943         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
944                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
945         /* perform calculations with most significant bits of pixel clock
946          * to prevent overflow of long. */
947         ret = (unsigned long)(dc->mode.pclk >> 16) *
948                 bpp / 8 *
949                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
950                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
951
952 /*
953  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
954  * will request 147MBps from EMC.
955  */
956         ret = ret * 2 + ret / 10;
957
958         /* if overflowed */
959         if (ret > (1UL << 31))
960                 return ULONG_MAX;
961
962         return ret << 16; /* restore the scaling we did above */
963 }
964
965 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
966 {
967         int i;
968
969         BUG_ON(n > DC_N_WINDOWS);
970
971         /* emc rate and latency allowance both need to know per window
972          * bandwidths */
973         for (i = 0; i < n; i++) {
974                 struct tegra_dc_win *w = windows[i];
975                 if (w)
976                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
977         }
978
979         return tegra_dc_find_max_bandwidth(windows, n);
980 }
981
982 /* to save power, call when display memory clients would be idle */
983 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
984 {
985         if (tegra_is_clk_enabled(dc->emc_clk))
986                 clk_disable(dc->emc_clk);
987         dc->emc_clk_rate = 0;
988 }
989
990 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
991 {
992         unsigned i;
993
994         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
995                 /* going from 0 to non-zero */
996                 if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk))
997                         clk_enable(dc->emc_clk);
998
999                 dc->emc_clk_rate = dc->new_emc_clk_rate;
1000                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
1001
1002                 if (!dc->new_emc_clk_rate) /* going from non-zero to 0 */
1003                         clk_disable(dc->emc_clk);
1004         }
1005
1006         for (i = 0; i < DC_N_WINDOWS; i++) {
1007                 struct tegra_dc_win *w = &dc->windows[i];
1008                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1009                         tegra_dc_set_latency_allowance(dc, w);
1010         }
1011 }
1012
1013 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1014 {
1015         unsigned long new_rate;
1016         struct tegra_dc *dc;
1017
1018         if (!use_dynamic_emc)
1019                 return 0;
1020
1021         dc = windows[0]->dc;
1022
1023         /* calculate the new rate based on this POST */
1024         new_rate = tegra_dc_get_bandwidth(windows, n);
1025         new_rate = EMC_BW_TO_FREQ(new_rate);
1026
1027         if (tegra_dc_has_multiple_dc())
1028                 new_rate = ULONG_MAX;
1029
1030         dc->new_emc_clk_rate = new_rate;
1031
1032         return 0;
1033 }
1034
1035 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1036                                   bool v, unsigned Bpp)
1037 {
1038         /*
1039          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1040          *           (post_scaled_size_in_pixels - 1)), MAX)
1041          * Where the value of MAX is as follows:
1042          * For V_DDA_INCREMENT: 15.0 (0xF000)
1043          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1044          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1045          */
1046
1047         fixed20_12 out = dfixed_init(out_int);
1048         u32 dda_inc;
1049         int max;
1050
1051         if (v) {
1052                 max = 15;
1053         } else {
1054                 switch (Bpp) {
1055                 default:
1056                         WARN_ON_ONCE(1);
1057                         /* fallthrough */
1058                 case 4:
1059                         max = 4;
1060                         break;
1061                 case 2:
1062                         max = 8;
1063                         break;
1064                 }
1065         }
1066
1067         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1068         in.full -= dfixed_const(1);
1069
1070         dda_inc = dfixed_div(in, out);
1071
1072         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1073
1074         return dda_inc;
1075 }
1076
1077 static inline u32 compute_initial_dda(fixed20_12 in)
1078 {
1079         return dfixed_frac(in);
1080 }
1081
1082 /* does not support updating windows on multiple dcs in one call */
1083 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1084 {
1085         struct tegra_dc *dc;
1086         unsigned long update_mask = GENERAL_ACT_REQ;
1087         unsigned long val;
1088         bool update_blend = false;
1089         int i;
1090
1091         dc = windows[0]->dc;
1092
1093         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1094                 /* Acquire one_shot_lock to avoid race condition between
1095                  * cancellation of old delayed work and schedule of new
1096                  * delayed work. */
1097                 mutex_lock(&dc->one_shot_lock);
1098                 cancel_delayed_work_sync(&dc->one_shot_work);
1099         }
1100         mutex_lock(&dc->lock);
1101
1102         if (!dc->enabled) {
1103                 mutex_unlock(&dc->lock);
1104                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1105                         mutex_unlock(&dc->one_shot_lock);
1106                 return -EFAULT;
1107         }
1108
1109         if (no_vsync)
1110                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1111         else
1112                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1113
1114         for (i = 0; i < DC_N_WINDOWS; i++) {
1115                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1116                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1117                 tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1118                 if (!no_vsync)
1119                         update_mask |= WIN_A_ACT_REQ << i;
1120         }
1121
1122         for (i = 0; i < n; i++) {
1123                 struct tegra_dc_win *win = windows[i];
1124                 unsigned h_dda;
1125                 unsigned v_dda;
1126                 fixed20_12 h_offset, v_offset;
1127                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1128                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1129                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1130                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1131                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1132                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1133                 const bool filter_h = win_use_h_filter(win);
1134                 const bool filter_v = win_use_v_filter(win);
1135
1136                 if (win->z != dc->blend.z[win->idx]) {
1137                         dc->blend.z[win->idx] = win->z;
1138                         update_blend = true;
1139                 }
1140                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1141                         dc->blend.flags[win->idx]) {
1142                         dc->blend.flags[win->idx] =
1143                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1144                         update_blend = true;
1145                 }
1146
1147                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1148                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1149
1150                 if (!no_vsync)
1151                         update_mask |= WIN_A_ACT_REQ << win->idx;
1152
1153                 if (!WIN_IS_ENABLED(win)) {
1154                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1155                         continue;
1156                 }
1157
1158                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1159                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1160
1161                 tegra_dc_writel(dc,
1162                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1163                                 DC_WIN_POSITION);
1164                 tegra_dc_writel(dc,
1165                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1166                                 DC_WIN_SIZE);
1167                 tegra_dc_writel(dc,
1168                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1169                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1170                                 DC_WIN_PRESCALED_SIZE);
1171
1172                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1173                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1174                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1175                                 DC_WIN_DDA_INCREMENT);
1176                 h_dda = compute_initial_dda(win->x);
1177                 v_dda = compute_initial_dda(win->y);
1178                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1179                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1180
1181                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1182                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1183                 tegra_dc_writel(dc,
1184                                 (unsigned long)win->phys_addr,
1185                                 DC_WINBUF_START_ADDR);
1186
1187                 if (!yuvp) {
1188                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1189                 } else {
1190                         tegra_dc_writel(dc,
1191                                         (unsigned long)win->phys_addr_u,
1192                                         DC_WINBUF_START_ADDR_U);
1193                         tegra_dc_writel(dc,
1194                                         (unsigned long)win->phys_addr_v,
1195                                         DC_WINBUF_START_ADDR_V);
1196                         tegra_dc_writel(dc,
1197                                         LINE_STRIDE(win->stride) |
1198                                         UV_LINE_STRIDE(win->stride_uv),
1199                                         DC_WIN_LINE_STRIDE);
1200                 }
1201
1202                 h_offset = win->x;
1203                 if (invert_h) {
1204                         h_offset.full += win->w.full - dfixed_const(1);
1205                 }
1206
1207                 v_offset = win->y;
1208                 if (invert_v) {
1209                         v_offset.full += win->h.full - dfixed_const(1);
1210                 }
1211
1212                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1213                                 DC_WINBUF_ADDR_H_OFFSET);
1214                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1215                                 DC_WINBUF_ADDR_V_OFFSET);
1216
1217                 if (WIN_IS_TILED(win))
1218                         tegra_dc_writel(dc,
1219                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1220                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1221                                         DC_WIN_BUFFER_ADDR_MODE);
1222                 else
1223                         tegra_dc_writel(dc,
1224                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1225                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1226                                         DC_WIN_BUFFER_ADDR_MODE);
1227
1228                 val = WIN_ENABLE;
1229                 if (yuvp)
1230                         val |= CSC_ENABLE;
1231                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1232                         val |= COLOR_EXPAND;
1233
1234                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1235                         val |= CP_ENABLE;
1236
1237                 if (filter_h)
1238                         val |= H_FILTER_ENABLE;
1239                 if (filter_v)
1240                         val |= V_FILTER_ENABLE;
1241
1242                 if (invert_h)
1243                         val |= H_DIRECTION_DECREMENT;
1244                 if (invert_v)
1245                         val |= V_DIRECTION_DECREMENT;
1246
1247                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1248
1249                 win->dirty = no_vsync ? 0 : 1;
1250
1251                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1252                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1253                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1254                         __func__, win->idx, win->z,
1255                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1256                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1257                         win->out_x, win->out_y, win->out_w, win->out_h,
1258                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1259         }
1260
1261         if (update_blend) {
1262                 tegra_dc_set_blending(dc, &dc->blend);
1263                 for (i = 0; i < DC_N_WINDOWS; i++) {
1264                         if (!no_vsync)
1265                                 dc->windows[i].dirty = 1;
1266                         update_mask |= WIN_A_ACT_REQ << i;
1267                 }
1268         }
1269
1270         tegra_dc_set_dynamic_emc(windows, n);
1271
1272         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1273
1274         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1275         if (!no_vsync) {
1276                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1277                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1278                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1279         } else {
1280                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1281                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1282                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1283         }
1284
1285         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1286                 schedule_delayed_work(&dc->one_shot_work,
1287                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1288
1289         /* update EMC clock if calculated bandwidth has changed */
1290         tegra_dc_program_bandwidth(dc);
1291
1292         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1293                 update_mask |= NC_HOST_TRIG;
1294
1295         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1296
1297         mutex_unlock(&dc->lock);
1298         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1299                 mutex_unlock(&dc->one_shot_lock);
1300
1301         return 0;
1302 }
1303 EXPORT_SYMBOL(tegra_dc_update_windows);
1304
1305 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1306 {
1307         return dc->syncpt[i].id;
1308 }
1309 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1310
1311 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1312 {
1313         u32 max;
1314
1315         mutex_lock(&dc->lock);
1316         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1317                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1318         dc->syncpt[i].max = max;
1319         mutex_unlock(&dc->lock);
1320
1321         return max;
1322 }
1323
1324 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1325 {
1326         mutex_lock(&dc->lock);
1327         if ( dc->enabled )
1328                 while (dc->syncpt[i].min < val) {
1329                         dc->syncpt[i].min++;
1330                         nvhost_syncpt_cpu_incr(
1331                                         &nvhost_get_host(dc->ndev)->syncpt,
1332                                         dc->syncpt[i].id);
1333                 }
1334         mutex_unlock(&dc->lock);
1335 }
1336
1337 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1338                                              int n)
1339 {
1340         int i;
1341
1342         for (i = 0; i < n; i++) {
1343                 if (windows[i]->dirty)
1344                         return false;
1345         }
1346
1347         return true;
1348 }
1349
1350 /* does not support syncing windows on multiple dcs in one call */
1351 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1352 {
1353         if (n < 1 || n > DC_N_WINDOWS)
1354                 return -EINVAL;
1355
1356         if (!windows[0]->dc->enabled)
1357                 return -EFAULT;
1358
1359 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1360         /* Don't want to timeout on simulator */
1361         return wait_event_interruptible(windows[0]->dc->wq,
1362                 tegra_dc_windows_are_clean(windows, n));
1363 #else
1364         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1365                                          tegra_dc_windows_are_clean(windows, n),
1366                                          HZ);
1367 #endif
1368 }
1369 EXPORT_SYMBOL(tegra_dc_sync_windows);
1370
1371 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1372 {
1373 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1374         return clk_get_rate(dc->clk);
1375 #else
1376         return 27000000;
1377 #endif
1378 }
1379
1380 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1381 {
1382         unsigned long rate;
1383         unsigned long div;
1384
1385         rate = tegra_dc_clk_get_rate(dc);
1386
1387         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1388
1389         if (div < 2)
1390                 return 0;
1391
1392         return rate * 2 / div;
1393 }
1394
1395 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1396 {
1397         unsigned long rate;
1398         unsigned long div;
1399
1400         rate = clk_get_rate(parent);
1401
1402         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1403
1404         if (div < 2)
1405                 return 0;
1406
1407         return rate * 2 / div;
1408 }
1409
1410 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1411 {
1412         int pclk;
1413
1414         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1415                 unsigned long rate;
1416                 struct clk *parent_clk =
1417                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1418
1419                 if (dc->out->parent_clk_backup &&
1420                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1421                         rate = tegra_dc_pclk_predict_rate(
1422                                 parent_clk, dc->mode.pclk);
1423                         /* use pll_d as last resort */
1424                         if (rate < (dc->mode.pclk / 100 * 99) ||
1425                             rate > (dc->mode.pclk / 100 * 109))
1426                                 parent_clk = clk_get_sys(
1427                                         NULL, dc->out->parent_clk_backup);
1428                 }
1429
1430                 if (clk_get_parent(clk) != parent_clk)
1431                         clk_set_parent(clk, parent_clk);
1432
1433                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1434                         struct clk *base_clk = clk_get_parent(parent_clk);
1435
1436                         /* Assuming either pll_d or pll_d2 is used */
1437                         rate = dc->mode.pclk * 2;
1438
1439                         if (rate != clk_get_rate(base_clk))
1440                                 clk_set_rate(base_clk, rate);
1441                 }
1442         }
1443
1444         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1445                 unsigned long rate;
1446                 struct clk *parent_clk =
1447                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1448                 struct clk *base_clk = clk_get_parent(parent_clk);
1449
1450                 /*
1451                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1452                  * The required rate needs to be setup at 4x multiplier,
1453                  * as out0 is 1/2 of the actual PLL output.
1454                  */
1455
1456                 rate = dc->mode.pclk * 4;
1457                 if (rate != clk_get_rate(base_clk))
1458                         clk_set_rate(base_clk, rate);
1459
1460                 if (clk_get_parent(clk) != parent_clk)
1461                         clk_set_parent(clk, parent_clk);
1462         }
1463
1464         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1465                 unsigned long rate;
1466                 struct clk *parent_clk;
1467                 struct clk *base_clk;
1468
1469                 if (clk == dc->clk) {
1470                         parent_clk = clk_get_sys(NULL,
1471                                         dc->out->parent_clk ? : "pll_d_out0");
1472                         base_clk = clk_get_parent(parent_clk);
1473                         tegra_clk_cfg_ex(base_clk,
1474                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1475                 } else {
1476                         if (dc->pdata->default_out->dsi->dsi_instance) {
1477                                 parent_clk = clk_get_sys(NULL,
1478                                         dc->out->parent_clk ? : "pll_d2_out0");
1479                                 base_clk = clk_get_parent(parent_clk);
1480                                 tegra_clk_cfg_ex(base_clk,
1481                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1482                         } else {
1483                                 parent_clk = clk_get_sys(NULL,
1484                                         dc->out->parent_clk ? : "pll_d_out0");
1485                                 base_clk = clk_get_parent(parent_clk);
1486                                 tegra_clk_cfg_ex(base_clk,
1487                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1488                         }
1489                 }
1490
1491                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1492                 if (rate != clk_get_rate(base_clk))
1493                         clk_set_rate(base_clk, rate);
1494
1495                 if (clk_get_parent(clk) != parent_clk)
1496                         clk_set_parent(clk, parent_clk);
1497         }
1498
1499         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1500         tegra_dvfs_set_rate(clk, pclk);
1501 }
1502
1503 /* return non-zero if constraint is violated */
1504 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1505 {
1506         long a, b;
1507
1508         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1509         a = 0;
1510
1511         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1512         b = mode->h_front_porch - 1;
1513
1514         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1515         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1516                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1517         /* check Constraint 1 and 6 */
1518         if (a > b)
1519                 return 1;
1520
1521         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1522         if (mode->h_sync_width < 1)
1523                 return 4;
1524
1525         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1526         if (mode->h_active < 16)
1527                 return 7;
1528
1529         if (href) {
1530                 if (b > a && a % 2)
1531                         *href = a + 1; /* use smallest even value */
1532                 else
1533                         *href = a; /* even or only possible value */
1534         }
1535
1536         return 0;
1537 }
1538
1539 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1540 {
1541         long a;
1542         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1543
1544         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1545         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1546                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1547
1548         /* Constraint 6 */
1549         if (mode->v_front_porch < a + 1)
1550                 a = mode->v_front_porch - 1;
1551
1552         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1553         if (mode->v_sync_width < 1)
1554                 return 4;
1555
1556         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1557         if (mode->v_active < 16)
1558                 return 7;
1559
1560         if (vref)
1561                 *vref = a;
1562         return 0;
1563 }
1564
1565 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1566 {
1567         int ret;
1568         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1569         if (ret)
1570                 return ret;
1571         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1572         if (ret)
1573                 return ret;
1574
1575         return 0;
1576 }
1577
1578 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1579 {
1580         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1581         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1582                 return false;
1583
1584         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1585         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1586                 return false;
1587
1588         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1589          * (vertical blank). */
1590         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1591                 return false;
1592
1593         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1594         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1595                 return false;
1596
1597         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1598         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1599                 return false;
1600
1601         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1602          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1603         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1604                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1605                 return false;
1606
1607         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1608         if (mode->h_active < 16 || mode->v_active < 16)
1609                 return false;
1610
1611         return true;
1612 }
1613
1614 #ifdef DEBUG
1615 /* return in 1000ths of a Hertz */
1616 static int calc_refresh(const struct tegra_dc_mode *m)
1617 {
1618         long h_total, v_total, refresh;
1619         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1620                 m->h_sync_width;
1621         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1622                 m->v_sync_width;
1623         refresh = m->pclk / h_total;
1624         refresh *= 1000;
1625         refresh /= v_total;
1626         return refresh;
1627 }
1628
1629 static void print_mode(struct tegra_dc *dc,
1630                         const struct tegra_dc_mode *mode, const char *note)
1631 {
1632         if (mode) {
1633                 int refresh = calc_refresh(dc, mode);
1634                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1635                         note ? note : "",
1636                         mode->h_active, mode->v_active,
1637                         refresh / 1000, refresh % 1000,
1638                         mode->pclk);
1639         }
1640 }
1641 #else /* !DEBUG */
1642 static inline void print_mode(struct tegra_dc *dc,
1643                         const struct tegra_dc_mode *mode, const char *note) { }
1644 #endif /* DEBUG */
1645
1646 static inline void enable_dc_irq(unsigned int irq)
1647 {
1648 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1649         enable_irq(irq);
1650 #else
1651         /* Always disable DC interrupts on FPGA. */
1652         disable_irq(irq);
1653 #endif
1654 }
1655
1656 static inline void disable_dc_irq(unsigned int irq)
1657 {
1658         disable_irq(irq);
1659 }
1660
1661 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1662 {
1663         unsigned long val;
1664         unsigned long rate;
1665         unsigned long div;
1666         unsigned long pclk;
1667
1668         print_mode(dc, mode, __func__);
1669
1670         /* use default EMC rate when switching modes */
1671         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1672         tegra_dc_program_bandwidth(dc);
1673
1674         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1675         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1676                         DC_DISP_REF_TO_SYNC);
1677         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1678                         DC_DISP_SYNC_WIDTH);
1679         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1680                         DC_DISP_BACK_PORCH);
1681         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1682                         DC_DISP_DISP_ACTIVE);
1683         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1684                         DC_DISP_FRONT_PORCH);
1685
1686         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1687                         DC_DISP_DATA_ENABLE_OPTIONS);
1688
1689         /* TODO: MIPI/CRT/HDMI clock cals */
1690
1691         val = DISP_DATA_FORMAT_DF1P1C;
1692
1693         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1694                 val |= DISP_DATA_ALIGNMENT_MSB;
1695         else
1696                 val |= DISP_DATA_ALIGNMENT_LSB;
1697
1698         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1699                 val |= DISP_DATA_ORDER_RED_BLUE;
1700         else
1701                 val |= DISP_DATA_ORDER_BLUE_RED;
1702
1703         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1704
1705         rate = tegra_dc_clk_get_rate(dc);
1706
1707         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1708         if (pclk < (mode->pclk / 100 * 99) ||
1709             pclk > (mode->pclk / 100 * 109)) {
1710                 dev_err(&dc->ndev->dev,
1711                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1712                         rate, mode->pclk,
1713                         pclk, (mode->pclk / 100 * 99),
1714                         (mode->pclk / 100 * 109));
1715                 return -EINVAL;
1716         }
1717
1718         div = (rate * 2 / pclk) - 2;
1719
1720         tegra_dc_writel(dc, 0x00010001,
1721                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1722         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1723                         DC_DISP_DISP_CLOCK_CONTROL);
1724
1725 #ifdef CONFIG_SWITCH
1726         switch_set_state(&dc->modeset_switch,
1727                          (mode->h_active << 16) | mode->v_active);
1728 #endif
1729
1730         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1731         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1732
1733         return 0;
1734 }
1735
1736
1737 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1738 {
1739         memcpy(&dc->mode, mode, sizeof(dc->mode));
1740
1741         print_mode(dc, mode, __func__);
1742
1743         return 0;
1744 }
1745 EXPORT_SYMBOL(tegra_dc_set_mode);
1746
1747 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1748                 const struct fb_videomode *fbmode, bool stereo_mode)
1749 {
1750         struct tegra_dc_mode mode;
1751
1752         if (!fbmode->pixclock)
1753                 return -EINVAL;
1754
1755         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1756         mode.h_sync_width = fbmode->hsync_len;
1757         mode.v_sync_width = fbmode->vsync_len;
1758         mode.h_back_porch = fbmode->left_margin;
1759         mode.v_back_porch = fbmode->upper_margin;
1760         mode.h_active = fbmode->xres;
1761         mode.v_active = fbmode->yres;
1762         mode.h_front_porch = fbmode->right_margin;
1763         mode.v_front_porch = fbmode->lower_margin;
1764         mode.stereo_mode = stereo_mode;
1765         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1766                 /* HDMI controller requires h_ref=1, v_ref=1 */
1767                 mode.h_ref_to_sync = 1;
1768                 mode.v_ref_to_sync = 1;
1769         } else {
1770                 calc_ref_to_sync(&mode);
1771         }
1772         if (!check_ref_to_sync(&mode)) {
1773                 dev_err(&dc->ndev->dev,
1774                                 "Display timing doesn't meet restrictions.\n");
1775                 return -EINVAL;
1776         }
1777         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1778                 mode.h_active, mode.v_active, mode.pclk,
1779                 mode.h_ref_to_sync, mode.v_ref_to_sync
1780         );
1781
1782 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1783         /* Double the pixel clock and update v_active only for frame packed mode */
1784         if (mode.stereo_mode) {
1785                 mode.pclk *= 2;
1786                 /* total v_active = yres*2 + activespace */
1787                 mode.v_active = fbmode->yres*2 +
1788                                 fbmode->vsync_len +
1789                                 fbmode->upper_margin +
1790                                 fbmode->lower_margin;
1791         }
1792 #endif
1793
1794         mode.flags = 0;
1795
1796         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1797                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1798
1799         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1800                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1801
1802         return tegra_dc_set_mode(dc, &mode);
1803 }
1804 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1805
1806 void
1807 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1808 {
1809         unsigned int ctrl;
1810         unsigned long out_sel;
1811         unsigned long cmd_state;
1812
1813         mutex_lock(&dc->lock);
1814         if (!dc->enabled) {
1815                 mutex_unlock(&dc->lock);
1816                 return;
1817         }
1818
1819         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1820                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1821                 cfg->clk_select);
1822
1823         /* The new value should be effected immediately */
1824         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1825         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1826
1827         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1828                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1829         else
1830                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1831
1832         switch (cfg->which_pwm) {
1833         case TEGRA_PWM_PM0:
1834                 /* Select the LM0 on PM0 */
1835                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1836                 out_sel &= ~(7 << 0);
1837                 out_sel |= (3 << 0);
1838                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1839                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1840                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1841                 break;
1842         case TEGRA_PWM_PM1:
1843                 /* Select the LM1 on PM1 */
1844                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1845                 out_sel &= ~(7 << 4);
1846                 out_sel |= (3 << 4);
1847                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1848                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1849                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1850                 break;
1851         default:
1852                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1853                 break;
1854         }
1855         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1856         mutex_unlock(&dc->lock);
1857 }
1858 EXPORT_SYMBOL(tegra_dc_config_pwm);
1859
1860 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1861                                 const struct tegra_dc_out_pin *pins,
1862                                 const unsigned int n_pins)
1863 {
1864         unsigned int i;
1865
1866         int name;
1867         int pol;
1868
1869         u32 pol1, pol3;
1870
1871         u32 set1, unset1;
1872         u32 set3, unset3;
1873
1874         set1 = set3 = unset1 = unset3 = 0;
1875
1876         for (i = 0; i < n_pins; i++) {
1877                 name = (pins + i)->name;
1878                 pol  = (pins + i)->pol;
1879
1880                 /* set polarity by name */
1881                 switch (name) {
1882                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1883                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1884                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1885                         else
1886                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1887                         break;
1888                 case TEGRA_DC_OUT_PIN_H_SYNC:
1889                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1890                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1891                         else
1892                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1893                         break;
1894                 case TEGRA_DC_OUT_PIN_V_SYNC:
1895                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1896                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1897                         else
1898                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1899                         break;
1900                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1901                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1902                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1903                         else
1904                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1905                         break;
1906                 default:
1907                         printk("Invalid argument in function %s\n",
1908                                __FUNCTION__);
1909                         break;
1910                 }
1911         }
1912
1913         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1914         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1915
1916         pol1 |= set1;
1917         pol1 &= ~unset1;
1918
1919         pol3 |= set3;
1920         pol3 &= ~unset3;
1921
1922         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1923         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1924 }
1925
1926 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1927 {
1928         dc->out = out;
1929
1930         if (out->n_modes > 0)
1931                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1932
1933         switch (out->type) {
1934         case TEGRA_DC_OUT_RGB:
1935                 dc->out_ops = &tegra_dc_rgb_ops;
1936                 break;
1937
1938         case TEGRA_DC_OUT_HDMI:
1939                 dc->out_ops = &tegra_dc_hdmi_ops;
1940                 break;
1941
1942         case TEGRA_DC_OUT_DSI:
1943                 dc->out_ops = &tegra_dc_dsi_ops;
1944                 break;
1945
1946         default:
1947                 dc->out_ops = NULL;
1948                 break;
1949         }
1950
1951         if (dc->out_ops && dc->out_ops->init)
1952                 dc->out_ops->init(dc);
1953
1954 }
1955
1956 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1957 {
1958         if (dc->out)
1959                 return dc->out->height;
1960         else
1961                 return 0;
1962 }
1963 EXPORT_SYMBOL(tegra_dc_get_out_height);
1964
1965 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1966 {
1967         if (dc->out)
1968                 return dc->out->width;
1969         else
1970                 return 0;
1971 }
1972 EXPORT_SYMBOL(tegra_dc_get_out_width);
1973
1974 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1975 {
1976         if (dc->out && dc->out->max_pixclock)
1977                 return dc->out->max_pixclock;
1978         else
1979                 return 0;
1980 }
1981 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1982
1983 void tegra_dc_enable_crc(struct tegra_dc *dc)
1984 {
1985         u32 val;
1986         tegra_dc_io_start(dc);
1987
1988         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1989                 CRC_ENABLE_ENABLE;
1990         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1991         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1992         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1993 }
1994
1995 void tegra_dc_disable_crc(struct tegra_dc *dc)
1996 {
1997         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1998         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1999         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2000
2001         tegra_dc_io_end(dc);
2002 }
2003
2004 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2005 {
2006         int crc = 0;
2007
2008         if(!dc) {
2009                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2010                 goto crc_error;
2011         }
2012
2013         /* TODO: Replace mdelay with code to sync VBlANK, since
2014          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2015         mdelay(TEGRA_CRC_LATCHED_DELAY);
2016
2017         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2018 crc_error:
2019         return crc;
2020 }
2021
2022 static void tegra_dc_vblank(struct work_struct *work)
2023 {
2024         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2025         bool nvsd_updated = false;
2026
2027         mutex_lock(&dc->lock);
2028
2029         /* Update the SD brightness */
2030         if (dc->enabled && dc->out->sd_settings)
2031                 nvsd_updated = nvsd_update_brightness(dc);
2032
2033         mutex_unlock(&dc->lock);
2034
2035         /* Do the actual brightness update outside of the mutex */
2036         if (nvsd_updated && dc->out->sd_settings &&
2037             dc->out->sd_settings->bl_device) {
2038
2039                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2040                 struct backlight_device *bl = platform_get_drvdata(pdev);
2041                 if (bl)
2042                         backlight_update_status(bl);
2043         }
2044 }
2045
2046 /* Must acquire dc lock and dc one-shot lock before invoking this function.
2047  * Acquire dc one-shot lock first and then dc lock. */
2048 void tegra_dc_host_trigger(struct tegra_dc *dc)
2049 {
2050         /* We release the lock here to prevent deadlock between
2051          * cancel_delayed_work_sync and one-shot work. */
2052         mutex_unlock(&dc->lock);
2053
2054         cancel_delayed_work_sync(&dc->one_shot_work);
2055         mutex_lock(&dc->lock);
2056
2057         schedule_delayed_work(&dc->one_shot_work,
2058                                 msecs_to_jiffies(dc->one_shot_delay_ms));
2059         tegra_dc_program_bandwidth(dc);
2060         tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
2061 }
2062
2063 static void tegra_dc_one_shot_worker(struct work_struct *work)
2064 {
2065         struct tegra_dc *dc = container_of(
2066                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2067         mutex_lock(&dc->lock);
2068         /* memory client has gone idle */
2069         tegra_dc_clear_bandwidth(dc);
2070         mutex_unlock(&dc->lock);
2071 }
2072
2073 /* return an arbitrarily large number if count overflow occurs.
2074  * make it a nice base-10 number to show up in stats output */
2075 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2076 {
2077         unsigned count = tegra_dc_readl(dc, reg);
2078         tegra_dc_writel(dc, 0, reg);
2079         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2080 }
2081
2082 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2083 {
2084         u32 val;
2085         int i;
2086
2087         dc->stats.underflows++;
2088         if (dc->underflow_mask & WIN_A_UF_INT)
2089                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2090                         DC_WINBUF_AD_UFLOW_STATUS);
2091         if (dc->underflow_mask & WIN_B_UF_INT)
2092                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2093                         DC_WINBUF_BD_UFLOW_STATUS);
2094         if (dc->underflow_mask & WIN_C_UF_INT)
2095                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2096                         DC_WINBUF_CD_UFLOW_STATUS);
2097
2098         /* Check for any underflow reset conditions */
2099         for (i = 0; i < DC_N_WINDOWS; i++) {
2100                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2101                         dc->windows[i].underflows++;
2102
2103 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2104                         if (dc->windows[i].underflows > 4)
2105                                 schedule_work(&dc->reset_work);
2106 #endif
2107                 } else {
2108                         dc->windows[i].underflows = 0;
2109                 }
2110         }
2111
2112         /* Clear the underflow mask now that we've checked it. */
2113         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2114         dc->underflow_mask = 0;
2115         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2116         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2117 }
2118
2119 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2120 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2121 {
2122 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2123         u32 val;
2124
2125         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2126         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2127             return true;
2128 #endif
2129         return false;
2130 }
2131
2132 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2133 {
2134         u32 val, i;
2135         u32 completed = 0;
2136         u32 dirty = 0;
2137
2138         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2139         for (i = 0; i < DC_N_WINDOWS; i++) {
2140 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2141                 /* FIXME: this is not needed when the simulator
2142                    clears WIN_x_UPDATE bits as in HW */
2143                 dc->windows[i].dirty = 0;
2144                 completed = 1;
2145 #else
2146                 if (!(val & (WIN_A_UPDATE << i))) {
2147                         dc->windows[i].dirty = 0;
2148                         completed = 1;
2149                 } else {
2150                         dirty = 1;
2151                 }
2152 #endif
2153         }
2154
2155         if (!dirty) {
2156                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2157                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2158                         val &= ~V_BLANK_INT;
2159                 else
2160                         val &= ~FRAME_END_INT;
2161                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2162         }
2163
2164         if (completed) {
2165                 if (!dirty) {
2166                         /* With the last completed window, go ahead
2167                            and enable the vblank interrupt for nvsd. */
2168                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2169                         val |= V_BLANK_INT;
2170                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2171                 }
2172
2173                 wake_up(&dc->wq);
2174         }
2175 }
2176
2177 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2178 {
2179         if (status & V_BLANK_INT) {
2180                 /* Sync up windows. */
2181                 tegra_dc_trigger_windows(dc);
2182
2183                 /* Schedule any additional bottom-half vblank actvities. */
2184                 schedule_work(&dc->vblank_work);
2185         }
2186
2187         if (status & FRAME_END_INT) {
2188                 /* Mark the frame_end as complete. */
2189                 if (!completion_done(&dc->frame_end_complete))
2190                         complete(&dc->frame_end_complete);
2191         }
2192 }
2193
2194 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2195 {
2196         if (status & V_BLANK_INT) {
2197                 /* Schedule any additional bottom-half vblank actvities. */
2198                 schedule_work(&dc->vblank_work);
2199
2200                 /* All windows updated. Mask subsequent V_BLANK interrupts */
2201                 if (!tegra_dc_windows_are_dirty(dc)) {
2202                         u32 val;
2203
2204                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2205                         val &= ~V_BLANK_INT;
2206                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2207                 }
2208         }
2209
2210         if (status & FRAME_END_INT) {
2211                 /* Mark the frame_end as complete. */
2212                 if (!completion_done(&dc->frame_end_complete))
2213                         complete(&dc->frame_end_complete);
2214
2215                 tegra_dc_trigger_windows(dc);
2216         }
2217 }
2218 #endif
2219
2220 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2221 {
2222 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2223         struct tegra_dc *dc = ptr;
2224         unsigned long status;
2225         unsigned long underflow_mask;
2226         u32 val;
2227
2228         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2229                 WARN(1, "IRQ when DC not powered!\n");
2230                 tegra_dc_io_start(dc);
2231                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2232                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2233                 tegra_dc_io_end(dc);
2234                 return IRQ_HANDLED;
2235         }
2236
2237         /* clear all status flags except underflow, save those for the worker */
2238         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2239         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2240         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2241         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2242
2243         /*
2244          * Overlays can get thier internal state corrupted during and underflow
2245          * condition.  The only way to fix this state is to reset the DC.
2246          * if we get 4 consecutive frames with underflows, assume we're
2247          * hosed and reset.
2248          */
2249         underflow_mask = status & ALL_UF_INT;
2250
2251         /* Check underflow */
2252         if (underflow_mask) {
2253                 dc->underflow_mask |= underflow_mask;
2254                 schedule_delayed_work(&dc->underflow_work,
2255                         msecs_to_jiffies(1));
2256         }
2257
2258         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2259                 tegra_dc_one_shot_irq(dc, status);
2260         else
2261                 tegra_dc_continuous_irq(dc, status);
2262
2263         return IRQ_HANDLED;
2264 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2265         return IRQ_NONE;
2266 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2267 }
2268
2269 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2270 {
2271         u32 color_control;
2272
2273         switch (dc->out->depth) {
2274         case 3:
2275                 color_control = BASE_COLOR_SIZE111;
2276                 break;
2277
2278         case 6:
2279                 color_control = BASE_COLOR_SIZE222;
2280                 break;
2281
2282         case 8:
2283                 color_control = BASE_COLOR_SIZE332;
2284                 break;
2285
2286         case 9:
2287                 color_control = BASE_COLOR_SIZE333;
2288                 break;
2289
2290         case 12:
2291                 color_control = BASE_COLOR_SIZE444;
2292                 break;
2293
2294         case 15:
2295                 color_control = BASE_COLOR_SIZE555;
2296                 break;
2297
2298         case 16:
2299                 color_control = BASE_COLOR_SIZE565;
2300                 break;
2301
2302         case 18:
2303                 color_control = BASE_COLOR_SIZE666;
2304                 break;
2305
2306         default:
2307                 color_control = BASE_COLOR_SIZE888;
2308                 break;
2309         }
2310
2311         switch (dc->out->dither) {
2312         case TEGRA_DC_DISABLE_DITHER:
2313                 color_control |= DITHER_CONTROL_DISABLE;
2314                 break;
2315         case TEGRA_DC_ORDERED_DITHER:
2316                 color_control |= DITHER_CONTROL_ORDERED;
2317                 break;
2318         case TEGRA_DC_ERRDIFF_DITHER:
2319                 /* The line buffer for error-diffusion dither is limited
2320                  * to 1280 pixels per line. This limits the maximum
2321                  * horizontal active area size to 1280 pixels when error
2322                  * diffusion is enabled.
2323                  */
2324                 BUG_ON(dc->mode.h_active > 1280);
2325                 color_control |= DITHER_CONTROL_ERRDIFF;
2326                 break;
2327         }
2328
2329         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2330 }
2331
2332 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2333 {
2334         u32 syncpt_id;
2335
2336         switch (dc->ndev->id) {
2337         case 0:
2338                 switch (idx) {
2339                 case 0:
2340                         syncpt_id = NVSYNCPT_DISP0_A;
2341                         break;
2342                 case 1:
2343                         syncpt_id = NVSYNCPT_DISP0_B;
2344                         break;
2345                 case 2:
2346                         syncpt_id = NVSYNCPT_DISP0_C;
2347                         break;
2348                 default:
2349                         BUG();
2350                         break;
2351                 }
2352                 break;
2353         case 1:
2354                 switch (idx) {
2355                 case 0:
2356                         syncpt_id = NVSYNCPT_DISP1_A;
2357                         break;
2358                 case 1:
2359                         syncpt_id = NVSYNCPT_DISP1_B;
2360                         break;
2361                 case 2:
2362                         syncpt_id = NVSYNCPT_DISP1_C;
2363                         break;
2364                 default:
2365                         BUG();
2366                         break;
2367                 }
2368                 break;
2369         default:
2370                 BUG();
2371                 break;
2372         }
2373
2374         return syncpt_id;
2375 }
2376
2377 static int tegra_dc_init(struct tegra_dc *dc)
2378 {
2379         int i;
2380
2381         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2382         if (dc->ndev->id == 0) {
2383                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2384                                       TEGRA_MC_PRIO_MED);
2385                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2386                                       TEGRA_MC_PRIO_MED);
2387                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2388                                       TEGRA_MC_PRIO_MED);
2389                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2390                                       TEGRA_MC_PRIO_MED);
2391                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2392                                       TEGRA_MC_PRIO_HIGH);
2393         } else if (dc->ndev->id == 1) {
2394                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2395                                       TEGRA_MC_PRIO_MED);
2396                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2397                                       TEGRA_MC_PRIO_MED);
2398                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2399                                       TEGRA_MC_PRIO_MED);
2400                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2401                                       TEGRA_MC_PRIO_MED);
2402                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2403                                       TEGRA_MC_PRIO_HIGH);
2404         }
2405         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2406                         DC_CMD_CONT_SYNCPT_VSYNC);
2407         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2408         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2409         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2410         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2411
2412         /* enable interrupts for vblank, frame_end and underflows */
2413         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2414                 DC_CMD_INT_ENABLE);
2415         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2416
2417         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2418
2419         tegra_dc_set_color_control(dc);
2420         for (i = 0; i < DC_N_WINDOWS; i++) {
2421                 struct tegra_dc_win *win = &dc->windows[i];
2422                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2423                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2424                 tegra_dc_set_csc(dc, &win->csc);
2425                 tegra_dc_set_lut(dc, win);
2426                 tegra_dc_set_scaling_filter(dc);
2427         }
2428
2429
2430         for (i = 0; i < dc->n_windows; i++) {
2431                 u32 syncpt = get_syncpt(dc, i);
2432
2433                 dc->syncpt[i].id = syncpt;
2434
2435                 dc->syncpt[i].min = dc->syncpt[i].max =
2436                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2437                                         syncpt);
2438         }
2439
2440         print_mode(dc, &dc->mode, __func__);
2441
2442         if (dc->mode.pclk)
2443                 if (tegra_dc_program_mode(dc, &dc->mode))
2444                         return -EINVAL;
2445
2446         /* Initialize SD AFTER the modeset.
2447            nvsd_init handles the sd_settings = NULL case. */
2448         nvsd_init(dc, dc->out->sd_settings);
2449
2450         return 0;
2451 }
2452
2453 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2454 {
2455         int failed_init = 0;
2456
2457         if (dc->out->enable)
2458                 dc->out->enable();
2459
2460         tegra_dc_setup_clk(dc, dc->clk);
2461         clk_enable(dc->clk);
2462
2463         /* do not accept interrupts during initialization */
2464         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2465         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2466
2467         enable_dc_irq(dc->irq);
2468
2469         failed_init = tegra_dc_init(dc);
2470         if (failed_init) {
2471                 _tegra_dc_controller_disable(dc);
2472                 return false;
2473         }
2474
2475         if (dc->out_ops && dc->out_ops->enable)
2476                 dc->out_ops->enable(dc);
2477
2478         if (dc->out->postpoweron)
2479                 dc->out->postpoweron();
2480
2481         /* force a full blending update */
2482         dc->blend.z[0] = -1;
2483
2484         tegra_dc_ext_enable(dc->ext);
2485
2486         return true;
2487 }
2488
2489 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2490 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2491 {
2492         bool ret = true;
2493
2494         if (dc->out->enable)
2495                 dc->out->enable();
2496
2497         tegra_dc_setup_clk(dc, dc->clk);
2498         clk_enable(dc->clk);
2499
2500         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2501                 mutex_lock(&tegra_dcs[1]->lock);
2502                 disable_irq(tegra_dcs[1]->irq);
2503         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2504                 mutex_lock(&tegra_dcs[0]->lock);
2505                 disable_irq(tegra_dcs[0]->irq);
2506         }
2507
2508         msleep(5);
2509         tegra_periph_reset_assert(dc->clk);
2510         msleep(2);
2511 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2512         tegra_periph_reset_deassert(dc->clk);
2513         msleep(1);
2514 #endif
2515
2516         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2517                 enable_dc_irq(tegra_dcs[1]->irq);
2518                 mutex_unlock(&tegra_dcs[1]->lock);
2519         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2520                 enable_dc_irq(tegra_dcs[0]->irq);
2521                 mutex_unlock(&tegra_dcs[0]->lock);
2522         }
2523
2524         enable_dc_irq(dc->irq);
2525
2526         if (tegra_dc_init(dc)) {
2527                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2528                 ret = false;
2529         }
2530
2531         if (dc->out_ops && dc->out_ops->enable)
2532                 dc->out_ops->enable(dc);
2533
2534         if (dc->out->postpoweron)
2535                 dc->out->postpoweron();
2536
2537         /* force a full blending update */
2538         dc->blend.z[0] = -1;
2539
2540         tegra_dc_ext_enable(dc->ext);
2541
2542         if (!ret) {
2543                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2544                 _tegra_dc_controller_disable(dc);
2545         }
2546
2547         return ret;
2548 }
2549 #endif
2550
2551 static bool _tegra_dc_enable(struct tegra_dc *dc)
2552 {
2553         if (dc->mode.pclk == 0)
2554                 return false;
2555
2556         if (!dc->out)
2557                 return false;
2558
2559         tegra_dc_io_start(dc);
2560
2561         return _tegra_dc_controller_enable(dc);
2562 }
2563
2564 void tegra_dc_enable(struct tegra_dc *dc)
2565 {
2566         mutex_lock(&dc->lock);
2567
2568         if (!dc->enabled)
2569                 dc->enabled = _tegra_dc_enable(dc);
2570
2571         mutex_unlock(&dc->lock);
2572 }
2573
2574 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2575 {
2576         unsigned i;
2577
2578         if (dc->out_ops && dc->out_ops->disable)
2579                 dc->out_ops->disable(dc);
2580
2581         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2582         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2583         disable_irq(dc->irq);
2584
2585         tegra_dc_clear_bandwidth(dc);
2586         clk_disable(dc->clk);
2587         tegra_dvfs_set_rate(dc->clk, 0);
2588
2589         if (dc->out && dc->out->disable)
2590                 dc->out->disable();
2591
2592         for (i = 0; i < dc->n_windows; i++) {
2593                 struct tegra_dc_win *w = &dc->windows[i];
2594
2595                 /* reset window bandwidth */
2596                 w->bandwidth = 0;
2597                 w->new_bandwidth = 0;
2598
2599                 /* disable windows */
2600                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2601
2602                 /* flush any pending syncpt waits */
2603                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2604                         dc->syncpt[i].min++;
2605                         nvhost_syncpt_cpu_incr(
2606                                 &nvhost_get_host(dc->ndev)->syncpt,
2607                                 dc->syncpt[i].id);
2608                 }
2609         }
2610 }
2611
2612 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2613 {
2614 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2615         u32 val;
2616         if (dc->enabled)  {
2617                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2618                 if (enable)
2619                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2620                 else
2621                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2622                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2623         }
2624 #endif
2625 }
2626
2627 bool tegra_dc_stats_get(struct tegra_dc *dc)
2628 {
2629 #if 0 /* right now it is always enabled */
2630         u32 val;
2631         bool res;
2632
2633         if (dc->enabled)  {
2634                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2635                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2636         } else {
2637                 res = false;
2638         }
2639
2640         return res;
2641 #endif
2642         return true;
2643 }
2644
2645 /* make the screen blank by disabling all windows */
2646 void tegra_dc_blank(struct tegra_dc *dc)
2647 {
2648         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2649         unsigned i;
2650
2651         for (i = 0; i < DC_N_WINDOWS; i++) {
2652                 dcwins[i] = tegra_dc_get_window(dc, i);
2653                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2654         }
2655
2656         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2657         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2658 }
2659
2660 static void _tegra_dc_disable(struct tegra_dc *dc)
2661 {
2662         _tegra_dc_controller_disable(dc);
2663         tegra_dc_io_end(dc);
2664 }
2665
2666 void tegra_dc_disable(struct tegra_dc *dc)
2667 {
2668         if (dc->overlay)
2669                 tegra_overlay_disable(dc->overlay);
2670
2671         tegra_dc_ext_disable(dc->ext);
2672
2673         /* it's important that new underflow work isn't scheduled before the
2674          * lock is acquired. */
2675         cancel_delayed_work_sync(&dc->underflow_work);
2676         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2677                 mutex_lock(&dc->one_shot_lock);
2678                 cancel_delayed_work_sync(&dc->one_shot_work);
2679         }
2680
2681         mutex_lock(&dc->lock);
2682
2683         if (dc->enabled) {
2684                 dc->enabled = false;
2685
2686                 if (!dc->suspended)
2687                         _tegra_dc_disable(dc);
2688         }
2689
2690 #ifdef CONFIG_SWITCH
2691         switch_set_state(&dc->modeset_switch, 0);
2692 #endif
2693
2694         mutex_unlock(&dc->lock);
2695         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2696                 mutex_unlock(&dc->one_shot_lock);
2697 }
2698
2699 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2700 static void tegra_dc_reset_worker(struct work_struct *work)
2701 {
2702         struct tegra_dc *dc =
2703                 container_of(work, struct tegra_dc, reset_work);
2704
2705         unsigned long val = 0;
2706
2707         mutex_lock(&shared_lock);
2708
2709         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2710
2711         tegra_dc_ext_disable(dc->ext);
2712
2713         mutex_lock(&dc->lock);
2714
2715         if (dc->enabled == false)
2716                 goto unlock;
2717
2718         dc->enabled = false;
2719
2720         /*
2721          * off host read bus
2722          */
2723         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2724         val &= ~(0x00000100);
2725         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2726
2727         /*
2728          * set DC to STOP mode
2729          */
2730         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2731
2732         msleep(10);
2733
2734         _tegra_dc_controller_disable(dc);
2735
2736         /* _tegra_dc_controller_reset_enable deasserts reset */
2737         _tegra_dc_controller_reset_enable(dc);
2738
2739         dc->enabled = true;
2740 unlock:
2741         mutex_unlock(&dc->lock);
2742         mutex_unlock(&shared_lock);
2743 }
2744 #endif
2745
2746 static void tegra_dc_underflow_worker(struct work_struct *work)
2747 {
2748         struct tegra_dc *dc = container_of(
2749                 to_delayed_work(work), struct tegra_dc, underflow_work);
2750
2751         mutex_lock(&dc->lock);
2752         if (dc->enabled) {
2753                 tegra_dc_underflow_handler(dc);
2754         }
2755         mutex_unlock(&dc->lock);
2756 }
2757
2758 #ifdef CONFIG_SWITCH
2759 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2760 {
2761         struct tegra_dc *dc =
2762                 container_of(sdev, struct tegra_dc, modeset_switch);
2763
2764         if (!sdev->state)
2765                 return sprintf(buf, "offline\n");
2766
2767         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2768 }
2769 #endif
2770
2771 static int tegra_dc_probe(struct nvhost_device *ndev)
2772 {
2773         struct tegra_dc *dc;
2774         struct clk *clk;
2775         struct clk *emc_clk;
2776         struct resource *res;
2777         struct resource *base_res;
2778         struct resource *fb_mem = NULL;
2779         int ret = 0;
2780         void __iomem *base;
2781         int irq;
2782         int i;
2783
2784         if (!ndev->dev.platform_data) {
2785                 dev_err(&ndev->dev, "no platform data\n");
2786                 return -ENOENT;
2787         }
2788
2789         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2790         if (!dc) {
2791                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2792                 return -ENOMEM;
2793         }
2794
2795         irq = nvhost_get_irq_byname(ndev, "irq");
2796         if (irq <= 0) {
2797                 dev_err(&ndev->dev, "no irq\n");
2798                 ret = -ENOENT;
2799                 goto err_free;
2800         }
2801
2802         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2803         if (!res) {
2804                 dev_err(&ndev->dev, "no mem resource\n");
2805                 ret = -ENOENT;
2806                 goto err_free;
2807         }
2808
2809         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2810         if (!base_res) {
2811                 dev_err(&ndev->dev, "request_mem_region failed\n");
2812                 ret = -EBUSY;
2813                 goto err_free;
2814         }
2815
2816         base = ioremap(res->start, resource_size(res));
2817         if (!base) {
2818                 dev_err(&ndev->dev, "registers can't be mapped\n");
2819                 ret = -EBUSY;
2820                 goto err_release_resource_reg;
2821         }
2822
2823         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2824
2825         clk = clk_get(&ndev->dev, NULL);
2826         if (IS_ERR_OR_NULL(clk)) {
2827                 dev_err(&ndev->dev, "can't get clock\n");
2828                 ret = -ENOENT;
2829                 goto err_iounmap_reg;
2830         }
2831
2832         emc_clk = clk_get(&ndev->dev, "emc");
2833         if (IS_ERR_OR_NULL(emc_clk)) {
2834                 dev_err(&ndev->dev, "can't get emc clock\n");
2835                 ret = -ENOENT;
2836                 goto err_put_clk;
2837         }
2838
2839         dc->clk = clk;
2840         dc->emc_clk = emc_clk;
2841         dc->shift_clk_div = 1;
2842         /* Initialize one shot work delay, it will be assigned by dsi
2843          * according to refresh rate later. */
2844         dc->one_shot_delay_ms = 40;
2845
2846         dc->base_res = base_res;
2847         dc->base = base;
2848         dc->irq = irq;
2849         dc->ndev = ndev;
2850         dc->pdata = ndev->dev.platform_data;
2851
2852         /*
2853          * The emc is a shared clock, it will be set based on
2854          * the requirements for each user on the bus.
2855          */
2856         dc->emc_clk_rate = 0;
2857
2858         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2859                 dc->enabled = true;
2860
2861         mutex_init(&dc->lock);
2862         mutex_init(&dc->one_shot_lock);
2863         init_completion(&dc->frame_end_complete);
2864         init_waitqueue_head(&dc->wq);
2865 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2866         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2867 #endif
2868         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2869         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2870         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2871
2872         tegra_dc_init_lut_defaults(&dc->fb_lut);
2873
2874         dc->n_windows = DC_N_WINDOWS;
2875         for (i = 0; i < dc->n_windows; i++) {
2876                 struct tegra_dc_win *win = &dc->windows[i];
2877                 win->idx = i;
2878                 win->dc = dc;
2879                 tegra_dc_init_csc_defaults(&win->csc);
2880                 tegra_dc_init_lut_defaults(&win->lut);
2881         }
2882
2883         ret = tegra_dc_set(dc, ndev->id);
2884         if (ret < 0) {
2885                 dev_err(&ndev->dev, "can't add dc\n");
2886                 goto err_free_irq;
2887         }
2888
2889         nvhost_set_drvdata(ndev, dc);
2890
2891 #ifdef CONFIG_SWITCH
2892         dc->modeset_switch.name = dev_name(&ndev->dev);
2893         dc->modeset_switch.state = 0;
2894         dc->modeset_switch.print_state = switch_modeset_print_mode;
2895         switch_dev_register(&dc->modeset_switch);
2896 #endif
2897
2898         if (dc->pdata->default_out)
2899                 tegra_dc_set_out(dc, dc->pdata->default_out);
2900         else
2901                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2902
2903         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2904                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2905
2906         dc->ext = tegra_dc_ext_register(ndev, dc);
2907         if (IS_ERR_OR_NULL(dc->ext)) {
2908                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2909                 dc->ext = NULL;
2910         }
2911
2912         /* interrupt handler must be registered before tegra_fb_register() */
2913         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2914                         dev_name(&ndev->dev), dc)) {
2915                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2916                 ret = -EBUSY;
2917                 goto err_put_emc_clk;
2918         }
2919
2920         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2921         disable_dc_irq(dc->irq);
2922
2923         mutex_lock(&dc->lock);
2924         if (dc->enabled)
2925                 _tegra_dc_enable(dc);
2926         mutex_unlock(&dc->lock);
2927
2928         tegra_dc_create_debugfs(dc);
2929
2930         dev_info(&ndev->dev, "probed\n");
2931
2932         if (dc->pdata->fb) {
2933                 if (dc->pdata->fb->bits_per_pixel == -1) {
2934                         unsigned long fmt;
2935                         tegra_dc_writel(dc,
2936                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2937                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2938
2939                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2940                         dc->pdata->fb->bits_per_pixel =
2941                                 tegra_dc_fmt_bpp(fmt);
2942                 }
2943
2944                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2945                 if (IS_ERR_OR_NULL(dc->fb))
2946                         dc->fb = NULL;
2947         }
2948
2949         if (dc->fb) {
2950                 dc->overlay = tegra_overlay_register(ndev, dc);
2951                 if (IS_ERR_OR_NULL(dc->overlay))
2952                         dc->overlay = NULL;
2953         }
2954
2955         if (dc->out && dc->out->hotplug_init)
2956                 dc->out->hotplug_init();
2957
2958         if (dc->out_ops && dc->out_ops->detect)
2959                 dc->out_ops->detect(dc);
2960         else
2961                 dc->connected = true;
2962
2963         tegra_dc_create_sysfs(&dc->ndev->dev);
2964
2965         return 0;
2966
2967 err_free_irq:
2968         free_irq(irq, dc);
2969 err_put_emc_clk:
2970         clk_put(emc_clk);
2971 err_put_clk:
2972         clk_put(clk);
2973 err_iounmap_reg:
2974         iounmap(base);
2975         if (fb_mem)
2976                 release_resource(fb_mem);
2977 err_release_resource_reg:
2978         release_resource(base_res);
2979 err_free:
2980         kfree(dc);
2981
2982         return ret;
2983 }
2984
2985 static int tegra_dc_remove(struct nvhost_device *ndev)
2986 {
2987         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2988
2989         tegra_dc_remove_sysfs(&dc->ndev->dev);
2990         tegra_dc_remove_debugfs(dc);
2991
2992         if (dc->overlay) {
2993                 tegra_overlay_unregister(dc->overlay);
2994         }
2995
2996         if (dc->fb) {
2997                 tegra_fb_unregister(dc->fb);
2998                 if (dc->fb_mem)
2999                         release_resource(dc->fb_mem);
3000         }
3001
3002         tegra_dc_ext_disable(dc->ext);
3003
3004         if (dc->ext)
3005                 tegra_dc_ext_unregister(dc->ext);
3006
3007         if (dc->enabled)
3008                 _tegra_dc_disable(dc);
3009
3010 #ifdef CONFIG_SWITCH
3011         switch_dev_unregister(&dc->modeset_switch);
3012 #endif
3013         free_irq(dc->irq, dc);
3014         clk_put(dc->emc_clk);
3015         clk_put(dc->clk);
3016         iounmap(dc->base);
3017         if (dc->fb_mem)
3018                 release_resource(dc->base_res);
3019         kfree(dc);
3020         tegra_dc_set(NULL, ndev->id);
3021         return 0;
3022 }
3023
3024 #ifdef CONFIG_PM
3025 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3026 {
3027         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3028
3029         dev_info(&ndev->dev, "suspend\n");
3030
3031         if (dc->overlay)
3032                 tegra_overlay_disable(dc->overlay);
3033
3034         tegra_dc_ext_disable(dc->ext);
3035
3036         mutex_lock(&dc->lock);
3037
3038         if (dc->out_ops && dc->out_ops->suspend)
3039                 dc->out_ops->suspend(dc);
3040
3041         if (dc->enabled) {
3042                 _tegra_dc_disable(dc);
3043
3044                 dc->suspended = true;
3045         }
3046
3047         if (dc->out && dc->out->postsuspend) {
3048                 dc->out->postsuspend();
3049                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3050                         /*
3051                          * avoid resume event due to voltage falling
3052                          */
3053                         msleep(100);
3054         }
3055
3056         mutex_unlock(&dc->lock);
3057
3058         return 0;
3059 }
3060
3061 static int tegra_dc_resume(struct nvhost_device *ndev)
3062 {
3063         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3064
3065         dev_info(&ndev->dev, "resume\n");
3066
3067         mutex_lock(&dc->lock);
3068         dc->suspended = false;
3069
3070         if (dc->enabled)
3071                 _tegra_dc_enable(dc);
3072
3073         if (dc->out && dc->out->hotplug_init)
3074                 dc->out->hotplug_init();
3075
3076         if (dc->out_ops && dc->out_ops->resume)
3077                 dc->out_ops->resume(dc);
3078         mutex_unlock(&dc->lock);
3079
3080         return 0;
3081 }
3082
3083 #endif /* CONFIG_PM */
3084
3085 extern int suspend_set(const char *val, struct kernel_param *kp)
3086 {
3087         if (!strcmp(val, "dump"))
3088                 dump_regs(tegra_dcs[0]);
3089 #ifdef CONFIG_PM
3090         else if (!strcmp(val, "suspend"))
3091                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3092         else if (!strcmp(val, "resume"))
3093                 tegra_dc_resume(tegra_dcs[0]->ndev);
3094 #endif
3095
3096         return 0;
3097 }
3098
3099 extern int suspend_get(char *buffer, struct kernel_param *kp)
3100 {
3101         return 0;
3102 }
3103
3104 int suspend;
3105
3106 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3107
3108 struct nvhost_driver tegra_dc_driver = {
3109         .driver = {
3110                 .name = "tegradc",
3111                 .owner = THIS_MODULE,
3112         },
3113         .probe = tegra_dc_probe,
3114         .remove = tegra_dc_remove,
3115 #ifdef CONFIG_PM
3116         .suspend = tegra_dc_suspend,
3117         .resume = tegra_dc_resume,
3118 #endif
3119 };
3120
3121 static int __init tegra_dc_module_init(void)
3122 {
3123         int ret = tegra_dc_ext_module_init();
3124         if (ret)
3125                 return ret;
3126         return nvhost_driver_register(&tegra_dc_driver);
3127 }
3128
3129 static void __exit tegra_dc_module_exit(void)
3130 {
3131         nvhost_driver_unregister(&tegra_dc_driver);
3132         tegra_dc_ext_module_exit();
3133 }
3134
3135 module_exit(tegra_dc_module_exit);
3136 module_init(tegra_dc_module_init);