video: backlight: use gpio request and free apis for backlight pin
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
62         .refresh = 60,
63         .xres = 640,
64         .yres = 480,
65         .pixclock = KHZ2PICOS(25200),
66         .hsync_len = 96,        /* h_sync_width */
67         .vsync_len = 2,         /* v_sync_width */
68         .left_margin = 48,      /* h_back_porch */
69         .upper_margin = 33,     /* v_back_porch */
70         .right_margin = 16,     /* h_front_porch */
71         .lower_margin = 10,     /* v_front_porch */
72         .vmode = 0,
73         .sync = 0,
74 };
75
76 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
77
78 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
79
80 DEFINE_MUTEX(tegra_dc_lock);
81 DEFINE_MUTEX(shared_lock);
82
83 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
84 {
85         if (!tegra_is_clk_enabled(dc->clk)) {
86                 clk_enable(dc->clk);
87                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
88         }
89 }
90
91 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
92 {
93         if (tegra_is_clk_enabled(dc->clk)) {
94                 clk_disable(dc->clk);
95                 tegra_dvfs_set_rate(dc->clk, 0);
96         }
97 }
98
99 #define DUMP_REG(a) do {                        \
100         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
101                  #a, a, tegra_dc_readl(dc, a));               \
102         print(data, buff);                                    \
103         } while (0)
104
105 #define print_underflow_info(dc) do {                 \
106         trace_printk("%s:Underflow stats: underflows : %llu, "      \
107                         "undeflows_a : %llu, "                          \
108                         "underflows_b : %llu, "                         \
109                         "underflows_c : %llu\n",                        \
110                         dc->ndev->name,                                 \
111                         dc->stats.underflows,                           \
112                         dc->stats.underflows_a, dc->stats.underflows_b, \
113                         dc->stats.underflows_c);                        \
114         } while (0)
115
116 static void _dump_regs(struct tegra_dc *dc, void *data,
117                        void (* print)(void *data, const char *str))
118 {
119         int i;
120         char buff[256];
121
122         tegra_dc_io_start(dc);
123         tegra_dc_clk_enable(dc);
124
125         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
126         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
127         DUMP_REG(DC_CMD_SIGNAL_RAISE);
128         DUMP_REG(DC_CMD_INT_STATUS);
129         DUMP_REG(DC_CMD_INT_MASK);
130         DUMP_REG(DC_CMD_INT_ENABLE);
131         DUMP_REG(DC_CMD_INT_TYPE);
132         DUMP_REG(DC_CMD_INT_POLARITY);
133         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
134         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
135         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
136         DUMP_REG(DC_CMD_STATE_ACCESS);
137         DUMP_REG(DC_CMD_STATE_CONTROL);
138         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
139         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
140
141         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
142         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
143         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
144         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
145         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
146         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
147         DUMP_REG(DC_DISP_REF_TO_SYNC);
148         DUMP_REG(DC_DISP_SYNC_WIDTH);
149         DUMP_REG(DC_DISP_BACK_PORCH);
150         DUMP_REG(DC_DISP_DISP_ACTIVE);
151         DUMP_REG(DC_DISP_FRONT_PORCH);
152         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
153         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
154         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
155         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
156         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
157         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
158         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
159         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
160         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
161         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
162         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
163         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
164         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
165         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
166         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
167         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
168         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
169         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
170         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
171         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
172         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
173         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
174         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
175         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
176         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
177         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
178         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
179         DUMP_REG(DC_DISP_M0_CONTROL);
180         DUMP_REG(DC_DISP_M1_CONTROL);
181         DUMP_REG(DC_DISP_DI_CONTROL);
182         DUMP_REG(DC_DISP_PP_CONTROL);
183         DUMP_REG(DC_DISP_PP_SELECT_A);
184         DUMP_REG(DC_DISP_PP_SELECT_B);
185         DUMP_REG(DC_DISP_PP_SELECT_C);
186         DUMP_REG(DC_DISP_PP_SELECT_D);
187         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
188         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
189         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
190         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
191         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
192         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
193         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
194         DUMP_REG(DC_DISP_BORDER_COLOR);
195         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
196         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
197         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
198         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
199         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
200         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
201         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
202         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
203         DUMP_REG(DC_DISP_CURSOR_POSITION);
204         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
205         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
206         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
207         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
208         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
209         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
210         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
211         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
212         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
213         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
214         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
215         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
216         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
217
218
219         for (i = 0; i < 3; i++) {
220                 print(data, "\n");
221                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
222                 print(data, buff);
223
224                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
225                                 DC_CMD_DISPLAY_WINDOW_HEADER);
226                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
227                 DUMP_REG(DC_WIN_WIN_OPTIONS);
228                 DUMP_REG(DC_WIN_BYTE_SWAP);
229                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
230                 DUMP_REG(DC_WIN_COLOR_DEPTH);
231                 DUMP_REG(DC_WIN_POSITION);
232                 DUMP_REG(DC_WIN_SIZE);
233                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
234                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
235                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
236                 DUMP_REG(DC_WIN_DDA_INCREMENT);
237                 DUMP_REG(DC_WIN_LINE_STRIDE);
238                 DUMP_REG(DC_WIN_BUF_STRIDE);
239                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
240                 DUMP_REG(DC_WIN_BLEND_NOKEY);
241                 DUMP_REG(DC_WIN_BLEND_1WIN);
242                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
243                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
244                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
245                 DUMP_REG(DC_WINBUF_START_ADDR);
246                 DUMP_REG(DC_WINBUF_START_ADDR_U);
247                 DUMP_REG(DC_WINBUF_START_ADDR_V);
248                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
249                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
250                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
251                 DUMP_REG(DC_WIN_CSC_YOF);
252                 DUMP_REG(DC_WIN_CSC_KYRGB);
253                 DUMP_REG(DC_WIN_CSC_KUR);
254                 DUMP_REG(DC_WIN_CSC_KVR);
255                 DUMP_REG(DC_WIN_CSC_KUG);
256                 DUMP_REG(DC_WIN_CSC_KVG);
257                 DUMP_REG(DC_WIN_CSC_KUB);
258                 DUMP_REG(DC_WIN_CSC_KVB);
259         }
260
261         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
262         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
263         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
264         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
265         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
266         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
267         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
268         DUMP_REG(DC_DISP_M1_CONTROL);
269         DUMP_REG(DC_COM_PM1_CONTROL);
270         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
271         DUMP_REG(DC_DISP_SD_CONTROL);
272
273         tegra_dc_clk_disable(dc);
274         tegra_dc_io_end(dc);
275 }
276
277 #undef DUMP_REG
278
279 #ifdef DEBUG
280 static void dump_regs_print(void *data, const char *str)
281 {
282         struct tegra_dc *dc = data;
283         dev_dbg(&dc->ndev->dev, "%s", str);
284 }
285
286 static void dump_regs(struct tegra_dc *dc)
287 {
288         _dump_regs(dc, dc, dump_regs_print);
289 }
290 #else /* !DEBUG */
291
292 static void dump_regs(struct tegra_dc *dc) {}
293
294 #endif /* DEBUG */
295
296 #ifdef CONFIG_DEBUG_FS
297
298 static void dbg_regs_print(void *data, const char *str)
299 {
300         struct seq_file *s = data;
301
302         seq_printf(s, "%s", str);
303 }
304
305 #undef DUMP_REG
306
307 static int dbg_dc_show(struct seq_file *s, void *unused)
308 {
309         struct tegra_dc *dc = s->private;
310
311         _dump_regs(dc, s, dbg_regs_print);
312
313         return 0;
314 }
315
316
317 static int dbg_dc_open(struct inode *inode, struct file *file)
318 {
319         return single_open(file, dbg_dc_show, inode->i_private);
320 }
321
322 static const struct file_operations regs_fops = {
323         .open           = dbg_dc_open,
324         .read           = seq_read,
325         .llseek         = seq_lseek,
326         .release        = single_release,
327 };
328
329 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
330 {
331         struct tegra_dc *dc = s->private;
332         struct tegra_dc_mode *m;
333
334         mutex_lock(&dc->lock);
335         m = &dc->mode;
336         seq_printf(s,
337                 "pclk: %d\n"
338                 "h_ref_to_sync: %d\n"
339                 "v_ref_to_sync: %d\n"
340                 "h_sync_width: %d\n"
341                 "v_sync_width: %d\n"
342                 "h_back_porch: %d\n"
343                 "v_back_porch: %d\n"
344                 "h_active: %d\n"
345                 "v_active: %d\n"
346                 "h_front_porch: %d\n"
347                 "v_front_porch: %d\n"
348                 "stereo_mode: %d\n",
349                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
350                 m->h_sync_width, m->v_sync_width,
351                 m->h_back_porch, m->v_back_porch,
352                 m->h_active, m->v_active,
353                 m->h_front_porch, m->v_front_porch,
354                 m->stereo_mode);
355         mutex_unlock(&dc->lock);
356         return 0;
357 }
358
359 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
360 {
361         return single_open(file, dbg_dc_mode_show, inode->i_private);
362 }
363
364 static const struct file_operations mode_fops = {
365         .open           = dbg_dc_mode_open,
366         .read           = seq_read,
367         .llseek         = seq_lseek,
368         .release        = single_release,
369 };
370
371 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
372 {
373         struct tegra_dc *dc = s->private;
374
375         mutex_lock(&dc->lock);
376         seq_printf(s,
377                 "underflows: %llu\n"
378                 "underflows_a: %llu\n"
379                 "underflows_b: %llu\n"
380                 "underflows_c: %llu\n",
381                 dc->stats.underflows,
382                 dc->stats.underflows_a,
383                 dc->stats.underflows_b,
384                 dc->stats.underflows_c);
385         mutex_unlock(&dc->lock);
386
387         return 0;
388 }
389
390 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
391 {
392         return single_open(file, dbg_dc_stats_show, inode->i_private);
393 }
394
395 static const struct file_operations stats_fops = {
396         .open           = dbg_dc_stats_open,
397         .read           = seq_read,
398         .llseek         = seq_lseek,
399         .release        = single_release,
400 };
401
402 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
403 {
404         if (dc->debugdir)
405                 debugfs_remove_recursive(dc->debugdir);
406         dc->debugdir = NULL;
407 }
408
409 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
410 {
411         struct dentry *retval;
412
413         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
414         if (!dc->debugdir)
415                 goto remove_out;
416
417         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
418                 &regs_fops);
419         if (!retval)
420                 goto remove_out;
421
422         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
423                 &mode_fops);
424         if (!retval)
425                 goto remove_out;
426
427         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
428                 &stats_fops);
429         if (!retval)
430                 goto remove_out;
431
432         return;
433 remove_out:
434         dev_err(&dc->ndev->dev, "could not create debugfs\n");
435         tegra_dc_remove_debugfs(dc);
436 }
437
438 #else /* !CONFIG_DEBUGFS */
439 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
440 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
441 #endif /* CONFIG_DEBUGFS */
442
443 static int tegra_dc_set(struct tegra_dc *dc, int index)
444 {
445         int ret = 0;
446
447         mutex_lock(&tegra_dc_lock);
448         if (index >= TEGRA_MAX_DC) {
449                 ret = -EINVAL;
450                 goto out;
451         }
452
453         if (dc != NULL && tegra_dcs[index] != NULL) {
454                 ret = -EBUSY;
455                 goto out;
456         }
457
458         tegra_dcs[index] = dc;
459
460 out:
461         mutex_unlock(&tegra_dc_lock);
462
463         return ret;
464 }
465
466 unsigned int tegra_dc_has_multiple_dc(void)
467 {
468         unsigned int idx;
469         unsigned int cnt = 0;
470         struct tegra_dc *dc;
471
472         mutex_lock(&tegra_dc_lock);
473         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
474                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
475         mutex_unlock(&tegra_dc_lock);
476
477         return (cnt > 1);
478 }
479
480 /* get the stride size of a window.
481  * return: stride size in bytes for window win. or 0 if unavailble. */
482 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
483 {
484         u32 stride;
485
486         if (!dc->enabled)
487                 return 0;
488         BUG_ON(win > DC_N_WINDOWS);
489         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
490                 DC_CMD_DISPLAY_WINDOW_HEADER);
491         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
492         return GET_LINE_STRIDE(stride);
493 }
494 EXPORT_SYMBOL(tegra_dc_get_stride);
495
496 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
497 {
498         if (idx < TEGRA_MAX_DC)
499                 return tegra_dcs[idx];
500         else
501                 return NULL;
502 }
503 EXPORT_SYMBOL(tegra_dc_get_dc);
504
505 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
506 {
507         if (win >= dc->n_windows)
508                 return NULL;
509
510         return &dc->windows[win];
511 }
512 EXPORT_SYMBOL(tegra_dc_get_window);
513
514 bool tegra_dc_get_connected(struct tegra_dc *dc)
515 {
516         return dc->connected;
517 }
518 EXPORT_SYMBOL(tegra_dc_get_connected);
519
520 bool tegra_dc_hpd(struct tegra_dc *dc)
521 {
522         int sense;
523         int level;
524
525         level = gpio_get_value(dc->out->hotplug_gpio);
526
527         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
528
529         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
530                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
531 }
532 EXPORT_SYMBOL(tegra_dc_hpd);
533
534 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
535 {
536         unsigned i;
537         unsigned v0 = 128;
538         unsigned v1 = 0;
539         /* linear horizontal and vertical filters */
540         for (i = 0; i < 16; i++) {
541                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
542                                 DC_WIN_H_FILTER_P(i));
543
544                 tegra_dc_writel(dc, v0,
545                                 DC_WIN_V_FILTER_P(i));
546                 v0 -= 8;
547                 v1 += 8;
548         }
549 }
550
551 void tegra_dc_host_suspend(struct tegra_dc *dc)
552 {
553         tegra_dsi_host_suspend(dc);
554         tegra_dc_clk_disable(dc);
555 }
556
557 void tegra_dc_host_resume(struct tegra_dc *dc) {
558         tegra_dc_clk_enable(dc);
559         tegra_dsi_host_resume(dc);
560 }
561
562 static inline void disable_dc_irq(unsigned int irq)
563 {
564         disable_irq(irq);
565 }
566
567 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
568 {
569         return dc->syncpt[i].id;
570 }
571 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
572
573 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
574 {
575         u32 max;
576
577         mutex_lock(&dc->lock);
578         max = nvhost_syncpt_incr_max_ext(dc->ndev,
579                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
580         dc->syncpt[i].max = max;
581         mutex_unlock(&dc->lock);
582
583         return max;
584 }
585
586 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
587 {
588         mutex_lock(&dc->lock);
589         if ( dc->enabled )
590                 while (dc->syncpt[i].min < val) {
591                         dc->syncpt[i].min++;
592                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
593                 }
594         mutex_unlock(&dc->lock);
595 }
596
597 void
598 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
599 {
600         unsigned int ctrl;
601         unsigned long out_sel;
602         unsigned long cmd_state;
603
604         mutex_lock(&dc->lock);
605         if (!dc->enabled) {
606                 mutex_unlock(&dc->lock);
607                 return;
608         }
609
610         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
611                 tegra_dc_host_resume(dc);
612
613         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
614                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
615                 cfg->clk_select);
616
617         /* The new value should be effected immediately */
618         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
619         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
620
621         switch (cfg->which_pwm) {
622         case TEGRA_PWM_PM0:
623                 /* Select the LM0 on PM0 */
624                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
625                 out_sel &= ~(7 << 0);
626                 out_sel |= (3 << 0);
627                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
628                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
629                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
630                 break;
631         case TEGRA_PWM_PM1:
632                 /* Select the LM1 on PM1 */
633                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
634                 out_sel &= ~(7 << 4);
635                 out_sel |= (3 << 4);
636                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
637                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
638                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
639                 break;
640         default:
641                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
642                 break;
643         }
644         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
645         mutex_unlock(&dc->lock);
646 }
647 EXPORT_SYMBOL(tegra_dc_config_pwm);
648
649 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
650                                 const struct tegra_dc_out_pin *pins,
651                                 const unsigned int n_pins)
652 {
653         unsigned int i;
654
655         int name;
656         int pol;
657
658         u32 pol1, pol3;
659
660         u32 set1, unset1;
661         u32 set3, unset3;
662
663         set1 = set3 = unset1 = unset3 = 0;
664
665         for (i = 0; i < n_pins; i++) {
666                 name = (pins + i)->name;
667                 pol  = (pins + i)->pol;
668
669                 /* set polarity by name */
670                 switch (name) {
671                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
672                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
673                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
674                         else
675                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
676                         break;
677                 case TEGRA_DC_OUT_PIN_H_SYNC:
678                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
679                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
680                         else
681                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
682                         break;
683                 case TEGRA_DC_OUT_PIN_V_SYNC:
684                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
685                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
686                         else
687                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
688                         break;
689                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
690                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
691                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
692                         else
693                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
694                         break;
695                 default:
696                         printk("Invalid argument in function %s\n",
697                                __FUNCTION__);
698                         break;
699                 }
700         }
701
702         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
703         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
704
705         pol1 |= set1;
706         pol1 &= ~unset1;
707
708         pol3 |= set3;
709         pol3 &= ~unset3;
710
711         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
712         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
713 }
714
715 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
716 {
717         dc->out = out;
718
719         if (out->n_modes > 0)
720                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
721
722         switch (out->type) {
723         case TEGRA_DC_OUT_RGB:
724                 dc->out_ops = &tegra_dc_rgb_ops;
725                 break;
726
727         case TEGRA_DC_OUT_HDMI:
728                 dc->out_ops = &tegra_dc_hdmi_ops;
729                 break;
730
731         case TEGRA_DC_OUT_DSI:
732                 dc->out_ops = &tegra_dc_dsi_ops;
733                 break;
734
735         default:
736                 dc->out_ops = NULL;
737                 break;
738         }
739
740         if (dc->out_ops && dc->out_ops->init)
741                 dc->out_ops->init(dc);
742
743 }
744
745 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
746 {
747         if (dc->out)
748                 return dc->out->height;
749         else
750                 return 0;
751 }
752 EXPORT_SYMBOL(tegra_dc_get_out_height);
753
754 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
755 {
756         if (dc->out)
757                 return dc->out->width;
758         else
759                 return 0;
760 }
761 EXPORT_SYMBOL(tegra_dc_get_out_width);
762
763 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
764 {
765         if (dc->out && dc->out->max_pixclock)
766                 return dc->out->max_pixclock;
767         else
768                 return 0;
769 }
770 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
771
772 void tegra_dc_enable_crc(struct tegra_dc *dc)
773 {
774         u32 val;
775         tegra_dc_io_start(dc);
776
777         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
778                 CRC_ENABLE_ENABLE;
779         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
780         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
781         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
782 }
783
784 void tegra_dc_disable_crc(struct tegra_dc *dc)
785 {
786         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
787         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
788         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
789
790         tegra_dc_io_end(dc);
791 }
792
793 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
794 {
795         int crc = 0;
796
797         if (!dc) {
798                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
799                 goto crc_error;
800         }
801
802         /* TODO: Replace mdelay with code to sync VBlANK, since
803          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
804         mdelay(TEGRA_CRC_LATCHED_DELAY);
805
806         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
807 crc_error:
808         return crc;
809 }
810
811 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
812 {
813 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
814         u32 val;
815
816         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
817         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
818             return true;
819 #endif
820         return false;
821 }
822
823 static inline void enable_dc_irq(unsigned int irq)
824 {
825 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
826         enable_irq(irq);
827 #else
828         /* Always disable DC interrupts on FPGA. */
829         disable_irq(irq);
830 #endif
831 }
832
833 static void tegra_dc_vblank(struct work_struct *work)
834 {
835         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
836         bool nvsd_updated = false;
837
838         mutex_lock(&dc->lock);
839
840         if (!dc->enabled) {
841                 mutex_unlock(&dc->lock);
842                 return;
843         }
844
845         /* use the new frame's bandwidth setting instead of max(current, new),
846          * skip this if we're using tegra_dc_one_shot_worker() */
847         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
848                 tegra_dc_program_bandwidth(dc, true);
849
850         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
851         if (!tegra_dc_windows_are_dirty(dc))
852                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
853
854         /* Update the SD brightness */
855         if (dc->enabled && dc->out->sd_settings) {
856                 nvsd_updated = nvsd_update_brightness(dc);
857                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
858                  * V_BLANK_NVSD bit of vblank ref-count. */
859                 if (nvsd_updated) {
860                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
861                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
862                 } else {
863                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
864                 }
865         }
866
867         /* Mask vblank interrupt if ref-count is zero. */
868         if (!dc->vblank_ref_count)
869                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
870
871         mutex_unlock(&dc->lock);
872
873         /* Do the actual brightness update outside of the mutex */
874         if (nvsd_updated && dc->out->sd_settings &&
875             dc->out->sd_settings->bl_device) {
876
877                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
878                 struct backlight_device *bl = platform_get_drvdata(pdev);
879                 if (bl)
880                         backlight_update_status(bl);
881         }
882 }
883
884 static void tegra_dc_one_shot_worker(struct work_struct *work)
885 {
886         struct tegra_dc *dc = container_of(
887                 to_delayed_work(work), struct tegra_dc, one_shot_work);
888         mutex_lock(&dc->lock);
889
890         /* memory client has gone idle */
891         tegra_dc_clear_bandwidth(dc);
892
893         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
894                 tegra_dc_host_suspend(dc);
895
896         mutex_unlock(&dc->lock);
897 }
898
899 /* return an arbitrarily large number if count overflow occurs.
900  * make it a nice base-10 number to show up in stats output */
901 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
902 {
903         unsigned count = tegra_dc_readl(dc, reg);
904         tegra_dc_writel(dc, 0, reg);
905         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
906 }
907
908 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
909 {
910         u32 val;
911         int i;
912
913         dc->stats.underflows++;
914         if (dc->underflow_mask & WIN_A_UF_INT) {
915                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
916                         DC_WINBUF_AD_UFLOW_STATUS);
917                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
918         }
919         if (dc->underflow_mask & WIN_B_UF_INT) {
920                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
921                         DC_WINBUF_BD_UFLOW_STATUS);
922                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
923         }
924         if (dc->underflow_mask & WIN_C_UF_INT) {
925                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
926                         DC_WINBUF_CD_UFLOW_STATUS);
927                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
928         }
929
930         /* Check for any underflow reset conditions */
931         for (i = 0; i < DC_N_WINDOWS; i++) {
932                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
933                         dc->windows[i].underflows++;
934
935 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
936                         if (dc->windows[i].underflows > 4) {
937                                 schedule_work(&dc->reset_work);
938                                 /* reset counter */
939                                 dc->windows[i].underflows = 0;
940                                 trace_printk("%s:Reset work scheduled for "
941                                                 "window %c\n",
942                                                 dc->ndev->name, (65 + i));
943                         }
944 #endif
945 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
946                         if (dc->windows[i].underflows > 4) {
947                                 printk("%s:dc in underflow state."
948                                         " enable UF_LINE_FLUSH to clear up\n",
949                                         __func__);
950                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
951                                                 DC_DISP_DISP_MISC_CONTROL);
952                                 tegra_dc_writel(dc, GENERAL_UPDATE,
953                                                 DC_CMD_STATE_CONTROL);
954                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
955                                                 DC_CMD_STATE_CONTROL);
956
957                                 tegra_dc_writel(dc, 0,
958                                                 DC_DISP_DISP_MISC_CONTROL);
959                                 tegra_dc_writel(dc, GENERAL_UPDATE,
960                                                 DC_CMD_STATE_CONTROL);
961                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
962                                                 DC_CMD_STATE_CONTROL);
963                         }
964 #endif
965                 } else {
966                         dc->windows[i].underflows = 0;
967                 }
968         }
969
970         /* Clear the underflow mask now that we've checked it. */
971         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
972         dc->underflow_mask = 0;
973         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
974         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
975         print_underflow_info(dc);
976 }
977
978 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
979 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
980 {
981         if (status & V_BLANK_INT) {
982                 /* Sync up windows. */
983                 tegra_dc_trigger_windows(dc);
984
985                 /* Schedule any additional bottom-half vblank actvities. */
986                 schedule_work(&dc->vblank_work);
987         }
988
989         if (status & FRAME_END_INT) {
990                 /* Mark the frame_end as complete. */
991                 if (!completion_done(&dc->frame_end_complete))
992                         complete(&dc->frame_end_complete);
993         }
994 }
995
996 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
997 {
998         /* Schedule any additional bottom-half vblank actvities. */
999         if (status & V_BLANK_INT)
1000                 schedule_work(&dc->vblank_work);
1001
1002         if (status & FRAME_END_INT) {
1003                 /* Mark the frame_end as complete. */
1004                 if (!completion_done(&dc->frame_end_complete))
1005                         complete(&dc->frame_end_complete);
1006
1007                 tegra_dc_trigger_windows(dc);
1008         }
1009 }
1010 #endif
1011
1012 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1013 {
1014 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1015         struct tegra_dc *dc = ptr;
1016         unsigned long status;
1017         unsigned long underflow_mask;
1018         u32 val;
1019
1020         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1021                 WARN(1, "IRQ when DC not powered!\n");
1022                 tegra_dc_io_start(dc);
1023                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1024                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1025                 tegra_dc_io_end(dc);
1026                 return IRQ_HANDLED;
1027         }
1028
1029         /* clear all status flags except underflow, save those for the worker */
1030         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1031         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1032         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1033         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1034
1035         /*
1036          * Overlays can get thier internal state corrupted during and underflow
1037          * condition.  The only way to fix this state is to reset the DC.
1038          * if we get 4 consecutive frames with underflows, assume we're
1039          * hosed and reset.
1040          */
1041         underflow_mask = status & ALL_UF_INT;
1042
1043         /* Check underflow */
1044         if (underflow_mask) {
1045                 dc->underflow_mask |= underflow_mask;
1046                 schedule_delayed_work(&dc->underflow_work,
1047                         msecs_to_jiffies(1));
1048         }
1049
1050         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1051                 tegra_dc_one_shot_irq(dc, status);
1052         else
1053                 tegra_dc_continuous_irq(dc, status);
1054
1055         return IRQ_HANDLED;
1056 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1057         return IRQ_NONE;
1058 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1059 }
1060
1061 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1062 {
1063         u32 color_control;
1064
1065         switch (dc->out->depth) {
1066         case 3:
1067                 color_control = BASE_COLOR_SIZE111;
1068                 break;
1069
1070         case 6:
1071                 color_control = BASE_COLOR_SIZE222;
1072                 break;
1073
1074         case 8:
1075                 color_control = BASE_COLOR_SIZE332;
1076                 break;
1077
1078         case 9:
1079                 color_control = BASE_COLOR_SIZE333;
1080                 break;
1081
1082         case 12:
1083                 color_control = BASE_COLOR_SIZE444;
1084                 break;
1085
1086         case 15:
1087                 color_control = BASE_COLOR_SIZE555;
1088                 break;
1089
1090         case 16:
1091                 color_control = BASE_COLOR_SIZE565;
1092                 break;
1093
1094         case 18:
1095                 color_control = BASE_COLOR_SIZE666;
1096                 break;
1097
1098         default:
1099                 color_control = BASE_COLOR_SIZE888;
1100                 break;
1101         }
1102
1103         switch (dc->out->dither) {
1104         case TEGRA_DC_DISABLE_DITHER:
1105                 color_control |= DITHER_CONTROL_DISABLE;
1106                 break;
1107         case TEGRA_DC_ORDERED_DITHER:
1108                 color_control |= DITHER_CONTROL_ORDERED;
1109                 break;
1110         case TEGRA_DC_ERRDIFF_DITHER:
1111                 /* The line buffer for error-diffusion dither is limited
1112                  * to 1280 pixels per line. This limits the maximum
1113                  * horizontal active area size to 1280 pixels when error
1114                  * diffusion is enabled.
1115                  */
1116                 BUG_ON(dc->mode.h_active > 1280);
1117                 color_control |= DITHER_CONTROL_ERRDIFF;
1118                 break;
1119         }
1120
1121         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1122 }
1123
1124 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1125 {
1126         u32 syncpt_id;
1127
1128         switch (dc->ndev->id) {
1129         case 0:
1130                 switch (idx) {
1131                 case 0:
1132                         syncpt_id = NVSYNCPT_DISP0_A;
1133                         break;
1134                 case 1:
1135                         syncpt_id = NVSYNCPT_DISP0_B;
1136                         break;
1137                 case 2:
1138                         syncpt_id = NVSYNCPT_DISP0_C;
1139                         break;
1140                 default:
1141                         BUG();
1142                         break;
1143                 }
1144                 break;
1145         case 1:
1146                 switch (idx) {
1147                 case 0:
1148                         syncpt_id = NVSYNCPT_DISP1_A;
1149                         break;
1150                 case 1:
1151                         syncpt_id = NVSYNCPT_DISP1_B;
1152                         break;
1153                 case 2:
1154                         syncpt_id = NVSYNCPT_DISP1_C;
1155                         break;
1156                 default:
1157                         BUG();
1158                         break;
1159                 }
1160                 break;
1161         default:
1162                 BUG();
1163                 break;
1164         }
1165
1166         return syncpt_id;
1167 }
1168
1169 static int tegra_dc_init(struct tegra_dc *dc)
1170 {
1171         int i;
1172
1173         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1174         if (dc->ndev->id == 0) {
1175                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1176                                       TEGRA_MC_PRIO_MED);
1177                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1178                                       TEGRA_MC_PRIO_MED);
1179                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1180                                       TEGRA_MC_PRIO_MED);
1181                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1182                                       TEGRA_MC_PRIO_MED);
1183                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1184                                       TEGRA_MC_PRIO_HIGH);
1185         } else if (dc->ndev->id == 1) {
1186                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1187                                       TEGRA_MC_PRIO_MED);
1188                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1189                                       TEGRA_MC_PRIO_MED);
1190                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1191                                       TEGRA_MC_PRIO_MED);
1192                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1193                                       TEGRA_MC_PRIO_MED);
1194                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1195                                       TEGRA_MC_PRIO_HIGH);
1196         }
1197         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1198                         DC_CMD_CONT_SYNCPT_VSYNC);
1199         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1200         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1201         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1202         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1203 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1204         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1205 #endif
1206         /* enable interrupts for vblank, frame_end and underflows */
1207         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1208                 DC_CMD_INT_ENABLE);
1209         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1210
1211         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1212
1213         tegra_dc_set_color_control(dc);
1214         for (i = 0; i < DC_N_WINDOWS; i++) {
1215                 struct tegra_dc_win *win = &dc->windows[i];
1216                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1217                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1218                 tegra_dc_set_csc(dc, &win->csc);
1219                 tegra_dc_set_lut(dc, win);
1220                 tegra_dc_set_scaling_filter(dc);
1221         }
1222
1223
1224         for (i = 0; i < dc->n_windows; i++) {
1225                 u32 syncpt = get_syncpt(dc, i);
1226
1227                 dc->syncpt[i].id = syncpt;
1228
1229                 dc->syncpt[i].min = dc->syncpt[i].max =
1230                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1231         }
1232
1233         print_mode_info(dc, dc->mode);
1234
1235         if (dc->mode.pclk)
1236                 if (tegra_dc_program_mode(dc, &dc->mode))
1237                         return -EINVAL;
1238
1239         /* Initialize SD AFTER the modeset.
1240            nvsd_init handles the sd_settings = NULL case. */
1241         nvsd_init(dc, dc->out->sd_settings);
1242
1243         return 0;
1244 }
1245
1246 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1247 {
1248         int failed_init = 0;
1249
1250         if (dc->out->enable)
1251                 dc->out->enable();
1252
1253         tegra_dc_setup_clk(dc, dc->clk);
1254         tegra_dc_clk_enable(dc);
1255
1256         /* do not accept interrupts during initialization */
1257         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1258         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1259
1260         enable_dc_irq(dc->irq);
1261
1262         failed_init = tegra_dc_init(dc);
1263         if (failed_init) {
1264                 _tegra_dc_controller_disable(dc);
1265                 return false;
1266         }
1267
1268         if (dc->out_ops && dc->out_ops->enable)
1269                 dc->out_ops->enable(dc);
1270
1271         if (dc->out->postpoweron)
1272                 dc->out->postpoweron();
1273
1274         /* force a full blending update */
1275         dc->blend.z[0] = -1;
1276
1277         tegra_dc_ext_enable(dc->ext);
1278
1279         trace_printk("%s:enable\n", dc->ndev->name);
1280         return true;
1281 }
1282
1283 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1284 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1285 {
1286         bool ret = true;
1287
1288         if (dc->out->enable)
1289                 dc->out->enable();
1290
1291         tegra_dc_setup_clk(dc, dc->clk);
1292         tegra_dc_clk_enable(dc);
1293
1294         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1295                 mutex_lock(&tegra_dcs[1]->lock);
1296                 disable_irq(tegra_dcs[1]->irq);
1297         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1298                 mutex_lock(&tegra_dcs[0]->lock);
1299                 disable_irq(tegra_dcs[0]->irq);
1300         }
1301
1302         msleep(5);
1303         tegra_periph_reset_assert(dc->clk);
1304         msleep(2);
1305 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1306         tegra_periph_reset_deassert(dc->clk);
1307         msleep(1);
1308 #endif
1309
1310         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1311                 enable_dc_irq(tegra_dcs[1]->irq);
1312                 mutex_unlock(&tegra_dcs[1]->lock);
1313         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1314                 enable_dc_irq(tegra_dcs[0]->irq);
1315                 mutex_unlock(&tegra_dcs[0]->lock);
1316         }
1317
1318         enable_dc_irq(dc->irq);
1319
1320         if (tegra_dc_init(dc)) {
1321                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1322                 ret = false;
1323         }
1324
1325         if (dc->out_ops && dc->out_ops->enable)
1326                 dc->out_ops->enable(dc);
1327
1328         if (dc->out->postpoweron)
1329                 dc->out->postpoweron();
1330
1331         /* force a full blending update */
1332         dc->blend.z[0] = -1;
1333
1334         tegra_dc_ext_enable(dc->ext);
1335
1336         if (!ret) {
1337                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1338                 _tegra_dc_controller_disable(dc);
1339         }
1340
1341         trace_printk("%s:reset enable\n", dc->ndev->name);
1342         return ret;
1343 }
1344 #endif
1345
1346 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1347 {
1348         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1349 }
1350
1351 static bool _tegra_dc_enable(struct tegra_dc *dc)
1352 {
1353         if (dc->mode.pclk == 0) {
1354                 switch (dc->out->type) {
1355                 case TEGRA_DC_OUT_HDMI:
1356                 /* DC enable called but no videomode is loaded.
1357                      Check if HDMI is connected, then set fallback mdoe */
1358                 if (tegra_dc_hpd(dc)) {
1359                         if (_tegra_dc_set_default_videomode(dc))
1360                                 return false;
1361                 } else
1362                         return false;
1363
1364                 break;
1365
1366                 /* Do nothing for other outputs for now */
1367                 case TEGRA_DC_OUT_RGB:
1368
1369                 case TEGRA_DC_OUT_DSI:
1370
1371                 default:
1372                         return false;
1373                 }
1374         }
1375
1376         if (!dc->out)
1377                 return false;
1378
1379         tegra_dc_io_start(dc);
1380
1381         return _tegra_dc_controller_enable(dc);
1382 }
1383
1384 void tegra_dc_enable(struct tegra_dc *dc)
1385 {
1386         mutex_lock(&dc->lock);
1387
1388         if (!dc->enabled)
1389                 dc->enabled = _tegra_dc_enable(dc);
1390
1391         mutex_unlock(&dc->lock);
1392         print_mode_info(dc, dc->mode);
1393 }
1394
1395 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1396 {
1397         unsigned i;
1398
1399         if (dc->out && dc->out->prepoweroff)
1400                 dc->out->prepoweroff();
1401
1402         if (dc->out_ops && dc->out_ops->disable)
1403                 dc->out_ops->disable(dc);
1404
1405         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1406         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1407         disable_irq(dc->irq);
1408
1409         tegra_dc_clear_bandwidth(dc);
1410         tegra_dc_clk_disable(dc);
1411
1412         if (dc->out && dc->out->disable)
1413                 dc->out->disable();
1414
1415         for (i = 0; i < dc->n_windows; i++) {
1416                 struct tegra_dc_win *w = &dc->windows[i];
1417
1418                 /* reset window bandwidth */
1419                 w->bandwidth = 0;
1420                 w->new_bandwidth = 0;
1421
1422                 /* disable windows */
1423                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1424
1425                 /* flush any pending syncpt waits */
1426                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1427                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1428                                 dc->syncpt[i].id);
1429                         dc->syncpt[i].min++;
1430                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1431                 }
1432         }
1433         trace_printk("%s:disabled\n", dc->ndev->name);
1434 }
1435
1436 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1437 {
1438 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1439         u32 val;
1440         if (dc->enabled)  {
1441                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1442                 if (enable)
1443                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1444                 else
1445                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1446                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1447         }
1448 #endif
1449 }
1450
1451 bool tegra_dc_stats_get(struct tegra_dc *dc)
1452 {
1453 #if 0 /* right now it is always enabled */
1454         u32 val;
1455         bool res;
1456
1457         if (dc->enabled)  {
1458                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1459                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1460         } else {
1461                 res = false;
1462         }
1463
1464         return res;
1465 #endif
1466         return true;
1467 }
1468
1469 /* make the screen blank by disabling all windows */
1470 void tegra_dc_blank(struct tegra_dc *dc)
1471 {
1472         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1473         unsigned i;
1474
1475         for (i = 0; i < DC_N_WINDOWS; i++) {
1476                 dcwins[i] = tegra_dc_get_window(dc, i);
1477                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1478         }
1479
1480         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1481         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1482 }
1483
1484 static void _tegra_dc_disable(struct tegra_dc *dc)
1485 {
1486         _tegra_dc_controller_disable(dc);
1487         tegra_dc_io_end(dc);
1488 }
1489
1490 void tegra_dc_disable(struct tegra_dc *dc)
1491 {
1492         tegra_dc_ext_disable(dc->ext);
1493
1494         /* it's important that new underflow work isn't scheduled before the
1495          * lock is acquired. */
1496         cancel_delayed_work_sync(&dc->underflow_work);
1497         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1498                 mutex_lock(&dc->one_shot_lock);
1499                 cancel_delayed_work_sync(&dc->one_shot_work);
1500         }
1501
1502         mutex_lock(&dc->lock);
1503
1504         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1505                 tegra_dc_host_resume(dc);
1506
1507         if (dc->enabled) {
1508                 dc->enabled = false;
1509
1510                 if (!dc->suspended)
1511                         _tegra_dc_disable(dc);
1512         }
1513
1514 #ifdef CONFIG_SWITCH
1515         switch_set_state(&dc->modeset_switch, 0);
1516 #endif
1517
1518         mutex_unlock(&dc->lock);
1519         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1520                 mutex_unlock(&dc->one_shot_lock);
1521         print_mode_info(dc, dc->mode);
1522 }
1523
1524 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1525 static void tegra_dc_reset_worker(struct work_struct *work)
1526 {
1527         struct tegra_dc *dc =
1528                 container_of(work, struct tegra_dc, reset_work);
1529
1530         unsigned long val = 0;
1531
1532         mutex_lock(&shared_lock);
1533
1534         dev_warn(&dc->ndev->dev,
1535                 "overlay stuck in underflow state.  resetting.\n");
1536
1537         tegra_dc_ext_disable(dc->ext);
1538
1539         mutex_lock(&dc->lock);
1540
1541         if (dc->enabled == false)
1542                 goto unlock;
1543
1544         dc->enabled = false;
1545
1546         /*
1547          * off host read bus
1548          */
1549         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1550         val &= ~(0x00000100);
1551         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1552
1553         /*
1554          * set DC to STOP mode
1555          */
1556         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1557
1558         msleep(10);
1559
1560         _tegra_dc_controller_disable(dc);
1561
1562         /* _tegra_dc_controller_reset_enable deasserts reset */
1563         _tegra_dc_controller_reset_enable(dc);
1564
1565         dc->enabled = true;
1566
1567         /* reopen host read bus */
1568         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1569         val &= ~(0x00000100);
1570         val |= 0x100;
1571         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1572
1573 unlock:
1574         mutex_unlock(&dc->lock);
1575         mutex_unlock(&shared_lock);
1576         trace_printk("%s:reset complete\n", dc->ndev->name);
1577 }
1578 #endif
1579
1580 static void tegra_dc_underflow_worker(struct work_struct *work)
1581 {
1582         struct tegra_dc *dc = container_of(
1583                 to_delayed_work(work), struct tegra_dc, underflow_work);
1584
1585         mutex_lock(&dc->lock);
1586         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1587                 tegra_dc_host_resume(dc);
1588
1589         if (dc->enabled) {
1590                 tegra_dc_underflow_handler(dc);
1591         }
1592         mutex_unlock(&dc->lock);
1593 }
1594
1595 #ifdef CONFIG_SWITCH
1596 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1597 {
1598         struct tegra_dc *dc =
1599                 container_of(sdev, struct tegra_dc, modeset_switch);
1600
1601         if (!sdev->state)
1602                 return sprintf(buf, "offline\n");
1603
1604         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1605 }
1606 #endif
1607
1608 static int tegra_dc_probe(struct nvhost_device *ndev,
1609         struct nvhost_device_id *id_table)
1610 {
1611         struct tegra_dc *dc;
1612         struct clk *clk;
1613         struct clk *emc_clk;
1614         struct resource *res;
1615         struct resource *base_res;
1616         struct resource *fb_mem = NULL;
1617         int ret = 0;
1618         void __iomem *base;
1619         int irq;
1620         int i;
1621
1622         if (!ndev->dev.platform_data) {
1623                 dev_err(&ndev->dev, "no platform data\n");
1624                 return -ENOENT;
1625         }
1626
1627         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1628         if (!dc) {
1629                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1630                 return -ENOMEM;
1631         }
1632
1633         irq = nvhost_get_irq_byname(ndev, "irq");
1634         if (irq <= 0) {
1635                 dev_err(&ndev->dev, "no irq\n");
1636                 ret = -ENOENT;
1637                 goto err_free;
1638         }
1639
1640         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1641         if (!res) {
1642                 dev_err(&ndev->dev, "no mem resource\n");
1643                 ret = -ENOENT;
1644                 goto err_free;
1645         }
1646
1647         base_res = request_mem_region(res->start, resource_size(res),
1648                 ndev->name);
1649         if (!base_res) {
1650                 dev_err(&ndev->dev, "request_mem_region failed\n");
1651                 ret = -EBUSY;
1652                 goto err_free;
1653         }
1654
1655         base = ioremap(res->start, resource_size(res));
1656         if (!base) {
1657                 dev_err(&ndev->dev, "registers can't be mapped\n");
1658                 ret = -EBUSY;
1659                 goto err_release_resource_reg;
1660         }
1661
1662         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1663
1664         clk = clk_get(&ndev->dev, NULL);
1665         if (IS_ERR_OR_NULL(clk)) {
1666                 dev_err(&ndev->dev, "can't get clock\n");
1667                 ret = -ENOENT;
1668                 goto err_iounmap_reg;
1669         }
1670
1671         emc_clk = clk_get(&ndev->dev, "emc");
1672         if (IS_ERR_OR_NULL(emc_clk)) {
1673                 dev_err(&ndev->dev, "can't get emc clock\n");
1674                 ret = -ENOENT;
1675                 goto err_put_clk;
1676         }
1677
1678         dc->clk = clk;
1679         dc->emc_clk = emc_clk;
1680         dc->shift_clk_div = 1;
1681         /* Initialize one shot work delay, it will be assigned by dsi
1682          * according to refresh rate later. */
1683         dc->one_shot_delay_ms = 40;
1684
1685         dc->base_res = base_res;
1686         dc->base = base;
1687         dc->irq = irq;
1688         dc->ndev = ndev;
1689         dc->pdata = ndev->dev.platform_data;
1690
1691         /*
1692          * The emc is a shared clock, it will be set based on
1693          * the requirements for each user on the bus.
1694          */
1695         dc->emc_clk_rate = 0;
1696
1697         mutex_init(&dc->lock);
1698         mutex_init(&dc->one_shot_lock);
1699         init_completion(&dc->frame_end_complete);
1700         init_waitqueue_head(&dc->wq);
1701 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1702         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1703 #endif
1704         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1705         dc->vblank_ref_count = 0;
1706         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
1707         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
1708
1709         tegra_dc_init_lut_defaults(&dc->fb_lut);
1710
1711         dc->n_windows = DC_N_WINDOWS;
1712         for (i = 0; i < dc->n_windows; i++) {
1713                 struct tegra_dc_win *win = &dc->windows[i];
1714                 win->idx = i;
1715                 win->dc = dc;
1716                 tegra_dc_init_csc_defaults(&win->csc);
1717                 tegra_dc_init_lut_defaults(&win->lut);
1718         }
1719
1720         ret = tegra_dc_set(dc, ndev->id);
1721         if (ret < 0) {
1722                 dev_err(&ndev->dev, "can't add dc\n");
1723                 goto err_free_irq;
1724         }
1725
1726         nvhost_set_drvdata(ndev, dc);
1727
1728 #ifdef CONFIG_SWITCH
1729         dc->modeset_switch.name = dev_name(&ndev->dev);
1730         dc->modeset_switch.state = 0;
1731         dc->modeset_switch.print_state = switch_modeset_print_mode;
1732         switch_dev_register(&dc->modeset_switch);
1733 #endif
1734
1735         tegra_dc_feature_register(dc);
1736
1737         if (dc->pdata->default_out)
1738                 tegra_dc_set_out(dc, dc->pdata->default_out);
1739         else
1740                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1741
1742         dc->vblank_syncpt = (dc->ndev->id == 0) ?
1743                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
1744
1745         dc->ext = tegra_dc_ext_register(ndev, dc);
1746         if (IS_ERR_OR_NULL(dc->ext)) {
1747                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
1748                 dc->ext = NULL;
1749         }
1750
1751         mutex_lock(&dc->lock);
1752         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
1753                 dc->enabled = _tegra_dc_enable(dc);
1754         mutex_unlock(&dc->lock);
1755
1756         /* interrupt handler must be registered before tegra_fb_register() */
1757         if (request_irq(irq, tegra_dc_irq, 0,
1758                         dev_name(&ndev->dev), dc)) {
1759                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1760                 ret = -EBUSY;
1761                 goto err_put_emc_clk;
1762         }
1763
1764         tegra_dc_create_debugfs(dc);
1765
1766         dev_info(&ndev->dev, "probed\n");
1767
1768         if (dc->pdata->fb) {
1769                 if (dc->pdata->fb->bits_per_pixel == -1) {
1770                         unsigned long fmt;
1771                         tegra_dc_writel(dc,
1772                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1773                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1774
1775                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1776                         dc->pdata->fb->bits_per_pixel =
1777                                 tegra_dc_fmt_bpp(fmt);
1778                 }
1779
1780                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1781                 if (IS_ERR_OR_NULL(dc->fb))
1782                         dc->fb = NULL;
1783         }
1784
1785         if (dc->out && dc->out->hotplug_init)
1786                 dc->out->hotplug_init();
1787
1788         if (dc->out_ops && dc->out_ops->detect)
1789                 dc->out_ops->detect(dc);
1790         else
1791                 dc->connected = true;
1792
1793         tegra_dc_create_sysfs(&dc->ndev->dev);
1794
1795         return 0;
1796
1797 err_free_irq:
1798         free_irq(irq, dc);
1799 err_put_emc_clk:
1800         clk_put(emc_clk);
1801 err_put_clk:
1802         clk_put(clk);
1803 err_iounmap_reg:
1804         iounmap(base);
1805         if (fb_mem)
1806                 release_resource(fb_mem);
1807 err_release_resource_reg:
1808         release_resource(base_res);
1809 err_free:
1810         kfree(dc);
1811
1812         return ret;
1813 }
1814
1815 static int tegra_dc_remove(struct nvhost_device *ndev)
1816 {
1817         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1818
1819         tegra_dc_remove_sysfs(&dc->ndev->dev);
1820         tegra_dc_remove_debugfs(dc);
1821
1822         if (dc->fb) {
1823                 tegra_fb_unregister(dc->fb);
1824                 if (dc->fb_mem)
1825                         release_resource(dc->fb_mem);
1826         }
1827
1828         tegra_dc_ext_disable(dc->ext);
1829
1830         if (dc->ext)
1831                 tegra_dc_ext_unregister(dc->ext);
1832
1833         if (dc->enabled)
1834                 _tegra_dc_disable(dc);
1835
1836 #ifdef CONFIG_SWITCH
1837         switch_dev_unregister(&dc->modeset_switch);
1838 #endif
1839         free_irq(dc->irq, dc);
1840         clk_put(dc->emc_clk);
1841         clk_put(dc->clk);
1842         iounmap(dc->base);
1843         if (dc->fb_mem)
1844                 release_resource(dc->base_res);
1845         kfree(dc);
1846         tegra_dc_set(NULL, ndev->id);
1847         return 0;
1848 }
1849
1850 #ifdef CONFIG_PM
1851 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
1852 {
1853         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1854
1855         trace_printk("%s:suspend\n", dc->ndev->name);
1856         dev_info(&ndev->dev, "suspend\n");
1857
1858         tegra_dc_ext_disable(dc->ext);
1859
1860         mutex_lock(&dc->lock);
1861
1862         if (dc->out_ops && dc->out_ops->suspend)
1863                 dc->out_ops->suspend(dc);
1864
1865         if (dc->enabled) {
1866                 _tegra_dc_disable(dc);
1867
1868                 dc->suspended = true;
1869         }
1870
1871         if (dc->out && dc->out->postsuspend) {
1872                 dc->out->postsuspend();
1873                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
1874                         /*
1875                          * avoid resume event due to voltage falling
1876                          */
1877                         msleep(100);
1878         }
1879
1880         mutex_unlock(&dc->lock);
1881
1882         return 0;
1883 }
1884
1885 static int tegra_dc_resume(struct nvhost_device *ndev)
1886 {
1887         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1888
1889         trace_printk("%s:resume\n", dc->ndev->name);
1890         dev_info(&ndev->dev, "resume\n");
1891
1892         mutex_lock(&dc->lock);
1893         dc->suspended = false;
1894
1895         if (dc->enabled)
1896                 _tegra_dc_enable(dc);
1897
1898         if (dc->out && dc->out->hotplug_init)
1899                 dc->out->hotplug_init();
1900
1901         if (dc->out_ops && dc->out_ops->resume)
1902                 dc->out_ops->resume(dc);
1903         mutex_unlock(&dc->lock);
1904
1905         return 0;
1906 }
1907
1908 #endif /* CONFIG_PM */
1909
1910 static void tegra_dc_shutdown(struct nvhost_device *ndev)
1911 {
1912         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1913
1914         if (!dc || !dc->enabled)
1915                 return;
1916
1917         tegra_dc_blank(dc);
1918         tegra_dc_disable(dc);
1919 }
1920
1921 extern int suspend_set(const char *val, struct kernel_param *kp)
1922 {
1923         if (!strcmp(val, "dump"))
1924                 dump_regs(tegra_dcs[0]);
1925 #ifdef CONFIG_PM
1926         else if (!strcmp(val, "suspend"))
1927                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
1928         else if (!strcmp(val, "resume"))
1929                 tegra_dc_resume(tegra_dcs[0]->ndev);
1930 #endif
1931
1932         return 0;
1933 }
1934
1935 extern int suspend_get(char *buffer, struct kernel_param *kp)
1936 {
1937         return 0;
1938 }
1939
1940 int suspend;
1941
1942 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
1943
1944 struct nvhost_driver tegra_dc_driver = {
1945         .driver = {
1946                 .name = "tegradc",
1947                 .owner = THIS_MODULE,
1948         },
1949         .probe = tegra_dc_probe,
1950         .remove = tegra_dc_remove,
1951 #ifdef CONFIG_PM
1952         .suspend = tegra_dc_suspend,
1953         .resume = tegra_dc_resume,
1954 #endif
1955         .shutdown = tegra_dc_shutdown,
1956 };
1957
1958 static int __init tegra_dc_module_init(void)
1959 {
1960         int ret = tegra_dc_ext_module_init();
1961         if (ret)
1962                 return ret;
1963         return nvhost_driver_register(&tegra_dc_driver);
1964 }
1965
1966 static void __exit tegra_dc_module_exit(void)
1967 {
1968         nvhost_driver_unregister(&tegra_dc_driver);
1969         tegra_dc_ext_module_exit();
1970 }
1971
1972 module_exit(tegra_dc_module_exit);
1973 module_init(tegra_dc_module_init);