video: tegra: dc: fix CEA timings for hdmi
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38
39 #include <mach/clk.h>
40 #include <mach/dc.h>
41 #include <mach/fb.h>
42 #include <mach/mc.h>
43 #include <mach/nvhost.h>
44 #include <mach/latency_allowance.h>
45
46 #include "dc_reg.h"
47 #include "dc_priv.h"
48 #include "overlay.h"
49 #include "nvsd.h"
50
51 #define TEGRA_CRC_LATCHED_DELAY         34
52
53 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
54 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
55 #else
56 /* ignore underflows when on simulation and fpga platform */
57 #define ALL_UF_INT (0)
58 #endif
59
60 static int no_vsync;
61
62 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
63
64 static int use_dynamic_emc = 1;
65
66 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
67
68 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
69
70 DEFINE_MUTEX(tegra_dc_lock);
71 DEFINE_MUTEX(shared_lock);
72
73 static const struct {
74         bool h;
75         bool v;
76 } can_filter[] = {
77         /* Window A has no filtering */
78         { false, false },
79         /* Window B has both H and V filtering */
80         { true,  true  },
81         /* Window C has only H filtering */
82         { false, true  },
83 };
84 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
85 {
86         return can_filter[win->idx].v &&
87                 win->h.full != dfixed_const(win->out_h);
88 }
89 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
90 {
91         return can_filter[win->idx].h &&
92                 win->w.full != dfixed_const(win->out_w);
93 }
94
95 static inline int tegra_dc_fmt_bpp(int fmt)
96 {
97         switch (fmt) {
98         case TEGRA_WIN_FMT_P1:
99                 return 1;
100
101         case TEGRA_WIN_FMT_P2:
102                 return 2;
103
104         case TEGRA_WIN_FMT_P4:
105                 return 4;
106
107         case TEGRA_WIN_FMT_P8:
108                 return 8;
109
110         case TEGRA_WIN_FMT_B4G4R4A4:
111         case TEGRA_WIN_FMT_B5G5R5A:
112         case TEGRA_WIN_FMT_B5G6R5:
113         case TEGRA_WIN_FMT_AB5G5R5:
114                 return 16;
115
116         case TEGRA_WIN_FMT_B8G8R8A8:
117         case TEGRA_WIN_FMT_R8G8B8A8:
118         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
119         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
120                 return 32;
121
122         /* for planar formats, size of the Y plane, 8bit */
123         case TEGRA_WIN_FMT_YCbCr420P:
124         case TEGRA_WIN_FMT_YUV420P:
125         case TEGRA_WIN_FMT_YCbCr422P:
126         case TEGRA_WIN_FMT_YUV422P:
127                 return 8;
128
129         case TEGRA_WIN_FMT_YCbCr422:
130         case TEGRA_WIN_FMT_YUV422:
131         case TEGRA_WIN_FMT_YCbCr422R:
132         case TEGRA_WIN_FMT_YUV422R:
133         case TEGRA_WIN_FMT_YCbCr422RA:
134         case TEGRA_WIN_FMT_YUV422RA:
135                 /* FIXME: need to know the bpp of these formats */
136                 return 0;
137         }
138         return 0;
139 }
140
141 static inline bool tegra_dc_is_yuv_planar(int fmt)
142 {
143         switch (fmt) {
144         case TEGRA_WIN_FMT_YUV420P:
145         case TEGRA_WIN_FMT_YCbCr420P:
146         case TEGRA_WIN_FMT_YCbCr422P:
147         case TEGRA_WIN_FMT_YUV422P:
148                 return true;
149         }
150         return false;
151 }
152
153 #define DUMP_REG(a) do {                        \
154         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
155                  #a, a, tegra_dc_readl(dc, a));               \
156         print(data, buff);                                    \
157         } while (0)
158
159 static void _dump_regs(struct tegra_dc *dc, void *data,
160                        void (* print)(void *data, const char *str))
161 {
162         int i;
163         char buff[256];
164
165         tegra_dc_io_start(dc);
166         clk_enable(dc->clk);
167
168         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
169         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
170         DUMP_REG(DC_CMD_SIGNAL_RAISE);
171         DUMP_REG(DC_CMD_INT_STATUS);
172         DUMP_REG(DC_CMD_INT_MASK);
173         DUMP_REG(DC_CMD_INT_ENABLE);
174         DUMP_REG(DC_CMD_INT_TYPE);
175         DUMP_REG(DC_CMD_INT_POLARITY);
176         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
177         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
178         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
179         DUMP_REG(DC_CMD_STATE_ACCESS);
180         DUMP_REG(DC_CMD_STATE_CONTROL);
181         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
182         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
183
184         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
185         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
186         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
187         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
188         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
189         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
190         DUMP_REG(DC_DISP_REF_TO_SYNC);
191         DUMP_REG(DC_DISP_SYNC_WIDTH);
192         DUMP_REG(DC_DISP_BACK_PORCH);
193         DUMP_REG(DC_DISP_DISP_ACTIVE);
194         DUMP_REG(DC_DISP_FRONT_PORCH);
195         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
196         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
197         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
198         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
199         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
200         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
201         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
202         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
203         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
204         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
205         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
206         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
207         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
208         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
209         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
210         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
211         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
212         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
213         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
214         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
215         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
216         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
217         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
218         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
219         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
220         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
221         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
222         DUMP_REG(DC_DISP_M0_CONTROL);
223         DUMP_REG(DC_DISP_M1_CONTROL);
224         DUMP_REG(DC_DISP_DI_CONTROL);
225         DUMP_REG(DC_DISP_PP_CONTROL);
226         DUMP_REG(DC_DISP_PP_SELECT_A);
227         DUMP_REG(DC_DISP_PP_SELECT_B);
228         DUMP_REG(DC_DISP_PP_SELECT_C);
229         DUMP_REG(DC_DISP_PP_SELECT_D);
230         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
231         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
232         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
233         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
234         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
235         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
236         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
237         DUMP_REG(DC_DISP_BORDER_COLOR);
238         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
239         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
240         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
241         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
242         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
243         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
244         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
245         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
246         DUMP_REG(DC_DISP_CURSOR_POSITION);
247         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
248         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
249         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
250         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
251         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
252         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
253         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
254         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
255         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
256         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
257         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
258         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
259         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
260
261
262         for (i = 0; i < 3; i++) {
263                 print(data, "\n");
264                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
265                 print(data, buff);
266
267                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
268                                 DC_CMD_DISPLAY_WINDOW_HEADER);
269                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
270                 DUMP_REG(DC_WIN_WIN_OPTIONS);
271                 DUMP_REG(DC_WIN_BYTE_SWAP);
272                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
273                 DUMP_REG(DC_WIN_COLOR_DEPTH);
274                 DUMP_REG(DC_WIN_POSITION);
275                 DUMP_REG(DC_WIN_SIZE);
276                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
277                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
278                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
279                 DUMP_REG(DC_WIN_DDA_INCREMENT);
280                 DUMP_REG(DC_WIN_LINE_STRIDE);
281                 DUMP_REG(DC_WIN_BUF_STRIDE);
282                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
283                 DUMP_REG(DC_WIN_BLEND_NOKEY);
284                 DUMP_REG(DC_WIN_BLEND_1WIN);
285                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
286                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
287                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
288                 DUMP_REG(DC_WINBUF_START_ADDR);
289                 DUMP_REG(DC_WINBUF_START_ADDR_U);
290                 DUMP_REG(DC_WINBUF_START_ADDR_V);
291                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
292                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
293                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
294                 DUMP_REG(DC_WIN_CSC_YOF);
295                 DUMP_REG(DC_WIN_CSC_KYRGB);
296                 DUMP_REG(DC_WIN_CSC_KUR);
297                 DUMP_REG(DC_WIN_CSC_KVR);
298                 DUMP_REG(DC_WIN_CSC_KUG);
299                 DUMP_REG(DC_WIN_CSC_KVG);
300                 DUMP_REG(DC_WIN_CSC_KUB);
301                 DUMP_REG(DC_WIN_CSC_KVB);
302         }
303
304         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
305         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
306         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
307         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
308         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
309         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
310         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
311         DUMP_REG(DC_DISP_M1_CONTROL);
312         DUMP_REG(DC_COM_PM1_CONTROL);
313         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
314         DUMP_REG(DC_DISP_SD_CONTROL);
315
316         clk_disable(dc->clk);
317         tegra_dc_io_end(dc);
318 }
319
320 #undef DUMP_REG
321
322 #ifdef DEBUG
323 static void dump_regs_print(void *data, const char *str)
324 {
325         struct tegra_dc *dc = data;
326         dev_dbg(&dc->ndev->dev, "%s", str);
327 }
328
329 static void dump_regs(struct tegra_dc *dc)
330 {
331         _dump_regs(dc, dc, dump_regs_print);
332 }
333 #else /* !DEBUG */
334
335 static void dump_regs(struct tegra_dc *dc) {}
336
337 #endif /* DEBUG */
338
339 #ifdef CONFIG_DEBUG_FS
340
341 static void dbg_regs_print(void *data, const char *str)
342 {
343         struct seq_file *s = data;
344
345         seq_printf(s, "%s", str);
346 }
347
348 #undef DUMP_REG
349
350 static int dbg_dc_show(struct seq_file *s, void *unused)
351 {
352         struct tegra_dc *dc = s->private;
353
354         _dump_regs(dc, s, dbg_regs_print);
355
356         return 0;
357 }
358
359
360 static int dbg_dc_open(struct inode *inode, struct file *file)
361 {
362         return single_open(file, dbg_dc_show, inode->i_private);
363 }
364
365 static const struct file_operations regs_fops = {
366         .open           = dbg_dc_open,
367         .read           = seq_read,
368         .llseek         = seq_lseek,
369         .release        = single_release,
370 };
371
372 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
373 {
374         struct tegra_dc *dc = s->private;
375         struct tegra_dc_mode *m;
376
377         mutex_lock(&dc->lock);
378         m = &dc->mode;
379         seq_printf(s,
380                 "pclk: %d\n"
381                 "h_ref_to_sync: %d\n"
382                 "v_ref_to_sync: %d\n"
383                 "h_sync_width: %d\n"
384                 "v_sync_width: %d\n"
385                 "h_back_porch: %d\n"
386                 "v_back_porch: %d\n"
387                 "h_active: %d\n"
388                 "v_active: %d\n"
389                 "h_front_porch: %d\n"
390                 "v_front_porch: %d\n"
391                 "stereo_mode: %d\n",
392                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
393                 m->h_sync_width, m->v_sync_width,
394                 m->h_back_porch, m->v_back_porch,
395                 m->h_active, m->v_active,
396                 m->h_front_porch, m->v_front_porch,
397                 m->stereo_mode);
398         mutex_unlock(&dc->lock);
399         return 0;
400 }
401
402 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
403 {
404         return single_open(file, dbg_dc_mode_show, inode->i_private);
405 }
406
407 static const struct file_operations mode_fops = {
408         .open           = dbg_dc_mode_open,
409         .read           = seq_read,
410         .llseek         = seq_lseek,
411         .release        = single_release,
412 };
413
414 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
415 {
416         struct tegra_dc *dc = s->private;
417
418         mutex_lock(&dc->lock);
419         seq_printf(s,
420                 "underflows: %u\n"
421                 "underflows_a: %u\n"
422                 "underflows_b: %u\n"
423                 "underflows_c: %u\n",
424                 dc->stats.underflows,
425                 dc->stats.underflows_a,
426                 dc->stats.underflows_b,
427                 dc->stats.underflows_c);
428         mutex_unlock(&dc->lock);
429
430         return 0;
431 }
432
433 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
434 {
435         return single_open(file, dbg_dc_stats_show, inode->i_private);
436 }
437
438 static const struct file_operations stats_fops = {
439         .open           = dbg_dc_stats_open,
440         .read           = seq_read,
441         .llseek         = seq_lseek,
442         .release        = single_release,
443 };
444
445 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
446 {
447         if (dc->debugdir)
448                 debugfs_remove_recursive(dc->debugdir);
449         dc->debugdir = NULL;
450 }
451
452 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
453 {
454         struct dentry *retval;
455
456         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
457         if (!dc->debugdir)
458                 goto remove_out;
459
460         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
461                 &regs_fops);
462         if (!retval)
463                 goto remove_out;
464
465         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
466                 &mode_fops);
467         if (!retval)
468                 goto remove_out;
469
470         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
471                 &stats_fops);
472         if (!retval)
473                 goto remove_out;
474
475         return;
476 remove_out:
477         dev_err(&dc->ndev->dev, "could not create debugfs\n");
478         tegra_dc_remove_debugfs(dc);
479 }
480
481 #else /* !CONFIG_DEBUGFS */
482 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
483 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
484 #endif /* CONFIG_DEBUGFS */
485
486 static int tegra_dc_set(struct tegra_dc *dc, int index)
487 {
488         int ret = 0;
489
490         mutex_lock(&tegra_dc_lock);
491         if (index >= TEGRA_MAX_DC) {
492                 ret = -EINVAL;
493                 goto out;
494         }
495
496         if (dc != NULL && tegra_dcs[index] != NULL) {
497                 ret = -EBUSY;
498                 goto out;
499         }
500
501         tegra_dcs[index] = dc;
502
503 out:
504         mutex_unlock(&tegra_dc_lock);
505
506         return ret;
507 }
508
509 unsigned int tegra_dc_has_multiple_dc(void)
510 {
511         unsigned int idx;
512         unsigned int cnt = 0;
513         struct tegra_dc *dc;
514
515         mutex_lock(&tegra_dc_lock);
516         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
517                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
518         mutex_unlock(&tegra_dc_lock);
519
520         return (cnt > 1);
521 }
522
523 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
524 {
525         if (idx < TEGRA_MAX_DC)
526                 return tegra_dcs[idx];
527         else
528                 return NULL;
529 }
530 EXPORT_SYMBOL(tegra_dc_get_dc);
531
532 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
533 {
534         if (win >= dc->n_windows)
535                 return NULL;
536
537         return &dc->windows[win];
538 }
539 EXPORT_SYMBOL(tegra_dc_get_window);
540
541 static int get_topmost_window(u32 *depths, unsigned long *wins)
542 {
543         int idx, best = -1;
544
545         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
546                 if (best == -1 || depths[idx] < depths[best])
547                         best = idx;
548         }
549         clear_bit(best, wins);
550         return best;
551 }
552
553 bool tegra_dc_get_connected(struct tegra_dc *dc)
554 {
555         return dc->connected;
556 }
557 EXPORT_SYMBOL(tegra_dc_get_connected);
558
559 static u32 blend_topwin(u32 flags)
560 {
561         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
562                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
563         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
564                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
565         else
566                 return BLEND(NOKEY, FIX, 0xff, 0xff);
567 }
568
569 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
570 {
571         int other;
572
573         for (other = 0; other < DC_N_WINDOWS; other++) {
574                 if (other != idx && (xy-- == 0))
575                         break;
576         }
577         if (BIT(other) & behind_mask)
578                 return blend_topwin(flags[idx]);
579         else if (flags[other])
580                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
581         else
582                 return BLEND(NOKEY, FIX, 0x00, 0x00);
583 }
584
585 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
586 {
587         unsigned long infront_mask;
588         int first;
589
590         infront_mask = ~(behind_mask | BIT(idx));
591         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
592         first = ffs(infront_mask) - 1;
593
594         if (!infront_mask)
595                 return blend_topwin(flags[idx]);
596         else if (behind_mask && first != -1 && flags[first])
597                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
598         else
599                 return BLEND(NOKEY, FIX, 0x0, 0x0);
600 }
601
602 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
603 {
604         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
605
606         while (mask) {
607                 int idx = get_topmost_window(blend->z, &mask);
608
609                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
610                                 DC_CMD_DISPLAY_WINDOW_HEADER);
611                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
612                                 DC_WIN_BLEND_NOKEY);
613                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
614                                 DC_WIN_BLEND_1WIN);
615                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
616                                 DC_WIN_BLEND_2WIN_X);
617                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
618                                 DC_WIN_BLEND_2WIN_Y);
619                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
620                                 DC_WIN_BLEND_3WIN_XY);
621         }
622 }
623
624 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
625 {
626         csc->yof   = 0x00f0;
627         csc->kyrgb = 0x012a;
628         csc->kur   = 0x0000;
629         csc->kvr   = 0x0198;
630         csc->kug   = 0x039b;
631         csc->kvg   = 0x032f;
632         csc->kub   = 0x0204;
633         csc->kvb   = 0x0000;
634 }
635
636 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
637 {
638         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
639         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
640         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
641         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
642         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
643         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
644         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
645         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
646 }
647
648 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
649 {
650         mutex_lock(&dc->lock);
651
652         if (!dc->enabled) {
653                 mutex_unlock(&dc->lock);
654                 return -EFAULT;
655         }
656
657         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
658                         DC_CMD_DISPLAY_WINDOW_HEADER);
659
660         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
661
662         mutex_unlock(&dc->lock);
663
664         return 0;
665 }
666 EXPORT_SYMBOL(tegra_dc_update_csc);
667
668 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
669 {
670         unsigned i;
671         unsigned v0 = 128;
672         unsigned v1 = 0;
673         /* linear horizontal and vertical filters */
674         for (i = 0; i < 16; i++) {
675                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
676                                 DC_WIN_H_FILTER_P(i));
677
678                 tegra_dc_writel(dc, v0,
679                                 DC_WIN_V_FILTER_P(i));
680                 v0 -= 8;
681                 v1 += 8;
682         }
683 }
684
685 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
686         struct tegra_dc_win *w)
687 {
688         /* windows A, B, C for first and second display */
689         static const enum tegra_la_id la_id_tab[2][3] = {
690                 /* first display */
691                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
692                         TEGRA_LA_DISPLAY_0C },
693                 /* second display */
694                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
695                         TEGRA_LA_DISPLAY_0CB },
696         };
697         /* window B V-filter tap for first and second display. */
698         static const enum tegra_la_id vfilter_tab[2] = {
699                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
700         };
701         unsigned long bw;
702
703         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
704         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
705         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
706
707         /* our bandwidth is in bytes/sec, but LA takes MBps.
708          * round up bandwidth to 1MBps */
709         bw = w->new_bandwidth / 1000000 + 1;
710
711         /* tegra_dc_get_bandwidth() treats V filter windows as double
712          * bandwidth, but LA has a seperate client for V filter */
713         if (w->idx == 1 && win_use_v_filter(w))
714                 bw /= 2;
715
716         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
717
718         /* if window B, also set the 1B client for the 2-tap V filter. */
719         if (w->idx == 1)
720                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
721
722         w->bandwidth = w->new_bandwidth;
723 }
724
725 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
726                                                    struct tegra_dc_win *b)
727 {
728         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
729                 return 0;
730
731         /* because memory access to load the fifo can overlap, only care
732          * if windows overlap vertically */
733         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
734                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
735 }
736
737 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
738                                                  int n)
739 {
740         unsigned i;
741         unsigned j;
742         unsigned overlap_count;
743         unsigned max_bw = 0;
744
745         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
746                          "inaccurate.\n");
747
748         /* If we had a large number of windows, we would compute adjacency
749          * graph representing 2 window overlaps, find all cliques in the graph,
750          * assign bandwidth to each clique, and then select the clique with
751          * maximum bandwidth. But because we have at most 3 windows,
752          * implementing proper Bron-Kerbosh algorithm would be an overkill,
753          * brute force will suffice.
754          *
755          * Thus: find maximum bandwidth for either single or a pair of windows
756          * and count number of window pair overlaps. If there are three
757          * pairs, all 3 window overlap.
758          */
759
760         overlap_count = 0;
761         for (i = 0; i < n; i++) {
762                 unsigned int bw1;
763
764                 if (wins[i] == NULL)
765                         continue;
766                 bw1 = wins[i]->new_bandwidth;
767                 if (bw1 > max_bw)
768                         /* Single window */
769                         max_bw = bw1;
770
771                 for (j = i + 1; j < n; j++) {
772                         if (wins[j] == NULL)
773                                 continue;
774                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
775                                 unsigned int bw2 = wins[j]->new_bandwidth;
776                                 if (bw1 + bw2 > max_bw)
777                                         /* Window pair overlaps */
778                                         max_bw = bw1 + bw2;
779                                 overlap_count++;
780                         }
781                 }
782         }
783
784         if (overlap_count == 3)
785                 /* All three windows overlap */
786                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
787                          wins[2]->new_bandwidth;
788
789         return max_bw;
790 }
791
792 /*
793  * Calculate peak EMC bandwidth for each enabled window =
794  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
795  * (windows_tiling ? 2 : 1)
796  *
797  *
798  * note:
799  * (*) We use 2 tap V filter, so need double BW if use V filter
800  * (*) Tiling mode on T30 and DDR3 requires double BW
801  */
802 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
803         struct tegra_dc_win *w)
804 {
805         unsigned long ret;
806         int tiled_windows_bw_multiplier;
807         unsigned long bpp;
808
809         if (!WIN_IS_ENABLED(w))
810                 return 0;
811
812         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
813             w->out_w == 0 || w->out_h == 0)
814                 return 0;
815
816         tiled_windows_bw_multiplier =
817                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
818
819         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
820          * but the size reported by tegra_dc_fmt_bpp for the planar version
821          * is of the luma plane's size only. */
822         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
823                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
824         /* perform calculations with most significant bits of pixel clock
825          * to prevent overflow of long. */
826         ret = (unsigned long)(dc->pixel_clk >> 16) *
827                 bpp / 8 *
828                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
829                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
830
831 /*
832  * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we
833  * will request 140MBps from EMC.
834  */
835 #define MEM_EFFICIENCY_SHIFT 1
836         ret <<= MEM_EFFICIENCY_SHIFT;
837 #undef MEM_EFFICIENCY_SHIFT
838
839         /* if overflowed */
840         if (ret > (1UL << 31))
841                 return ULONG_MAX;
842
843         return ret << 16; /* restore the scaling we did above */
844 }
845
846 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
847 {
848         int i;
849
850         BUG_ON(n > DC_N_WINDOWS);
851
852         /* emc rate and latency allowance both need to know per window
853          * bandwidths */
854         for (i = 0; i < n; i++) {
855                 struct tegra_dc_win *w = windows[i];
856                 if (w)
857                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
858         }
859
860         return tegra_dc_find_max_bandwidth(windows, n);
861 }
862
863 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
864 {
865         unsigned i;
866
867         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
868                 dc->emc_clk_rate = dc->new_emc_clk_rate;
869                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
870         }
871
872         for (i = 0; i < DC_N_WINDOWS; i++) {
873                 struct tegra_dc_win *w = &dc->windows[i];
874                 if (w->bandwidth != w->new_bandwidth)
875                         tegra_dc_set_latency_allowance(dc, w);
876         }
877 }
878
879 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
880 {
881         unsigned long new_rate;
882         struct tegra_dc *dc;
883
884         if (!use_dynamic_emc)
885                 return 0;
886
887         dc = windows[0]->dc;
888
889         /* calculate the new rate based on this POST */
890         new_rate = tegra_dc_get_bandwidth(windows, n);
891         new_rate = EMC_BW_TO_FREQ(new_rate);
892
893         if (tegra_dc_has_multiple_dc())
894                 new_rate = ULONG_MAX;
895
896         dc->new_emc_clk_rate = new_rate;
897
898         return 0;
899 }
900
901 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
902                                   bool v, unsigned Bpp)
903 {
904         /*
905          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
906          *           (post_scaled_size_in_pixels - 1)), MAX)
907          * Where the value of MAX is as follows:
908          * For V_DDA_INCREMENT: 15.0 (0xF000)
909          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
910          *                       8.0 (0x8000) for 2 Bytes/pix formats.
911          */
912
913         fixed20_12 out = dfixed_init(out_int);
914         u32 dda_inc;
915         int max;
916
917         if (v) {
918                 max = 15;
919         } else {
920                 switch (Bpp) {
921                 default:
922                         WARN_ON_ONCE(1);
923                         /* fallthrough */
924                 case 4:
925                         max = 4;
926                         break;
927                 case 2:
928                         max = 8;
929                         break;
930                 }
931         }
932
933         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
934         in.full -= dfixed_const(1);
935
936         dda_inc = dfixed_div(in, out);
937
938         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
939
940         return dda_inc;
941 }
942
943 static inline u32 compute_initial_dda(fixed20_12 in)
944 {
945         return dfixed_frac(in);
946 }
947
948 /* does not support updating windows on multiple dcs in one call */
949 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
950 {
951         struct tegra_dc *dc;
952         unsigned long update_mask = GENERAL_ACT_REQ;
953         unsigned long val;
954         bool update_blend = false;
955         int i;
956
957         dc = windows[0]->dc;
958
959         mutex_lock(&dc->lock);
960
961         if (!dc->enabled) {
962                 mutex_unlock(&dc->lock);
963                 return -EFAULT;
964         }
965
966         if (no_vsync)
967                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
968         else
969                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
970
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *win = windows[i];
973                 unsigned h_dda;
974                 unsigned v_dda;
975                 fixed20_12 h_offset, v_offset;
976                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
977                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
978                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
979                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
980                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
981                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
982                 const bool filter_h = win_use_h_filter(win);
983                 const bool filter_v = win_use_v_filter(win);
984
985                 if (win->z != dc->blend.z[win->idx]) {
986                         dc->blend.z[win->idx] = win->z;
987                         update_blend = true;
988                 }
989                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
990                         dc->blend.flags[win->idx]) {
991                         dc->blend.flags[win->idx] =
992                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
993                         update_blend = true;
994                 }
995
996                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
997                                 DC_CMD_DISPLAY_WINDOW_HEADER);
998
999                 if (!no_vsync)
1000                         update_mask |= WIN_A_ACT_REQ << win->idx;
1001
1002                 if (!WIN_IS_ENABLED(win)) {
1003                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1004                         continue;
1005                 }
1006
1007                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1008                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1009
1010                 tegra_dc_writel(dc,
1011                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1012                                 DC_WIN_POSITION);
1013                 tegra_dc_writel(dc,
1014                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1015                                 DC_WIN_SIZE);
1016                 tegra_dc_writel(dc,
1017                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1018                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1019                                 DC_WIN_PRESCALED_SIZE);
1020
1021                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1022                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1023                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1024                                 DC_WIN_DDA_INCREMENT);
1025                 h_dda = compute_initial_dda(win->x);
1026                 v_dda = compute_initial_dda(win->y);
1027                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1028                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1029
1030                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1031                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1032                 tegra_dc_writel(dc,
1033                                 (unsigned long)win->phys_addr +
1034                                 (unsigned long)win->offset,
1035                                 DC_WINBUF_START_ADDR);
1036
1037                 if (!yuvp) {
1038                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1039                 } else {
1040                         tegra_dc_writel(dc,
1041                                         (unsigned long)win->phys_addr +
1042                                         (unsigned long)win->offset_u,
1043                                         DC_WINBUF_START_ADDR_U);
1044                         tegra_dc_writel(dc,
1045                                         (unsigned long)win->phys_addr +
1046                                         (unsigned long)win->offset_v,
1047                                         DC_WINBUF_START_ADDR_V);
1048                         tegra_dc_writel(dc,
1049                                         LINE_STRIDE(win->stride) |
1050                                         UV_LINE_STRIDE(win->stride_uv),
1051                                         DC_WIN_LINE_STRIDE);
1052                 }
1053
1054                 h_offset = win->x;
1055                 if (invert_h) {
1056                         h_offset.full += win->w.full - dfixed_const(1);
1057                 }
1058
1059                 v_offset = win->y;
1060                 if (invert_v) {
1061                         v_offset.full += win->h.full - dfixed_const(1);
1062                 }
1063
1064                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1065                                 DC_WINBUF_ADDR_H_OFFSET);
1066                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1067                                 DC_WINBUF_ADDR_V_OFFSET);
1068
1069                 if (WIN_IS_TILED(win))
1070                         tegra_dc_writel(dc,
1071                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1072                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1073                                         DC_WIN_BUFFER_ADDR_MODE);
1074                 else
1075                         tegra_dc_writel(dc,
1076                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1077                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1078                                         DC_WIN_BUFFER_ADDR_MODE);
1079
1080                 val = WIN_ENABLE;
1081                 if (yuvp)
1082                         val |= CSC_ENABLE;
1083                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1084                         val |= COLOR_EXPAND;
1085
1086                 if (filter_h)
1087                         val |= H_FILTER_ENABLE;
1088                 if (filter_v)
1089                         val |= V_FILTER_ENABLE;
1090
1091                 if (invert_h)
1092                         val |= H_DIRECTION_DECREMENT;
1093                 if (invert_v)
1094                         val |= V_DIRECTION_DECREMENT;
1095
1096                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1097
1098                 win->dirty = no_vsync ? 0 : 1;
1099         }
1100
1101         if (update_blend) {
1102                 tegra_dc_set_blending(dc, &dc->blend);
1103                 for (i = 0; i < DC_N_WINDOWS; i++) {
1104                         if (!no_vsync)
1105                                 dc->windows[i].dirty = 1;
1106                         update_mask |= WIN_A_ACT_REQ << i;
1107                 }
1108         }
1109
1110         tegra_dc_set_dynamic_emc(windows, n);
1111
1112         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1113
1114         if (!no_vsync) {
1115                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1116                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1117                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1118         } else {
1119                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1120                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1121
1122                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1123         }
1124
1125         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1126
1127         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1128                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1129
1130         mutex_unlock(&dc->lock);
1131
1132         return 0;
1133 }
1134 EXPORT_SYMBOL(tegra_dc_update_windows);
1135
1136 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1137 {
1138         return dc->syncpt[i].id;
1139 }
1140 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1141
1142 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1143 {
1144         u32 max;
1145
1146         mutex_lock(&dc->lock);
1147         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1148                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1149         dc->syncpt[i].max = max;
1150         mutex_unlock(&dc->lock);
1151
1152         return max;
1153 }
1154
1155 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1156 {
1157         mutex_lock(&dc->lock);
1158         if ( dc->enabled )
1159                 while (dc->syncpt[i].min < val) {
1160                         dc->syncpt[i].min++;
1161                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1162                                         dc->syncpt[i].id);
1163                 }
1164         mutex_unlock(&dc->lock);
1165 }
1166
1167 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1168                                              int n)
1169 {
1170         int i;
1171
1172         for (i = 0; i < n; i++) {
1173                 if (windows[i]->dirty)
1174                         return false;
1175         }
1176
1177         return true;
1178 }
1179
1180 /* does not support syncing windows on multiple dcs in one call */
1181 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1182 {
1183         if (n < 1 || n > DC_N_WINDOWS)
1184                 return -EINVAL;
1185
1186         if (!windows[0]->dc->enabled)
1187                 return -EFAULT;
1188
1189         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1190                                          tegra_dc_windows_are_clean(windows, n),
1191                                          HZ);
1192 }
1193 EXPORT_SYMBOL(tegra_dc_sync_windows);
1194
1195 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1196 {
1197 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1198         return clk_get_rate(dc->clk);
1199 #else
1200         return 27000000;
1201 #endif
1202 }
1203
1204 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1205 {
1206         unsigned long rate;
1207         unsigned long div;
1208
1209         rate = tegra_dc_clk_get_rate(dc);
1210
1211         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1212
1213         if (div < 2)
1214                 return 0;
1215
1216         return rate * 2 / div;
1217 }
1218
1219 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1220 {
1221         int pclk;
1222
1223         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1224                 struct clk *parent_clk =
1225                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1226
1227                 if (clk_get_parent(clk) != parent_clk)
1228                         clk_set_parent(clk, parent_clk);
1229         }
1230
1231         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1232                 unsigned long rate;
1233                 struct clk *parent_clk =
1234                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1235                 struct clk *base_clk = clk_get_parent(parent_clk);
1236
1237                 /* needs to match tegra_dc_hdmi_supported_modes[]
1238                 and tegra_pll_d_freq_table[] */
1239                 if (dc->mode.pclk > 70000000)
1240                         rate = 594000000;
1241                 else if (dc->mode.pclk > 25200000)
1242                         rate = 216000000;
1243                 else
1244                         rate = 504000000;
1245
1246                 if (rate != clk_get_rate(base_clk))
1247                         clk_set_rate(base_clk, rate);
1248
1249                 if (clk_get_parent(clk) != parent_clk)
1250                         clk_set_parent(clk, parent_clk);
1251         }
1252
1253         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1254                 unsigned long rate;
1255                 struct clk *parent_clk;
1256                 struct clk *base_clk;
1257
1258                 if (clk == dc->clk) {
1259                         parent_clk = clk_get_sys(NULL,
1260                                         dc->out->parent_clk ? : "pll_d_out0");
1261                         base_clk = clk_get_parent(parent_clk);
1262                         tegra_clk_cfg_ex(base_clk,
1263                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1264                 } else {
1265                         if (dc->pdata->default_out->dsi->dsi_instance) {
1266                                 parent_clk = clk_get_sys(NULL,
1267                                         dc->out->parent_clk ? : "pll_d2_out0");
1268                                 base_clk = clk_get_parent(parent_clk);
1269                                 tegra_clk_cfg_ex(base_clk,
1270                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1271                         } else {
1272                                 parent_clk = clk_get_sys(NULL,
1273                                         dc->out->parent_clk ? : "pll_d_out0");
1274                                 base_clk = clk_get_parent(parent_clk);
1275                                 tegra_clk_cfg_ex(base_clk,
1276                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1277                         }
1278                 }
1279
1280                 rate = dc->mode.pclk;
1281                 if (rate != clk_get_rate(base_clk))
1282                         clk_set_rate(base_clk, rate);
1283
1284                 if (clk_get_parent(clk) != parent_clk)
1285                         clk_set_parent(clk, parent_clk);
1286         }
1287
1288         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1289         tegra_dvfs_set_rate(clk, pclk);
1290 }
1291
1292 /* return non-zero if constraint is violated */
1293 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1294 {
1295         long a, b;
1296
1297         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1298         a = 0;
1299
1300         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1301         b = mode->h_front_porch - 1;
1302
1303         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1304         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1305                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1306         /* check Constraint 1 and 6 */
1307         if (a > b)
1308                 return 1;
1309
1310         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1311         if (mode->h_sync_width < 1)
1312                 return 4;
1313
1314         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1315         if (mode->h_active < 16)
1316                 return 7;
1317
1318         if (href) {
1319                 if (b > a && a % 2)
1320                         *href = a + 1; /* use smallest even value */
1321                 else
1322                         *href = a; /* even or only possible value */
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1329 {
1330         long a;
1331         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1332
1333         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1334         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1335                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1336
1337         /* Constraint 6 */
1338         if (mode->v_front_porch < a + 1)
1339                 a = mode->v_front_porch - 1;
1340
1341         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1342         if (mode->v_sync_width < 1)
1343                 return 4;
1344
1345         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1346         if (mode->v_active < 16)
1347                 return 7;
1348
1349         if (vref)
1350                 *vref = a;
1351         return 0;
1352 }
1353
1354 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1355 {
1356         int ret;
1357         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1358         if (ret)
1359                 return ret;
1360         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1361         if (ret)
1362                 return ret;
1363
1364         return 0;
1365 }
1366
1367 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1368 {
1369         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1370         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1371                 return false;
1372
1373         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1374         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1375                 return false;
1376
1377         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1378          * (vertical blank). */
1379         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1380                 return false;
1381
1382         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1383         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1384                 return false;
1385
1386         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1387         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1388                 return false;
1389
1390         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1391          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1392         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1393                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1394                 return false;
1395
1396         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1397         if (mode->h_active < 16 || mode->v_active < 16)
1398                 return false;
1399
1400         return true;
1401 }
1402
1403 #ifdef DEBUG
1404 /* return in 1000ths of a Hertz */
1405 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1406 {
1407         long h_total, v_total, refresh;
1408         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1409                 m->h_sync_width;
1410         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1411                 m->v_sync_width;
1412         refresh = dc->pixel_clk / h_total;
1413         refresh *= 1000;
1414         refresh /= v_total;
1415         return refresh;
1416 }
1417
1418 static void print_mode(struct tegra_dc *dc,
1419                         const struct tegra_dc_mode *mode, const char *note)
1420 {
1421         if (mode) {
1422                 int refresh = calc_refresh(mode);
1423                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1424                         note ? note : "",
1425                         mode->h_active, mode->v_active,
1426                         refresh / 1000, refresh % 1000,
1427                         mode->pclk);
1428         }
1429 }
1430 #else /* !DEBUG */
1431 static inline void print_mode(struct tegra_dc *dc,
1432                         const struct tegra_dc_mode *mode, const char *note) { }
1433 #endif /* DEBUG */
1434
1435 static inline void enable_dc_irq(unsigned int irq)
1436 {
1437 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1438         enable_irq(irq);
1439 #else
1440         /* Always disable DC interrupts on FPGA. */
1441         disable_irq(irq);
1442 #endif
1443 }
1444
1445 static inline void disable_dc_irq(unsigned int irq)
1446 {
1447         disable_irq(irq);
1448 }
1449
1450 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1451 {
1452         unsigned long val;
1453         unsigned long rate;
1454         unsigned long div;
1455         unsigned long pclk;
1456
1457         print_mode(dc, mode, __func__);
1458
1459         /* use default EMC rate when switching modes */
1460         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1461         tegra_dc_program_bandwidth(dc);
1462
1463         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1464         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1465                         DC_DISP_REF_TO_SYNC);
1466         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1467                         DC_DISP_SYNC_WIDTH);
1468         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1469                         DC_DISP_BACK_PORCH);
1470         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1471                         DC_DISP_DISP_ACTIVE);
1472         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1473                         DC_DISP_FRONT_PORCH);
1474
1475         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1476                         DC_DISP_DATA_ENABLE_OPTIONS);
1477
1478         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1479         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1480                 val |= PIN1_LVS_OUTPUT;
1481         else
1482                 val &= ~PIN1_LVS_OUTPUT;
1483
1484         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1485                 val |= PIN1_LHS_OUTPUT;
1486         else
1487                 val &= ~PIN1_LHS_OUTPUT;
1488         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1489
1490         /* TODO: MIPI/CRT/HDMI clock cals */
1491
1492         val = DISP_DATA_FORMAT_DF1P1C;
1493
1494         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1495                 val |= DISP_DATA_ALIGNMENT_MSB;
1496         else
1497                 val |= DISP_DATA_ALIGNMENT_LSB;
1498
1499         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1500                 val |= DISP_DATA_ORDER_RED_BLUE;
1501         else
1502                 val |= DISP_DATA_ORDER_BLUE_RED;
1503
1504         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1505
1506         rate = tegra_dc_clk_get_rate(dc);
1507
1508         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1509         if (pclk < (mode->pclk / 100 * 99) ||
1510             pclk > (mode->pclk / 100 * 109)) {
1511                 dev_err(&dc->ndev->dev,
1512                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1513                         rate, mode->pclk,
1514                         pclk, (mode->pclk / 100 * 99),
1515                         (mode->pclk / 100 * 109));
1516                 return -EINVAL;
1517         }
1518
1519         div = (rate * 2 / pclk) - 2;
1520
1521         tegra_dc_writel(dc, 0x00010001,
1522                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1523         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1524                         DC_DISP_DISP_CLOCK_CONTROL);
1525
1526         dc->pixel_clk = dc->mode.pclk;
1527
1528         return 0;
1529 }
1530
1531
1532 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1533 {
1534         memcpy(&dc->mode, mode, sizeof(dc->mode));
1535
1536         print_mode(dc, mode, __func__);
1537
1538         return 0;
1539 }
1540 EXPORT_SYMBOL(tegra_dc_set_mode);
1541
1542 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1543                 const struct fb_videomode *fbmode, bool stereo_mode)
1544 {
1545         struct tegra_dc_mode mode;
1546
1547         if (!fbmode->pixclock)
1548                 return -EINVAL;
1549
1550         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1551         mode.h_sync_width = fbmode->hsync_len;
1552         mode.v_sync_width = fbmode->vsync_len;
1553         mode.h_back_porch = fbmode->left_margin;
1554         mode.v_back_porch = fbmode->upper_margin;
1555         mode.h_active = fbmode->xres;
1556         mode.v_active = fbmode->yres;
1557         mode.h_front_porch = fbmode->right_margin;
1558         mode.v_front_porch = fbmode->lower_margin;
1559         mode.stereo_mode = stereo_mode;
1560         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1561                 /* HDMI controller requires h_ref=1, v_ref=1 */
1562                 mode.h_ref_to_sync = 1;
1563                 mode.v_ref_to_sync = 1;
1564         } else {
1565                 calc_ref_to_sync(&mode);
1566         }
1567         if (!check_ref_to_sync(&mode)) {
1568                 dev_err(&dc->ndev->dev,
1569                                 "Display timing doesn't meet restrictions.\n");
1570                 return -EINVAL;
1571         }
1572         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1573                 mode.h_active, mode.v_active, mode.pclk,
1574                 mode.h_ref_to_sync, mode.v_ref_to_sync
1575         );
1576
1577         if (mode.stereo_mode) {
1578                 mode.pclk *= 2;
1579                 /* total v_active = yres*2 + activespace */
1580                 mode.v_active = fbmode->yres*2 +
1581                                 fbmode->vsync_len +
1582                                 fbmode->upper_margin +
1583                                 fbmode->lower_margin;
1584         }
1585
1586         mode.flags = 0;
1587
1588         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1589                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1590
1591         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1592                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1593
1594         return tegra_dc_set_mode(dc, &mode);
1595 }
1596 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1597
1598 void
1599 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1600 {
1601         unsigned int ctrl;
1602         unsigned long out_sel;
1603         unsigned long cmd_state;
1604
1605         mutex_lock(&dc->lock);
1606         if (!dc->enabled) {
1607                 mutex_unlock(&dc->lock);
1608                 return;
1609         }
1610
1611         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1612                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1613                 cfg->clk_select);
1614
1615         /* The new value should be effected immediately */
1616         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1617         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1618
1619         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1620                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1621         else
1622                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1623
1624         switch (cfg->which_pwm) {
1625         case TEGRA_PWM_PM0:
1626                 /* Select the LM0 on PM0 */
1627                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1628                 out_sel &= ~(7 << 0);
1629                 out_sel |= (3 << 0);
1630                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1631                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1632                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1633                 break;
1634         case TEGRA_PWM_PM1:
1635                 /* Select the LM1 on PM1 */
1636                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1637                 out_sel &= ~(7 << 4);
1638                 out_sel |= (3 << 4);
1639                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1640                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1641                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1642                 break;
1643         default:
1644                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1645                 break;
1646         }
1647         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1648         mutex_unlock(&dc->lock);
1649 }
1650 EXPORT_SYMBOL(tegra_dc_config_pwm);
1651
1652 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1653                                 const struct tegra_dc_out_pin *pins,
1654                                 const unsigned int n_pins)
1655 {
1656         unsigned int i;
1657
1658         int name;
1659         int pol;
1660
1661         u32 pol1, pol3;
1662
1663         u32 set1, unset1;
1664         u32 set3, unset3;
1665
1666         set1 = set3 = unset1 = unset3 = 0;
1667
1668         for (i = 0; i < n_pins; i++) {
1669                 name = (pins + i)->name;
1670                 pol  = (pins + i)->pol;
1671
1672                 /* set polarity by name */
1673                 switch (name) {
1674                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1675                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1676                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1677                         else
1678                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1679                         break;
1680                 case TEGRA_DC_OUT_PIN_H_SYNC:
1681                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1682                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1683                         else
1684                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1685                         break;
1686                 case TEGRA_DC_OUT_PIN_V_SYNC:
1687                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1688                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1689                         else
1690                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1691                         break;
1692                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1693                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1694                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1695                         else
1696                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1697                         break;
1698                 default:
1699                         printk("Invalid argument in function %s\n",
1700                                __FUNCTION__);
1701                         break;
1702                 }
1703         }
1704
1705         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1706         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1707
1708         pol1 |= set1;
1709         pol1 &= ~unset1;
1710
1711         pol3 |= set3;
1712         pol3 &= ~unset3;
1713
1714         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1715         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1716 }
1717
1718 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1719 {
1720         dc->out = out;
1721
1722         if (out->n_modes > 0)
1723                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1724
1725         switch (out->type) {
1726         case TEGRA_DC_OUT_RGB:
1727                 dc->out_ops = &tegra_dc_rgb_ops;
1728                 break;
1729
1730         case TEGRA_DC_OUT_HDMI:
1731                 dc->out_ops = &tegra_dc_hdmi_ops;
1732                 break;
1733
1734         case TEGRA_DC_OUT_DSI:
1735                 dc->out_ops = &tegra_dc_dsi_ops;
1736                 break;
1737
1738         default:
1739                 dc->out_ops = NULL;
1740                 break;
1741         }
1742
1743         if (dc->out_ops && dc->out_ops->init)
1744                 dc->out_ops->init(dc);
1745
1746 }
1747
1748 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1749 {
1750         if (dc->out)
1751                 return dc->out->height;
1752         else
1753                 return 0;
1754 }
1755 EXPORT_SYMBOL(tegra_dc_get_out_height);
1756
1757 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1758 {
1759         if (dc->out)
1760                 return dc->out->width;
1761         else
1762                 return 0;
1763 }
1764 EXPORT_SYMBOL(tegra_dc_get_out_width);
1765
1766 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1767 {
1768         if (dc->out && dc->out->max_pixclock)
1769                 return dc->out->max_pixclock;
1770         else
1771                 return 0;
1772 }
1773 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1774
1775 void tegra_dc_enable_crc(struct tegra_dc *dc)
1776 {
1777         u32 val;
1778         tegra_dc_io_start(dc);
1779
1780         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1781                 CRC_ENABLE_ENABLE;
1782         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1783         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1784         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1785 }
1786
1787 void tegra_dc_disable_crc(struct tegra_dc *dc)
1788 {
1789         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1790         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1791         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1792
1793         tegra_dc_io_end(dc);
1794 }
1795
1796 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1797 {
1798         int crc = 0;
1799
1800         if(!dc) {
1801                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1802                 goto crc_error;
1803         }
1804
1805         /* TODO: Replace mdelay with code to sync VBlANK, since
1806          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1807         mdelay(TEGRA_CRC_LATCHED_DELAY);
1808
1809         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1810 crc_error:
1811         return crc;
1812 }
1813
1814 static void tegra_dc_vblank(struct work_struct *work)
1815 {
1816         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1817         bool nvsd_updated = false;
1818
1819         mutex_lock(&dc->lock);
1820
1821         /* update EMC clock if calculated bandwidth has changed */
1822         tegra_dc_program_bandwidth(dc);
1823
1824         /* Update the SD brightness */
1825         nvsd_updated = nvsd_update_brightness(dc);
1826
1827         mutex_unlock(&dc->lock);
1828
1829         /* Do the actual brightness update outside of the mutex */
1830         if (nvsd_updated && dc->out->sd_settings &&
1831             dc->out->sd_settings->bl_device) {
1832
1833                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1834                 struct backlight_device *bl = platform_get_drvdata(pdev);
1835                 if (bl)
1836                         backlight_update_status(bl);
1837         }
1838 }
1839
1840 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1841 {
1842 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1843         struct tegra_dc *dc = ptr;
1844         unsigned long status;
1845         unsigned long val;
1846         unsigned long underflow_mask;
1847         int i;
1848
1849         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1850         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1851
1852         /*
1853          * Overlays can get thier internal state corrupted during and underflow
1854          * condition.  The only way to fix this state is to reset the DC.
1855          * if we get 4 consecutive frames with underflows, assume we're
1856          * hosed and reset.
1857          */
1858         underflow_mask = status & ALL_UF_INT;
1859
1860         if (underflow_mask) {
1861                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1862                 val |= V_BLANK_INT;
1863                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1864                 dc->underflow_mask |= underflow_mask;
1865                 dc->stats.underflows++;
1866                 if (status & WIN_A_UF_INT)
1867                         dc->stats.underflows_a++;
1868                 if (status & WIN_B_UF_INT)
1869                         dc->stats.underflows_b++;
1870                 if (status & WIN_C_UF_INT)
1871                         dc->stats.underflows_c++;
1872         }
1873
1874         if (status & V_BLANK_INT) {
1875                 int i;
1876
1877                 /* Check for any underflow reset conditions */
1878                 for (i = 0; i< DC_N_WINDOWS; i++) {
1879                         if (dc->underflow_mask & (WIN_A_UF_INT <<i)) {
1880                                 dc->windows[i].underflows++;
1881
1882 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1883                                 if (dc->windows[i].underflows > 4)
1884                                         schedule_work(&dc->reset_work);
1885 #endif
1886                         } else {
1887                                 dc->windows[i].underflows = 0;
1888                         }
1889                 }
1890
1891                 if (!dc->underflow_mask) {
1892                         /* If we have no underflow to check, go ahead
1893                            and disable the interrupt */
1894                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1895                         val &= ~V_BLANK_INT;
1896                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1897                 }
1898
1899                 /* Clear the underflow mask now that we've checked it. */
1900                 dc->underflow_mask = 0;
1901
1902                 /* Schedule any additional bottom-half vblank actvities. */
1903                 schedule_work(&dc->vblank_work);
1904
1905                 /* Mark the vblank as complete. */
1906                 complete(&dc->vblank_complete);
1907         }
1908
1909         if (status & FRAME_END_INT) {
1910                 int completed = 0;
1911                 int dirty = 0;
1912
1913                 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1914                 for (i = 0; i < DC_N_WINDOWS; i++) {
1915                         if (!(val & (WIN_A_UPDATE << i))) {
1916                                 dc->windows[i].dirty = 0;
1917                                 completed = 1;
1918                         } else {
1919                                 dirty = 1;
1920                         }
1921                 }
1922
1923                 if (!dirty) {
1924                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1925                         val &= ~FRAME_END_INT;
1926                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1927                 }
1928
1929                 if (completed) {
1930                         if (!dirty) {
1931                                 /* With the last completed window, go ahead
1932                                    and enable the vblank interrupt for nvsd. */
1933                                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1934                                 val |= V_BLANK_INT;
1935                                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1936
1937                                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1938                                 val |= V_BLANK_INT;
1939                                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1940                         }
1941
1942                         /* Wake up the workqueue regardless. */
1943                         wake_up(&dc->wq);
1944                 }
1945         }
1946
1947         return IRQ_HANDLED;
1948 #else /* CONFIG_TEGRA_SILICON_PLATFORM */
1949         return IRQ_NONE;
1950 #endif /* !CONFIG_TEGRA_SILICON_PLATFORM */
1951 }
1952
1953 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1954 {
1955         u32 color_control;
1956
1957         switch (dc->out->depth) {
1958         case 3:
1959                 color_control = BASE_COLOR_SIZE111;
1960                 break;
1961
1962         case 6:
1963                 color_control = BASE_COLOR_SIZE222;
1964                 break;
1965
1966         case 8:
1967                 color_control = BASE_COLOR_SIZE332;
1968                 break;
1969
1970         case 9:
1971                 color_control = BASE_COLOR_SIZE333;
1972                 break;
1973
1974         case 12:
1975                 color_control = BASE_COLOR_SIZE444;
1976                 break;
1977
1978         case 15:
1979                 color_control = BASE_COLOR_SIZE555;
1980                 break;
1981
1982         case 16:
1983                 color_control = BASE_COLOR_SIZE565;
1984                 break;
1985
1986         case 18:
1987                 color_control = BASE_COLOR_SIZE666;
1988                 break;
1989
1990         default:
1991                 color_control = BASE_COLOR_SIZE888;
1992                 break;
1993         }
1994
1995         switch (dc->out->dither) {
1996         case TEGRA_DC_DISABLE_DITHER:
1997                 color_control |= DITHER_CONTROL_DISABLE;
1998                 break;
1999         case TEGRA_DC_ORDERED_DITHER:
2000                 color_control |= DITHER_CONTROL_ORDERED;
2001                 break;
2002         case TEGRA_DC_ERRDIFF_DITHER:
2003                 /* The line buffer for error-diffusion dither is limited
2004                  * to 640 pixels per line. This limits the maximum
2005                  * horizontal active area size to 640 pixels when error
2006                  * diffusion is enabled.
2007                  */
2008                 BUG_ON(dc->mode.h_active > 640);
2009                 color_control |= DITHER_CONTROL_ERRDIFF;
2010                 break;
2011         }
2012
2013         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2014 }
2015
2016 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2017 {
2018         u32 syncpt_id;
2019
2020         switch (dc->ndev->id) {
2021         case 0:
2022                 switch (idx) {
2023                 case 0:
2024                         syncpt_id = NVSYNCPT_DISP0_A;
2025                         break;
2026                 case 1:
2027                         syncpt_id = NVSYNCPT_DISP0_B;
2028                         break;
2029                 case 2:
2030                         syncpt_id = NVSYNCPT_DISP0_C;
2031                         break;
2032                 default:
2033                         BUG();
2034                         break;
2035                 }
2036                 break;
2037         case 1:
2038                 switch (idx) {
2039                 case 0:
2040                         syncpt_id = NVSYNCPT_DISP1_A;
2041                         break;
2042                 case 1:
2043                         syncpt_id = NVSYNCPT_DISP1_B;
2044                         break;
2045                 case 2:
2046                         syncpt_id = NVSYNCPT_DISP1_C;
2047                         break;
2048                 default:
2049                         BUG();
2050                         break;
2051                 }
2052                 break;
2053         default:
2054                 BUG();
2055                 break;
2056         }
2057
2058         return syncpt_id;
2059 }
2060
2061 static void tegra_dc_init(struct tegra_dc *dc)
2062 {
2063         int i;
2064
2065         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2066         if (dc->ndev->id == 0) {
2067                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2068                                       TEGRA_MC_PRIO_MED);
2069                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2070                                       TEGRA_MC_PRIO_MED);
2071                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2072                                       TEGRA_MC_PRIO_MED);
2073                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2074                                       TEGRA_MC_PRIO_MED);
2075                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2076                                       TEGRA_MC_PRIO_HIGH);
2077         } else if (dc->ndev->id == 1) {
2078                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2079                                       TEGRA_MC_PRIO_MED);
2080                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2081                                       TEGRA_MC_PRIO_MED);
2082                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2083                                       TEGRA_MC_PRIO_MED);
2084                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2085                                       TEGRA_MC_PRIO_MED);
2086                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2087                                       TEGRA_MC_PRIO_HIGH);
2088         }
2089         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2090                         DC_CMD_CONT_SYNCPT_VSYNC);
2091         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2092         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2093         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2094         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2095
2096         tegra_dc_writel(dc, (FRAME_END_INT |
2097                              V_BLANK_INT |
2098                              ALL_UF_INT), DC_CMD_INT_MASK);
2099         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_ENABLE);
2100
2101         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2102
2103         tegra_dc_set_color_control(dc);
2104         for (i = 0; i < DC_N_WINDOWS; i++) {
2105                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2106                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2107                 tegra_dc_init_csc_defaults(&dc->windows[i].csc);
2108                 tegra_dc_set_csc(dc, &dc->windows[i].csc);
2109                 tegra_dc_set_scaling_filter(dc);
2110         }
2111
2112
2113         for (i = 0; i < dc->n_windows; i++) {
2114                 u32 syncpt = get_syncpt(dc, i);
2115
2116                 dc->syncpt[i].id = syncpt;
2117
2118                 dc->syncpt[i].min = dc->syncpt[i].max =
2119                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2120         }
2121
2122         print_mode(dc, &dc->mode, __func__);
2123
2124         if (dc->mode.pclk)
2125                 tegra_dc_program_mode(dc, &dc->mode);
2126
2127         /* Initialize SD AFTER the modeset.
2128            nvsd_init handles the sd_settings = NULL case. */
2129         nvsd_init(dc, dc->out->sd_settings);
2130 }
2131
2132 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2133 {
2134         if (dc->out->enable)
2135                 dc->out->enable();
2136
2137         tegra_dc_setup_clk(dc, dc->clk);
2138         tegra_periph_reset_assert(dc->clk);
2139         clk_enable(dc->clk);
2140         clk_enable(dc->emc_clk);
2141         enable_dc_irq(dc->irq);
2142
2143         tegra_dc_init(dc);
2144
2145         if (dc->out_ops && dc->out_ops->enable)
2146                 dc->out_ops->enable(dc);
2147
2148         if (dc->out->out_pins)
2149                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2150                                             dc->out->n_out_pins);
2151
2152         if (dc->out->postpoweron)
2153                 dc->out->postpoweron();
2154
2155         /* force a full blending update */
2156         dc->blend.z[0] = -1;
2157
2158         tegra_dc_ext_enable(dc->ext);
2159
2160         return true;
2161 }
2162
2163 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2164 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2165 {
2166         if (dc->out->enable)
2167                 dc->out->enable();
2168
2169         tegra_dc_setup_clk(dc, dc->clk);
2170         clk_enable(dc->clk);
2171         clk_enable(dc->emc_clk);
2172
2173         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2174                 mutex_lock(&tegra_dcs[1]->lock);
2175                 disable_irq(tegra_dcs[1]->irq);
2176         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2177                 mutex_lock(&tegra_dcs[0]->lock);
2178                 disable_irq(tegra_dcs[0]->irq);
2179         }
2180
2181         msleep(5);
2182         tegra_periph_reset_assert(dc->clk);
2183         msleep(2);
2184 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2185         tegra_periph_reset_deassert(dc->clk);
2186         msleep(1);
2187 #endif
2188
2189         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2190                 enable_dc_irq(tegra_dcs[1]->irq);
2191                 mutex_unlock(&tegra_dcs[1]->lock);
2192         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2193                 enable_dc_irq(tegra_dcs[0]->irq);
2194                 mutex_unlock(&tegra_dcs[0]->lock);
2195         }
2196
2197         enable_dc_irq(dc->irq);
2198
2199         tegra_dc_init(dc);
2200
2201         if (dc->out_ops && dc->out_ops->enable)
2202                 dc->out_ops->enable(dc);
2203
2204         if (dc->out->out_pins)
2205                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2206                                             dc->out->n_out_pins);
2207
2208         if (dc->out->postpoweron)
2209                 dc->out->postpoweron();
2210
2211         /* force a full blending update */
2212         dc->blend.z[0] = -1;
2213
2214         return true;
2215 }
2216 #endif
2217
2218 static bool _tegra_dc_enable(struct tegra_dc *dc)
2219 {
2220         if (dc->mode.pclk == 0)
2221                 return false;
2222
2223         if (!dc->out)
2224                 return false;
2225
2226         tegra_dc_io_start(dc);
2227
2228         return _tegra_dc_controller_enable(dc);
2229 }
2230
2231 void tegra_dc_enable(struct tegra_dc *dc)
2232 {
2233         mutex_lock(&dc->lock);
2234
2235         if (!dc->enabled)
2236                 dc->enabled = _tegra_dc_enable(dc);
2237
2238         mutex_unlock(&dc->lock);
2239 }
2240
2241 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2242 {
2243         unsigned i;
2244
2245         disable_irq(dc->irq);
2246
2247         if (dc->out_ops && dc->out_ops->disable)
2248                 dc->out_ops->disable(dc);
2249
2250         clk_disable(dc->emc_clk);
2251         clk_disable(dc->clk);
2252         tegra_dvfs_set_rate(dc->clk, 0);
2253
2254         for (i = 0; i < DC_N_WINDOWS; i++) {
2255                 struct tegra_dc_win *w = &dc->windows[i];
2256                 w->bandwidth = 0;
2257                 w->new_bandwidth = 0;
2258         }
2259
2260         if (dc->out && dc->out->disable)
2261                 dc->out->disable();
2262
2263         /* flush any pending syncpt waits */
2264         for (i = 0; i < dc->n_windows; i++) {
2265                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2266                         dc->syncpt[i].min++;
2267                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2268                                 dc->syncpt[i].id);
2269                 }
2270         }
2271 }
2272
2273 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2274 {
2275 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2276         u32 val;
2277         if (dc->enabled)  {
2278                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2279                 if (enable)
2280                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2281                 else
2282                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2283                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2284         }
2285 #endif
2286 }
2287
2288 bool tegra_dc_stats_get(struct tegra_dc *dc)
2289 {
2290 #if 0 /* right now it is always enabled */
2291         u32 val;
2292         bool res;
2293
2294         if (dc->enabled)  {
2295                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2296                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2297         } else {
2298                 res = false;
2299         }
2300
2301         return res;
2302 #endif
2303         return true;
2304 }
2305
2306 static void _tegra_dc_disable(struct tegra_dc *dc)
2307 {
2308         _tegra_dc_controller_disable(dc);
2309         tegra_dc_io_end(dc);
2310 }
2311
2312 void tegra_dc_disable(struct tegra_dc *dc)
2313 {
2314         if (dc->overlay)
2315                 tegra_overlay_disable(dc->overlay);
2316
2317         tegra_dc_ext_disable(dc->ext);
2318
2319         mutex_lock(&dc->lock);
2320
2321         if (dc->enabled) {
2322                 dc->enabled = false;
2323
2324                 if (!dc->suspended)
2325                         _tegra_dc_disable(dc);
2326         }
2327
2328         mutex_unlock(&dc->lock);
2329 }
2330
2331 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2332 static void tegra_dc_reset_worker(struct work_struct *work)
2333 {
2334         struct tegra_dc *dc =
2335                 container_of(work, struct tegra_dc, reset_work);
2336
2337         unsigned long val = 0;
2338
2339         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2340
2341         tegra_dc_ext_disable(dc->ext);
2342
2343         mutex_lock(&shared_lock);
2344         mutex_lock(&dc->lock);
2345
2346         if (dc->enabled == false)
2347                 goto unlock;
2348
2349         dc->enabled = false;
2350
2351         /*
2352          * off host read bus
2353          */
2354         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2355         val &= ~(0x00000100);
2356         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2357
2358         /*
2359          * set DC to STOP mode
2360          */
2361         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2362
2363         msleep(10);
2364
2365         _tegra_dc_controller_disable(dc);
2366
2367         /* _tegra_dc_controller_reset_enable deasserts reset */
2368         _tegra_dc_controller_reset_enable(dc);
2369
2370         dc->enabled = true;
2371 unlock:
2372         mutex_unlock(&dc->lock);
2373         mutex_unlock(&shared_lock);
2374 }
2375 #endif
2376
2377
2378 static int tegra_dc_probe(struct nvhost_device *ndev)
2379 {
2380         struct tegra_dc *dc;
2381         struct clk *clk;
2382         struct clk *emc_clk;
2383         struct resource *res;
2384         struct resource *base_res;
2385         struct resource *fb_mem = NULL;
2386         int ret = 0;
2387         void __iomem *base;
2388         int irq;
2389         int i;
2390
2391         if (!ndev->dev.platform_data) {
2392                 dev_err(&ndev->dev, "no platform data\n");
2393                 return -ENOENT;
2394         }
2395
2396         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2397         if (!dc) {
2398                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2399                 return -ENOMEM;
2400         }
2401
2402         irq = nvhost_get_irq_byname(ndev, "irq");
2403         if (irq <= 0) {
2404                 dev_err(&ndev->dev, "no irq\n");
2405                 ret = -ENOENT;
2406                 goto err_free;
2407         }
2408
2409         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2410         if (!res) {
2411                 dev_err(&ndev->dev, "no mem resource\n");
2412                 ret = -ENOENT;
2413                 goto err_free;
2414         }
2415
2416         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2417         if (!base_res) {
2418                 dev_err(&ndev->dev, "request_mem_region failed\n");
2419                 ret = -EBUSY;
2420                 goto err_free;
2421         }
2422
2423         base = ioremap(res->start, resource_size(res));
2424         if (!base) {
2425                 dev_err(&ndev->dev, "registers can't be mapped\n");
2426                 ret = -EBUSY;
2427                 goto err_release_resource_reg;
2428         }
2429
2430         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2431
2432         clk = clk_get(&ndev->dev, NULL);
2433         if (IS_ERR_OR_NULL(clk)) {
2434                 dev_err(&ndev->dev, "can't get clock\n");
2435                 ret = -ENOENT;
2436                 goto err_iounmap_reg;
2437         }
2438
2439         emc_clk = clk_get(&ndev->dev, "emc");
2440         if (IS_ERR_OR_NULL(emc_clk)) {
2441                 dev_err(&ndev->dev, "can't get emc clock\n");
2442                 ret = -ENOENT;
2443                 goto err_put_clk;
2444         }
2445
2446         dc->clk = clk;
2447         dc->emc_clk = emc_clk;
2448
2449         dc->base_res = base_res;
2450         dc->base = base;
2451         dc->irq = irq;
2452         dc->ndev = ndev;
2453         dc->pdata = ndev->dev.platform_data;
2454
2455         /*
2456          * The emc is a shared clock, it will be set based on
2457          * the requirements for each user on the bus.
2458          */
2459         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2460         clk_set_rate(emc_clk, dc->emc_clk_rate);
2461
2462         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2463                 dc->enabled = true;
2464
2465         mutex_init(&dc->lock);
2466         init_completion(&dc->vblank_complete);
2467         init_waitqueue_head(&dc->wq);
2468 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2469         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2470 #endif
2471         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2472
2473         dc->n_windows = DC_N_WINDOWS;
2474         for (i = 0; i < dc->n_windows; i++) {
2475                 dc->windows[i].idx = i;
2476                 dc->windows[i].dc = dc;
2477         }
2478
2479         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2480                         dev_name(&ndev->dev), dc)) {
2481                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2482                 ret = -EBUSY;
2483                 goto err_put_emc_clk;
2484         }
2485
2486         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2487         disable_dc_irq(dc->irq);
2488
2489         ret = tegra_dc_set(dc, ndev->id);
2490         if (ret < 0) {
2491                 dev_err(&ndev->dev, "can't add dc\n");
2492                 goto err_free_irq;
2493         }
2494
2495         nvhost_set_drvdata(ndev, dc);
2496
2497         if (dc->pdata->default_out)
2498                 tegra_dc_set_out(dc, dc->pdata->default_out);
2499         else
2500                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2501
2502         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2503                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2504
2505         dc->ext = tegra_dc_ext_register(ndev, dc);
2506         if (IS_ERR_OR_NULL(dc->ext)) {
2507                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2508                 dc->ext = NULL;
2509         }
2510
2511         mutex_lock(&dc->lock);
2512         if (dc->enabled)
2513                 _tegra_dc_enable(dc);
2514         mutex_unlock(&dc->lock);
2515
2516         tegra_dc_create_debugfs(dc);
2517
2518         dev_info(&ndev->dev, "probed\n");
2519
2520         if (dc->pdata->fb) {
2521                 if (dc->pdata->fb->bits_per_pixel == -1) {
2522                         unsigned long fmt;
2523                         tegra_dc_writel(dc,
2524                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2525                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2526
2527                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2528                         dc->pdata->fb->bits_per_pixel =
2529                                 tegra_dc_fmt_bpp(fmt);
2530                 }
2531
2532                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2533                 if (IS_ERR_OR_NULL(dc->fb))
2534                         dc->fb = NULL;
2535         }
2536
2537         if (dc->fb) {
2538                 dc->overlay = tegra_overlay_register(ndev, dc);
2539                 if (IS_ERR_OR_NULL(dc->overlay))
2540                         dc->overlay = NULL;
2541         }
2542
2543         if (dc->out && dc->out->hotplug_init)
2544                 dc->out->hotplug_init();
2545
2546         if (dc->out_ops && dc->out_ops->detect)
2547                 dc->out_ops->detect(dc);
2548         else
2549                 dc->connected = true;
2550
2551         tegra_dc_create_sysfs(&dc->ndev->dev);
2552
2553         return 0;
2554
2555 err_free_irq:
2556         free_irq(irq, dc);
2557 err_put_emc_clk:
2558         clk_put(emc_clk);
2559 err_put_clk:
2560         clk_put(clk);
2561 err_iounmap_reg:
2562         iounmap(base);
2563         if (fb_mem)
2564                 release_resource(fb_mem);
2565 err_release_resource_reg:
2566         release_resource(base_res);
2567 err_free:
2568         kfree(dc);
2569
2570         return ret;
2571 }
2572
2573 static int tegra_dc_remove(struct nvhost_device *ndev)
2574 {
2575         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2576
2577         tegra_dc_remove_sysfs(&dc->ndev->dev);
2578         tegra_dc_remove_debugfs(dc);
2579
2580         if (dc->overlay) {
2581                 tegra_overlay_unregister(dc->overlay);
2582         }
2583
2584         if (dc->fb) {
2585                 tegra_fb_unregister(dc->fb);
2586                 if (dc->fb_mem)
2587                         release_resource(dc->fb_mem);
2588         }
2589
2590         tegra_dc_ext_disable(dc->ext);
2591
2592         if (dc->ext)
2593                 tegra_dc_ext_unregister(dc->ext);
2594
2595         if (dc->enabled)
2596                 _tegra_dc_disable(dc);
2597
2598         free_irq(dc->irq, dc);
2599         clk_put(dc->emc_clk);
2600         clk_put(dc->clk);
2601         iounmap(dc->base);
2602         if (dc->fb_mem)
2603                 release_resource(dc->base_res);
2604         kfree(dc);
2605         tegra_dc_set(NULL, ndev->id);
2606         return 0;
2607 }
2608
2609 #ifdef CONFIG_PM
2610 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2611 {
2612         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2613
2614         dev_info(&ndev->dev, "suspend\n");
2615
2616         if (dc->overlay)
2617                 tegra_overlay_disable(dc->overlay);
2618
2619         tegra_dc_ext_disable(dc->ext);
2620
2621         mutex_lock(&dc->lock);
2622
2623         if (dc->out_ops && dc->out_ops->suspend)
2624                 dc->out_ops->suspend(dc);
2625
2626         if (dc->enabled) {
2627                 _tegra_dc_disable(dc);
2628
2629                 dc->suspended = true;
2630         }
2631
2632         if (dc->out && dc->out->postsuspend) {
2633                 dc->out->postsuspend();
2634                 msleep(100); /* avoid resume event due to voltage falling */
2635         }
2636
2637         mutex_unlock(&dc->lock);
2638
2639         return 0;
2640 }
2641
2642 static int tegra_dc_resume(struct nvhost_device *ndev)
2643 {
2644         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2645
2646         dev_info(&ndev->dev, "resume\n");
2647
2648         mutex_lock(&dc->lock);
2649         dc->suspended = false;
2650
2651         if (dc->enabled)
2652                 _tegra_dc_enable(dc);
2653
2654         if (dc->out && dc->out->hotplug_init)
2655                 dc->out->hotplug_init();
2656
2657         if (dc->out_ops && dc->out_ops->resume)
2658                 dc->out_ops->resume(dc);
2659         mutex_unlock(&dc->lock);
2660
2661         return 0;
2662 }
2663
2664 #endif /* CONFIG_PM */
2665
2666 extern int suspend_set(const char *val, struct kernel_param *kp)
2667 {
2668         if (!strcmp(val, "dump"))
2669                 dump_regs(tegra_dcs[0]);
2670 #ifdef CONFIG_PM
2671         else if (!strcmp(val, "suspend"))
2672                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2673         else if (!strcmp(val, "resume"))
2674                 tegra_dc_resume(tegra_dcs[0]->ndev);
2675 #endif
2676
2677         return 0;
2678 }
2679
2680 extern int suspend_get(char *buffer, struct kernel_param *kp)
2681 {
2682         return 0;
2683 }
2684
2685 int suspend;
2686
2687 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2688
2689 struct nvhost_driver tegra_dc_driver = {
2690         .driver = {
2691                 .name = "tegradc",
2692                 .owner = THIS_MODULE,
2693         },
2694         .probe = tegra_dc_probe,
2695         .remove = tegra_dc_remove,
2696 #ifdef CONFIG_PM
2697         .suspend = tegra_dc_suspend,
2698         .resume = tegra_dc_resume,
2699 #endif
2700 };
2701
2702 static int __init tegra_dc_module_init(void)
2703 {
2704         int ret = tegra_dc_ext_module_init();
2705         if (ret)
2706                 return ret;
2707         return nvhost_driver_register(&tegra_dc_driver);
2708 }
2709
2710 static void __exit tegra_dc_module_exit(void)
2711 {
2712         nvhost_driver_unregister(&tegra_dc_driver);
2713         tegra_dc_ext_module_exit();
2714 }
2715
2716 module_exit(tegra_dc_module_exit);
2717 module_init(tegra_dc_module_init);