e9bbf11d9019e8dab42b487224ac8b11a23680e7
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134         case TEGRA_WIN_FMT_YCbCr422R:
135         case TEGRA_WIN_FMT_YUV422R:
136         case TEGRA_WIN_FMT_YCbCr422RA:
137         case TEGRA_WIN_FMT_YUV422RA:
138                 return 8;
139
140         case TEGRA_WIN_FMT_YCbCr422:
141         case TEGRA_WIN_FMT_YUV422:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155         case TEGRA_WIN_FMT_YCbCr422R:
156         case TEGRA_WIN_FMT_YUV422R:
157         case TEGRA_WIN_FMT_YCbCr422RA:
158         case TEGRA_WIN_FMT_YUV422RA:
159                 return true;
160         }
161         return false;
162 }
163
164 #define DUMP_REG(a) do {                        \
165         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
166                  #a, a, tegra_dc_readl(dc, a));               \
167         print(data, buff);                                    \
168         } while (0)
169
170 static void _dump_regs(struct tegra_dc *dc, void *data,
171                        void (* print)(void *data, const char *str))
172 {
173         int i;
174         char buff[256];
175
176         tegra_dc_io_start(dc);
177         clk_enable(dc->clk);
178
179         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
180         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
181         DUMP_REG(DC_CMD_SIGNAL_RAISE);
182         DUMP_REG(DC_CMD_INT_STATUS);
183         DUMP_REG(DC_CMD_INT_MASK);
184         DUMP_REG(DC_CMD_INT_ENABLE);
185         DUMP_REG(DC_CMD_INT_TYPE);
186         DUMP_REG(DC_CMD_INT_POLARITY);
187         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
188         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
190         DUMP_REG(DC_CMD_STATE_ACCESS);
191         DUMP_REG(DC_CMD_STATE_CONTROL);
192         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
193         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
194
195         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
196         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
197         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
198         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
199         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
200         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
201         DUMP_REG(DC_DISP_REF_TO_SYNC);
202         DUMP_REG(DC_DISP_SYNC_WIDTH);
203         DUMP_REG(DC_DISP_BACK_PORCH);
204         DUMP_REG(DC_DISP_DISP_ACTIVE);
205         DUMP_REG(DC_DISP_FRONT_PORCH);
206         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
211         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
212         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
213         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
216         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
217         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
218         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
221         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
229         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
230         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
231         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
233         DUMP_REG(DC_DISP_M0_CONTROL);
234         DUMP_REG(DC_DISP_M1_CONTROL);
235         DUMP_REG(DC_DISP_DI_CONTROL);
236         DUMP_REG(DC_DISP_PP_CONTROL);
237         DUMP_REG(DC_DISP_PP_SELECT_A);
238         DUMP_REG(DC_DISP_PP_SELECT_B);
239         DUMP_REG(DC_DISP_PP_SELECT_C);
240         DUMP_REG(DC_DISP_PP_SELECT_D);
241         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
242         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
243         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
244         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
245         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
246         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
247         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
248         DUMP_REG(DC_DISP_BORDER_COLOR);
249         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
250         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
251         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
253         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
254         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
255         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
256         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
257         DUMP_REG(DC_DISP_CURSOR_POSITION);
258         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
259         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
260         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
261         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
264         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
265         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
266         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
269         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
270         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
271
272
273         for (i = 0; i < 3; i++) {
274                 print(data, "\n");
275                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
276                 print(data, buff);
277
278                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
279                                 DC_CMD_DISPLAY_WINDOW_HEADER);
280                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
281                 DUMP_REG(DC_WIN_WIN_OPTIONS);
282                 DUMP_REG(DC_WIN_BYTE_SWAP);
283                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
284                 DUMP_REG(DC_WIN_COLOR_DEPTH);
285                 DUMP_REG(DC_WIN_POSITION);
286                 DUMP_REG(DC_WIN_SIZE);
287                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
288                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
289                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
290                 DUMP_REG(DC_WIN_DDA_INCREMENT);
291                 DUMP_REG(DC_WIN_LINE_STRIDE);
292                 DUMP_REG(DC_WIN_BUF_STRIDE);
293                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
294                 DUMP_REG(DC_WIN_BLEND_NOKEY);
295                 DUMP_REG(DC_WIN_BLEND_1WIN);
296                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
297                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
298                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
299                 DUMP_REG(DC_WINBUF_START_ADDR);
300                 DUMP_REG(DC_WINBUF_START_ADDR_U);
301                 DUMP_REG(DC_WINBUF_START_ADDR_V);
302                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
303                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
304                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
305                 DUMP_REG(DC_WIN_CSC_YOF);
306                 DUMP_REG(DC_WIN_CSC_KYRGB);
307                 DUMP_REG(DC_WIN_CSC_KUR);
308                 DUMP_REG(DC_WIN_CSC_KVR);
309                 DUMP_REG(DC_WIN_CSC_KUG);
310                 DUMP_REG(DC_WIN_CSC_KVG);
311                 DUMP_REG(DC_WIN_CSC_KUB);
312                 DUMP_REG(DC_WIN_CSC_KVB);
313         }
314
315         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
316         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
317         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
318         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
319         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
321         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
322         DUMP_REG(DC_DISP_M1_CONTROL);
323         DUMP_REG(DC_COM_PM1_CONTROL);
324         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
325         DUMP_REG(DC_DISP_SD_CONTROL);
326
327         clk_disable(dc->clk);
328         tegra_dc_io_end(dc);
329 }
330
331 #undef DUMP_REG
332
333 #ifdef DEBUG
334 static void dump_regs_print(void *data, const char *str)
335 {
336         struct tegra_dc *dc = data;
337         dev_dbg(&dc->ndev->dev, "%s", str);
338 }
339
340 static void dump_regs(struct tegra_dc *dc)
341 {
342         _dump_regs(dc, dc, dump_regs_print);
343 }
344 #else /* !DEBUG */
345
346 static void dump_regs(struct tegra_dc *dc) {}
347
348 #endif /* DEBUG */
349
350 #ifdef CONFIG_DEBUG_FS
351
352 static void dbg_regs_print(void *data, const char *str)
353 {
354         struct seq_file *s = data;
355
356         seq_printf(s, "%s", str);
357 }
358
359 #undef DUMP_REG
360
361 static int dbg_dc_show(struct seq_file *s, void *unused)
362 {
363         struct tegra_dc *dc = s->private;
364
365         _dump_regs(dc, s, dbg_regs_print);
366
367         return 0;
368 }
369
370
371 static int dbg_dc_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_show, inode->i_private);
374 }
375
376 static const struct file_operations regs_fops = {
377         .open           = dbg_dc_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386         struct tegra_dc_mode *m;
387
388         mutex_lock(&dc->lock);
389         m = &dc->mode;
390         seq_printf(s,
391                 "pclk: %d\n"
392                 "h_ref_to_sync: %d\n"
393                 "v_ref_to_sync: %d\n"
394                 "h_sync_width: %d\n"
395                 "v_sync_width: %d\n"
396                 "h_back_porch: %d\n"
397                 "v_back_porch: %d\n"
398                 "h_active: %d\n"
399                 "v_active: %d\n"
400                 "h_front_porch: %d\n"
401                 "v_front_porch: %d\n"
402                 "stereo_mode: %d\n",
403                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
404                 m->h_sync_width, m->v_sync_width,
405                 m->h_back_porch, m->v_back_porch,
406                 m->h_active, m->v_active,
407                 m->h_front_porch, m->v_front_porch,
408                 m->stereo_mode);
409         mutex_unlock(&dc->lock);
410         return 0;
411 }
412
413 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
414 {
415         return single_open(file, dbg_dc_mode_show, inode->i_private);
416 }
417
418 static const struct file_operations mode_fops = {
419         .open           = dbg_dc_mode_open,
420         .read           = seq_read,
421         .llseek         = seq_lseek,
422         .release        = single_release,
423 };
424
425 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
426 {
427         struct tegra_dc *dc = s->private;
428
429         mutex_lock(&dc->lock);
430         seq_printf(s,
431                 "underflows: %llu\n"
432                 "underflows_a: %llu\n"
433                 "underflows_b: %llu\n"
434                 "underflows_c: %llu\n",
435                 dc->stats.underflows,
436                 dc->stats.underflows_a,
437                 dc->stats.underflows_b,
438                 dc->stats.underflows_c);
439         mutex_unlock(&dc->lock);
440
441         return 0;
442 }
443
444 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
445 {
446         return single_open(file, dbg_dc_stats_show, inode->i_private);
447 }
448
449 static const struct file_operations stats_fops = {
450         .open           = dbg_dc_stats_open,
451         .read           = seq_read,
452         .llseek         = seq_lseek,
453         .release        = single_release,
454 };
455
456 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
457 {
458         if (dc->debugdir)
459                 debugfs_remove_recursive(dc->debugdir);
460         dc->debugdir = NULL;
461 }
462
463 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
464 {
465         struct dentry *retval;
466
467         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
468         if (!dc->debugdir)
469                 goto remove_out;
470
471         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
472                 &regs_fops);
473         if (!retval)
474                 goto remove_out;
475
476         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
477                 &mode_fops);
478         if (!retval)
479                 goto remove_out;
480
481         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
482                 &stats_fops);
483         if (!retval)
484                 goto remove_out;
485
486         return;
487 remove_out:
488         dev_err(&dc->ndev->dev, "could not create debugfs\n");
489         tegra_dc_remove_debugfs(dc);
490 }
491
492 #else /* !CONFIG_DEBUGFS */
493 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
494 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
495 #endif /* CONFIG_DEBUGFS */
496
497 static int tegra_dc_set(struct tegra_dc *dc, int index)
498 {
499         int ret = 0;
500
501         mutex_lock(&tegra_dc_lock);
502         if (index >= TEGRA_MAX_DC) {
503                 ret = -EINVAL;
504                 goto out;
505         }
506
507         if (dc != NULL && tegra_dcs[index] != NULL) {
508                 ret = -EBUSY;
509                 goto out;
510         }
511
512         tegra_dcs[index] = dc;
513
514 out:
515         mutex_unlock(&tegra_dc_lock);
516
517         return ret;
518 }
519
520 unsigned int tegra_dc_has_multiple_dc(void)
521 {
522         unsigned int idx;
523         unsigned int cnt = 0;
524         struct tegra_dc *dc;
525
526         mutex_lock(&tegra_dc_lock);
527         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
528                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
529         mutex_unlock(&tegra_dc_lock);
530
531         return (cnt > 1);
532 }
533
534 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
535 {
536         if (idx < TEGRA_MAX_DC)
537                 return tegra_dcs[idx];
538         else
539                 return NULL;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_dc);
542
543 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
544 {
545         if (win >= dc->n_windows)
546                 return NULL;
547
548         return &dc->windows[win];
549 }
550 EXPORT_SYMBOL(tegra_dc_get_window);
551
552 static int get_topmost_window(u32 *depths, unsigned long *wins)
553 {
554         int idx, best = -1;
555
556         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
557                 if (best == -1 || depths[idx] < depths[best])
558                         best = idx;
559         }
560         clear_bit(best, wins);
561         return best;
562 }
563
564 bool tegra_dc_get_connected(struct tegra_dc *dc)
565 {
566         return dc->connected;
567 }
568 EXPORT_SYMBOL(tegra_dc_get_connected);
569
570 static u32 blend_topwin(u32 flags)
571 {
572         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
573                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
574         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
575                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
576         else
577                 return BLEND(NOKEY, FIX, 0xff, 0xff);
578 }
579
580 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
581 {
582         int other;
583
584         for (other = 0; other < DC_N_WINDOWS; other++) {
585                 if (other != idx && (xy-- == 0))
586                         break;
587         }
588         if (BIT(other) & behind_mask)
589                 return blend_topwin(flags[idx]);
590         else if (flags[other])
591                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
592         else
593                 return BLEND(NOKEY, FIX, 0x00, 0x00);
594 }
595
596 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
597 {
598         unsigned long infront_mask;
599         int first;
600
601         infront_mask = ~(behind_mask | BIT(idx));
602         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
603         first = ffs(infront_mask) - 1;
604
605         if (!infront_mask)
606                 return blend_topwin(flags[idx]);
607         else if (behind_mask && first != -1 && flags[first])
608                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
609         else
610                 return BLEND(NOKEY, FIX, 0x0, 0x0);
611 }
612
613 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
614 {
615         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
616
617         while (mask) {
618                 int idx = get_topmost_window(blend->z, &mask);
619
620                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
621                                 DC_CMD_DISPLAY_WINDOW_HEADER);
622                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
623                                 DC_WIN_BLEND_NOKEY);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_1WIN);
626                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
627                                 DC_WIN_BLEND_2WIN_X);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
629                                 DC_WIN_BLEND_2WIN_Y);
630                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
631                                 DC_WIN_BLEND_3WIN_XY);
632         }
633 }
634
635 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 {
637         csc->yof   = 0x00f0;
638         csc->kyrgb = 0x012a;
639         csc->kur   = 0x0000;
640         csc->kvr   = 0x0198;
641         csc->kug   = 0x039b;
642         csc->kvg   = 0x032f;
643         csc->kub   = 0x0204;
644         csc->kvb   = 0x0000;
645 }
646
647 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
648 {
649         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
650         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
651         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
652         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
653         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
654         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
655         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
656         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
657 }
658
659 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
660 {
661         mutex_lock(&dc->lock);
662
663         if (!dc->enabled) {
664                 mutex_unlock(&dc->lock);
665                 return -EFAULT;
666         }
667
668         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
669                         DC_CMD_DISPLAY_WINDOW_HEADER);
670
671         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
672
673         mutex_unlock(&dc->lock);
674
675         return 0;
676 }
677 EXPORT_SYMBOL(tegra_dc_update_csc);
678
679 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
680 {
681         int i;
682         for (i = 0; i < 256; i++)
683                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
684 }
685
686 static int tegra_dc_loop_lut(struct tegra_dc *dc,
687                              struct tegra_dc_win *win,
688                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
689 {
690         struct tegra_dc_lut *lut = &win->lut;
691         struct tegra_dc_lut *global_lut = &dc->fb_lut;
692         int i;
693         for (i = 0; i < 256; i++) {
694
695                 u32 r = (u32)lut->r[i];
696                 u32 g = (u32)lut->g[i];
697                 u32 b = (u32)lut->b[i];
698
699                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
700                         r = (u32)global_lut->r[r];
701                         g = (u32)global_lut->g[g];
702                         b = (u32)global_lut->b[b];
703                 }
704
705                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
706                         return 0;
707         }
708         return 1;
709 }
710
711 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
712 {
713         if (rgb != (i | (i<<8) | (i<<16)))
714                 return 0;
715         return 1;
716 }
717
718 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
719 {
720         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
721         return 1;
722 }
723
724 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
725 {
726         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
727
728         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
729
730         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
731                 val |= CP_ENABLE;
732         else
733                 val &= ~CP_ENABLE;
734
735         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
736 }
737
738 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
739 {
740         struct tegra_dc_win *win = &dc->windows[win_idx];
741
742         mutex_lock(&dc->lock);
743
744         if (!dc->enabled) {
745                 mutex_unlock(&dc->lock);
746                 return -EFAULT;
747         }
748
749         if (fbovr > 0)
750                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
751         else if (fbovr == 0)
752                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753
754         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
756         else
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
758
759         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
760                         DC_CMD_DISPLAY_WINDOW_HEADER);
761
762         tegra_dc_set_lut(dc, win);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768
769 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
770 {
771         if (win_idx > -1)
772                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
773
774         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
775                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
776                 if (err)
777                         return err;
778         }
779
780         return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_update_lut);
783
784 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
785 {
786         unsigned i;
787         unsigned v0 = 128;
788         unsigned v1 = 0;
789         /* linear horizontal and vertical filters */
790         for (i = 0; i < 16; i++) {
791                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
792                                 DC_WIN_H_FILTER_P(i));
793
794                 tegra_dc_writel(dc, v0,
795                                 DC_WIN_V_FILTER_P(i));
796                 v0 -= 8;
797                 v1 += 8;
798         }
799 }
800
801 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
802         struct tegra_dc_win *w)
803 {
804         /* windows A, B, C for first and second display */
805         static const enum tegra_la_id la_id_tab[2][3] = {
806                 /* first display */
807                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
808                         TEGRA_LA_DISPLAY_0C },
809                 /* second display */
810                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
811                         TEGRA_LA_DISPLAY_0CB },
812         };
813         /* window B V-filter tap for first and second display. */
814         static const enum tegra_la_id vfilter_tab[2] = {
815                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
816         };
817         unsigned long bw;
818
819         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
820         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
821         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
822
823         bw = w->new_bandwidth;
824
825         /* tegra_dc_get_bandwidth() treats V filter windows as double
826          * bandwidth, but LA has a seperate client for V filter */
827         if (w->idx == 1 && win_use_v_filter(w))
828                 bw /= 2;
829
830         /* our bandwidth is in bytes/sec, but LA takes MBps.
831          * round up bandwidth to 1MBps */
832         bw = bw / 1000000 + 1;
833
834 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
835         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
836         /* if window B, also set the 1B client for the 2-tap V filter. */
837         if (w->idx == 1)
838                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
839 #endif
840
841         w->bandwidth = w->new_bandwidth;
842 }
843
844 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
845                                                    struct tegra_dc_win *b)
846 {
847         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
848                 return 0;
849
850         /* because memory access to load the fifo can overlap, only care
851          * if windows overlap vertically */
852         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
853                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
854 }
855
856 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
857                                                  int n)
858 {
859         unsigned i;
860         unsigned j;
861         unsigned overlap_count;
862         unsigned max_bw = 0;
863
864         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
865                          "inaccurate.\n");
866
867         /* If we had a large number of windows, we would compute adjacency
868          * graph representing 2 window overlaps, find all cliques in the graph,
869          * assign bandwidth to each clique, and then select the clique with
870          * maximum bandwidth. But because we have at most 3 windows,
871          * implementing proper Bron-Kerbosh algorithm would be an overkill,
872          * brute force will suffice.
873          *
874          * Thus: find maximum bandwidth for either single or a pair of windows
875          * and count number of window pair overlaps. If there are three
876          * pairs, all 3 window overlap.
877          */
878
879         overlap_count = 0;
880         for (i = 0; i < n; i++) {
881                 unsigned int bw1;
882
883                 if (wins[i] == NULL)
884                         continue;
885                 bw1 = wins[i]->new_bandwidth;
886                 if (bw1 > max_bw)
887                         /* Single window */
888                         max_bw = bw1;
889
890                 for (j = i + 1; j < n; j++) {
891                         if (wins[j] == NULL)
892                                 continue;
893                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
894                                 unsigned int bw2 = wins[j]->new_bandwidth;
895                                 if (bw1 + bw2 > max_bw)
896                                         /* Window pair overlaps */
897                                         max_bw = bw1 + bw2;
898                                 overlap_count++;
899                         }
900                 }
901         }
902
903         if (overlap_count == 3)
904                 /* All three windows overlap */
905                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
906                          wins[2]->new_bandwidth;
907
908         return max_bw;
909 }
910
911 /*
912  * Calculate peak EMC bandwidth for each enabled window =
913  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
914  * (windows_tiling ? 2 : 1)
915  *
916  *
917  * note:
918  * (*) We use 2 tap V filter, so need double BW if use V filter
919  * (*) Tiling mode on T30 and DDR3 requires double BW
920  */
921 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
922         struct tegra_dc_win *w)
923 {
924         unsigned long ret;
925         int tiled_windows_bw_multiplier;
926         unsigned long bpp;
927
928         if (!WIN_IS_ENABLED(w))
929                 return 0;
930
931         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
932             w->out_w == 0 || w->out_h == 0)
933                 return 0;
934
935         tiled_windows_bw_multiplier =
936                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
937
938         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
939          * but the size reported by tegra_dc_fmt_bpp for the planar version
940          * is of the luma plane's size only. */
941         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
942                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
943         /* perform calculations with most significant bits of pixel clock
944          * to prevent overflow of long. */
945         ret = (unsigned long)(dc->pixel_clk >> 16) *
946                 bpp / 8 *
947                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
948                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
949
950 /*
951  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
952  * will request 147MBps from EMC.
953  */
954         ret = ret * 2 + ret / 10;
955
956         /* if overflowed */
957         if (ret > (1UL << 31))
958                 return ULONG_MAX;
959
960         return ret << 16; /* restore the scaling we did above */
961 }
962
963 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
964 {
965         int i;
966
967         BUG_ON(n > DC_N_WINDOWS);
968
969         /* emc rate and latency allowance both need to know per window
970          * bandwidths */
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *w = windows[i];
973                 if (w)
974                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
975         }
976
977         return tegra_dc_find_max_bandwidth(windows, n);
978 }
979
980 /* program bandwidth needs if higher than old bandwidth */
981 static void tegra_dc_increase_bandwidth(struct tegra_dc *dc)
982 {
983         unsigned i;
984
985         if (dc->emc_clk_rate < dc->new_emc_clk_rate) {
986                 dc->emc_clk_rate = dc->new_emc_clk_rate;
987                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
988         }
989
990         for (i = 0; i < DC_N_WINDOWS; i++) {
991                 struct tegra_dc_win *w = &dc->windows[i];
992                 if (w->bandwidth < w->new_bandwidth && w->new_bandwidth != 0)
993                         tegra_dc_set_latency_allowance(dc, w);
994         }
995 }
996
997 /* program the current bandwidth */
998 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
999 {
1000         unsigned i;
1001
1002         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
1003                 dc->emc_clk_rate = dc->new_emc_clk_rate;
1004                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
1005         }
1006
1007         for (i = 0; i < DC_N_WINDOWS; i++) {
1008                 struct tegra_dc_win *w = &dc->windows[i];
1009                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1010                         tegra_dc_set_latency_allowance(dc, w);
1011         }
1012 }
1013
1014 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1015 {
1016         unsigned long new_rate;
1017         struct tegra_dc *dc;
1018
1019         if (!use_dynamic_emc)
1020                 return 0;
1021
1022         dc = windows[0]->dc;
1023
1024         /* calculate the new rate based on this POST */
1025         new_rate = tegra_dc_get_bandwidth(windows, n);
1026         new_rate = EMC_BW_TO_FREQ(new_rate);
1027
1028         if (tegra_dc_has_multiple_dc())
1029                 new_rate = ULONG_MAX;
1030
1031         dc->new_emc_clk_rate = new_rate;
1032
1033         return 0;
1034 }
1035
1036 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1037                                   bool v, unsigned Bpp)
1038 {
1039         /*
1040          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1041          *           (post_scaled_size_in_pixels - 1)), MAX)
1042          * Where the value of MAX is as follows:
1043          * For V_DDA_INCREMENT: 15.0 (0xF000)
1044          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1045          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1046          */
1047
1048         fixed20_12 out = dfixed_init(out_int);
1049         u32 dda_inc;
1050         int max;
1051
1052         if (v) {
1053                 max = 15;
1054         } else {
1055                 switch (Bpp) {
1056                 default:
1057                         WARN_ON_ONCE(1);
1058                         /* fallthrough */
1059                 case 4:
1060                         max = 4;
1061                         break;
1062                 case 2:
1063                         max = 8;
1064                         break;
1065                 }
1066         }
1067
1068         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1069         in.full -= dfixed_const(1);
1070
1071         dda_inc = dfixed_div(in, out);
1072
1073         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1074
1075         return dda_inc;
1076 }
1077
1078 static inline u32 compute_initial_dda(fixed20_12 in)
1079 {
1080         return dfixed_frac(in);
1081 }
1082
1083 /* does not support updating windows on multiple dcs in one call */
1084 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1085 {
1086         struct tegra_dc *dc;
1087         unsigned long update_mask = GENERAL_ACT_REQ;
1088         unsigned long val;
1089         bool update_blend = false;
1090         int i;
1091
1092         dc = windows[0]->dc;
1093
1094         mutex_lock(&dc->lock);
1095
1096         if (!dc->enabled) {
1097                 mutex_unlock(&dc->lock);
1098                 return -EFAULT;
1099         }
1100
1101         if (no_vsync)
1102                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1103         else
1104                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1105
1106         for (i = 0; i < n; i++) {
1107                 struct tegra_dc_win *win = windows[i];
1108                 unsigned h_dda;
1109                 unsigned v_dda;
1110                 fixed20_12 h_offset, v_offset;
1111                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1112                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1113                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1114                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1115                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1116                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1117                 const bool filter_h = win_use_h_filter(win);
1118                 const bool filter_v = win_use_v_filter(win);
1119
1120                 if (win->z != dc->blend.z[win->idx]) {
1121                         dc->blend.z[win->idx] = win->z;
1122                         update_blend = true;
1123                 }
1124                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1125                         dc->blend.flags[win->idx]) {
1126                         dc->blend.flags[win->idx] =
1127                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1128                         update_blend = true;
1129                 }
1130
1131                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1132                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1133
1134                 if (!no_vsync)
1135                         update_mask |= WIN_A_ACT_REQ << win->idx;
1136
1137                 if (!WIN_IS_ENABLED(win)) {
1138                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1139                         continue;
1140                 }
1141
1142                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1143                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1144
1145                 tegra_dc_writel(dc,
1146                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1147                                 DC_WIN_POSITION);
1148                 tegra_dc_writel(dc,
1149                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1150                                 DC_WIN_SIZE);
1151                 tegra_dc_writel(dc,
1152                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1153                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1154                                 DC_WIN_PRESCALED_SIZE);
1155
1156                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1157                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1158                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1159                                 DC_WIN_DDA_INCREMENT);
1160                 h_dda = compute_initial_dda(win->x);
1161                 v_dda = compute_initial_dda(win->y);
1162                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1163                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1164
1165                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1166                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1167                 tegra_dc_writel(dc,
1168                                 (unsigned long)win->phys_addr,
1169                                 DC_WINBUF_START_ADDR);
1170
1171                 if (!yuvp) {
1172                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1173                 } else {
1174                         tegra_dc_writel(dc,
1175                                         (unsigned long)win->phys_addr_u,
1176                                         DC_WINBUF_START_ADDR_U);
1177                         tegra_dc_writel(dc,
1178                                         (unsigned long)win->phys_addr_v,
1179                                         DC_WINBUF_START_ADDR_V);
1180                         tegra_dc_writel(dc,
1181                                         LINE_STRIDE(win->stride) |
1182                                         UV_LINE_STRIDE(win->stride_uv),
1183                                         DC_WIN_LINE_STRIDE);
1184                 }
1185
1186                 h_offset = win->x;
1187                 if (invert_h) {
1188                         h_offset.full += win->w.full - dfixed_const(1);
1189                 }
1190
1191                 v_offset = win->y;
1192                 if (invert_v) {
1193                         v_offset.full += win->h.full - dfixed_const(1);
1194                 }
1195
1196                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1197                                 DC_WINBUF_ADDR_H_OFFSET);
1198                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1199                                 DC_WINBUF_ADDR_V_OFFSET);
1200
1201                 if (WIN_IS_TILED(win))
1202                         tegra_dc_writel(dc,
1203                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1204                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1205                                         DC_WIN_BUFFER_ADDR_MODE);
1206                 else
1207                         tegra_dc_writel(dc,
1208                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1209                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1210                                         DC_WIN_BUFFER_ADDR_MODE);
1211
1212                 val = WIN_ENABLE;
1213                 if (yuvp)
1214                         val |= CSC_ENABLE;
1215                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1216                         val |= COLOR_EXPAND;
1217
1218                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1219                         val |= CP_ENABLE;
1220
1221                 if (filter_h)
1222                         val |= H_FILTER_ENABLE;
1223                 if (filter_v)
1224                         val |= V_FILTER_ENABLE;
1225
1226                 if (invert_h)
1227                         val |= H_DIRECTION_DECREMENT;
1228                 if (invert_v)
1229                         val |= V_DIRECTION_DECREMENT;
1230
1231                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1232
1233                 win->dirty = no_vsync ? 0 : 1;
1234
1235                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1236                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1237                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1238                         __func__, win->idx, win->z,
1239                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1240                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1241                         win->out_x, win->out_y, win->out_w, win->out_h,
1242                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1243         }
1244
1245         if (update_blend) {
1246                 tegra_dc_set_blending(dc, &dc->blend);
1247                 for (i = 0; i < DC_N_WINDOWS; i++) {
1248                         if (!no_vsync)
1249                                 dc->windows[i].dirty = 1;
1250                         update_mask |= WIN_A_ACT_REQ << i;
1251                 }
1252         }
1253
1254         tegra_dc_set_dynamic_emc(windows, n);
1255         tegra_dc_increase_bandwidth(dc);
1256
1257         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1258
1259         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1260         if (!no_vsync) {
1261                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1262                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1263                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1264         } else {
1265                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1266                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1267                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1268         }
1269
1270         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1271
1272         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1273                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1274
1275         mutex_unlock(&dc->lock);
1276
1277         return 0;
1278 }
1279 EXPORT_SYMBOL(tegra_dc_update_windows);
1280
1281 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1282 {
1283         return dc->syncpt[i].id;
1284 }
1285 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1286
1287 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1288 {
1289         u32 max;
1290
1291         mutex_lock(&dc->lock);
1292         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1293                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1294         dc->syncpt[i].max = max;
1295         mutex_unlock(&dc->lock);
1296
1297         return max;
1298 }
1299
1300 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1301 {
1302         mutex_lock(&dc->lock);
1303         if ( dc->enabled )
1304                 while (dc->syncpt[i].min < val) {
1305                         dc->syncpt[i].min++;
1306                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1307                                         dc->syncpt[i].id);
1308                 }
1309         mutex_unlock(&dc->lock);
1310 }
1311
1312 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1313                                              int n)
1314 {
1315         int i;
1316
1317         for (i = 0; i < n; i++) {
1318                 if (windows[i]->dirty)
1319                         return false;
1320         }
1321
1322         return true;
1323 }
1324
1325 /* does not support syncing windows on multiple dcs in one call */
1326 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1327 {
1328         if (n < 1 || n > DC_N_WINDOWS)
1329                 return -EINVAL;
1330
1331         if (!windows[0]->dc->enabled)
1332                 return -EFAULT;
1333
1334 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1335         /* Don't want to timeout on simulator */
1336         return wait_event_interruptible(windows[0]->dc->wq,
1337                 tegra_dc_windows_are_clean(windows, n));
1338 #else
1339         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1340                                          tegra_dc_windows_are_clean(windows, n),
1341                                          HZ);
1342 #endif
1343 }
1344 EXPORT_SYMBOL(tegra_dc_sync_windows);
1345
1346 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1347 {
1348 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1349         return clk_get_rate(dc->clk);
1350 #else
1351         return 27000000;
1352 #endif
1353 }
1354
1355 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1356 {
1357         unsigned long rate;
1358         unsigned long div;
1359
1360         rate = tegra_dc_clk_get_rate(dc);
1361
1362         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1363
1364         if (div < 2)
1365                 return 0;
1366
1367         return rate * 2 / div;
1368 }
1369
1370 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1371 {
1372         int pclk;
1373
1374         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1375                 unsigned long rate;
1376                 struct clk *parent_clk =
1377                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1378
1379                 if (clk_get_parent(clk) != parent_clk)
1380                         clk_set_parent(clk, parent_clk);
1381
1382                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1383                         struct clk *base_clk = clk_get_parent(parent_clk);
1384
1385                         /* Assuming either pll_d or pll_d2 is used */
1386                         rate = dc->mode.pclk * 2;
1387
1388                         if (rate != clk_get_rate(base_clk))
1389                                 clk_set_rate(base_clk, rate);
1390                 }
1391         }
1392
1393         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1394                 unsigned long rate;
1395                 struct clk *parent_clk =
1396                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1397                 struct clk *base_clk = clk_get_parent(parent_clk);
1398
1399                 /* needs to match tegra_dc_hdmi_supported_modes[]
1400                 and tegra_pll_d_freq_table[] */
1401                 if (dc->mode.pclk > 70000000)
1402                         rate = 594000000;
1403                 else if (dc->mode.pclk > 25200000)
1404                         rate = 216000000;
1405                 else
1406                         rate = 504000000;
1407
1408                 if (rate != clk_get_rate(base_clk))
1409                         clk_set_rate(base_clk, rate);
1410
1411                 if (clk_get_parent(clk) != parent_clk)
1412                         clk_set_parent(clk, parent_clk);
1413         }
1414
1415         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1416                 unsigned long rate;
1417                 struct clk *parent_clk;
1418                 struct clk *base_clk;
1419
1420                 if (clk == dc->clk) {
1421                         parent_clk = clk_get_sys(NULL,
1422                                         dc->out->parent_clk ? : "pll_d_out0");
1423                         base_clk = clk_get_parent(parent_clk);
1424                         tegra_clk_cfg_ex(base_clk,
1425                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1426                 } else {
1427                         if (dc->pdata->default_out->dsi->dsi_instance) {
1428                                 parent_clk = clk_get_sys(NULL,
1429                                         dc->out->parent_clk ? : "pll_d2_out0");
1430                                 base_clk = clk_get_parent(parent_clk);
1431                                 tegra_clk_cfg_ex(base_clk,
1432                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1433                         } else {
1434                                 parent_clk = clk_get_sys(NULL,
1435                                         dc->out->parent_clk ? : "pll_d_out0");
1436                                 base_clk = clk_get_parent(parent_clk);
1437                                 tegra_clk_cfg_ex(base_clk,
1438                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1439                         }
1440                 }
1441
1442                 rate = dc->mode.pclk * 2;
1443                 if (rate != clk_get_rate(base_clk))
1444                         clk_set_rate(base_clk, rate);
1445
1446                 if (clk_get_parent(clk) != parent_clk)
1447                         clk_set_parent(clk, parent_clk);
1448         }
1449
1450         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1451         tegra_dvfs_set_rate(clk, pclk);
1452 }
1453
1454 /* return non-zero if constraint is violated */
1455 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1456 {
1457         long a, b;
1458
1459         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1460         a = 0;
1461
1462         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1463         b = mode->h_front_porch - 1;
1464
1465         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1466         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1467                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1468         /* check Constraint 1 and 6 */
1469         if (a > b)
1470                 return 1;
1471
1472         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1473         if (mode->h_sync_width < 1)
1474                 return 4;
1475
1476         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1477         if (mode->h_active < 16)
1478                 return 7;
1479
1480         if (href) {
1481                 if (b > a && a % 2)
1482                         *href = a + 1; /* use smallest even value */
1483                 else
1484                         *href = a; /* even or only possible value */
1485         }
1486
1487         return 0;
1488 }
1489
1490 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1491 {
1492         long a;
1493         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1494
1495         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1496         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1497                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1498
1499         /* Constraint 6 */
1500         if (mode->v_front_porch < a + 1)
1501                 a = mode->v_front_porch - 1;
1502
1503         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1504         if (mode->v_sync_width < 1)
1505                 return 4;
1506
1507         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1508         if (mode->v_active < 16)
1509                 return 7;
1510
1511         if (vref)
1512                 *vref = a;
1513         return 0;
1514 }
1515
1516 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1517 {
1518         int ret;
1519         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1520         if (ret)
1521                 return ret;
1522         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1523         if (ret)
1524                 return ret;
1525
1526         return 0;
1527 }
1528
1529 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1530 {
1531         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1532         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1533                 return false;
1534
1535         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1536         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1537                 return false;
1538
1539         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1540          * (vertical blank). */
1541         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1542                 return false;
1543
1544         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1545         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1546                 return false;
1547
1548         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1549         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1550                 return false;
1551
1552         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1553          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1554         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1555                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1556                 return false;
1557
1558         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1559         if (mode->h_active < 16 || mode->v_active < 16)
1560                 return false;
1561
1562         return true;
1563 }
1564
1565 #ifdef DEBUG
1566 /* return in 1000ths of a Hertz */
1567 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1568 {
1569         long h_total, v_total, refresh;
1570         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1571                 m->h_sync_width;
1572         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1573                 m->v_sync_width;
1574         refresh = dc->pixel_clk / h_total;
1575         refresh *= 1000;
1576         refresh /= v_total;
1577         return refresh;
1578 }
1579
1580 static void print_mode(struct tegra_dc *dc,
1581                         const struct tegra_dc_mode *mode, const char *note)
1582 {
1583         if (mode) {
1584                 int refresh = calc_refresh(dc, mode);
1585                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1586                         note ? note : "",
1587                         mode->h_active, mode->v_active,
1588                         refresh / 1000, refresh % 1000,
1589                         mode->pclk);
1590         }
1591 }
1592 #else /* !DEBUG */
1593 static inline void print_mode(struct tegra_dc *dc,
1594                         const struct tegra_dc_mode *mode, const char *note) { }
1595 #endif /* DEBUG */
1596
1597 static inline void enable_dc_irq(unsigned int irq)
1598 {
1599 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1600         enable_irq(irq);
1601 #else
1602         /* Always disable DC interrupts on FPGA. */
1603         disable_irq(irq);
1604 #endif
1605 }
1606
1607 static inline void disable_dc_irq(unsigned int irq)
1608 {
1609         disable_irq(irq);
1610 }
1611
1612 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1613 {
1614         unsigned long val;
1615         unsigned long rate;
1616         unsigned long div;
1617         unsigned long pclk;
1618
1619         print_mode(dc, mode, __func__);
1620
1621         /* use default EMC rate when switching modes */
1622         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1623         tegra_dc_program_bandwidth(dc);
1624
1625         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1626         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1627                         DC_DISP_REF_TO_SYNC);
1628         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1629                         DC_DISP_SYNC_WIDTH);
1630         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1631                         DC_DISP_BACK_PORCH);
1632         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1633                         DC_DISP_DISP_ACTIVE);
1634         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1635                         DC_DISP_FRONT_PORCH);
1636
1637         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1638                         DC_DISP_DATA_ENABLE_OPTIONS);
1639
1640         /* TODO: MIPI/CRT/HDMI clock cals */
1641
1642         val = DISP_DATA_FORMAT_DF1P1C;
1643
1644         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1645                 val |= DISP_DATA_ALIGNMENT_MSB;
1646         else
1647                 val |= DISP_DATA_ALIGNMENT_LSB;
1648
1649         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1650                 val |= DISP_DATA_ORDER_RED_BLUE;
1651         else
1652                 val |= DISP_DATA_ORDER_BLUE_RED;
1653
1654         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1655
1656         rate = tegra_dc_clk_get_rate(dc);
1657
1658         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1659         if (pclk < (mode->pclk / 100 * 99) ||
1660             pclk > (mode->pclk / 100 * 109)) {
1661                 dev_err(&dc->ndev->dev,
1662                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1663                         rate, mode->pclk,
1664                         pclk, (mode->pclk / 100 * 99),
1665                         (mode->pclk / 100 * 109));
1666                 return -EINVAL;
1667         }
1668
1669         div = (rate * 2 / pclk) - 2;
1670
1671         tegra_dc_writel(dc, 0x00010001,
1672                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1673         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1674                         DC_DISP_DISP_CLOCK_CONTROL);
1675
1676 #ifdef CONFIG_SWITCH
1677         switch_set_state(&dc->modeset_switch,
1678                          (mode->h_active << 16) | mode->v_active);
1679 #endif
1680
1681         dc->pixel_clk = dc->mode.pclk;
1682
1683         return 0;
1684 }
1685
1686
1687 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1688 {
1689         memcpy(&dc->mode, mode, sizeof(dc->mode));
1690
1691         print_mode(dc, mode, __func__);
1692
1693         return 0;
1694 }
1695 EXPORT_SYMBOL(tegra_dc_set_mode);
1696
1697 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1698                 const struct fb_videomode *fbmode, bool stereo_mode)
1699 {
1700         struct tegra_dc_mode mode;
1701
1702         if (!fbmode->pixclock)
1703                 return -EINVAL;
1704
1705         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1706         mode.h_sync_width = fbmode->hsync_len;
1707         mode.v_sync_width = fbmode->vsync_len;
1708         mode.h_back_porch = fbmode->left_margin;
1709         mode.v_back_porch = fbmode->upper_margin;
1710         mode.h_active = fbmode->xres;
1711         mode.v_active = fbmode->yres;
1712         mode.h_front_porch = fbmode->right_margin;
1713         mode.v_front_porch = fbmode->lower_margin;
1714         mode.stereo_mode = stereo_mode;
1715         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1716                 /* HDMI controller requires h_ref=1, v_ref=1 */
1717                 mode.h_ref_to_sync = 1;
1718                 mode.v_ref_to_sync = 1;
1719         } else {
1720                 calc_ref_to_sync(&mode);
1721         }
1722         if (!check_ref_to_sync(&mode)) {
1723                 dev_err(&dc->ndev->dev,
1724                                 "Display timing doesn't meet restrictions.\n");
1725                 return -EINVAL;
1726         }
1727         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1728                 mode.h_active, mode.v_active, mode.pclk,
1729                 mode.h_ref_to_sync, mode.v_ref_to_sync
1730         );
1731
1732         if (mode.stereo_mode) {
1733                 mode.pclk *= 2;
1734                 /* total v_active = yres*2 + activespace */
1735                 mode.v_active = fbmode->yres*2 +
1736                                 fbmode->vsync_len +
1737                                 fbmode->upper_margin +
1738                                 fbmode->lower_margin;
1739         }
1740
1741         mode.flags = 0;
1742
1743         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1744                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1745
1746         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1747                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1748
1749         return tegra_dc_set_mode(dc, &mode);
1750 }
1751 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1752
1753 void
1754 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1755 {
1756         unsigned int ctrl;
1757         unsigned long out_sel;
1758         unsigned long cmd_state;
1759
1760         mutex_lock(&dc->lock);
1761         if (!dc->enabled) {
1762                 mutex_unlock(&dc->lock);
1763                 return;
1764         }
1765
1766         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1767                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1768                 cfg->clk_select);
1769
1770         /* The new value should be effected immediately */
1771         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1772         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1773
1774         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1775                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1776         else
1777                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1778
1779         switch (cfg->which_pwm) {
1780         case TEGRA_PWM_PM0:
1781                 /* Select the LM0 on PM0 */
1782                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1783                 out_sel &= ~(7 << 0);
1784                 out_sel |= (3 << 0);
1785                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1786                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1787                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1788                 break;
1789         case TEGRA_PWM_PM1:
1790                 /* Select the LM1 on PM1 */
1791                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1792                 out_sel &= ~(7 << 4);
1793                 out_sel |= (3 << 4);
1794                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1795                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1796                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1797                 break;
1798         default:
1799                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1800                 break;
1801         }
1802         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1803         mutex_unlock(&dc->lock);
1804 }
1805 EXPORT_SYMBOL(tegra_dc_config_pwm);
1806
1807 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1808                                 const struct tegra_dc_out_pin *pins,
1809                                 const unsigned int n_pins)
1810 {
1811         unsigned int i;
1812
1813         int name;
1814         int pol;
1815
1816         u32 pol1, pol3;
1817
1818         u32 set1, unset1;
1819         u32 set3, unset3;
1820
1821         set1 = set3 = unset1 = unset3 = 0;
1822
1823         for (i = 0; i < n_pins; i++) {
1824                 name = (pins + i)->name;
1825                 pol  = (pins + i)->pol;
1826
1827                 /* set polarity by name */
1828                 switch (name) {
1829                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1830                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1831                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1832                         else
1833                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1834                         break;
1835                 case TEGRA_DC_OUT_PIN_H_SYNC:
1836                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1837                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1838                         else
1839                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1840                         break;
1841                 case TEGRA_DC_OUT_PIN_V_SYNC:
1842                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1843                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1844                         else
1845                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1846                         break;
1847                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1848                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1849                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1850                         else
1851                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1852                         break;
1853                 default:
1854                         printk("Invalid argument in function %s\n",
1855                                __FUNCTION__);
1856                         break;
1857                 }
1858         }
1859
1860         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1861         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1862
1863         pol1 |= set1;
1864         pol1 &= ~unset1;
1865
1866         pol3 |= set3;
1867         pol3 &= ~unset3;
1868
1869         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1870         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1871 }
1872
1873 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1874 {
1875         dc->out = out;
1876
1877         if (out->n_modes > 0)
1878                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1879
1880         switch (out->type) {
1881         case TEGRA_DC_OUT_RGB:
1882                 dc->out_ops = &tegra_dc_rgb_ops;
1883                 break;
1884
1885         case TEGRA_DC_OUT_HDMI:
1886                 dc->out_ops = &tegra_dc_hdmi_ops;
1887                 break;
1888
1889         case TEGRA_DC_OUT_DSI:
1890                 dc->out_ops = &tegra_dc_dsi_ops;
1891                 break;
1892
1893         default:
1894                 dc->out_ops = NULL;
1895                 break;
1896         }
1897
1898         if (dc->out_ops && dc->out_ops->init)
1899                 dc->out_ops->init(dc);
1900
1901 }
1902
1903 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1904 {
1905         if (dc->out)
1906                 return dc->out->height;
1907         else
1908                 return 0;
1909 }
1910 EXPORT_SYMBOL(tegra_dc_get_out_height);
1911
1912 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1913 {
1914         if (dc->out)
1915                 return dc->out->width;
1916         else
1917                 return 0;
1918 }
1919 EXPORT_SYMBOL(tegra_dc_get_out_width);
1920
1921 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1922 {
1923         if (dc->out && dc->out->max_pixclock)
1924                 return dc->out->max_pixclock;
1925         else
1926                 return 0;
1927 }
1928 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1929
1930 void tegra_dc_enable_crc(struct tegra_dc *dc)
1931 {
1932         u32 val;
1933         tegra_dc_io_start(dc);
1934
1935         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1936                 CRC_ENABLE_ENABLE;
1937         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1938         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1939         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1940 }
1941
1942 void tegra_dc_disable_crc(struct tegra_dc *dc)
1943 {
1944         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1945         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1946         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1947
1948         tegra_dc_io_end(dc);
1949 }
1950
1951 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1952 {
1953         int crc = 0;
1954
1955         if(!dc) {
1956                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1957                 goto crc_error;
1958         }
1959
1960         /* TODO: Replace mdelay with code to sync VBlANK, since
1961          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1962         mdelay(TEGRA_CRC_LATCHED_DELAY);
1963
1964         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1965 crc_error:
1966         return crc;
1967 }
1968
1969 static void tegra_dc_vblank(struct work_struct *work)
1970 {
1971         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1972         bool nvsd_updated = false;
1973
1974         mutex_lock(&dc->lock);
1975
1976         /* update EMC clock if calculated bandwidth has changed */
1977         tegra_dc_program_bandwidth(dc);
1978
1979         /* Update the SD brightness */
1980         if (dc->enabled && dc->out->sd_settings)
1981                 nvsd_updated = nvsd_update_brightness(dc);
1982
1983         mutex_unlock(&dc->lock);
1984
1985         /* Do the actual brightness update outside of the mutex */
1986         if (nvsd_updated && dc->out->sd_settings &&
1987             dc->out->sd_settings->bl_device) {
1988
1989                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1990                 struct backlight_device *bl = platform_get_drvdata(pdev);
1991                 if (bl)
1992                         backlight_update_status(bl);
1993         }
1994 }
1995
1996 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1997 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1998 {
1999         u32 val, i;
2000
2001         /* Check for any underflow reset conditions */
2002         for (i = 0; i < DC_N_WINDOWS; i++) {
2003                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2004                         dc->windows[i].underflows++;
2005
2006 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2007                         if (dc->windows[i].underflows > 4)
2008                                 schedule_work(&dc->reset_work);
2009 #endif
2010                 } else {
2011                         dc->windows[i].underflows = 0;
2012                 }
2013         }
2014
2015         if (!dc->underflow_mask) {
2016                 /* If we have no underflow to check, go ahead
2017                    and disable the interrupt */
2018                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2019                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2020                         val &= ~FRAME_END_INT;
2021                 else
2022                         val &= ~V_BLANK_INT;
2023                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2024         }
2025
2026         /* Clear the underflow mask now that we've checked it. */
2027         dc->underflow_mask = 0;
2028 }
2029
2030 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2031 {
2032         u32 val, i;
2033         u32 completed = 0;
2034         u32 dirty = 0;
2035
2036         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2037         for (i = 0; i < DC_N_WINDOWS; i++) {
2038 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2039                 /* FIXME: this is not needed when the simulator
2040                    clears WIN_x_UPDATE bits as in HW */
2041                 dc->windows[i].dirty = 0;
2042                 completed = 1;
2043 #else
2044                 if (!(val & (WIN_A_UPDATE << i))) {
2045                         dc->windows[i].dirty = 0;
2046                         completed = 1;
2047                 } else {
2048                         dirty = 1;
2049                 }
2050 #endif
2051         }
2052
2053         if (!dirty) {
2054                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2055                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2056                         val &= ~V_BLANK_INT;
2057                 else
2058                         val &= ~FRAME_END_INT;
2059                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2060         }
2061
2062         if (completed) {
2063                 if (!dirty) {
2064                         /* With the last completed window, go ahead
2065                            and enable the vblank interrupt for nvsd. */
2066                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2067                         val |= V_BLANK_INT;
2068                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2069                 }
2070
2071                 wake_up(&dc->wq);
2072         }
2073 }
2074
2075 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2076 {
2077         if (status & V_BLANK_INT) {
2078                 /* Sync up windows. */
2079                 tegra_dc_trigger_windows(dc);
2080
2081                 /* Schedule any additional bottom-half vblank actvities. */
2082                 schedule_work(&dc->vblank_work);
2083         }
2084
2085         /* Check underflow at frame end */
2086         if (status & FRAME_END_INT) {
2087                 tegra_dc_underflow_handler(dc);
2088
2089                 /* Mark the frame_end as complete. */
2090                 if (!completion_done(&dc->frame_end_complete))
2091                         complete(&dc->frame_end_complete);
2092         }
2093 }
2094
2095 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2096 {
2097         if (status & V_BLANK_INT) {
2098                 /* Check underflow */
2099                 tegra_dc_underflow_handler(dc);
2100
2101                 /* Schedule any additional bottom-half vblank actvities. */
2102                 schedule_work(&dc->vblank_work);
2103         }
2104
2105         if (status & FRAME_END_INT) {
2106                 /* Mark the frame_end as complete. */
2107                 if (!completion_done(&dc->frame_end_complete))
2108                         complete(&dc->frame_end_complete);
2109
2110                 tegra_dc_trigger_windows(dc);
2111         }
2112 }
2113 #endif
2114
2115 /* return an arbitrarily large number if count overflow occurs.
2116  * make it a nice base-10 number to show up in stats output */
2117 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2118 {
2119         unsigned count = tegra_dc_readl(dc, reg);
2120         tegra_dc_writel(dc, 0, reg);
2121         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2122 }
2123
2124 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2125 {
2126 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2127         struct tegra_dc *dc = ptr;
2128         unsigned long status;
2129         unsigned long val;
2130         unsigned long underflow_mask;
2131
2132         if (!nvhost_module_powered(&dc->ndev->host->mod)) {
2133                 WARN(1, "IRQ when DC not powered!\n");
2134                 tegra_dc_io_start(dc);
2135                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2136                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2137                 tegra_dc_io_end(dc);
2138                 return IRQ_HANDLED;
2139         }
2140
2141         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2142         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2143
2144         /*
2145          * Overlays can get thier internal state corrupted during and underflow
2146          * condition.  The only way to fix this state is to reset the DC.
2147          * if we get 4 consecutive frames with underflows, assume we're
2148          * hosed and reset.
2149          */
2150         underflow_mask = status & ALL_UF_INT;
2151
2152         if (underflow_mask) {
2153                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2154                 val |= V_BLANK_INT;
2155                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2156                 dc->underflow_mask |= underflow_mask;
2157                 dc->stats.underflows++;
2158                 if (status & WIN_A_UF_INT)
2159                         dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2160                                 DC_WINBUF_AD_UFLOW_STATUS);
2161                 if (status & WIN_B_UF_INT)
2162                         dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2163                                 DC_WINBUF_BD_UFLOW_STATUS);
2164                 if (status & WIN_C_UF_INT)
2165                         dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2166                                 DC_WINBUF_CD_UFLOW_STATUS);
2167         }
2168
2169         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2170                 tegra_dc_one_shot_irq(dc, status);
2171         else
2172                 tegra_dc_continuous_irq(dc, status);
2173
2174         return IRQ_HANDLED;
2175 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2176         return IRQ_NONE;
2177 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2178 }
2179
2180 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2181 {
2182         u32 color_control;
2183
2184         switch (dc->out->depth) {
2185         case 3:
2186                 color_control = BASE_COLOR_SIZE111;
2187                 break;
2188
2189         case 6:
2190                 color_control = BASE_COLOR_SIZE222;
2191                 break;
2192
2193         case 8:
2194                 color_control = BASE_COLOR_SIZE332;
2195                 break;
2196
2197         case 9:
2198                 color_control = BASE_COLOR_SIZE333;
2199                 break;
2200
2201         case 12:
2202                 color_control = BASE_COLOR_SIZE444;
2203                 break;
2204
2205         case 15:
2206                 color_control = BASE_COLOR_SIZE555;
2207                 break;
2208
2209         case 16:
2210                 color_control = BASE_COLOR_SIZE565;
2211                 break;
2212
2213         case 18:
2214                 color_control = BASE_COLOR_SIZE666;
2215                 break;
2216
2217         default:
2218                 color_control = BASE_COLOR_SIZE888;
2219                 break;
2220         }
2221
2222         switch (dc->out->dither) {
2223         case TEGRA_DC_DISABLE_DITHER:
2224                 color_control |= DITHER_CONTROL_DISABLE;
2225                 break;
2226         case TEGRA_DC_ORDERED_DITHER:
2227                 color_control |= DITHER_CONTROL_ORDERED;
2228                 break;
2229         case TEGRA_DC_ERRDIFF_DITHER:
2230                 /* The line buffer for error-diffusion dither is limited
2231                  * to 1280 pixels per line. This limits the maximum
2232                  * horizontal active area size to 1280 pixels when error
2233                  * diffusion is enabled.
2234                  */
2235                 BUG_ON(dc->mode.h_active > 1280);
2236                 color_control |= DITHER_CONTROL_ERRDIFF;
2237                 break;
2238         }
2239
2240         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2241 }
2242
2243 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2244 {
2245         u32 syncpt_id;
2246
2247         switch (dc->ndev->id) {
2248         case 0:
2249                 switch (idx) {
2250                 case 0:
2251                         syncpt_id = NVSYNCPT_DISP0_A;
2252                         break;
2253                 case 1:
2254                         syncpt_id = NVSYNCPT_DISP0_B;
2255                         break;
2256                 case 2:
2257                         syncpt_id = NVSYNCPT_DISP0_C;
2258                         break;
2259                 default:
2260                         BUG();
2261                         break;
2262                 }
2263                 break;
2264         case 1:
2265                 switch (idx) {
2266                 case 0:
2267                         syncpt_id = NVSYNCPT_DISP1_A;
2268                         break;
2269                 case 1:
2270                         syncpt_id = NVSYNCPT_DISP1_B;
2271                         break;
2272                 case 2:
2273                         syncpt_id = NVSYNCPT_DISP1_C;
2274                         break;
2275                 default:
2276                         BUG();
2277                         break;
2278                 }
2279                 break;
2280         default:
2281                 BUG();
2282                 break;
2283         }
2284
2285         return syncpt_id;
2286 }
2287
2288 static void tegra_dc_init(struct tegra_dc *dc)
2289 {
2290         int i;
2291
2292         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2293         if (dc->ndev->id == 0) {
2294                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2295                                       TEGRA_MC_PRIO_MED);
2296                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2297                                       TEGRA_MC_PRIO_MED);
2298                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2299                                       TEGRA_MC_PRIO_MED);
2300                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2301                                       TEGRA_MC_PRIO_MED);
2302                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2303                                       TEGRA_MC_PRIO_HIGH);
2304         } else if (dc->ndev->id == 1) {
2305                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2306                                       TEGRA_MC_PRIO_MED);
2307                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2308                                       TEGRA_MC_PRIO_MED);
2309                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2310                                       TEGRA_MC_PRIO_MED);
2311                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2312                                       TEGRA_MC_PRIO_MED);
2313                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2314                                       TEGRA_MC_PRIO_HIGH);
2315         }
2316         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2317                         DC_CMD_CONT_SYNCPT_VSYNC);
2318         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2319         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2320         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2321         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2322
2323         /* enable interrupts for vblank, frame_end and underflows */
2324         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2325                 DC_CMD_INT_ENABLE);
2326         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2327
2328         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2329
2330         tegra_dc_set_color_control(dc);
2331         for (i = 0; i < DC_N_WINDOWS; i++) {
2332                 struct tegra_dc_win *win = &dc->windows[i];
2333                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2334                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2335                 tegra_dc_set_csc(dc, &win->csc);
2336                 tegra_dc_set_lut(dc, win);
2337                 tegra_dc_set_scaling_filter(dc);
2338         }
2339
2340
2341         for (i = 0; i < dc->n_windows; i++) {
2342                 u32 syncpt = get_syncpt(dc, i);
2343
2344                 dc->syncpt[i].id = syncpt;
2345
2346                 dc->syncpt[i].min = dc->syncpt[i].max =
2347                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2348         }
2349
2350         print_mode(dc, &dc->mode, __func__);
2351
2352         if (dc->mode.pclk)
2353                 tegra_dc_program_mode(dc, &dc->mode);
2354
2355         /* Initialize SD AFTER the modeset.
2356            nvsd_init handles the sd_settings = NULL case. */
2357         nvsd_init(dc, dc->out->sd_settings);
2358 }
2359
2360 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2361 {
2362         if (dc->out->enable)
2363                 dc->out->enable();
2364
2365         tegra_dc_setup_clk(dc, dc->clk);
2366         clk_enable(dc->clk);
2367         clk_enable(dc->emc_clk);
2368
2369         /* do not accept interrupts during initialization */
2370         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2371         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2372
2373         enable_dc_irq(dc->irq);
2374
2375         tegra_dc_init(dc);
2376
2377         if (dc->out_ops && dc->out_ops->enable)
2378                 dc->out_ops->enable(dc);
2379
2380         if (dc->out->postpoweron)
2381                 dc->out->postpoweron();
2382
2383         /* force a full blending update */
2384         dc->blend.z[0] = -1;
2385
2386         tegra_dc_ext_enable(dc->ext);
2387
2388         return true;
2389 }
2390
2391 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2392 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2393 {
2394         if (dc->out->enable)
2395                 dc->out->enable();
2396
2397         tegra_dc_setup_clk(dc, dc->clk);
2398         clk_enable(dc->clk);
2399         clk_enable(dc->emc_clk);
2400
2401         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2402                 mutex_lock(&tegra_dcs[1]->lock);
2403                 disable_irq(tegra_dcs[1]->irq);
2404         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2405                 mutex_lock(&tegra_dcs[0]->lock);
2406                 disable_irq(tegra_dcs[0]->irq);
2407         }
2408
2409         msleep(5);
2410         tegra_periph_reset_assert(dc->clk);
2411         msleep(2);
2412 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2413         tegra_periph_reset_deassert(dc->clk);
2414         msleep(1);
2415 #endif
2416
2417         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2418                 enable_dc_irq(tegra_dcs[1]->irq);
2419                 mutex_unlock(&tegra_dcs[1]->lock);
2420         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2421                 enable_dc_irq(tegra_dcs[0]->irq);
2422                 mutex_unlock(&tegra_dcs[0]->lock);
2423         }
2424
2425         enable_dc_irq(dc->irq);
2426
2427         tegra_dc_init(dc);
2428
2429         if (dc->out_ops && dc->out_ops->enable)
2430                 dc->out_ops->enable(dc);
2431
2432         if (dc->out->postpoweron)
2433                 dc->out->postpoweron();
2434
2435         /* force a full blending update */
2436         dc->blend.z[0] = -1;
2437
2438         return true;
2439 }
2440 #endif
2441
2442 static bool _tegra_dc_enable(struct tegra_dc *dc)
2443 {
2444         if (dc->mode.pclk == 0)
2445                 return false;
2446
2447         if (!dc->out)
2448                 return false;
2449
2450         tegra_dc_io_start(dc);
2451
2452         return _tegra_dc_controller_enable(dc);
2453 }
2454
2455 void tegra_dc_enable(struct tegra_dc *dc)
2456 {
2457         mutex_lock(&dc->lock);
2458
2459         if (!dc->enabled)
2460                 dc->enabled = _tegra_dc_enable(dc);
2461
2462         mutex_unlock(&dc->lock);
2463 }
2464
2465 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2466 {
2467         unsigned i;
2468
2469         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2470         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2471         disable_irq(dc->irq);
2472
2473         if (dc->out_ops && dc->out_ops->disable)
2474                 dc->out_ops->disable(dc);
2475
2476         clk_disable(dc->emc_clk);
2477         clk_disable(dc->clk);
2478         tegra_dvfs_set_rate(dc->clk, 0);
2479
2480         if (dc->out && dc->out->disable)
2481                 dc->out->disable();
2482
2483         for (i = 0; i < dc->n_windows; i++) {
2484                 struct tegra_dc_win *w = &dc->windows[i];
2485
2486                 /* reset window bandwidth */
2487                 w->bandwidth = 0;
2488                 w->new_bandwidth = 0;
2489
2490                 /* disable windows */
2491                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2492
2493                 /* flush any pending syncpt waits */
2494                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2495                         dc->syncpt[i].min++;
2496                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2497                                 dc->syncpt[i].id);
2498                 }
2499         }
2500 }
2501
2502 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2503 {
2504 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2505         u32 val;
2506         if (dc->enabled)  {
2507                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2508                 if (enable)
2509                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2510                 else
2511                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2512                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2513         }
2514 #endif
2515 }
2516
2517 bool tegra_dc_stats_get(struct tegra_dc *dc)
2518 {
2519 #if 0 /* right now it is always enabled */
2520         u32 val;
2521         bool res;
2522
2523         if (dc->enabled)  {
2524                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2525                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2526         } else {
2527                 res = false;
2528         }
2529
2530         return res;
2531 #endif
2532         return true;
2533 }
2534
2535 /* make the screen blank by disabling all windows */
2536 void tegra_dc_blank(struct tegra_dc *dc)
2537 {
2538         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2539         unsigned i;
2540
2541         for (i = 0; i < DC_N_WINDOWS; i++) {
2542                 dcwins[i] = tegra_dc_get_window(dc, i);
2543                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2544         }
2545
2546         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2547         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2548 }
2549
2550 static void _tegra_dc_disable(struct tegra_dc *dc)
2551 {
2552         _tegra_dc_controller_disable(dc);
2553         tegra_dc_io_end(dc);
2554 }
2555
2556 void tegra_dc_disable(struct tegra_dc *dc)
2557 {
2558         if (dc->overlay)
2559                 tegra_overlay_disable(dc->overlay);
2560
2561         tegra_dc_ext_disable(dc->ext);
2562
2563         mutex_lock(&dc->lock);
2564
2565         if (dc->enabled) {
2566                 dc->enabled = false;
2567
2568                 if (!dc->suspended)
2569                         _tegra_dc_disable(dc);
2570         }
2571
2572 #ifdef CONFIG_SWITCH
2573         switch_set_state(&dc->modeset_switch, 0);
2574 #endif
2575
2576         mutex_unlock(&dc->lock);
2577 }
2578
2579 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2580 static void tegra_dc_reset_worker(struct work_struct *work)
2581 {
2582         struct tegra_dc *dc =
2583                 container_of(work, struct tegra_dc, reset_work);
2584
2585         unsigned long val = 0;
2586
2587         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2588
2589         tegra_dc_ext_disable(dc->ext);
2590
2591         mutex_lock(&shared_lock);
2592         mutex_lock(&dc->lock);
2593
2594         if (dc->enabled == false)
2595                 goto unlock;
2596
2597         dc->enabled = false;
2598
2599         /*
2600          * off host read bus
2601          */
2602         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2603         val &= ~(0x00000100);
2604         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2605
2606         /*
2607          * set DC to STOP mode
2608          */
2609         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2610
2611         msleep(10);
2612
2613         _tegra_dc_controller_disable(dc);
2614
2615         /* _tegra_dc_controller_reset_enable deasserts reset */
2616         _tegra_dc_controller_reset_enable(dc);
2617
2618         dc->enabled = true;
2619 unlock:
2620         mutex_unlock(&dc->lock);
2621         mutex_unlock(&shared_lock);
2622 }
2623 #endif
2624
2625 #ifdef CONFIG_SWITCH
2626 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2627 {
2628         struct tegra_dc *dc =
2629                 container_of(sdev, struct tegra_dc, modeset_switch);
2630
2631         if (!sdev->state)
2632                 return sprintf(buf, "offline\n");
2633
2634         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2635 }
2636 #endif
2637
2638 static int tegra_dc_probe(struct nvhost_device *ndev)
2639 {
2640         struct tegra_dc *dc;
2641         struct clk *clk;
2642         struct clk *emc_clk;
2643         struct resource *res;
2644         struct resource *base_res;
2645         struct resource *fb_mem = NULL;
2646         int ret = 0;
2647         void __iomem *base;
2648         int irq;
2649         int i;
2650
2651         if (!ndev->dev.platform_data) {
2652                 dev_err(&ndev->dev, "no platform data\n");
2653                 return -ENOENT;
2654         }
2655
2656         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2657         if (!dc) {
2658                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2659                 return -ENOMEM;
2660         }
2661
2662         irq = nvhost_get_irq_byname(ndev, "irq");
2663         if (irq <= 0) {
2664                 dev_err(&ndev->dev, "no irq\n");
2665                 ret = -ENOENT;
2666                 goto err_free;
2667         }
2668
2669         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2670         if (!res) {
2671                 dev_err(&ndev->dev, "no mem resource\n");
2672                 ret = -ENOENT;
2673                 goto err_free;
2674         }
2675
2676         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2677         if (!base_res) {
2678                 dev_err(&ndev->dev, "request_mem_region failed\n");
2679                 ret = -EBUSY;
2680                 goto err_free;
2681         }
2682
2683         base = ioremap(res->start, resource_size(res));
2684         if (!base) {
2685                 dev_err(&ndev->dev, "registers can't be mapped\n");
2686                 ret = -EBUSY;
2687                 goto err_release_resource_reg;
2688         }
2689
2690         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2691
2692         clk = clk_get(&ndev->dev, NULL);
2693         if (IS_ERR_OR_NULL(clk)) {
2694                 dev_err(&ndev->dev, "can't get clock\n");
2695                 ret = -ENOENT;
2696                 goto err_iounmap_reg;
2697         }
2698
2699         emc_clk = clk_get(&ndev->dev, "emc");
2700         if (IS_ERR_OR_NULL(emc_clk)) {
2701                 dev_err(&ndev->dev, "can't get emc clock\n");
2702                 ret = -ENOENT;
2703                 goto err_put_clk;
2704         }
2705
2706         dc->clk = clk;
2707         dc->emc_clk = emc_clk;
2708
2709         dc->base_res = base_res;
2710         dc->base = base;
2711         dc->irq = irq;
2712         dc->ndev = ndev;
2713         dc->pdata = ndev->dev.platform_data;
2714
2715         /*
2716          * The emc is a shared clock, it will be set based on
2717          * the requirements for each user on the bus.
2718          */
2719         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2720         clk_set_rate(emc_clk, dc->emc_clk_rate);
2721
2722         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2723                 dc->enabled = true;
2724
2725         mutex_init(&dc->lock);
2726         init_completion(&dc->frame_end_complete);
2727         init_waitqueue_head(&dc->wq);
2728 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2729         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2730 #endif
2731         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2732
2733         tegra_dc_init_lut_defaults(&dc->fb_lut);
2734
2735         dc->n_windows = DC_N_WINDOWS;
2736         for (i = 0; i < dc->n_windows; i++) {
2737                 struct tegra_dc_win *win = &dc->windows[i];
2738                 win->idx = i;
2739                 win->dc = dc;
2740                 tegra_dc_init_csc_defaults(&win->csc);
2741                 tegra_dc_init_lut_defaults(&win->lut);
2742         }
2743
2744         ret = tegra_dc_set(dc, ndev->id);
2745         if (ret < 0) {
2746                 dev_err(&ndev->dev, "can't add dc\n");
2747                 goto err_free_irq;
2748         }
2749
2750         nvhost_set_drvdata(ndev, dc);
2751
2752 #ifdef CONFIG_SWITCH
2753         dc->modeset_switch.name = dev_name(&ndev->dev);
2754         dc->modeset_switch.state = 0;
2755         dc->modeset_switch.print_state = switch_modeset_print_mode;
2756         switch_dev_register(&dc->modeset_switch);
2757 #endif
2758
2759         if (dc->pdata->default_out)
2760                 tegra_dc_set_out(dc, dc->pdata->default_out);
2761         else
2762                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2763
2764         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2765                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2766
2767         dc->ext = tegra_dc_ext_register(ndev, dc);
2768         if (IS_ERR_OR_NULL(dc->ext)) {
2769                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2770                 dc->ext = NULL;
2771         }
2772
2773         /* interrupt handler must be registered before tegra_fb_register() */
2774         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2775                         dev_name(&ndev->dev), dc)) {
2776                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2777                 ret = -EBUSY;
2778                 goto err_put_emc_clk;
2779         }
2780
2781         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2782         disable_dc_irq(dc->irq);
2783
2784         mutex_lock(&dc->lock);
2785         if (dc->enabled)
2786                 _tegra_dc_enable(dc);
2787         mutex_unlock(&dc->lock);
2788
2789         tegra_dc_create_debugfs(dc);
2790
2791         dev_info(&ndev->dev, "probed\n");
2792
2793         if (dc->pdata->fb) {
2794                 if (dc->pdata->fb->bits_per_pixel == -1) {
2795                         unsigned long fmt;
2796                         tegra_dc_writel(dc,
2797                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2798                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2799
2800                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2801                         dc->pdata->fb->bits_per_pixel =
2802                                 tegra_dc_fmt_bpp(fmt);
2803                 }
2804
2805                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2806                 if (IS_ERR_OR_NULL(dc->fb))
2807                         dc->fb = NULL;
2808         }
2809
2810         if (dc->fb) {
2811                 dc->overlay = tegra_overlay_register(ndev, dc);
2812                 if (IS_ERR_OR_NULL(dc->overlay))
2813                         dc->overlay = NULL;
2814         }
2815
2816         if (dc->out && dc->out->hotplug_init)
2817                 dc->out->hotplug_init();
2818
2819         if (dc->out_ops && dc->out_ops->detect)
2820                 dc->out_ops->detect(dc);
2821         else
2822                 dc->connected = true;
2823
2824         tegra_dc_create_sysfs(&dc->ndev->dev);
2825
2826         return 0;
2827
2828 err_free_irq:
2829         free_irq(irq, dc);
2830 err_put_emc_clk:
2831         clk_put(emc_clk);
2832 err_put_clk:
2833         clk_put(clk);
2834 err_iounmap_reg:
2835         iounmap(base);
2836         if (fb_mem)
2837                 release_resource(fb_mem);
2838 err_release_resource_reg:
2839         release_resource(base_res);
2840 err_free:
2841         kfree(dc);
2842
2843         return ret;
2844 }
2845
2846 static int tegra_dc_remove(struct nvhost_device *ndev)
2847 {
2848         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2849
2850         tegra_dc_remove_sysfs(&dc->ndev->dev);
2851         tegra_dc_remove_debugfs(dc);
2852
2853         if (dc->overlay) {
2854                 tegra_overlay_unregister(dc->overlay);
2855         }
2856
2857         if (dc->fb) {
2858                 tegra_fb_unregister(dc->fb);
2859                 if (dc->fb_mem)
2860                         release_resource(dc->fb_mem);
2861         }
2862
2863         tegra_dc_ext_disable(dc->ext);
2864
2865         if (dc->ext)
2866                 tegra_dc_ext_unregister(dc->ext);
2867
2868         if (dc->enabled)
2869                 _tegra_dc_disable(dc);
2870
2871 #ifdef CONFIG_SWITCH
2872         switch_dev_unregister(&dc->modeset_switch);
2873 #endif
2874         free_irq(dc->irq, dc);
2875         clk_put(dc->emc_clk);
2876         clk_put(dc->clk);
2877         iounmap(dc->base);
2878         if (dc->fb_mem)
2879                 release_resource(dc->base_res);
2880         kfree(dc);
2881         tegra_dc_set(NULL, ndev->id);
2882         return 0;
2883 }
2884
2885 #ifdef CONFIG_PM
2886 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2887 {
2888         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2889
2890         dev_info(&ndev->dev, "suspend\n");
2891
2892         if (dc->overlay)
2893                 tegra_overlay_disable(dc->overlay);
2894
2895         tegra_dc_ext_disable(dc->ext);
2896
2897         mutex_lock(&dc->lock);
2898
2899         if (dc->out_ops && dc->out_ops->suspend)
2900                 dc->out_ops->suspend(dc);
2901
2902         if (dc->enabled) {
2903                 _tegra_dc_disable(dc);
2904
2905                 dc->suspended = true;
2906         }
2907
2908         if (dc->out && dc->out->postsuspend) {
2909                 dc->out->postsuspend();
2910                 msleep(100); /* avoid resume event due to voltage falling */
2911         }
2912
2913         mutex_unlock(&dc->lock);
2914
2915         return 0;
2916 }
2917
2918 static int tegra_dc_resume(struct nvhost_device *ndev)
2919 {
2920         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2921
2922         dev_info(&ndev->dev, "resume\n");
2923
2924         mutex_lock(&dc->lock);
2925         dc->suspended = false;
2926
2927         if (dc->enabled)
2928                 _tegra_dc_enable(dc);
2929
2930         if (dc->out && dc->out->hotplug_init)
2931                 dc->out->hotplug_init();
2932
2933         if (dc->out_ops && dc->out_ops->resume)
2934                 dc->out_ops->resume(dc);
2935         mutex_unlock(&dc->lock);
2936
2937         return 0;
2938 }
2939
2940 #endif /* CONFIG_PM */
2941
2942 extern int suspend_set(const char *val, struct kernel_param *kp)
2943 {
2944         if (!strcmp(val, "dump"))
2945                 dump_regs(tegra_dcs[0]);
2946 #ifdef CONFIG_PM
2947         else if (!strcmp(val, "suspend"))
2948                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2949         else if (!strcmp(val, "resume"))
2950                 tegra_dc_resume(tegra_dcs[0]->ndev);
2951 #endif
2952
2953         return 0;
2954 }
2955
2956 extern int suspend_get(char *buffer, struct kernel_param *kp)
2957 {
2958         return 0;
2959 }
2960
2961 int suspend;
2962
2963 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2964
2965 struct nvhost_driver tegra_dc_driver = {
2966         .driver = {
2967                 .name = "tegradc",
2968                 .owner = THIS_MODULE,
2969         },
2970         .probe = tegra_dc_probe,
2971         .remove = tegra_dc_remove,
2972 #ifdef CONFIG_PM
2973         .suspend = tegra_dc_suspend,
2974         .resume = tegra_dc_resume,
2975 #endif
2976 };
2977
2978 static int __init tegra_dc_module_init(void)
2979 {
2980         int ret = tegra_dc_ext_module_init();
2981         if (ret)
2982                 return ret;
2983         return nvhost_driver_register(&tegra_dc_driver);
2984 }
2985
2986 static void __exit tegra_dc_module_exit(void)
2987 {
2988         nvhost_driver_unregister(&tegra_dc_driver);
2989         tegra_dc_ext_module_exit();
2990 }
2991
2992 module_exit(tegra_dc_module_exit);
2993 module_init(tegra_dc_module_init);