video: tegra: dc: 1-shot bandwidth calculation
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134         case TEGRA_WIN_FMT_YCbCr422R:
135         case TEGRA_WIN_FMT_YUV422R:
136         case TEGRA_WIN_FMT_YCbCr422RA:
137         case TEGRA_WIN_FMT_YUV422RA:
138                 return 8;
139
140         case TEGRA_WIN_FMT_YCbCr422:
141         case TEGRA_WIN_FMT_YUV422:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155         case TEGRA_WIN_FMT_YCbCr422R:
156         case TEGRA_WIN_FMT_YUV422R:
157         case TEGRA_WIN_FMT_YCbCr422RA:
158         case TEGRA_WIN_FMT_YUV422RA:
159                 return true;
160         }
161         return false;
162 }
163
164 #define DUMP_REG(a) do {                        \
165         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
166                  #a, a, tegra_dc_readl(dc, a));               \
167         print(data, buff);                                    \
168         } while (0)
169
170 static void _dump_regs(struct tegra_dc *dc, void *data,
171                        void (* print)(void *data, const char *str))
172 {
173         int i;
174         char buff[256];
175
176         tegra_dc_io_start(dc);
177         clk_enable(dc->clk);
178
179         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
180         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
181         DUMP_REG(DC_CMD_SIGNAL_RAISE);
182         DUMP_REG(DC_CMD_INT_STATUS);
183         DUMP_REG(DC_CMD_INT_MASK);
184         DUMP_REG(DC_CMD_INT_ENABLE);
185         DUMP_REG(DC_CMD_INT_TYPE);
186         DUMP_REG(DC_CMD_INT_POLARITY);
187         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
188         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
190         DUMP_REG(DC_CMD_STATE_ACCESS);
191         DUMP_REG(DC_CMD_STATE_CONTROL);
192         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
193         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
194
195         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
196         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
197         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
198         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
199         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
200         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
201         DUMP_REG(DC_DISP_REF_TO_SYNC);
202         DUMP_REG(DC_DISP_SYNC_WIDTH);
203         DUMP_REG(DC_DISP_BACK_PORCH);
204         DUMP_REG(DC_DISP_DISP_ACTIVE);
205         DUMP_REG(DC_DISP_FRONT_PORCH);
206         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
211         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
212         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
213         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
216         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
217         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
218         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
221         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
229         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
230         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
231         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
233         DUMP_REG(DC_DISP_M0_CONTROL);
234         DUMP_REG(DC_DISP_M1_CONTROL);
235         DUMP_REG(DC_DISP_DI_CONTROL);
236         DUMP_REG(DC_DISP_PP_CONTROL);
237         DUMP_REG(DC_DISP_PP_SELECT_A);
238         DUMP_REG(DC_DISP_PP_SELECT_B);
239         DUMP_REG(DC_DISP_PP_SELECT_C);
240         DUMP_REG(DC_DISP_PP_SELECT_D);
241         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
242         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
243         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
244         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
245         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
246         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
247         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
248         DUMP_REG(DC_DISP_BORDER_COLOR);
249         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
250         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
251         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
253         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
254         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
255         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
256         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
257         DUMP_REG(DC_DISP_CURSOR_POSITION);
258         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
259         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
260         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
261         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
264         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
265         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
266         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
269         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
270         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
271
272
273         for (i = 0; i < 3; i++) {
274                 print(data, "\n");
275                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
276                 print(data, buff);
277
278                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
279                                 DC_CMD_DISPLAY_WINDOW_HEADER);
280                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
281                 DUMP_REG(DC_WIN_WIN_OPTIONS);
282                 DUMP_REG(DC_WIN_BYTE_SWAP);
283                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
284                 DUMP_REG(DC_WIN_COLOR_DEPTH);
285                 DUMP_REG(DC_WIN_POSITION);
286                 DUMP_REG(DC_WIN_SIZE);
287                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
288                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
289                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
290                 DUMP_REG(DC_WIN_DDA_INCREMENT);
291                 DUMP_REG(DC_WIN_LINE_STRIDE);
292                 DUMP_REG(DC_WIN_BUF_STRIDE);
293                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
294                 DUMP_REG(DC_WIN_BLEND_NOKEY);
295                 DUMP_REG(DC_WIN_BLEND_1WIN);
296                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
297                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
298                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
299                 DUMP_REG(DC_WINBUF_START_ADDR);
300                 DUMP_REG(DC_WINBUF_START_ADDR_U);
301                 DUMP_REG(DC_WINBUF_START_ADDR_V);
302                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
303                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
304                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
305                 DUMP_REG(DC_WIN_CSC_YOF);
306                 DUMP_REG(DC_WIN_CSC_KYRGB);
307                 DUMP_REG(DC_WIN_CSC_KUR);
308                 DUMP_REG(DC_WIN_CSC_KVR);
309                 DUMP_REG(DC_WIN_CSC_KUG);
310                 DUMP_REG(DC_WIN_CSC_KVG);
311                 DUMP_REG(DC_WIN_CSC_KUB);
312                 DUMP_REG(DC_WIN_CSC_KVB);
313         }
314
315         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
316         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
317         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
318         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
319         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
321         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
322         DUMP_REG(DC_DISP_M1_CONTROL);
323         DUMP_REG(DC_COM_PM1_CONTROL);
324         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
325         DUMP_REG(DC_DISP_SD_CONTROL);
326
327         clk_disable(dc->clk);
328         tegra_dc_io_end(dc);
329 }
330
331 #undef DUMP_REG
332
333 #ifdef DEBUG
334 static void dump_regs_print(void *data, const char *str)
335 {
336         struct tegra_dc *dc = data;
337         dev_dbg(&dc->ndev->dev, "%s", str);
338 }
339
340 static void dump_regs(struct tegra_dc *dc)
341 {
342         _dump_regs(dc, dc, dump_regs_print);
343 }
344 #else /* !DEBUG */
345
346 static void dump_regs(struct tegra_dc *dc) {}
347
348 #endif /* DEBUG */
349
350 #ifdef CONFIG_DEBUG_FS
351
352 static void dbg_regs_print(void *data, const char *str)
353 {
354         struct seq_file *s = data;
355
356         seq_printf(s, "%s", str);
357 }
358
359 #undef DUMP_REG
360
361 static int dbg_dc_show(struct seq_file *s, void *unused)
362 {
363         struct tegra_dc *dc = s->private;
364
365         _dump_regs(dc, s, dbg_regs_print);
366
367         return 0;
368 }
369
370
371 static int dbg_dc_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_show, inode->i_private);
374 }
375
376 static const struct file_operations regs_fops = {
377         .open           = dbg_dc_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386         struct tegra_dc_mode *m;
387
388         mutex_lock(&dc->lock);
389         m = &dc->mode;
390         seq_printf(s,
391                 "pclk: %d\n"
392                 "h_ref_to_sync: %d\n"
393                 "v_ref_to_sync: %d\n"
394                 "h_sync_width: %d\n"
395                 "v_sync_width: %d\n"
396                 "h_back_porch: %d\n"
397                 "v_back_porch: %d\n"
398                 "h_active: %d\n"
399                 "v_active: %d\n"
400                 "h_front_porch: %d\n"
401                 "v_front_porch: %d\n"
402                 "stereo_mode: %d\n",
403                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
404                 m->h_sync_width, m->v_sync_width,
405                 m->h_back_porch, m->v_back_porch,
406                 m->h_active, m->v_active,
407                 m->h_front_porch, m->v_front_porch,
408                 m->stereo_mode);
409         mutex_unlock(&dc->lock);
410         return 0;
411 }
412
413 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
414 {
415         return single_open(file, dbg_dc_mode_show, inode->i_private);
416 }
417
418 static const struct file_operations mode_fops = {
419         .open           = dbg_dc_mode_open,
420         .read           = seq_read,
421         .llseek         = seq_lseek,
422         .release        = single_release,
423 };
424
425 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
426 {
427         struct tegra_dc *dc = s->private;
428
429         mutex_lock(&dc->lock);
430         seq_printf(s,
431                 "underflows: %llu\n"
432                 "underflows_a: %llu\n"
433                 "underflows_b: %llu\n"
434                 "underflows_c: %llu\n",
435                 dc->stats.underflows,
436                 dc->stats.underflows_a,
437                 dc->stats.underflows_b,
438                 dc->stats.underflows_c);
439         mutex_unlock(&dc->lock);
440
441         return 0;
442 }
443
444 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
445 {
446         return single_open(file, dbg_dc_stats_show, inode->i_private);
447 }
448
449 static const struct file_operations stats_fops = {
450         .open           = dbg_dc_stats_open,
451         .read           = seq_read,
452         .llseek         = seq_lseek,
453         .release        = single_release,
454 };
455
456 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
457 {
458         if (dc->debugdir)
459                 debugfs_remove_recursive(dc->debugdir);
460         dc->debugdir = NULL;
461 }
462
463 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
464 {
465         struct dentry *retval;
466
467         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
468         if (!dc->debugdir)
469                 goto remove_out;
470
471         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
472                 &regs_fops);
473         if (!retval)
474                 goto remove_out;
475
476         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
477                 &mode_fops);
478         if (!retval)
479                 goto remove_out;
480
481         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
482                 &stats_fops);
483         if (!retval)
484                 goto remove_out;
485
486         return;
487 remove_out:
488         dev_err(&dc->ndev->dev, "could not create debugfs\n");
489         tegra_dc_remove_debugfs(dc);
490 }
491
492 #else /* !CONFIG_DEBUGFS */
493 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
494 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
495 #endif /* CONFIG_DEBUGFS */
496
497 static int tegra_dc_set(struct tegra_dc *dc, int index)
498 {
499         int ret = 0;
500
501         mutex_lock(&tegra_dc_lock);
502         if (index >= TEGRA_MAX_DC) {
503                 ret = -EINVAL;
504                 goto out;
505         }
506
507         if (dc != NULL && tegra_dcs[index] != NULL) {
508                 ret = -EBUSY;
509                 goto out;
510         }
511
512         tegra_dcs[index] = dc;
513
514 out:
515         mutex_unlock(&tegra_dc_lock);
516
517         return ret;
518 }
519
520 unsigned int tegra_dc_has_multiple_dc(void)
521 {
522         unsigned int idx;
523         unsigned int cnt = 0;
524         struct tegra_dc *dc;
525
526         mutex_lock(&tegra_dc_lock);
527         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
528                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
529         mutex_unlock(&tegra_dc_lock);
530
531         return (cnt > 1);
532 }
533
534 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
535 {
536         if (idx < TEGRA_MAX_DC)
537                 return tegra_dcs[idx];
538         else
539                 return NULL;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_dc);
542
543 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
544 {
545         if (win >= dc->n_windows)
546                 return NULL;
547
548         return &dc->windows[win];
549 }
550 EXPORT_SYMBOL(tegra_dc_get_window);
551
552 static int get_topmost_window(u32 *depths, unsigned long *wins)
553 {
554         int idx, best = -1;
555
556         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
557                 if (best == -1 || depths[idx] < depths[best])
558                         best = idx;
559         }
560         clear_bit(best, wins);
561         return best;
562 }
563
564 bool tegra_dc_get_connected(struct tegra_dc *dc)
565 {
566         return dc->connected;
567 }
568 EXPORT_SYMBOL(tegra_dc_get_connected);
569
570 static u32 blend_topwin(u32 flags)
571 {
572         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
573                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
574         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
575                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
576         else
577                 return BLEND(NOKEY, FIX, 0xff, 0xff);
578 }
579
580 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
581 {
582         int other;
583
584         for (other = 0; other < DC_N_WINDOWS; other++) {
585                 if (other != idx && (xy-- == 0))
586                         break;
587         }
588         if (BIT(other) & behind_mask)
589                 return blend_topwin(flags[idx]);
590         else if (flags[other])
591                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
592         else
593                 return BLEND(NOKEY, FIX, 0x00, 0x00);
594 }
595
596 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
597 {
598         unsigned long infront_mask;
599         int first;
600
601         infront_mask = ~(behind_mask | BIT(idx));
602         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
603         first = ffs(infront_mask) - 1;
604
605         if (!infront_mask)
606                 return blend_topwin(flags[idx]);
607         else if (behind_mask && first != -1 && flags[first])
608                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
609         else
610                 return BLEND(NOKEY, FIX, 0x0, 0x0);
611 }
612
613 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
614 {
615         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
616
617         while (mask) {
618                 int idx = get_topmost_window(blend->z, &mask);
619
620                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
621                                 DC_CMD_DISPLAY_WINDOW_HEADER);
622                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
623                                 DC_WIN_BLEND_NOKEY);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_1WIN);
626                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
627                                 DC_WIN_BLEND_2WIN_X);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
629                                 DC_WIN_BLEND_2WIN_Y);
630                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
631                                 DC_WIN_BLEND_3WIN_XY);
632         }
633 }
634
635 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 {
637         csc->yof   = 0x00f0;
638         csc->kyrgb = 0x012a;
639         csc->kur   = 0x0000;
640         csc->kvr   = 0x0198;
641         csc->kug   = 0x039b;
642         csc->kvg   = 0x032f;
643         csc->kub   = 0x0204;
644         csc->kvb   = 0x0000;
645 }
646
647 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
648 {
649         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
650         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
651         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
652         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
653         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
654         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
655         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
656         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
657 }
658
659 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
660 {
661         mutex_lock(&dc->lock);
662
663         if (!dc->enabled) {
664                 mutex_unlock(&dc->lock);
665                 return -EFAULT;
666         }
667
668         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
669                         DC_CMD_DISPLAY_WINDOW_HEADER);
670
671         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
672
673         mutex_unlock(&dc->lock);
674
675         return 0;
676 }
677 EXPORT_SYMBOL(tegra_dc_update_csc);
678
679 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
680 {
681         int i;
682         for (i = 0; i < 256; i++)
683                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
684 }
685
686 static int tegra_dc_loop_lut(struct tegra_dc *dc,
687                              struct tegra_dc_win *win,
688                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
689 {
690         struct tegra_dc_lut *lut = &win->lut;
691         struct tegra_dc_lut *global_lut = &dc->fb_lut;
692         int i;
693         for (i = 0; i < 256; i++) {
694
695                 u32 r = (u32)lut->r[i];
696                 u32 g = (u32)lut->g[i];
697                 u32 b = (u32)lut->b[i];
698
699                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
700                         r = (u32)global_lut->r[r];
701                         g = (u32)global_lut->g[g];
702                         b = (u32)global_lut->b[b];
703                 }
704
705                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
706                         return 0;
707         }
708         return 1;
709 }
710
711 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
712 {
713         if (rgb != (i | (i<<8) | (i<<16)))
714                 return 0;
715         return 1;
716 }
717
718 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
719 {
720         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
721         return 1;
722 }
723
724 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
725 {
726         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
727
728         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
729
730         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
731                 val |= CP_ENABLE;
732         else
733                 val &= ~CP_ENABLE;
734
735         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
736 }
737
738 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
739 {
740         struct tegra_dc_win *win = &dc->windows[win_idx];
741
742         mutex_lock(&dc->lock);
743
744         if (!dc->enabled) {
745                 mutex_unlock(&dc->lock);
746                 return -EFAULT;
747         }
748
749         if (fbovr > 0)
750                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
751         else if (fbovr == 0)
752                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753
754         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
756         else
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
758
759         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
760                         DC_CMD_DISPLAY_WINDOW_HEADER);
761
762         tegra_dc_set_lut(dc, win);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768
769 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
770 {
771         if (win_idx > -1)
772                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
773
774         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
775                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
776                 if (err)
777                         return err;
778         }
779
780         return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_update_lut);
783
784 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
785 {
786         unsigned i;
787         unsigned v0 = 128;
788         unsigned v1 = 0;
789         /* linear horizontal and vertical filters */
790         for (i = 0; i < 16; i++) {
791                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
792                                 DC_WIN_H_FILTER_P(i));
793
794                 tegra_dc_writel(dc, v0,
795                                 DC_WIN_V_FILTER_P(i));
796                 v0 -= 8;
797                 v1 += 8;
798         }
799 }
800
801 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
802         struct tegra_dc_win *w)
803 {
804         /* windows A, B, C for first and second display */
805         static const enum tegra_la_id la_id_tab[2][3] = {
806                 /* first display */
807                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
808                         TEGRA_LA_DISPLAY_0C },
809                 /* second display */
810                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
811                         TEGRA_LA_DISPLAY_0CB },
812         };
813         /* window B V-filter tap for first and second display. */
814         static const enum tegra_la_id vfilter_tab[2] = {
815                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
816         };
817         unsigned long bw;
818
819         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
820         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
821         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
822
823         bw = w->new_bandwidth;
824
825         /* tegra_dc_get_bandwidth() treats V filter windows as double
826          * bandwidth, but LA has a seperate client for V filter */
827         if (w->idx == 1 && win_use_v_filter(w))
828                 bw /= 2;
829
830         /* our bandwidth is in bytes/sec, but LA takes MBps.
831          * round up bandwidth to 1MBps */
832         bw = bw / 1000000 + 1;
833
834 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
835         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
836         /* if window B, also set the 1B client for the 2-tap V filter. */
837         if (w->idx == 1)
838                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
839 #endif
840
841         w->bandwidth = w->new_bandwidth;
842 }
843
844 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
845                                                    struct tegra_dc_win *b)
846 {
847         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
848                 return 0;
849
850         /* because memory access to load the fifo can overlap, only care
851          * if windows overlap vertically */
852         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
853                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
854 }
855
856 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
857                                                  int n)
858 {
859         unsigned i;
860         unsigned j;
861         unsigned overlap_count;
862         unsigned max_bw = 0;
863
864         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
865                          "inaccurate.\n");
866
867         /* If we had a large number of windows, we would compute adjacency
868          * graph representing 2 window overlaps, find all cliques in the graph,
869          * assign bandwidth to each clique, and then select the clique with
870          * maximum bandwidth. But because we have at most 3 windows,
871          * implementing proper Bron-Kerbosh algorithm would be an overkill,
872          * brute force will suffice.
873          *
874          * Thus: find maximum bandwidth for either single or a pair of windows
875          * and count number of window pair overlaps. If there are three
876          * pairs, all 3 window overlap.
877          */
878
879         overlap_count = 0;
880         for (i = 0; i < n; i++) {
881                 unsigned int bw1;
882
883                 if (wins[i] == NULL)
884                         continue;
885                 bw1 = wins[i]->new_bandwidth;
886                 if (bw1 > max_bw)
887                         /* Single window */
888                         max_bw = bw1;
889
890                 for (j = i + 1; j < n; j++) {
891                         if (wins[j] == NULL)
892                                 continue;
893                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
894                                 unsigned int bw2 = wins[j]->new_bandwidth;
895                                 if (bw1 + bw2 > max_bw)
896                                         /* Window pair overlaps */
897                                         max_bw = bw1 + bw2;
898                                 overlap_count++;
899                         }
900                 }
901         }
902
903         if (overlap_count == 3)
904                 /* All three windows overlap */
905                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
906                          wins[2]->new_bandwidth;
907
908         return max_bw;
909 }
910
911 /*
912  * Calculate peak EMC bandwidth for each enabled window =
913  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
914  * (windows_tiling ? 2 : 1)
915  *
916  *
917  * note:
918  * (*) We use 2 tap V filter, so need double BW if use V filter
919  * (*) Tiling mode on T30 and DDR3 requires double BW
920  */
921 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
922         struct tegra_dc_win *w)
923 {
924         unsigned long ret;
925         int tiled_windows_bw_multiplier;
926         unsigned long bpp;
927
928         if (!WIN_IS_ENABLED(w))
929                 return 0;
930
931         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
932             w->out_w == 0 || w->out_h == 0)
933                 return 0;
934
935         tiled_windows_bw_multiplier =
936                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
937
938         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
939          * but the size reported by tegra_dc_fmt_bpp for the planar version
940          * is of the luma plane's size only. */
941         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
942                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
943         /* perform calculations with most significant bits of pixel clock
944          * to prevent overflow of long. */
945         ret = (unsigned long)(dc->mode.pclk >> 16) *
946                 bpp / 8 *
947                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
948                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
949
950 /*
951  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
952  * will request 147MBps from EMC.
953  */
954         ret = ret * 2 + ret / 10;
955
956         /* if overflowed */
957         if (ret > (1UL << 31))
958                 return ULONG_MAX;
959
960         return ret << 16; /* restore the scaling we did above */
961 }
962
963 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
964 {
965         int i;
966
967         BUG_ON(n > DC_N_WINDOWS);
968
969         /* emc rate and latency allowance both need to know per window
970          * bandwidths */
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *w = windows[i];
973                 if (w)
974                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
975         }
976
977         return tegra_dc_find_max_bandwidth(windows, n);
978 }
979
980 /* to save power, call when display memory clients would be idle */
981 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
982 {
983         if (dc->emc_clk_rate)
984                 clk_disable(dc->emc_clk);
985         dc->emc_clk_rate = 0;
986 }
987
988 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
989 {
990         unsigned i;
991
992         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
993                 if (!dc->emc_clk_rate) /* going from 0 to non-zero */
994                         clk_enable(dc->emc_clk);
995                 dc->emc_clk_rate = dc->new_emc_clk_rate;
996                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
997         }
998
999         for (i = 0; i < DC_N_WINDOWS; i++) {
1000                 struct tegra_dc_win *w = &dc->windows[i];
1001                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1002                         tegra_dc_set_latency_allowance(dc, w);
1003         }
1004 }
1005
1006 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1007 {
1008         unsigned long new_rate;
1009         struct tegra_dc *dc;
1010
1011         if (!use_dynamic_emc)
1012                 return 0;
1013
1014         dc = windows[0]->dc;
1015
1016         /* calculate the new rate based on this POST */
1017         new_rate = tegra_dc_get_bandwidth(windows, n);
1018         new_rate = EMC_BW_TO_FREQ(new_rate);
1019
1020         if (tegra_dc_has_multiple_dc())
1021                 new_rate = ULONG_MAX;
1022
1023         dc->new_emc_clk_rate = new_rate;
1024
1025         return 0;
1026 }
1027
1028 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1029                                   bool v, unsigned Bpp)
1030 {
1031         /*
1032          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1033          *           (post_scaled_size_in_pixels - 1)), MAX)
1034          * Where the value of MAX is as follows:
1035          * For V_DDA_INCREMENT: 15.0 (0xF000)
1036          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1037          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1038          */
1039
1040         fixed20_12 out = dfixed_init(out_int);
1041         u32 dda_inc;
1042         int max;
1043
1044         if (v) {
1045                 max = 15;
1046         } else {
1047                 switch (Bpp) {
1048                 default:
1049                         WARN_ON_ONCE(1);
1050                         /* fallthrough */
1051                 case 4:
1052                         max = 4;
1053                         break;
1054                 case 2:
1055                         max = 8;
1056                         break;
1057                 }
1058         }
1059
1060         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1061         in.full -= dfixed_const(1);
1062
1063         dda_inc = dfixed_div(in, out);
1064
1065         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1066
1067         return dda_inc;
1068 }
1069
1070 static inline u32 compute_initial_dda(fixed20_12 in)
1071 {
1072         return dfixed_frac(in);
1073 }
1074
1075 /* does not support updating windows on multiple dcs in one call */
1076 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1077 {
1078         struct tegra_dc *dc;
1079         unsigned long update_mask = GENERAL_ACT_REQ;
1080         unsigned long val;
1081         bool update_blend = false;
1082         int i;
1083
1084         dc = windows[0]->dc;
1085
1086         mutex_lock(&dc->lock);
1087
1088         if (!dc->enabled) {
1089                 mutex_unlock(&dc->lock);
1090                 return -EFAULT;
1091         }
1092
1093         if (no_vsync)
1094                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1095         else
1096                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1097
1098         for (i = 0; i < n; i++) {
1099                 struct tegra_dc_win *win = windows[i];
1100                 unsigned h_dda;
1101                 unsigned v_dda;
1102                 fixed20_12 h_offset, v_offset;
1103                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1104                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1105                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1106                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1107                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1108                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1109                 const bool filter_h = win_use_h_filter(win);
1110                 const bool filter_v = win_use_v_filter(win);
1111
1112                 if (win->z != dc->blend.z[win->idx]) {
1113                         dc->blend.z[win->idx] = win->z;
1114                         update_blend = true;
1115                 }
1116                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1117                         dc->blend.flags[win->idx]) {
1118                         dc->blend.flags[win->idx] =
1119                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1120                         update_blend = true;
1121                 }
1122
1123                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1124                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1125
1126                 if (!no_vsync)
1127                         update_mask |= WIN_A_ACT_REQ << win->idx;
1128
1129                 if (!WIN_IS_ENABLED(win)) {
1130                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1131                         continue;
1132                 }
1133
1134                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1135                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1136
1137                 tegra_dc_writel(dc,
1138                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1139                                 DC_WIN_POSITION);
1140                 tegra_dc_writel(dc,
1141                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1142                                 DC_WIN_SIZE);
1143                 tegra_dc_writel(dc,
1144                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1145                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1146                                 DC_WIN_PRESCALED_SIZE);
1147
1148                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1149                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1150                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1151                                 DC_WIN_DDA_INCREMENT);
1152                 h_dda = compute_initial_dda(win->x);
1153                 v_dda = compute_initial_dda(win->y);
1154                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1155                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1156
1157                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1158                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1159                 tegra_dc_writel(dc,
1160                                 (unsigned long)win->phys_addr,
1161                                 DC_WINBUF_START_ADDR);
1162
1163                 if (!yuvp) {
1164                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1165                 } else {
1166                         tegra_dc_writel(dc,
1167                                         (unsigned long)win->phys_addr_u,
1168                                         DC_WINBUF_START_ADDR_U);
1169                         tegra_dc_writel(dc,
1170                                         (unsigned long)win->phys_addr_v,
1171                                         DC_WINBUF_START_ADDR_V);
1172                         tegra_dc_writel(dc,
1173                                         LINE_STRIDE(win->stride) |
1174                                         UV_LINE_STRIDE(win->stride_uv),
1175                                         DC_WIN_LINE_STRIDE);
1176                 }
1177
1178                 h_offset = win->x;
1179                 if (invert_h) {
1180                         h_offset.full += win->w.full - dfixed_const(1);
1181                 }
1182
1183                 v_offset = win->y;
1184                 if (invert_v) {
1185                         v_offset.full += win->h.full - dfixed_const(1);
1186                 }
1187
1188                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1189                                 DC_WINBUF_ADDR_H_OFFSET);
1190                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1191                                 DC_WINBUF_ADDR_V_OFFSET);
1192
1193                 if (WIN_IS_TILED(win))
1194                         tegra_dc_writel(dc,
1195                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1196                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1197                                         DC_WIN_BUFFER_ADDR_MODE);
1198                 else
1199                         tegra_dc_writel(dc,
1200                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1201                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1202                                         DC_WIN_BUFFER_ADDR_MODE);
1203
1204                 val = WIN_ENABLE;
1205                 if (yuvp)
1206                         val |= CSC_ENABLE;
1207                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1208                         val |= COLOR_EXPAND;
1209
1210                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1211                         val |= CP_ENABLE;
1212
1213                 if (filter_h)
1214                         val |= H_FILTER_ENABLE;
1215                 if (filter_v)
1216                         val |= V_FILTER_ENABLE;
1217
1218                 if (invert_h)
1219                         val |= H_DIRECTION_DECREMENT;
1220                 if (invert_v)
1221                         val |= V_DIRECTION_DECREMENT;
1222
1223                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1224
1225                 win->dirty = no_vsync ? 0 : 1;
1226
1227                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1228                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1229                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1230                         __func__, win->idx, win->z,
1231                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1232                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1233                         win->out_x, win->out_y, win->out_w, win->out_h,
1234                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1235         }
1236
1237         if (update_blend) {
1238                 tegra_dc_set_blending(dc, &dc->blend);
1239                 for (i = 0; i < DC_N_WINDOWS; i++) {
1240                         if (!no_vsync)
1241                                 dc->windows[i].dirty = 1;
1242                         update_mask |= WIN_A_ACT_REQ << i;
1243                 }
1244         }
1245
1246         tegra_dc_set_dynamic_emc(windows, n);
1247
1248         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1249
1250         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1251         if (!no_vsync) {
1252                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1253                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1254                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1255         } else {
1256                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1257                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1258                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1259         }
1260
1261         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1262
1263         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1264                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1265
1266         /* update EMC clock if calculated bandwidth has changed */
1267         tegra_dc_program_bandwidth(dc);
1268
1269         mutex_unlock(&dc->lock);
1270
1271         return 0;
1272 }
1273 EXPORT_SYMBOL(tegra_dc_update_windows);
1274
1275 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1276 {
1277         return dc->syncpt[i].id;
1278 }
1279 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1280
1281 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1282 {
1283         u32 max;
1284
1285         mutex_lock(&dc->lock);
1286         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1287                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1288         dc->syncpt[i].max = max;
1289         mutex_unlock(&dc->lock);
1290
1291         return max;
1292 }
1293
1294 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1295 {
1296         mutex_lock(&dc->lock);
1297         if ( dc->enabled )
1298                 while (dc->syncpt[i].min < val) {
1299                         dc->syncpt[i].min++;
1300                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1301                                         dc->syncpt[i].id);
1302                 }
1303         mutex_unlock(&dc->lock);
1304 }
1305
1306 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1307                                              int n)
1308 {
1309         int i;
1310
1311         for (i = 0; i < n; i++) {
1312                 if (windows[i]->dirty)
1313                         return false;
1314         }
1315
1316         return true;
1317 }
1318
1319 /* does not support syncing windows on multiple dcs in one call */
1320 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1321 {
1322         if (n < 1 || n > DC_N_WINDOWS)
1323                 return -EINVAL;
1324
1325         if (!windows[0]->dc->enabled)
1326                 return -EFAULT;
1327
1328 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1329         /* Don't want to timeout on simulator */
1330         return wait_event_interruptible(windows[0]->dc->wq,
1331                 tegra_dc_windows_are_clean(windows, n));
1332 #else
1333         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1334                                          tegra_dc_windows_are_clean(windows, n),
1335                                          HZ);
1336 #endif
1337 }
1338 EXPORT_SYMBOL(tegra_dc_sync_windows);
1339
1340 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1341 {
1342 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1343         return clk_get_rate(dc->clk);
1344 #else
1345         return 27000000;
1346 #endif
1347 }
1348
1349 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1350 {
1351         unsigned long rate;
1352         unsigned long div;
1353
1354         rate = tegra_dc_clk_get_rate(dc);
1355
1356         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1357
1358         if (div < 2)
1359                 return 0;
1360
1361         return rate * 2 / div;
1362 }
1363
1364 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1365 {
1366         int pclk;
1367
1368         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1369                 unsigned long rate;
1370                 struct clk *parent_clk =
1371                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1372
1373                 if (clk_get_parent(clk) != parent_clk)
1374                         clk_set_parent(clk, parent_clk);
1375
1376                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1377                         struct clk *base_clk = clk_get_parent(parent_clk);
1378
1379                         /* Assuming either pll_d or pll_d2 is used */
1380                         rate = dc->mode.pclk * 2;
1381
1382                         if (rate != clk_get_rate(base_clk))
1383                                 clk_set_rate(base_clk, rate);
1384                 }
1385         }
1386
1387         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1388                 unsigned long rate;
1389                 struct clk *parent_clk =
1390                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1391                 struct clk *base_clk = clk_get_parent(parent_clk);
1392
1393                 /* needs to match tegra_dc_hdmi_supported_modes[]
1394                 and tegra_pll_d_freq_table[] */
1395                 if (dc->mode.pclk > 70000000)
1396                         rate = 594000000;
1397                 else if (dc->mode.pclk > 25200000)
1398                         rate = 216000000;
1399                 else
1400                         rate = 504000000;
1401
1402                 if (rate != clk_get_rate(base_clk))
1403                         clk_set_rate(base_clk, rate);
1404
1405                 if (clk_get_parent(clk) != parent_clk)
1406                         clk_set_parent(clk, parent_clk);
1407         }
1408
1409         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1410                 unsigned long rate;
1411                 struct clk *parent_clk;
1412                 struct clk *base_clk;
1413
1414                 if (clk == dc->clk) {
1415                         parent_clk = clk_get_sys(NULL,
1416                                         dc->out->parent_clk ? : "pll_d_out0");
1417                         base_clk = clk_get_parent(parent_clk);
1418                         tegra_clk_cfg_ex(base_clk,
1419                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1420                 } else {
1421                         if (dc->pdata->default_out->dsi->dsi_instance) {
1422                                 parent_clk = clk_get_sys(NULL,
1423                                         dc->out->parent_clk ? : "pll_d2_out0");
1424                                 base_clk = clk_get_parent(parent_clk);
1425                                 tegra_clk_cfg_ex(base_clk,
1426                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1427                         } else {
1428                                 parent_clk = clk_get_sys(NULL,
1429                                         dc->out->parent_clk ? : "pll_d_out0");
1430                                 base_clk = clk_get_parent(parent_clk);
1431                                 tegra_clk_cfg_ex(base_clk,
1432                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1433                         }
1434                 }
1435
1436                 rate = dc->mode.pclk * 2;
1437                 if (rate != clk_get_rate(base_clk))
1438                         clk_set_rate(base_clk, rate);
1439
1440                 if (clk_get_parent(clk) != parent_clk)
1441                         clk_set_parent(clk, parent_clk);
1442         }
1443
1444         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1445         tegra_dvfs_set_rate(clk, pclk);
1446 }
1447
1448 /* return non-zero if constraint is violated */
1449 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1450 {
1451         long a, b;
1452
1453         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1454         a = 0;
1455
1456         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1457         b = mode->h_front_porch - 1;
1458
1459         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1460         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1461                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1462         /* check Constraint 1 and 6 */
1463         if (a > b)
1464                 return 1;
1465
1466         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1467         if (mode->h_sync_width < 1)
1468                 return 4;
1469
1470         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1471         if (mode->h_active < 16)
1472                 return 7;
1473
1474         if (href) {
1475                 if (b > a && a % 2)
1476                         *href = a + 1; /* use smallest even value */
1477                 else
1478                         *href = a; /* even or only possible value */
1479         }
1480
1481         return 0;
1482 }
1483
1484 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1485 {
1486         long a;
1487         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1488
1489         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1490         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1491                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1492
1493         /* Constraint 6 */
1494         if (mode->v_front_porch < a + 1)
1495                 a = mode->v_front_porch - 1;
1496
1497         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1498         if (mode->v_sync_width < 1)
1499                 return 4;
1500
1501         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1502         if (mode->v_active < 16)
1503                 return 7;
1504
1505         if (vref)
1506                 *vref = a;
1507         return 0;
1508 }
1509
1510 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1511 {
1512         int ret;
1513         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1514         if (ret)
1515                 return ret;
1516         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1517         if (ret)
1518                 return ret;
1519
1520         return 0;
1521 }
1522
1523 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1524 {
1525         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1526         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1527                 return false;
1528
1529         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1530         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1531                 return false;
1532
1533         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1534          * (vertical blank). */
1535         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1536                 return false;
1537
1538         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1539         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1540                 return false;
1541
1542         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1543         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1544                 return false;
1545
1546         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1547          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1548         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1549                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1550                 return false;
1551
1552         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1553         if (mode->h_active < 16 || mode->v_active < 16)
1554                 return false;
1555
1556         return true;
1557 }
1558
1559 #ifdef DEBUG
1560 /* return in 1000ths of a Hertz */
1561 static int calc_refresh(const struct tegra_dc_mode *m)
1562 {
1563         long h_total, v_total, refresh;
1564         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1565                 m->h_sync_width;
1566         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1567                 m->v_sync_width;
1568         refresh = m->pclk / h_total;
1569         refresh *= 1000;
1570         refresh /= v_total;
1571         return refresh;
1572 }
1573
1574 static void print_mode(struct tegra_dc *dc,
1575                         const struct tegra_dc_mode *mode, const char *note)
1576 {
1577         if (mode) {
1578                 int refresh = calc_refresh(dc, mode);
1579                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1580                         note ? note : "",
1581                         mode->h_active, mode->v_active,
1582                         refresh / 1000, refresh % 1000,
1583                         mode->pclk);
1584         }
1585 }
1586 #else /* !DEBUG */
1587 static inline void print_mode(struct tegra_dc *dc,
1588                         const struct tegra_dc_mode *mode, const char *note) { }
1589 #endif /* DEBUG */
1590
1591 static inline void enable_dc_irq(unsigned int irq)
1592 {
1593 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1594         enable_irq(irq);
1595 #else
1596         /* Always disable DC interrupts on FPGA. */
1597         disable_irq(irq);
1598 #endif
1599 }
1600
1601 static inline void disable_dc_irq(unsigned int irq)
1602 {
1603         disable_irq(irq);
1604 }
1605
1606 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1607 {
1608         unsigned long val;
1609         unsigned long rate;
1610         unsigned long div;
1611         unsigned long pclk;
1612
1613         print_mode(dc, mode, __func__);
1614
1615         /* use default EMC rate when switching modes */
1616         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1617         tegra_dc_program_bandwidth(dc);
1618
1619         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1620         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1621                         DC_DISP_REF_TO_SYNC);
1622         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1623                         DC_DISP_SYNC_WIDTH);
1624         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1625                         DC_DISP_BACK_PORCH);
1626         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1627                         DC_DISP_DISP_ACTIVE);
1628         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1629                         DC_DISP_FRONT_PORCH);
1630
1631         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1632                         DC_DISP_DATA_ENABLE_OPTIONS);
1633
1634         /* TODO: MIPI/CRT/HDMI clock cals */
1635
1636         val = DISP_DATA_FORMAT_DF1P1C;
1637
1638         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1639                 val |= DISP_DATA_ALIGNMENT_MSB;
1640         else
1641                 val |= DISP_DATA_ALIGNMENT_LSB;
1642
1643         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1644                 val |= DISP_DATA_ORDER_RED_BLUE;
1645         else
1646                 val |= DISP_DATA_ORDER_BLUE_RED;
1647
1648         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1649
1650         rate = tegra_dc_clk_get_rate(dc);
1651
1652         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1653         if (pclk < (mode->pclk / 100 * 99) ||
1654             pclk > (mode->pclk / 100 * 109)) {
1655                 dev_err(&dc->ndev->dev,
1656                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1657                         rate, mode->pclk,
1658                         pclk, (mode->pclk / 100 * 99),
1659                         (mode->pclk / 100 * 109));
1660                 return -EINVAL;
1661         }
1662
1663         div = (rate * 2 / pclk) - 2;
1664
1665         tegra_dc_writel(dc, 0x00010001,
1666                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1667         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1668                         DC_DISP_DISP_CLOCK_CONTROL);
1669
1670 #ifdef CONFIG_SWITCH
1671         switch_set_state(&dc->modeset_switch,
1672                          (mode->h_active << 16) | mode->v_active);
1673 #endif
1674
1675         return 0;
1676 }
1677
1678
1679 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1680 {
1681         memcpy(&dc->mode, mode, sizeof(dc->mode));
1682
1683         print_mode(dc, mode, __func__);
1684
1685         return 0;
1686 }
1687 EXPORT_SYMBOL(tegra_dc_set_mode);
1688
1689 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1690                 const struct fb_videomode *fbmode, bool stereo_mode)
1691 {
1692         struct tegra_dc_mode mode;
1693
1694         if (!fbmode->pixclock)
1695                 return -EINVAL;
1696
1697         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1698         mode.h_sync_width = fbmode->hsync_len;
1699         mode.v_sync_width = fbmode->vsync_len;
1700         mode.h_back_porch = fbmode->left_margin;
1701         mode.v_back_porch = fbmode->upper_margin;
1702         mode.h_active = fbmode->xres;
1703         mode.v_active = fbmode->yres;
1704         mode.h_front_porch = fbmode->right_margin;
1705         mode.v_front_porch = fbmode->lower_margin;
1706         mode.stereo_mode = stereo_mode;
1707         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1708                 /* HDMI controller requires h_ref=1, v_ref=1 */
1709                 mode.h_ref_to_sync = 1;
1710                 mode.v_ref_to_sync = 1;
1711         } else {
1712                 calc_ref_to_sync(&mode);
1713         }
1714         if (!check_ref_to_sync(&mode)) {
1715                 dev_err(&dc->ndev->dev,
1716                                 "Display timing doesn't meet restrictions.\n");
1717                 return -EINVAL;
1718         }
1719         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1720                 mode.h_active, mode.v_active, mode.pclk,
1721                 mode.h_ref_to_sync, mode.v_ref_to_sync
1722         );
1723
1724         if (mode.stereo_mode) {
1725                 mode.pclk *= 2;
1726                 /* total v_active = yres*2 + activespace */
1727                 mode.v_active = fbmode->yres*2 +
1728                                 fbmode->vsync_len +
1729                                 fbmode->upper_margin +
1730                                 fbmode->lower_margin;
1731         }
1732
1733         mode.flags = 0;
1734
1735         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1736                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1737
1738         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1739                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1740
1741         return tegra_dc_set_mode(dc, &mode);
1742 }
1743 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1744
1745 void
1746 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1747 {
1748         unsigned int ctrl;
1749         unsigned long out_sel;
1750         unsigned long cmd_state;
1751
1752         mutex_lock(&dc->lock);
1753         if (!dc->enabled) {
1754                 mutex_unlock(&dc->lock);
1755                 return;
1756         }
1757
1758         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1759                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1760                 cfg->clk_select);
1761
1762         /* The new value should be effected immediately */
1763         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1764         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1765
1766         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1767                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1768         else
1769                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1770
1771         switch (cfg->which_pwm) {
1772         case TEGRA_PWM_PM0:
1773                 /* Select the LM0 on PM0 */
1774                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1775                 out_sel &= ~(7 << 0);
1776                 out_sel |= (3 << 0);
1777                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1778                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1779                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1780                 break;
1781         case TEGRA_PWM_PM1:
1782                 /* Select the LM1 on PM1 */
1783                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1784                 out_sel &= ~(7 << 4);
1785                 out_sel |= (3 << 4);
1786                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1787                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1788                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1789                 break;
1790         default:
1791                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1792                 break;
1793         }
1794         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1795         mutex_unlock(&dc->lock);
1796 }
1797 EXPORT_SYMBOL(tegra_dc_config_pwm);
1798
1799 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1800                                 const struct tegra_dc_out_pin *pins,
1801                                 const unsigned int n_pins)
1802 {
1803         unsigned int i;
1804
1805         int name;
1806         int pol;
1807
1808         u32 pol1, pol3;
1809
1810         u32 set1, unset1;
1811         u32 set3, unset3;
1812
1813         set1 = set3 = unset1 = unset3 = 0;
1814
1815         for (i = 0; i < n_pins; i++) {
1816                 name = (pins + i)->name;
1817                 pol  = (pins + i)->pol;
1818
1819                 /* set polarity by name */
1820                 switch (name) {
1821                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1822                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1823                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1824                         else
1825                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1826                         break;
1827                 case TEGRA_DC_OUT_PIN_H_SYNC:
1828                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1829                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1830                         else
1831                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1832                         break;
1833                 case TEGRA_DC_OUT_PIN_V_SYNC:
1834                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1835                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1836                         else
1837                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1838                         break;
1839                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1840                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1841                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1842                         else
1843                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1844                         break;
1845                 default:
1846                         printk("Invalid argument in function %s\n",
1847                                __FUNCTION__);
1848                         break;
1849                 }
1850         }
1851
1852         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1853         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1854
1855         pol1 |= set1;
1856         pol1 &= ~unset1;
1857
1858         pol3 |= set3;
1859         pol3 &= ~unset3;
1860
1861         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1862         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1863 }
1864
1865 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1866 {
1867         dc->out = out;
1868
1869         if (out->n_modes > 0)
1870                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1871
1872         switch (out->type) {
1873         case TEGRA_DC_OUT_RGB:
1874                 dc->out_ops = &tegra_dc_rgb_ops;
1875                 break;
1876
1877         case TEGRA_DC_OUT_HDMI:
1878                 dc->out_ops = &tegra_dc_hdmi_ops;
1879                 break;
1880
1881         case TEGRA_DC_OUT_DSI:
1882                 dc->out_ops = &tegra_dc_dsi_ops;
1883                 break;
1884
1885         default:
1886                 dc->out_ops = NULL;
1887                 break;
1888         }
1889
1890         if (dc->out_ops && dc->out_ops->init)
1891                 dc->out_ops->init(dc);
1892
1893 }
1894
1895 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1896 {
1897         if (dc->out)
1898                 return dc->out->height;
1899         else
1900                 return 0;
1901 }
1902 EXPORT_SYMBOL(tegra_dc_get_out_height);
1903
1904 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1905 {
1906         if (dc->out)
1907                 return dc->out->width;
1908         else
1909                 return 0;
1910 }
1911 EXPORT_SYMBOL(tegra_dc_get_out_width);
1912
1913 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1914 {
1915         if (dc->out && dc->out->max_pixclock)
1916                 return dc->out->max_pixclock;
1917         else
1918                 return 0;
1919 }
1920 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1921
1922 void tegra_dc_enable_crc(struct tegra_dc *dc)
1923 {
1924         u32 val;
1925         tegra_dc_io_start(dc);
1926
1927         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1928                 CRC_ENABLE_ENABLE;
1929         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1930         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1931         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1932 }
1933
1934 void tegra_dc_disable_crc(struct tegra_dc *dc)
1935 {
1936         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1937         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1938         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1939
1940         tegra_dc_io_end(dc);
1941 }
1942
1943 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1944 {
1945         int crc = 0;
1946
1947         if(!dc) {
1948                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1949                 goto crc_error;
1950         }
1951
1952         /* TODO: Replace mdelay with code to sync VBlANK, since
1953          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1954         mdelay(TEGRA_CRC_LATCHED_DELAY);
1955
1956         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1957 crc_error:
1958         return crc;
1959 }
1960
1961 static void tegra_dc_vblank(struct work_struct *work)
1962 {
1963         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1964         bool nvsd_updated = false;
1965
1966         mutex_lock(&dc->lock);
1967
1968         /* Update the SD brightness */
1969         if (dc->enabled && dc->out->sd_settings)
1970                 nvsd_updated = nvsd_update_brightness(dc);
1971
1972         mutex_unlock(&dc->lock);
1973
1974         /* Do the actual brightness update outside of the mutex */
1975         if (nvsd_updated && dc->out->sd_settings &&
1976             dc->out->sd_settings->bl_device) {
1977
1978                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1979                 struct backlight_device *bl = platform_get_drvdata(pdev);
1980                 if (bl)
1981                         backlight_update_status(bl);
1982         }
1983 }
1984
1985 static void tegra_dc_one_shot_worker(struct work_struct *work)
1986 {
1987         struct tegra_dc *dc = container_of(work, struct tegra_dc, one_shot_work);
1988         /* memory client has gone idle */
1989         tegra_dc_clear_bandwidth(dc);
1990 }
1991
1992 /* return an arbitrarily large number if count overflow occurs.
1993  * make it a nice base-10 number to show up in stats output */
1994 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1995 {
1996         unsigned count = tegra_dc_readl(dc, reg);
1997         tegra_dc_writel(dc, 0, reg);
1998         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1999 }
2000
2001 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2002 {
2003         u32 val;
2004         int i;
2005
2006         dc->stats.underflows++;
2007         if (dc->underflow_mask & WIN_A_UF_INT)
2008                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2009                         DC_WINBUF_AD_UFLOW_STATUS);
2010         if (dc->underflow_mask & WIN_B_UF_INT)
2011                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2012                         DC_WINBUF_BD_UFLOW_STATUS);
2013         if (dc->underflow_mask & WIN_C_UF_INT)
2014                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2015                         DC_WINBUF_CD_UFLOW_STATUS);
2016
2017         /* Check for any underflow reset conditions */
2018         for (i = 0; i < DC_N_WINDOWS; i++) {
2019                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2020                         dc->windows[i].underflows++;
2021
2022 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2023                         if (dc->windows[i].underflows > 4)
2024                                 schedule_work(&dc->reset_work);
2025 #endif
2026                 } else {
2027                         dc->windows[i].underflows = 0;
2028                 }
2029         }
2030
2031         /* Clear the underflow mask now that we've checked it. */
2032         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2033         dc->underflow_mask = 0;
2034         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2035         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2036 }
2037
2038 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2039 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2040 {
2041         u32 val, i;
2042         u32 completed = 0;
2043         u32 dirty = 0;
2044
2045         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2046         for (i = 0; i < DC_N_WINDOWS; i++) {
2047 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2048                 /* FIXME: this is not needed when the simulator
2049                    clears WIN_x_UPDATE bits as in HW */
2050                 dc->windows[i].dirty = 0;
2051                 completed = 1;
2052 #else
2053                 if (!(val & (WIN_A_UPDATE << i))) {
2054                         dc->windows[i].dirty = 0;
2055                         completed = 1;
2056                 } else {
2057                         dirty = 1;
2058                 }
2059 #endif
2060         }
2061
2062         if (!dirty) {
2063                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2064                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2065                         val &= ~V_BLANK_INT;
2066                 else
2067                         val &= ~FRAME_END_INT;
2068                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2069         }
2070
2071         if (completed) {
2072                 if (!dirty) {
2073                         /* With the last completed window, go ahead
2074                            and enable the vblank interrupt for nvsd. */
2075                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2076                         val |= V_BLANK_INT;
2077                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2078                 }
2079
2080                 wake_up(&dc->wq);
2081         }
2082 }
2083
2084 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2085 {
2086         if (status & V_BLANK_INT) {
2087                 /* Sync up windows. */
2088                 tegra_dc_trigger_windows(dc);
2089
2090                 /* Schedule any additional bottom-half vblank actvities. */
2091                 schedule_work(&dc->vblank_work);
2092         }
2093
2094         if (status & FRAME_END_INT) {
2095                 schedule_work(&dc->one_shot_work);
2096
2097                 /* Mark the frame_end as complete. */
2098                 if (!completion_done(&dc->frame_end_complete))
2099                         complete(&dc->frame_end_complete);
2100         }
2101 }
2102
2103 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2104 {
2105         if (status & V_BLANK_INT) {
2106                 /* Schedule any additional bottom-half vblank actvities. */
2107                 schedule_work(&dc->vblank_work);
2108         }
2109
2110         if (status & FRAME_END_INT) {
2111                 /* Mark the frame_end as complete. */
2112                 if (!completion_done(&dc->frame_end_complete))
2113                         complete(&dc->frame_end_complete);
2114
2115                 tegra_dc_trigger_windows(dc);
2116         }
2117 }
2118 #endif
2119
2120 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2121 {
2122 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2123         struct tegra_dc *dc = ptr;
2124         unsigned long status;
2125         unsigned long underflow_mask;
2126         u32 val;
2127
2128         if (!nvhost_module_powered(dc->ndev->host->dev)) {
2129                 WARN(1, "IRQ when DC not powered!\n");
2130                 tegra_dc_io_start(dc);
2131                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2132                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2133                 tegra_dc_io_end(dc);
2134                 return IRQ_HANDLED;
2135         }
2136
2137         /* clear all status flags except underflow, save those for the worker */
2138         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2139         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2140         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2141         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2142
2143         /*
2144          * Overlays can get thier internal state corrupted during and underflow
2145          * condition.  The only way to fix this state is to reset the DC.
2146          * if we get 4 consecutive frames with underflows, assume we're
2147          * hosed and reset.
2148          */
2149         underflow_mask = status & ALL_UF_INT;
2150
2151         /* Check underflow */
2152         if (underflow_mask) {
2153                 dc->underflow_mask |= underflow_mask;
2154                 schedule_delayed_work(&dc->underflow_work,
2155                         msecs_to_jiffies(1));
2156         }
2157
2158         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2159                 tegra_dc_one_shot_irq(dc, status);
2160         else
2161                 tegra_dc_continuous_irq(dc, status);
2162
2163         return IRQ_HANDLED;
2164 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2165         return IRQ_NONE;
2166 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2167 }
2168
2169 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2170 {
2171         u32 color_control;
2172
2173         switch (dc->out->depth) {
2174         case 3:
2175                 color_control = BASE_COLOR_SIZE111;
2176                 break;
2177
2178         case 6:
2179                 color_control = BASE_COLOR_SIZE222;
2180                 break;
2181
2182         case 8:
2183                 color_control = BASE_COLOR_SIZE332;
2184                 break;
2185
2186         case 9:
2187                 color_control = BASE_COLOR_SIZE333;
2188                 break;
2189
2190         case 12:
2191                 color_control = BASE_COLOR_SIZE444;
2192                 break;
2193
2194         case 15:
2195                 color_control = BASE_COLOR_SIZE555;
2196                 break;
2197
2198         case 16:
2199                 color_control = BASE_COLOR_SIZE565;
2200                 break;
2201
2202         case 18:
2203                 color_control = BASE_COLOR_SIZE666;
2204                 break;
2205
2206         default:
2207                 color_control = BASE_COLOR_SIZE888;
2208                 break;
2209         }
2210
2211         switch (dc->out->dither) {
2212         case TEGRA_DC_DISABLE_DITHER:
2213                 color_control |= DITHER_CONTROL_DISABLE;
2214                 break;
2215         case TEGRA_DC_ORDERED_DITHER:
2216                 color_control |= DITHER_CONTROL_ORDERED;
2217                 break;
2218         case TEGRA_DC_ERRDIFF_DITHER:
2219                 /* The line buffer for error-diffusion dither is limited
2220                  * to 1280 pixels per line. This limits the maximum
2221                  * horizontal active area size to 1280 pixels when error
2222                  * diffusion is enabled.
2223                  */
2224                 BUG_ON(dc->mode.h_active > 1280);
2225                 color_control |= DITHER_CONTROL_ERRDIFF;
2226                 break;
2227         }
2228
2229         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2230 }
2231
2232 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2233 {
2234         u32 syncpt_id;
2235
2236         switch (dc->ndev->id) {
2237         case 0:
2238                 switch (idx) {
2239                 case 0:
2240                         syncpt_id = NVSYNCPT_DISP0_A;
2241                         break;
2242                 case 1:
2243                         syncpt_id = NVSYNCPT_DISP0_B;
2244                         break;
2245                 case 2:
2246                         syncpt_id = NVSYNCPT_DISP0_C;
2247                         break;
2248                 default:
2249                         BUG();
2250                         break;
2251                 }
2252                 break;
2253         case 1:
2254                 switch (idx) {
2255                 case 0:
2256                         syncpt_id = NVSYNCPT_DISP1_A;
2257                         break;
2258                 case 1:
2259                         syncpt_id = NVSYNCPT_DISP1_B;
2260                         break;
2261                 case 2:
2262                         syncpt_id = NVSYNCPT_DISP1_C;
2263                         break;
2264                 default:
2265                         BUG();
2266                         break;
2267                 }
2268                 break;
2269         default:
2270                 BUG();
2271                 break;
2272         }
2273
2274         return syncpt_id;
2275 }
2276
2277 static void tegra_dc_init(struct tegra_dc *dc)
2278 {
2279         int i;
2280
2281         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2282         if (dc->ndev->id == 0) {
2283                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2284                                       TEGRA_MC_PRIO_MED);
2285                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2286                                       TEGRA_MC_PRIO_MED);
2287                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2288                                       TEGRA_MC_PRIO_MED);
2289                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2290                                       TEGRA_MC_PRIO_MED);
2291                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2292                                       TEGRA_MC_PRIO_HIGH);
2293         } else if (dc->ndev->id == 1) {
2294                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2295                                       TEGRA_MC_PRIO_MED);
2296                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2297                                       TEGRA_MC_PRIO_MED);
2298                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2299                                       TEGRA_MC_PRIO_MED);
2300                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2301                                       TEGRA_MC_PRIO_MED);
2302                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2303                                       TEGRA_MC_PRIO_HIGH);
2304         }
2305         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2306                         DC_CMD_CONT_SYNCPT_VSYNC);
2307         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2308         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2309         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2310         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2311
2312         /* enable interrupts for vblank, frame_end and underflows */
2313         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2314                 DC_CMD_INT_ENABLE);
2315         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2316
2317         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2318
2319         tegra_dc_set_color_control(dc);
2320         for (i = 0; i < DC_N_WINDOWS; i++) {
2321                 struct tegra_dc_win *win = &dc->windows[i];
2322                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2323                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2324                 tegra_dc_set_csc(dc, &win->csc);
2325                 tegra_dc_set_lut(dc, win);
2326                 tegra_dc_set_scaling_filter(dc);
2327         }
2328
2329
2330         for (i = 0; i < dc->n_windows; i++) {
2331                 u32 syncpt = get_syncpt(dc, i);
2332
2333                 dc->syncpt[i].id = syncpt;
2334
2335                 dc->syncpt[i].min = dc->syncpt[i].max =
2336                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2337         }
2338
2339         print_mode(dc, &dc->mode, __func__);
2340
2341         if (dc->mode.pclk)
2342                 tegra_dc_program_mode(dc, &dc->mode);
2343
2344         /* Initialize SD AFTER the modeset.
2345            nvsd_init handles the sd_settings = NULL case. */
2346         nvsd_init(dc, dc->out->sd_settings);
2347 }
2348
2349 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2350 {
2351         if (dc->out->enable)
2352                 dc->out->enable();
2353
2354         tegra_dc_setup_clk(dc, dc->clk);
2355         clk_enable(dc->clk);
2356
2357         /* do not accept interrupts during initialization */
2358         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2359         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2360
2361         enable_dc_irq(dc->irq);
2362
2363         tegra_dc_init(dc);
2364
2365         if (dc->out_ops && dc->out_ops->enable)
2366                 dc->out_ops->enable(dc);
2367
2368         if (dc->out->postpoweron)
2369                 dc->out->postpoweron();
2370
2371         /* force a full blending update */
2372         dc->blend.z[0] = -1;
2373
2374         tegra_dc_ext_enable(dc->ext);
2375
2376         return true;
2377 }
2378
2379 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2380 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2381 {
2382         if (dc->out->enable)
2383                 dc->out->enable();
2384
2385         tegra_dc_setup_clk(dc, dc->clk);
2386         clk_enable(dc->clk);
2387
2388         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2389                 mutex_lock(&tegra_dcs[1]->lock);
2390                 disable_irq(tegra_dcs[1]->irq);
2391         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2392                 mutex_lock(&tegra_dcs[0]->lock);
2393                 disable_irq(tegra_dcs[0]->irq);
2394         }
2395
2396         msleep(5);
2397         tegra_periph_reset_assert(dc->clk);
2398         msleep(2);
2399 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2400         tegra_periph_reset_deassert(dc->clk);
2401         msleep(1);
2402 #endif
2403
2404         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2405                 enable_dc_irq(tegra_dcs[1]->irq);
2406                 mutex_unlock(&tegra_dcs[1]->lock);
2407         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2408                 enable_dc_irq(tegra_dcs[0]->irq);
2409                 mutex_unlock(&tegra_dcs[0]->lock);
2410         }
2411
2412         enable_dc_irq(dc->irq);
2413
2414         tegra_dc_init(dc);
2415
2416         if (dc->out_ops && dc->out_ops->enable)
2417                 dc->out_ops->enable(dc);
2418
2419         if (dc->out->postpoweron)
2420                 dc->out->postpoweron();
2421
2422         /* force a full blending update */
2423         dc->blend.z[0] = -1;
2424
2425         return true;
2426 }
2427 #endif
2428
2429 static bool _tegra_dc_enable(struct tegra_dc *dc)
2430 {
2431         if (dc->mode.pclk == 0)
2432                 return false;
2433
2434         if (!dc->out)
2435                 return false;
2436
2437         tegra_dc_io_start(dc);
2438
2439         return _tegra_dc_controller_enable(dc);
2440 }
2441
2442 void tegra_dc_enable(struct tegra_dc *dc)
2443 {
2444         mutex_lock(&dc->lock);
2445
2446         if (!dc->enabled)
2447                 dc->enabled = _tegra_dc_enable(dc);
2448
2449         mutex_unlock(&dc->lock);
2450 }
2451
2452 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2453 {
2454         unsigned i;
2455
2456         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2457         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2458         disable_irq(dc->irq);
2459
2460         if (dc->out_ops && dc->out_ops->disable)
2461                 dc->out_ops->disable(dc);
2462
2463         tegra_dc_clear_bandwidth(dc);
2464         clk_disable(dc->clk);
2465         tegra_dvfs_set_rate(dc->clk, 0);
2466
2467         if (dc->out && dc->out->disable)
2468                 dc->out->disable();
2469
2470         for (i = 0; i < dc->n_windows; i++) {
2471                 struct tegra_dc_win *w = &dc->windows[i];
2472
2473                 /* reset window bandwidth */
2474                 w->bandwidth = 0;
2475                 w->new_bandwidth = 0;
2476
2477                 /* disable windows */
2478                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2479
2480                 /* flush any pending syncpt waits */
2481                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2482                         dc->syncpt[i].min++;
2483                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2484                                 dc->syncpt[i].id);
2485                 }
2486         }
2487 }
2488
2489 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2490 {
2491 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2492         u32 val;
2493         if (dc->enabled)  {
2494                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2495                 if (enable)
2496                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2497                 else
2498                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2499                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2500         }
2501 #endif
2502 }
2503
2504 bool tegra_dc_stats_get(struct tegra_dc *dc)
2505 {
2506 #if 0 /* right now it is always enabled */
2507         u32 val;
2508         bool res;
2509
2510         if (dc->enabled)  {
2511                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2512                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2513         } else {
2514                 res = false;
2515         }
2516
2517         return res;
2518 #endif
2519         return true;
2520 }
2521
2522 /* make the screen blank by disabling all windows */
2523 void tegra_dc_blank(struct tegra_dc *dc)
2524 {
2525         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2526         unsigned i;
2527
2528         for (i = 0; i < DC_N_WINDOWS; i++) {
2529                 dcwins[i] = tegra_dc_get_window(dc, i);
2530                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2531         }
2532
2533         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2534         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2535 }
2536
2537 static void _tegra_dc_disable(struct tegra_dc *dc)
2538 {
2539         _tegra_dc_controller_disable(dc);
2540         tegra_dc_io_end(dc);
2541 }
2542
2543 void tegra_dc_disable(struct tegra_dc *dc)
2544 {
2545         if (dc->overlay)
2546                 tegra_overlay_disable(dc->overlay);
2547
2548         tegra_dc_ext_disable(dc->ext);
2549
2550         /* it's important that new underflow work isn't scheduled before the
2551          * lock is acquired. */
2552         cancel_delayed_work_sync(&dc->underflow_work);
2553
2554         mutex_lock(&dc->lock);
2555
2556         if (dc->enabled) {
2557                 dc->enabled = false;
2558
2559                 if (!dc->suspended)
2560                         _tegra_dc_disable(dc);
2561         }
2562
2563 #ifdef CONFIG_SWITCH
2564         switch_set_state(&dc->modeset_switch, 0);
2565 #endif
2566
2567         mutex_unlock(&dc->lock);
2568 }
2569
2570 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2571 static void tegra_dc_reset_worker(struct work_struct *work)
2572 {
2573         struct tegra_dc *dc =
2574                 container_of(work, struct tegra_dc, reset_work);
2575
2576         unsigned long val = 0;
2577
2578         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2579
2580         tegra_dc_ext_disable(dc->ext);
2581
2582         mutex_lock(&shared_lock);
2583         mutex_lock(&dc->lock);
2584
2585         if (dc->enabled == false)
2586                 goto unlock;
2587
2588         dc->enabled = false;
2589
2590         /*
2591          * off host read bus
2592          */
2593         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2594         val &= ~(0x00000100);
2595         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2596
2597         /*
2598          * set DC to STOP mode
2599          */
2600         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2601
2602         msleep(10);
2603
2604         _tegra_dc_controller_disable(dc);
2605
2606         /* _tegra_dc_controller_reset_enable deasserts reset */
2607         _tegra_dc_controller_reset_enable(dc);
2608
2609         dc->enabled = true;
2610 unlock:
2611         mutex_unlock(&dc->lock);
2612         mutex_unlock(&shared_lock);
2613 }
2614 #endif
2615
2616 static void tegra_dc_underflow_worker(struct work_struct *work)
2617 {
2618         struct tegra_dc *dc = container_of(
2619                 to_delayed_work(work), struct tegra_dc, underflow_work);
2620
2621         mutex_lock(&dc->lock);
2622         if (dc->enabled) {
2623                 tegra_dc_underflow_handler(dc);
2624         }
2625         mutex_unlock(&dc->lock);
2626 }
2627
2628 #ifdef CONFIG_SWITCH
2629 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2630 {
2631         struct tegra_dc *dc =
2632                 container_of(sdev, struct tegra_dc, modeset_switch);
2633
2634         if (!sdev->state)
2635                 return sprintf(buf, "offline\n");
2636
2637         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2638 }
2639 #endif
2640
2641 static int tegra_dc_probe(struct nvhost_device *ndev)
2642 {
2643         struct tegra_dc *dc;
2644         struct clk *clk;
2645         struct clk *emc_clk;
2646         struct resource *res;
2647         struct resource *base_res;
2648         struct resource *fb_mem = NULL;
2649         int ret = 0;
2650         void __iomem *base;
2651         int irq;
2652         int i;
2653
2654         if (!ndev->dev.platform_data) {
2655                 dev_err(&ndev->dev, "no platform data\n");
2656                 return -ENOENT;
2657         }
2658
2659         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2660         if (!dc) {
2661                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2662                 return -ENOMEM;
2663         }
2664
2665         irq = nvhost_get_irq_byname(ndev, "irq");
2666         if (irq <= 0) {
2667                 dev_err(&ndev->dev, "no irq\n");
2668                 ret = -ENOENT;
2669                 goto err_free;
2670         }
2671
2672         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2673         if (!res) {
2674                 dev_err(&ndev->dev, "no mem resource\n");
2675                 ret = -ENOENT;
2676                 goto err_free;
2677         }
2678
2679         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2680         if (!base_res) {
2681                 dev_err(&ndev->dev, "request_mem_region failed\n");
2682                 ret = -EBUSY;
2683                 goto err_free;
2684         }
2685
2686         base = ioremap(res->start, resource_size(res));
2687         if (!base) {
2688                 dev_err(&ndev->dev, "registers can't be mapped\n");
2689                 ret = -EBUSY;
2690                 goto err_release_resource_reg;
2691         }
2692
2693         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2694
2695         clk = clk_get(&ndev->dev, NULL);
2696         if (IS_ERR_OR_NULL(clk)) {
2697                 dev_err(&ndev->dev, "can't get clock\n");
2698                 ret = -ENOENT;
2699                 goto err_iounmap_reg;
2700         }
2701
2702         emc_clk = clk_get(&ndev->dev, "emc");
2703         if (IS_ERR_OR_NULL(emc_clk)) {
2704                 dev_err(&ndev->dev, "can't get emc clock\n");
2705                 ret = -ENOENT;
2706                 goto err_put_clk;
2707         }
2708
2709         dc->clk = clk;
2710         dc->emc_clk = emc_clk;
2711
2712         dc->base_res = base_res;
2713         dc->base = base;
2714         dc->irq = irq;
2715         dc->ndev = ndev;
2716         dc->pdata = ndev->dev.platform_data;
2717
2718         /*
2719          * The emc is a shared clock, it will be set based on
2720          * the requirements for each user on the bus.
2721          */
2722         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2723         clk_set_rate(emc_clk, dc->emc_clk_rate);
2724
2725         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2726                 dc->enabled = true;
2727
2728         mutex_init(&dc->lock);
2729         init_completion(&dc->frame_end_complete);
2730         init_waitqueue_head(&dc->wq);
2731 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2732         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2733 #endif
2734         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2735         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2736         INIT_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2737
2738         tegra_dc_init_lut_defaults(&dc->fb_lut);
2739
2740         dc->n_windows = DC_N_WINDOWS;
2741         for (i = 0; i < dc->n_windows; i++) {
2742                 struct tegra_dc_win *win = &dc->windows[i];
2743                 win->idx = i;
2744                 win->dc = dc;
2745                 tegra_dc_init_csc_defaults(&win->csc);
2746                 tegra_dc_init_lut_defaults(&win->lut);
2747         }
2748
2749         ret = tegra_dc_set(dc, ndev->id);
2750         if (ret < 0) {
2751                 dev_err(&ndev->dev, "can't add dc\n");
2752                 goto err_free_irq;
2753         }
2754
2755         nvhost_set_drvdata(ndev, dc);
2756
2757 #ifdef CONFIG_SWITCH
2758         dc->modeset_switch.name = dev_name(&ndev->dev);
2759         dc->modeset_switch.state = 0;
2760         dc->modeset_switch.print_state = switch_modeset_print_mode;
2761         switch_dev_register(&dc->modeset_switch);
2762 #endif
2763
2764         if (dc->pdata->default_out)
2765                 tegra_dc_set_out(dc, dc->pdata->default_out);
2766         else
2767                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2768
2769         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2770                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2771
2772         dc->ext = tegra_dc_ext_register(ndev, dc);
2773         if (IS_ERR_OR_NULL(dc->ext)) {
2774                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2775                 dc->ext = NULL;
2776         }
2777
2778         /* interrupt handler must be registered before tegra_fb_register() */
2779         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2780                         dev_name(&ndev->dev), dc)) {
2781                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2782                 ret = -EBUSY;
2783                 goto err_put_emc_clk;
2784         }
2785
2786         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2787         disable_dc_irq(dc->irq);
2788
2789         mutex_lock(&dc->lock);
2790         if (dc->enabled)
2791                 _tegra_dc_enable(dc);
2792         mutex_unlock(&dc->lock);
2793
2794         tegra_dc_create_debugfs(dc);
2795
2796         dev_info(&ndev->dev, "probed\n");
2797
2798         if (dc->pdata->fb) {
2799                 if (dc->pdata->fb->bits_per_pixel == -1) {
2800                         unsigned long fmt;
2801                         tegra_dc_writel(dc,
2802                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2803                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2804
2805                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2806                         dc->pdata->fb->bits_per_pixel =
2807                                 tegra_dc_fmt_bpp(fmt);
2808                 }
2809
2810                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2811                 if (IS_ERR_OR_NULL(dc->fb))
2812                         dc->fb = NULL;
2813         }
2814
2815         if (dc->fb) {
2816                 dc->overlay = tegra_overlay_register(ndev, dc);
2817                 if (IS_ERR_OR_NULL(dc->overlay))
2818                         dc->overlay = NULL;
2819         }
2820
2821         if (dc->out && dc->out->hotplug_init)
2822                 dc->out->hotplug_init();
2823
2824         if (dc->out_ops && dc->out_ops->detect)
2825                 dc->out_ops->detect(dc);
2826         else
2827                 dc->connected = true;
2828
2829         tegra_dc_create_sysfs(&dc->ndev->dev);
2830
2831         return 0;
2832
2833 err_free_irq:
2834         free_irq(irq, dc);
2835 err_put_emc_clk:
2836         clk_put(emc_clk);
2837 err_put_clk:
2838         clk_put(clk);
2839 err_iounmap_reg:
2840         iounmap(base);
2841         if (fb_mem)
2842                 release_resource(fb_mem);
2843 err_release_resource_reg:
2844         release_resource(base_res);
2845 err_free:
2846         kfree(dc);
2847
2848         return ret;
2849 }
2850
2851 static int tegra_dc_remove(struct nvhost_device *ndev)
2852 {
2853         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2854
2855         tegra_dc_remove_sysfs(&dc->ndev->dev);
2856         tegra_dc_remove_debugfs(dc);
2857
2858         if (dc->overlay) {
2859                 tegra_overlay_unregister(dc->overlay);
2860         }
2861
2862         if (dc->fb) {
2863                 tegra_fb_unregister(dc->fb);
2864                 if (dc->fb_mem)
2865                         release_resource(dc->fb_mem);
2866         }
2867
2868         tegra_dc_ext_disable(dc->ext);
2869
2870         if (dc->ext)
2871                 tegra_dc_ext_unregister(dc->ext);
2872
2873         if (dc->enabled)
2874                 _tegra_dc_disable(dc);
2875
2876 #ifdef CONFIG_SWITCH
2877         switch_dev_unregister(&dc->modeset_switch);
2878 #endif
2879         free_irq(dc->irq, dc);
2880         clk_put(dc->emc_clk);
2881         clk_put(dc->clk);
2882         iounmap(dc->base);
2883         if (dc->fb_mem)
2884                 release_resource(dc->base_res);
2885         kfree(dc);
2886         tegra_dc_set(NULL, ndev->id);
2887         return 0;
2888 }
2889
2890 #ifdef CONFIG_PM
2891 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2892 {
2893         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2894
2895         dev_info(&ndev->dev, "suspend\n");
2896
2897         if (dc->overlay)
2898                 tegra_overlay_disable(dc->overlay);
2899
2900         tegra_dc_ext_disable(dc->ext);
2901
2902         mutex_lock(&dc->lock);
2903
2904         if (dc->out_ops && dc->out_ops->suspend)
2905                 dc->out_ops->suspend(dc);
2906
2907         if (dc->enabled) {
2908                 _tegra_dc_disable(dc);
2909
2910                 dc->suspended = true;
2911         }
2912
2913         if (dc->out && dc->out->postsuspend) {
2914                 dc->out->postsuspend();
2915                 msleep(100); /* avoid resume event due to voltage falling */
2916         }
2917
2918         mutex_unlock(&dc->lock);
2919
2920         return 0;
2921 }
2922
2923 static int tegra_dc_resume(struct nvhost_device *ndev)
2924 {
2925         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2926
2927         dev_info(&ndev->dev, "resume\n");
2928
2929         mutex_lock(&dc->lock);
2930         dc->suspended = false;
2931
2932         if (dc->enabled)
2933                 _tegra_dc_enable(dc);
2934
2935         if (dc->out && dc->out->hotplug_init)
2936                 dc->out->hotplug_init();
2937
2938         if (dc->out_ops && dc->out_ops->resume)
2939                 dc->out_ops->resume(dc);
2940         mutex_unlock(&dc->lock);
2941
2942         return 0;
2943 }
2944
2945 #endif /* CONFIG_PM */
2946
2947 extern int suspend_set(const char *val, struct kernel_param *kp)
2948 {
2949         if (!strcmp(val, "dump"))
2950                 dump_regs(tegra_dcs[0]);
2951 #ifdef CONFIG_PM
2952         else if (!strcmp(val, "suspend"))
2953                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2954         else if (!strcmp(val, "resume"))
2955                 tegra_dc_resume(tegra_dcs[0]->ndev);
2956 #endif
2957
2958         return 0;
2959 }
2960
2961 extern int suspend_get(char *buffer, struct kernel_param *kp)
2962 {
2963         return 0;
2964 }
2965
2966 int suspend;
2967
2968 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2969
2970 struct nvhost_driver tegra_dc_driver = {
2971         .driver = {
2972                 .name = "tegradc",
2973                 .owner = THIS_MODULE,
2974         },
2975         .probe = tegra_dc_probe,
2976         .remove = tegra_dc_remove,
2977 #ifdef CONFIG_PM
2978         .suspend = tegra_dc_suspend,
2979         .resume = tegra_dc_resume,
2980 #endif
2981 };
2982
2983 static int __init tegra_dc_module_init(void)
2984 {
2985         int ret = tegra_dc_ext_module_init();
2986         if (ret)
2987                 return ret;
2988         return nvhost_driver_register(&tegra_dc_driver);
2989 }
2990
2991 static void __exit tegra_dc_module_exit(void)
2992 {
2993         nvhost_driver_unregister(&tegra_dc_driver);
2994         tegra_dc_ext_module_exit();
2995 }
2996
2997 module_exit(tegra_dc_module_exit);
2998 module_init(tegra_dc_module_init);