d01df2f520b83d38d49439ee2e40a28a2ae5d282
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
62         .refresh = 60,
63         .xres = 640,
64         .yres = 480,
65         .pixclock = KHZ2PICOS(25200),
66         .hsync_len = 96,        /* h_sync_width */
67         .vsync_len = 2,         /* v_sync_width */
68         .left_margin = 48,      /* h_back_porch */
69         .upper_margin = 33,     /* v_back_porch */
70         .right_margin = 16,     /* h_front_porch */
71         .lower_margin = 10,     /* v_front_porch */
72         .vmode = 0,
73         .sync = 0,
74 };
75
76 static struct tegra_dc_mode override_disp_mode[3];
77
78 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
79
80 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
81
82 DEFINE_MUTEX(tegra_dc_lock);
83 DEFINE_MUTEX(shared_lock);
84
85 void tegra_dc_clk_enable(struct tegra_dc *dc)
86 {
87         if (!tegra_is_clk_enabled(dc->clk)) {
88                 clk_enable(dc->clk);
89                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
90         }
91 }
92
93 void tegra_dc_clk_disable(struct tegra_dc *dc)
94 {
95         if (tegra_is_clk_enabled(dc->clk)) {
96                 clk_disable(dc->clk);
97                 tegra_dvfs_set_rate(dc->clk, 0);
98         }
99 }
100
101 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
102 {
103         if (dc->out_ops->hold)
104                 dc->out_ops->hold(dc);
105 }
106
107 void tegra_dc_release_dc_out(struct tegra_dc *dc)
108 {
109         if (dc->out_ops->release)
110                 dc->out_ops->release(dc);
111 }
112
113 #define DUMP_REG(a) do {                        \
114         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
115                  #a, a, tegra_dc_readl(dc, a));               \
116         print(data, buff);                                    \
117         } while (0)
118
119 #define print_underflow_info(dc) do {                 \
120         trace_printk("%s:Underflow stats: underflows : %llu, "      \
121                         "undeflows_a : %llu, "                          \
122                         "underflows_b : %llu, "                         \
123                         "underflows_c : %llu\n",                        \
124                         dc->ndev->name,                                 \
125                         dc->stats.underflows,                           \
126                         dc->stats.underflows_a, dc->stats.underflows_b, \
127                         dc->stats.underflows_c);                        \
128         } while (0)
129
130 static void _dump_regs(struct tegra_dc *dc, void *data,
131                        void (* print)(void *data, const char *str))
132 {
133         int i;
134         char buff[256];
135
136         mutex_lock(&dc->lock);
137         tegra_dc_hold_dc_out(dc);
138         tegra_dc_io_start(dc);
139
140         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
141         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
142         DUMP_REG(DC_CMD_SIGNAL_RAISE);
143         DUMP_REG(DC_CMD_INT_STATUS);
144         DUMP_REG(DC_CMD_INT_MASK);
145         DUMP_REG(DC_CMD_INT_ENABLE);
146         DUMP_REG(DC_CMD_INT_TYPE);
147         DUMP_REG(DC_CMD_INT_POLARITY);
148         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
149         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
150         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
151         DUMP_REG(DC_CMD_STATE_ACCESS);
152         DUMP_REG(DC_CMD_STATE_CONTROL);
153         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
154         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
155
156         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
157         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
158         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
159         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
160         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
161         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
162         DUMP_REG(DC_DISP_REF_TO_SYNC);
163         DUMP_REG(DC_DISP_SYNC_WIDTH);
164         DUMP_REG(DC_DISP_BACK_PORCH);
165         DUMP_REG(DC_DISP_DISP_ACTIVE);
166         DUMP_REG(DC_DISP_FRONT_PORCH);
167         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
168         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
169         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
170         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
171         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
172         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
173         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
174         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
175         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
176         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
177         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
178         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
179         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
180         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
181         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
182         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
183         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
184         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
185         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
186         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
187         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
188         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
189         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
190         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
191         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
192         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
193         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
194         DUMP_REG(DC_DISP_M0_CONTROL);
195         DUMP_REG(DC_DISP_M1_CONTROL);
196         DUMP_REG(DC_DISP_DI_CONTROL);
197         DUMP_REG(DC_DISP_PP_CONTROL);
198         DUMP_REG(DC_DISP_PP_SELECT_A);
199         DUMP_REG(DC_DISP_PP_SELECT_B);
200         DUMP_REG(DC_DISP_PP_SELECT_C);
201         DUMP_REG(DC_DISP_PP_SELECT_D);
202         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
203         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
204         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
205         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
206         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
207         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
208         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
209         DUMP_REG(DC_DISP_BORDER_COLOR);
210         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
211         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
212         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
213         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
214         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
215         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
216         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
217         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
218         DUMP_REG(DC_DISP_CURSOR_POSITION);
219         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
220         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
221         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
222         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
223         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
224         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
225         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
226         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
227         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
228         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
229         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
230         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
231         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
232
233
234         for (i = 0; i < 3; i++) {
235                 print(data, "\n");
236                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
237                 print(data, buff);
238
239                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
240                                 DC_CMD_DISPLAY_WINDOW_HEADER);
241                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
242                 DUMP_REG(DC_WIN_WIN_OPTIONS);
243                 DUMP_REG(DC_WIN_BYTE_SWAP);
244                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
245                 DUMP_REG(DC_WIN_COLOR_DEPTH);
246                 DUMP_REG(DC_WIN_POSITION);
247                 DUMP_REG(DC_WIN_SIZE);
248                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
249                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
250                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
251                 DUMP_REG(DC_WIN_DDA_INCREMENT);
252                 DUMP_REG(DC_WIN_LINE_STRIDE);
253                 DUMP_REG(DC_WIN_BUF_STRIDE);
254                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
255                 DUMP_REG(DC_WIN_BLEND_NOKEY);
256                 DUMP_REG(DC_WIN_BLEND_1WIN);
257                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
258                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
259                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
260                 DUMP_REG(DC_WINBUF_START_ADDR);
261                 DUMP_REG(DC_WINBUF_START_ADDR_U);
262                 DUMP_REG(DC_WINBUF_START_ADDR_V);
263                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
264                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
265                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
266                 DUMP_REG(DC_WIN_CSC_YOF);
267                 DUMP_REG(DC_WIN_CSC_KYRGB);
268                 DUMP_REG(DC_WIN_CSC_KUR);
269                 DUMP_REG(DC_WIN_CSC_KVR);
270                 DUMP_REG(DC_WIN_CSC_KUG);
271                 DUMP_REG(DC_WIN_CSC_KVG);
272                 DUMP_REG(DC_WIN_CSC_KUB);
273                 DUMP_REG(DC_WIN_CSC_KVB);
274         }
275
276         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
277         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
278         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
279         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
280         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
281         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
282         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
283         DUMP_REG(DC_DISP_M1_CONTROL);
284         DUMP_REG(DC_COM_PM1_CONTROL);
285         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
286         DUMP_REG(DC_DISP_SD_CONTROL);
287
288         tegra_dc_io_end(dc);
289         tegra_dc_release_dc_out(dc);
290         mutex_unlock(&dc->lock);
291 }
292
293 #undef DUMP_REG
294
295 #ifdef DEBUG
296 static void dump_regs_print(void *data, const char *str)
297 {
298         struct tegra_dc *dc = data;
299         dev_dbg(&dc->ndev->dev, "%s", str);
300 }
301
302 static void dump_regs(struct tegra_dc *dc)
303 {
304         _dump_regs(dc, dc, dump_regs_print);
305 }
306 #else /* !DEBUG */
307
308 static void dump_regs(struct tegra_dc *dc) {}
309
310 #endif /* DEBUG */
311
312 #ifdef CONFIG_DEBUG_FS
313
314 static void dbg_regs_print(void *data, const char *str)
315 {
316         struct seq_file *s = data;
317
318         seq_printf(s, "%s", str);
319 }
320
321 #undef DUMP_REG
322
323 static int dbg_dc_show(struct seq_file *s, void *unused)
324 {
325         struct tegra_dc *dc = s->private;
326
327         _dump_regs(dc, s, dbg_regs_print);
328
329         return 0;
330 }
331
332
333 static int dbg_dc_open(struct inode *inode, struct file *file)
334 {
335         return single_open(file, dbg_dc_show, inode->i_private);
336 }
337
338 static const struct file_operations regs_fops = {
339         .open           = dbg_dc_open,
340         .read           = seq_read,
341         .llseek         = seq_lseek,
342         .release        = single_release,
343 };
344
345 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
346 {
347         struct tegra_dc *dc = s->private;
348         struct tegra_dc_mode *m;
349
350         mutex_lock(&dc->lock);
351         m = &dc->mode;
352         seq_printf(s,
353                 "pclk: %d\n"
354                 "h_ref_to_sync: %d\n"
355                 "v_ref_to_sync: %d\n"
356                 "h_sync_width: %d\n"
357                 "v_sync_width: %d\n"
358                 "h_back_porch: %d\n"
359                 "v_back_porch: %d\n"
360                 "h_active: %d\n"
361                 "v_active: %d\n"
362                 "h_front_porch: %d\n"
363                 "v_front_porch: %d\n"
364                 "stereo_mode: %d\n",
365                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
366                 m->h_sync_width, m->v_sync_width,
367                 m->h_back_porch, m->v_back_porch,
368                 m->h_active, m->v_active,
369                 m->h_front_porch, m->v_front_porch,
370                 m->stereo_mode);
371         mutex_unlock(&dc->lock);
372         return 0;
373 }
374
375 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
376 {
377         return single_open(file, dbg_dc_mode_show, inode->i_private);
378 }
379
380 static const struct file_operations mode_fops = {
381         .open           = dbg_dc_mode_open,
382         .read           = seq_read,
383         .llseek         = seq_lseek,
384         .release        = single_release,
385 };
386
387 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
388 {
389         struct tegra_dc *dc = s->private;
390
391         mutex_lock(&dc->lock);
392         seq_printf(s,
393                 "underflows: %llu\n"
394                 "underflows_a: %llu\n"
395                 "underflows_b: %llu\n"
396                 "underflows_c: %llu\n",
397                 dc->stats.underflows,
398                 dc->stats.underflows_a,
399                 dc->stats.underflows_b,
400                 dc->stats.underflows_c);
401         mutex_unlock(&dc->lock);
402
403         return 0;
404 }
405
406 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
407 {
408         return single_open(file, dbg_dc_stats_show, inode->i_private);
409 }
410
411 static const struct file_operations stats_fops = {
412         .open           = dbg_dc_stats_open,
413         .read           = seq_read,
414         .llseek         = seq_lseek,
415         .release        = single_release,
416 };
417
418 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
419 {
420         if (dc->debugdir)
421                 debugfs_remove_recursive(dc->debugdir);
422         dc->debugdir = NULL;
423 }
424
425 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
426 {
427         struct dentry *retval;
428
429         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
430         if (!dc->debugdir)
431                 goto remove_out;
432
433         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
434                 &regs_fops);
435         if (!retval)
436                 goto remove_out;
437
438         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
439                 &mode_fops);
440         if (!retval)
441                 goto remove_out;
442
443         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
444                 &stats_fops);
445         if (!retval)
446                 goto remove_out;
447
448         return;
449 remove_out:
450         dev_err(&dc->ndev->dev, "could not create debugfs\n");
451         tegra_dc_remove_debugfs(dc);
452 }
453
454 #else /* !CONFIG_DEBUGFS */
455 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
456 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
457 #endif /* CONFIG_DEBUGFS */
458
459 static int tegra_dc_set(struct tegra_dc *dc, int index)
460 {
461         int ret = 0;
462
463         mutex_lock(&tegra_dc_lock);
464         if (index >= TEGRA_MAX_DC) {
465                 ret = -EINVAL;
466                 goto out;
467         }
468
469         if (dc != NULL && tegra_dcs[index] != NULL) {
470                 ret = -EBUSY;
471                 goto out;
472         }
473
474         tegra_dcs[index] = dc;
475
476 out:
477         mutex_unlock(&tegra_dc_lock);
478
479         return ret;
480 }
481
482 unsigned int tegra_dc_has_multiple_dc(void)
483 {
484         unsigned int idx;
485         unsigned int cnt = 0;
486         struct tegra_dc *dc;
487
488         mutex_lock(&tegra_dc_lock);
489         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
490                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
491         mutex_unlock(&tegra_dc_lock);
492
493         return (cnt > 1);
494 }
495
496 /* get the stride size of a window.
497  * return: stride size in bytes for window win. or 0 if unavailble. */
498 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
499 {
500         u32 stride;
501
502         if (!dc->enabled)
503                 return 0;
504         BUG_ON(win > DC_N_WINDOWS);
505         mutex_lock(&dc->lock);
506         tegra_dc_hold_dc_out(dc);
507         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
508                 DC_CMD_DISPLAY_WINDOW_HEADER);
509         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
510         tegra_dc_release_dc_out(dc);
511         mutex_unlock(&dc->lock);
512         return GET_LINE_STRIDE(stride);
513 }
514 EXPORT_SYMBOL(tegra_dc_get_stride);
515
516 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
517 {
518         if (idx < TEGRA_MAX_DC)
519                 return tegra_dcs[idx];
520         else
521                 return NULL;
522 }
523 EXPORT_SYMBOL(tegra_dc_get_dc);
524
525 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
526 {
527         if (win >= dc->n_windows)
528                 return NULL;
529
530         return &dc->windows[win];
531 }
532 EXPORT_SYMBOL(tegra_dc_get_window);
533
534 bool tegra_dc_get_connected(struct tegra_dc *dc)
535 {
536         return dc->connected;
537 }
538 EXPORT_SYMBOL(tegra_dc_get_connected);
539
540 bool tegra_dc_hpd(struct tegra_dc *dc)
541 {
542         int sense;
543         int level;
544
545         level = gpio_get_value(dc->out->hotplug_gpio);
546
547         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
548
549         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
550                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
551 }
552 EXPORT_SYMBOL(tegra_dc_hpd);
553
554 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
555 {
556         unsigned i;
557         unsigned v0 = 128;
558         unsigned v1 = 0;
559         /* linear horizontal and vertical filters */
560         for (i = 0; i < 16; i++) {
561                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
562                                 DC_WIN_H_FILTER_P(i));
563
564                 tegra_dc_writel(dc, v0,
565                                 DC_WIN_V_FILTER_P(i));
566                 v0 -= 8;
567                 v1 += 8;
568         }
569 }
570
571 static inline void disable_dc_irq(unsigned int irq)
572 {
573         disable_irq(irq);
574 }
575
576 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
577 {
578         return dc->syncpt[i].id;
579 }
580 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
581
582 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
583 {
584         u32 max;
585
586         mutex_lock(&dc->lock);
587         tegra_dc_hold_dc_out(dc);
588         max = nvhost_syncpt_incr_max_ext(dc->ndev,
589                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
590         dc->syncpt[i].max = max;
591         tegra_dc_release_dc_out(dc);
592         mutex_unlock(&dc->lock);
593
594         return max;
595 }
596
597 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
598 {
599         mutex_lock(&dc->lock);
600         if (dc->enabled) {
601                 tegra_dc_hold_dc_out(dc);
602                 while (dc->syncpt[i].min < val) {
603                         dc->syncpt[i].min++;
604                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
605                 }
606                 tegra_dc_release_dc_out(dc);
607         }
608         mutex_unlock(&dc->lock);
609 }
610
611 void
612 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
613 {
614         unsigned int ctrl;
615         unsigned long out_sel;
616         unsigned long cmd_state;
617
618         mutex_lock(&dc->lock);
619         if (!dc->enabled) {
620                 mutex_unlock(&dc->lock);
621                 return;
622         }
623
624         tegra_dc_hold_dc_out(dc);
625
626         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
627                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
628                 cfg->clk_select);
629
630         /* The new value should be effected immediately */
631         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
632         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
633
634         switch (cfg->which_pwm) {
635         case TEGRA_PWM_PM0:
636                 /* Select the LM0 on PM0 */
637                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
638                 out_sel &= ~(7 << 0);
639                 out_sel |= (3 << 0);
640                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
641                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
642                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
643                 break;
644         case TEGRA_PWM_PM1:
645                 /* Select the LM1 on PM1 */
646                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
647                 out_sel &= ~(7 << 4);
648                 out_sel |= (3 << 4);
649                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
650                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
651                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
652                 break;
653         default:
654                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
655                 break;
656         }
657         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
658         tegra_dc_release_dc_out(dc);
659         mutex_unlock(&dc->lock);
660 }
661 EXPORT_SYMBOL(tegra_dc_config_pwm);
662
663 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
664                                 const struct tegra_dc_out_pin *pins,
665                                 const unsigned int n_pins)
666 {
667         unsigned int i;
668
669         int name;
670         int pol;
671
672         u32 pol1, pol3;
673
674         u32 set1, unset1;
675         u32 set3, unset3;
676
677         set1 = set3 = unset1 = unset3 = 0;
678
679         for (i = 0; i < n_pins; i++) {
680                 name = (pins + i)->name;
681                 pol  = (pins + i)->pol;
682
683                 /* set polarity by name */
684                 switch (name) {
685                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
686                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
687                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
688                         else
689                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
690                         break;
691                 case TEGRA_DC_OUT_PIN_H_SYNC:
692                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
693                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
694                         else
695                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
696                         break;
697                 case TEGRA_DC_OUT_PIN_V_SYNC:
698                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
699                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
700                         else
701                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
702                         break;
703                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
704                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
705                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
706                         else
707                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
708                         break;
709                 default:
710                         printk("Invalid argument in function %s\n",
711                                __FUNCTION__);
712                         break;
713                 }
714         }
715
716         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
717         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
718
719         pol1 |= set1;
720         pol1 &= ~unset1;
721
722         pol3 |= set3;
723         pol3 &= ~unset3;
724
725         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
726         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
727 }
728
729 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
730 {
731         if (dc->out->type == TEGRA_DC_OUT_RGB ||
732                 dc->out->type == TEGRA_DC_OUT_HDMI ||
733                 dc->out->type == TEGRA_DC_OUT_DSI)
734                 return override_disp_mode[dc->out->type].pclk ?
735                         &override_disp_mode[dc->out->type] : NULL;
736         else
737                 return NULL;
738 }
739
740 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
741 {
742         struct tegra_dc_mode *mode;
743
744         dc->out = out;
745         mode = tegra_dc_get_override_mode(dc);
746
747         if (mode)
748                 tegra_dc_set_mode(dc, mode);
749         else if (out->n_modes > 0)
750                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
751
752         switch (out->type) {
753         case TEGRA_DC_OUT_RGB:
754                 dc->out_ops = &tegra_dc_rgb_ops;
755                 break;
756
757         case TEGRA_DC_OUT_HDMI:
758                 dc->out_ops = &tegra_dc_hdmi_ops;
759                 break;
760
761         case TEGRA_DC_OUT_DSI:
762                 dc->out_ops = &tegra_dc_dsi_ops;
763                 break;
764
765         default:
766                 dc->out_ops = NULL;
767                 break;
768         }
769
770         if (dc->out_ops && dc->out_ops->init)
771                 dc->out_ops->init(dc);
772
773 }
774
775 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
776 {
777         if (dc->out)
778                 return dc->out->height;
779         else
780                 return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_get_out_height);
783
784 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
785 {
786         if (dc->out)
787                 return dc->out->width;
788         else
789                 return 0;
790 }
791 EXPORT_SYMBOL(tegra_dc_get_out_width);
792
793 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
794 {
795         if (dc->out && dc->out->max_pixclock)
796                 return dc->out->max_pixclock;
797         else
798                 return 0;
799 }
800 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
801
802 void tegra_dc_enable_crc(struct tegra_dc *dc)
803 {
804         u32 val;
805
806         mutex_lock(&dc->lock);
807         tegra_dc_hold_dc_out(dc);
808         tegra_dc_io_start(dc);
809
810         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
811                 CRC_ENABLE_ENABLE;
812         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
813         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
814         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
815         tegra_dc_release_dc_out(dc);
816         mutex_unlock(&dc->lock);
817 }
818
819 void tegra_dc_disable_crc(struct tegra_dc *dc)
820 {
821         mutex_lock(&dc->lock);
822         tegra_dc_hold_dc_out(dc);
823         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
824         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
825         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
826
827         tegra_dc_io_end(dc);
828         tegra_dc_release_dc_out(dc);
829         mutex_unlock(&dc->lock);
830 }
831
832 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
833 {
834         int crc = 0;
835
836         if (!dc) {
837                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
838                 goto crc_error;
839         }
840
841         /* TODO: Replace mdelay with code to sync VBlANK, since
842          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
843         mdelay(TEGRA_CRC_LATCHED_DELAY);
844
845         mutex_lock(&dc->lock);
846         tegra_dc_hold_dc_out(dc);
847         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
848         tegra_dc_release_dc_out(dc);
849         mutex_unlock(&dc->lock);
850 crc_error:
851         return crc;
852 }
853
854 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
855 {
856 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
857         u32 val;
858
859         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
860         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
861             return true;
862 #endif
863         return false;
864 }
865
866 static inline void enable_dc_irq(unsigned int irq)
867 {
868 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
869         enable_irq(irq);
870 #else
871         /* Always disable DC interrupts on FPGA. */
872         disable_irq(irq);
873 #endif
874 }
875
876 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
877 {
878         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
879                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
880 }
881
882 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
883 {
884         int ret = -ENOTTY;
885
886         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
887                 return ret;
888
889         /*
890          * Logic is as follows
891          * a) Indicate we need a vblank.
892          * b) Wait for completion to be signalled from isr.
893          * c) Initialize completion for next iteration.
894          */
895
896         tegra_dc_hold_dc_out(dc);
897         dc->out->user_needs_vblank = true;
898
899         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
900         init_completion(&dc->out->user_vblank_comp);
901         tegra_dc_release_dc_out(dc);
902
903         return ret;
904 }
905
906 static void tegra_dc_vblank(struct work_struct *work)
907 {
908         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
909         bool nvsd_updated = false;
910
911         mutex_lock(&dc->lock);
912
913         if (!dc->enabled) {
914                 mutex_unlock(&dc->lock);
915                 return;
916         }
917
918         tegra_dc_hold_dc_out(dc);
919         /* use the new frame's bandwidth setting instead of max(current, new),
920          * skip this if we're using tegra_dc_one_shot_worker() */
921         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
922                 tegra_dc_program_bandwidth(dc, true);
923
924         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
925         if (!tegra_dc_windows_are_dirty(dc))
926                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
927
928         /* Update the SD brightness */
929         if (dc->enabled && dc->out->sd_settings) {
930                 nvsd_updated = nvsd_update_brightness(dc);
931                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
932                  * V_BLANK_NVSD bit of vblank ref-count. */
933                 if (nvsd_updated) {
934                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
935                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
936                 } else {
937                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
938                 }
939         }
940
941         /* Mask vblank interrupt if ref-count is zero. */
942         if (!dc->vblank_ref_count)
943                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
944
945         tegra_dc_release_dc_out(dc);
946         mutex_unlock(&dc->lock);
947
948         /* Do the actual brightness update outside of the mutex */
949         if (nvsd_updated && dc->out->sd_settings &&
950             dc->out->sd_settings->bl_device) {
951
952                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
953                 struct backlight_device *bl = platform_get_drvdata(pdev);
954                 if (bl)
955                         backlight_update_status(bl);
956         }
957 }
958
959 static void tegra_dc_one_shot_worker(struct work_struct *work)
960 {
961         struct tegra_dc *dc = container_of(
962                 to_delayed_work(work), struct tegra_dc, one_shot_work);
963         mutex_lock(&dc->lock);
964
965         /* memory client has gone idle */
966         tegra_dc_clear_bandwidth(dc);
967
968         if (dc->out_ops->idle)
969                 dc->out_ops->idle(dc);
970
971         mutex_unlock(&dc->lock);
972 }
973
974 /* return an arbitrarily large number if count overflow occurs.
975  * make it a nice base-10 number to show up in stats output */
976 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
977 {
978         unsigned count = tegra_dc_readl(dc, reg);
979         tegra_dc_writel(dc, 0, reg);
980         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
981 }
982
983 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
984 {
985         u32 val;
986         int i;
987
988         dc->stats.underflows++;
989         if (dc->underflow_mask & WIN_A_UF_INT) {
990                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
991                         DC_WINBUF_AD_UFLOW_STATUS);
992                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
993         }
994         if (dc->underflow_mask & WIN_B_UF_INT) {
995                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
996                         DC_WINBUF_BD_UFLOW_STATUS);
997                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
998         }
999         if (dc->underflow_mask & WIN_C_UF_INT) {
1000                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1001                         DC_WINBUF_CD_UFLOW_STATUS);
1002                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1003         }
1004
1005         /* Check for any underflow reset conditions */
1006         for (i = 0; i < DC_N_WINDOWS; i++) {
1007                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1008                         dc->windows[i].underflows++;
1009
1010 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1011                         if (dc->windows[i].underflows > 4) {
1012                                 schedule_work(&dc->reset_work);
1013                                 /* reset counter */
1014                                 dc->windows[i].underflows = 0;
1015                                 trace_printk("%s:Reset work scheduled for "
1016                                                 "window %c\n",
1017                                                 dc->ndev->name, (65 + i));
1018                         }
1019 #endif
1020 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1021                         if (dc->windows[i].underflows > 4) {
1022                                 trace_printk("%s:window %c in underflow state."
1023                                         " enable UF_LINE_FLUSH to clear up\n",
1024                                         dc->ndev->name, (65 + i));
1025                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1026                                                 DC_DISP_DISP_MISC_CONTROL);
1027                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1028                                                 DC_CMD_STATE_CONTROL);
1029                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1030                                                 DC_CMD_STATE_CONTROL);
1031
1032                                 tegra_dc_writel(dc, 0,
1033                                                 DC_DISP_DISP_MISC_CONTROL);
1034                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1035                                                 DC_CMD_STATE_CONTROL);
1036                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1037                                                 DC_CMD_STATE_CONTROL);
1038                         }
1039 #endif
1040                 } else {
1041                         dc->windows[i].underflows = 0;
1042                 }
1043         }
1044
1045         /* Clear the underflow mask now that we've checked it. */
1046         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1047         dc->underflow_mask = 0;
1048         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1049         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1050         print_underflow_info(dc);
1051 }
1052
1053 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1054 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1055 {
1056         /* pending user vblank, so wakeup */
1057         if ((status & (V_BLANK_INT | MSF_INT)) &&
1058             (dc->out->user_needs_vblank)) {
1059                 dc->out->user_needs_vblank = false;
1060                 complete(&dc->out->user_vblank_comp);
1061         }
1062
1063         if (status & V_BLANK_INT) {
1064                 /* Sync up windows. */
1065                 tegra_dc_trigger_windows(dc);
1066
1067                 /* Schedule any additional bottom-half vblank actvities. */
1068                 queue_work(system_freezable_wq, &dc->vblank_work);
1069         }
1070
1071         if (status & FRAME_END_INT) {
1072                 /* Mark the frame_end as complete. */
1073                 if (!completion_done(&dc->frame_end_complete))
1074                         complete(&dc->frame_end_complete);
1075         }
1076 }
1077
1078 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1079 {
1080         /* Schedule any additional bottom-half vblank actvities. */
1081         if (status & V_BLANK_INT)
1082                 queue_work(system_freezable_wq, &dc->vblank_work);
1083
1084         if (status & FRAME_END_INT) {
1085                 struct timespec tm = CURRENT_TIME;
1086                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1087                 wake_up(&dc->timestamp_wq);
1088
1089                 /* Mark the frame_end as complete. */
1090                 if (!completion_done(&dc->frame_end_complete))
1091                         complete(&dc->frame_end_complete);
1092
1093                 tegra_dc_trigger_windows(dc);
1094         }
1095 }
1096
1097 /* XXX: Not sure if we limit look ahead to 1 frame */
1098 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1099 {
1100         BUG_ON(!dc->frametime_ns);
1101         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1102 }
1103
1104 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1105 {
1106         BUG_ON(!dc->frametime_ns);
1107         return (((new_ts - old_ts) > dc->frametime_ns)
1108                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1109                         != div_s64((old_ts - dc->frame_end_timestamp),
1110                                 dc->frametime_ns)));
1111 }
1112 #endif
1113
1114 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1115 {
1116 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1117         struct tegra_dc *dc = ptr;
1118         unsigned long status;
1119         unsigned long underflow_mask;
1120         u32 val;
1121
1122         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1123                 WARN(1, "IRQ when DC not powered!\n");
1124                 tegra_dc_io_start(dc);
1125                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1126                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1127                 tegra_dc_io_end(dc);
1128                 return IRQ_HANDLED;
1129         }
1130
1131         /* clear all status flags except underflow, save those for the worker */
1132         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1133         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1134         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1135         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1136
1137         /*
1138          * Overlays can get thier internal state corrupted during and underflow
1139          * condition.  The only way to fix this state is to reset the DC.
1140          * if we get 4 consecutive frames with underflows, assume we're
1141          * hosed and reset.
1142          */
1143         underflow_mask = status & ALL_UF_INT;
1144
1145         /* Check underflow */
1146         if (underflow_mask) {
1147                 dc->underflow_mask |= underflow_mask;
1148                 schedule_delayed_work(&dc->underflow_work,
1149                         msecs_to_jiffies(1));
1150         }
1151
1152         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1153                 tegra_dc_one_shot_irq(dc, status);
1154         else
1155                 tegra_dc_continuous_irq(dc, status);
1156
1157         return IRQ_HANDLED;
1158 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1159         return IRQ_NONE;
1160 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1161 }
1162
1163 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1164 {
1165         u32 color_control;
1166
1167         switch (dc->out->depth) {
1168         case 3:
1169                 color_control = BASE_COLOR_SIZE111;
1170                 break;
1171
1172         case 6:
1173                 color_control = BASE_COLOR_SIZE222;
1174                 break;
1175
1176         case 8:
1177                 color_control = BASE_COLOR_SIZE332;
1178                 break;
1179
1180         case 9:
1181                 color_control = BASE_COLOR_SIZE333;
1182                 break;
1183
1184         case 12:
1185                 color_control = BASE_COLOR_SIZE444;
1186                 break;
1187
1188         case 15:
1189                 color_control = BASE_COLOR_SIZE555;
1190                 break;
1191
1192         case 16:
1193                 color_control = BASE_COLOR_SIZE565;
1194                 break;
1195
1196         case 18:
1197                 color_control = BASE_COLOR_SIZE666;
1198                 break;
1199
1200         default:
1201                 color_control = BASE_COLOR_SIZE888;
1202                 break;
1203         }
1204
1205         switch (dc->out->dither) {
1206         case TEGRA_DC_DISABLE_DITHER:
1207                 color_control |= DITHER_CONTROL_DISABLE;
1208                 break;
1209         case TEGRA_DC_ORDERED_DITHER:
1210                 color_control |= DITHER_CONTROL_ORDERED;
1211                 break;
1212         case TEGRA_DC_ERRDIFF_DITHER:
1213                 /* The line buffer for error-diffusion dither is limited
1214                  * to 1280 pixels per line. This limits the maximum
1215                  * horizontal active area size to 1280 pixels when error
1216                  * diffusion is enabled.
1217                  */
1218                 BUG_ON(dc->mode.h_active > 1280);
1219                 color_control |= DITHER_CONTROL_ERRDIFF;
1220                 break;
1221         }
1222
1223         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1224 }
1225
1226 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1227 {
1228         u32 syncpt_id;
1229
1230         switch (dc->ndev->id) {
1231         case 0:
1232                 switch (idx) {
1233                 case 0:
1234                         syncpt_id = NVSYNCPT_DISP0_A;
1235                         break;
1236                 case 1:
1237                         syncpt_id = NVSYNCPT_DISP0_B;
1238                         break;
1239                 case 2:
1240                         syncpt_id = NVSYNCPT_DISP0_C;
1241                         break;
1242                 default:
1243                         BUG();
1244                         break;
1245                 }
1246                 break;
1247         case 1:
1248                 switch (idx) {
1249                 case 0:
1250                         syncpt_id = NVSYNCPT_DISP1_A;
1251                         break;
1252                 case 1:
1253                         syncpt_id = NVSYNCPT_DISP1_B;
1254                         break;
1255                 case 2:
1256                         syncpt_id = NVSYNCPT_DISP1_C;
1257                         break;
1258                 default:
1259                         BUG();
1260                         break;
1261                 }
1262                 break;
1263         default:
1264                 BUG();
1265                 break;
1266         }
1267
1268         return syncpt_id;
1269 }
1270
1271 static int tegra_dc_init(struct tegra_dc *dc)
1272 {
1273         int i;
1274         int int_enable;
1275
1276         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1277         if (dc->ndev->id == 0) {
1278                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1279                                       TEGRA_MC_PRIO_MED);
1280                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1281                                       TEGRA_MC_PRIO_MED);
1282                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1283                                       TEGRA_MC_PRIO_MED);
1284                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1285                                       TEGRA_MC_PRIO_MED);
1286                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1287                                       TEGRA_MC_PRIO_HIGH);
1288         } else if (dc->ndev->id == 1) {
1289                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1290                                       TEGRA_MC_PRIO_MED);
1291                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1292                                       TEGRA_MC_PRIO_MED);
1293                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1294                                       TEGRA_MC_PRIO_MED);
1295                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1296                                       TEGRA_MC_PRIO_MED);
1297                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1298                                       TEGRA_MC_PRIO_HIGH);
1299         }
1300         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1301                         DC_CMD_CONT_SYNCPT_VSYNC);
1302         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1303         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1304         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1305         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1306 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1307         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1308 #endif
1309         /* enable interrupts for vblank, frame_end and underflows */
1310         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1311         /* for panels with one-shot mode enable tearing effect interrupt */
1312         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1313                 int_enable |= MSF_INT;
1314
1315         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1316         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1317
1318         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1319
1320         tegra_dc_set_color_control(dc);
1321         for (i = 0; i < DC_N_WINDOWS; i++) {
1322                 struct tegra_dc_win *win = &dc->windows[i];
1323                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1324                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1325                 tegra_dc_set_csc(dc, &win->csc);
1326                 tegra_dc_set_lut(dc, win);
1327                 tegra_dc_set_scaling_filter(dc);
1328         }
1329
1330
1331         for (i = 0; i < dc->n_windows; i++) {
1332                 u32 syncpt = get_syncpt(dc, i);
1333
1334                 dc->syncpt[i].id = syncpt;
1335
1336                 dc->syncpt[i].min = dc->syncpt[i].max =
1337                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1338         }
1339
1340         print_mode_info(dc, dc->mode);
1341
1342         if (dc->mode.pclk)
1343                 if (tegra_dc_program_mode(dc, &dc->mode))
1344                         return -EINVAL;
1345
1346         /* Initialize SD AFTER the modeset.
1347            nvsd_init handles the sd_settings = NULL case. */
1348         nvsd_init(dc, dc->out->sd_settings);
1349
1350         return 0;
1351 }
1352
1353 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1354 {
1355         int failed_init = 0;
1356
1357         if (dc->out->enable)
1358                 dc->out->enable();
1359
1360         tegra_dc_setup_clk(dc, dc->clk);
1361         tegra_dc_clk_enable(dc);
1362
1363         /* do not accept interrupts during initialization */
1364         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1365
1366         enable_dc_irq(dc->irq);
1367
1368         failed_init = tegra_dc_init(dc);
1369         if (failed_init) {
1370                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1371                 disable_irq(dc->irq);
1372                 tegra_dc_clear_bandwidth(dc);
1373                 tegra_dc_clk_disable(dc);
1374                 if (dc->out && dc->out->disable)
1375                         dc->out->disable();
1376                 return false;
1377         }
1378
1379         if (dc->out_ops && dc->out_ops->enable)
1380                 dc->out_ops->enable(dc);
1381
1382         /* force a full blending update */
1383         dc->blend.z[0] = -1;
1384
1385         tegra_dc_ext_enable(dc->ext);
1386
1387         trace_printk("%s:enable\n", dc->ndev->name);
1388
1389         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1390         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1391
1392         if (dc->out->postpoweron)
1393                 dc->out->postpoweron();
1394
1395         return true;
1396 }
1397
1398 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1399 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1400 {
1401         bool ret = true;
1402
1403         if (dc->out->enable)
1404                 dc->out->enable();
1405
1406         tegra_dc_setup_clk(dc, dc->clk);
1407         tegra_dc_clk_enable(dc);
1408
1409         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1410                 mutex_lock(&tegra_dcs[1]->lock);
1411                 disable_irq(tegra_dcs[1]->irq);
1412         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1413                 mutex_lock(&tegra_dcs[0]->lock);
1414                 disable_irq(tegra_dcs[0]->irq);
1415         }
1416
1417         msleep(5);
1418         tegra_periph_reset_assert(dc->clk);
1419         msleep(2);
1420 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1421         tegra_periph_reset_deassert(dc->clk);
1422         msleep(1);
1423 #endif
1424
1425         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1426                 enable_dc_irq(tegra_dcs[1]->irq);
1427                 mutex_unlock(&tegra_dcs[1]->lock);
1428         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1429                 enable_dc_irq(tegra_dcs[0]->irq);
1430                 mutex_unlock(&tegra_dcs[0]->lock);
1431         }
1432
1433         enable_dc_irq(dc->irq);
1434
1435         if (tegra_dc_init(dc)) {
1436                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1437                 ret = false;
1438         }
1439
1440         if (dc->out_ops && dc->out_ops->enable)
1441                 dc->out_ops->enable(dc);
1442
1443         if (dc->out->postpoweron)
1444                 dc->out->postpoweron();
1445
1446         /* force a full blending update */
1447         dc->blend.z[0] = -1;
1448
1449         tegra_dc_ext_enable(dc->ext);
1450
1451         if (!ret) {
1452                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1453                 _tegra_dc_controller_disable(dc);
1454         }
1455
1456         trace_printk("%s:reset enable\n", dc->ndev->name);
1457         return ret;
1458 }
1459 #endif
1460
1461 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1462 {
1463         if (dc->mode.pclk == 0) {
1464                 switch (dc->out->type) {
1465                 case TEGRA_DC_OUT_HDMI:
1466                 /* DC enable called but no videomode is loaded.
1467                      Check if HDMI is connected, then set fallback mdoe */
1468                 if (tegra_dc_hpd(dc)) {
1469                         return tegra_dc_set_fb_mode(dc,
1470                                         &tegra_dc_hdmi_fallback_mode, 0);
1471                 } else
1472                         return false;
1473
1474                 break;
1475
1476                 /* Do nothing for other outputs for now */
1477                 case TEGRA_DC_OUT_RGB:
1478
1479                 case TEGRA_DC_OUT_DSI:
1480
1481                 default:
1482                         return false;
1483                 }
1484         }
1485
1486         return false;
1487 }
1488
1489 static bool _tegra_dc_enable(struct tegra_dc *dc)
1490 {
1491         if (dc->mode.pclk == 0)
1492                 return false;
1493
1494         if (!dc->out)
1495                 return false;
1496
1497         tegra_dc_io_start(dc);
1498
1499         if (!_tegra_dc_controller_enable(dc)) {
1500                 tegra_dc_io_end(dc);
1501                 return false;
1502         }
1503         return true;
1504 }
1505
1506 void tegra_dc_enable(struct tegra_dc *dc)
1507 {
1508         mutex_lock(&dc->lock);
1509
1510         if (!dc->enabled)
1511                 dc->enabled = _tegra_dc_enable(dc);
1512
1513         mutex_unlock(&dc->lock);
1514         print_mode_info(dc, dc->mode);
1515 }
1516
1517 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1518 {
1519         unsigned i;
1520
1521         if (dc->out && dc->out->prepoweroff)
1522                 dc->out->prepoweroff();
1523
1524         if (dc->out_ops && dc->out_ops->disable)
1525                 dc->out_ops->disable(dc);
1526
1527         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1528         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1529         disable_irq(dc->irq);
1530
1531         tegra_dc_clear_bandwidth(dc);
1532         tegra_dc_clk_disable(dc);
1533
1534         if (dc->out && dc->out->disable)
1535                 dc->out->disable();
1536
1537         for (i = 0; i < dc->n_windows; i++) {
1538                 struct tegra_dc_win *w = &dc->windows[i];
1539
1540                 /* reset window bandwidth */
1541                 w->bandwidth = 0;
1542                 w->new_bandwidth = 0;
1543
1544                 /* disable windows */
1545                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1546
1547                 /* flush any pending syncpt waits */
1548                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1549                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1550                                 dc->syncpt[i].id);
1551                         dc->syncpt[i].min++;
1552                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1553                 }
1554         }
1555         trace_printk("%s:disabled\n", dc->ndev->name);
1556 }
1557
1558 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1559 {
1560 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1561         u32 val;
1562         if (dc->enabled)  {
1563                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1564                 if (enable)
1565                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1566                 else
1567                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1568                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1569         }
1570 #endif
1571 }
1572
1573 bool tegra_dc_stats_get(struct tegra_dc *dc)
1574 {
1575 #if 0 /* right now it is always enabled */
1576         u32 val;
1577         bool res;
1578
1579         if (dc->enabled)  {
1580                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1581                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1582         } else {
1583                 res = false;
1584         }
1585
1586         return res;
1587 #endif
1588         return true;
1589 }
1590
1591 /* make the screen blank by disabling all windows */
1592 void tegra_dc_blank(struct tegra_dc *dc)
1593 {
1594         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1595         unsigned i;
1596
1597         for (i = 0; i < DC_N_WINDOWS; i++) {
1598                 dcwins[i] = tegra_dc_get_window(dc, i);
1599                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1600         }
1601
1602         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1603         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1604 }
1605
1606 static void _tegra_dc_disable(struct tegra_dc *dc)
1607 {
1608         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1609                 mutex_lock(&dc->one_shot_lock);
1610                 cancel_delayed_work_sync(&dc->one_shot_work);
1611         }
1612
1613         tegra_dc_hold_dc_out(dc);
1614
1615         _tegra_dc_controller_disable(dc);
1616         tegra_dc_io_end(dc);
1617
1618         tegra_dc_release_dc_out(dc);
1619
1620         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1621                 mutex_unlock(&dc->one_shot_lock);
1622 }
1623
1624 void tegra_dc_disable(struct tegra_dc *dc)
1625 {
1626         tegra_dc_ext_disable(dc->ext);
1627
1628         /* it's important that new underflow work isn't scheduled before the
1629          * lock is acquired. */
1630         cancel_delayed_work_sync(&dc->underflow_work);
1631
1632         mutex_lock(&dc->lock);
1633
1634         if (dc->enabled) {
1635                 dc->enabled = false;
1636
1637                 if (!dc->suspended)
1638                         _tegra_dc_disable(dc);
1639         }
1640
1641 #ifdef CONFIG_SWITCH
1642         switch_set_state(&dc->modeset_switch, 0);
1643 #endif
1644
1645         mutex_unlock(&dc->lock);
1646         print_mode_info(dc, dc->mode);
1647 }
1648
1649 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1650 static void tegra_dc_reset_worker(struct work_struct *work)
1651 {
1652         struct tegra_dc *dc =
1653                 container_of(work, struct tegra_dc, reset_work);
1654
1655         unsigned long val = 0;
1656
1657         mutex_lock(&shared_lock);
1658
1659         dev_warn(&dc->ndev->dev,
1660                 "overlay stuck in underflow state.  resetting.\n");
1661
1662         tegra_dc_ext_disable(dc->ext);
1663
1664         mutex_lock(&dc->lock);
1665
1666         if (dc->enabled == false)
1667                 goto unlock;
1668
1669         dc->enabled = false;
1670
1671         /*
1672          * off host read bus
1673          */
1674         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1675         val &= ~(0x00000100);
1676         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1677
1678         /*
1679          * set DC to STOP mode
1680          */
1681         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1682
1683         msleep(10);
1684
1685         _tegra_dc_controller_disable(dc);
1686
1687         /* _tegra_dc_controller_reset_enable deasserts reset */
1688         _tegra_dc_controller_reset_enable(dc);
1689
1690         dc->enabled = true;
1691
1692         /* reopen host read bus */
1693         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1694         val &= ~(0x00000100);
1695         val |= 0x100;
1696         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1697
1698 unlock:
1699         mutex_unlock(&dc->lock);
1700         mutex_unlock(&shared_lock);
1701         trace_printk("%s:reset complete\n", dc->ndev->name);
1702 }
1703 #endif
1704
1705 static void tegra_dc_underflow_worker(struct work_struct *work)
1706 {
1707         struct tegra_dc *dc = container_of(
1708                 to_delayed_work(work), struct tegra_dc, underflow_work);
1709
1710         mutex_lock(&dc->lock);
1711         tegra_dc_hold_dc_out(dc);
1712
1713         if (dc->enabled) {
1714                 tegra_dc_underflow_handler(dc);
1715         }
1716         tegra_dc_release_dc_out(dc);
1717         mutex_unlock(&dc->lock);
1718 }
1719
1720 #ifdef CONFIG_SWITCH
1721 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1722 {
1723         struct tegra_dc *dc =
1724                 container_of(sdev, struct tegra_dc, modeset_switch);
1725
1726         if (!sdev->state)
1727                 return sprintf(buf, "offline\n");
1728
1729         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1730 }
1731 #endif
1732
1733 static int tegra_dc_probe(struct nvhost_device *ndev,
1734         struct nvhost_device_id *id_table)
1735 {
1736         struct tegra_dc *dc;
1737         struct tegra_dc_mode *mode;
1738         struct clk *clk;
1739         struct clk *emc_clk;
1740         struct resource *res;
1741         struct resource *base_res;
1742         struct resource *fb_mem = NULL;
1743         int ret = 0;
1744         void __iomem *base;
1745         int irq;
1746         int i;
1747
1748         if (!ndev->dev.platform_data) {
1749                 dev_err(&ndev->dev, "no platform data\n");
1750                 return -ENOENT;
1751         }
1752
1753         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1754         if (!dc) {
1755                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1756                 return -ENOMEM;
1757         }
1758
1759         irq = nvhost_get_irq_byname(ndev, "irq");
1760         if (irq <= 0) {
1761                 dev_err(&ndev->dev, "no irq\n");
1762                 ret = -ENOENT;
1763                 goto err_free;
1764         }
1765
1766         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1767         if (!res) {
1768                 dev_err(&ndev->dev, "no mem resource\n");
1769                 ret = -ENOENT;
1770                 goto err_free;
1771         }
1772
1773         base_res = request_mem_region(res->start, resource_size(res),
1774                 ndev->name);
1775         if (!base_res) {
1776                 dev_err(&ndev->dev, "request_mem_region failed\n");
1777                 ret = -EBUSY;
1778                 goto err_free;
1779         }
1780
1781         base = ioremap(res->start, resource_size(res));
1782         if (!base) {
1783                 dev_err(&ndev->dev, "registers can't be mapped\n");
1784                 ret = -EBUSY;
1785                 goto err_release_resource_reg;
1786         }
1787
1788         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1789
1790         clk = clk_get(&ndev->dev, NULL);
1791         if (IS_ERR_OR_NULL(clk)) {
1792                 dev_err(&ndev->dev, "can't get clock\n");
1793                 ret = -ENOENT;
1794                 goto err_iounmap_reg;
1795         }
1796
1797         emc_clk = clk_get(&ndev->dev, "emc");
1798         if (IS_ERR_OR_NULL(emc_clk)) {
1799                 dev_err(&ndev->dev, "can't get emc clock\n");
1800                 ret = -ENOENT;
1801                 goto err_put_clk;
1802         }
1803
1804         dc->clk = clk;
1805         dc->emc_clk = emc_clk;
1806         dc->shift_clk_div = 1;
1807         /* Initialize one shot work delay, it will be assigned by dsi
1808          * according to refresh rate later. */
1809         dc->one_shot_delay_ms = 40;
1810
1811         dc->base_res = base_res;
1812         dc->base = base;
1813         dc->irq = irq;
1814         dc->ndev = ndev;
1815         dc->pdata = ndev->dev.platform_data;
1816
1817         /*
1818          * The emc is a shared clock, it will be set based on
1819          * the requirements for each user on the bus.
1820          */
1821         dc->emc_clk_rate = 0;
1822
1823         mutex_init(&dc->lock);
1824         mutex_init(&dc->one_shot_lock);
1825         init_completion(&dc->frame_end_complete);
1826         init_waitqueue_head(&dc->wq);
1827         init_waitqueue_head(&dc->timestamp_wq);
1828 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1829         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1830 #endif
1831         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1832         dc->vblank_ref_count = 0;
1833         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
1834         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
1835
1836         tegra_dc_init_lut_defaults(&dc->fb_lut);
1837
1838         dc->n_windows = DC_N_WINDOWS;
1839         for (i = 0; i < dc->n_windows; i++) {
1840                 struct tegra_dc_win *win = &dc->windows[i];
1841                 win->idx = i;
1842                 win->dc = dc;
1843                 tegra_dc_init_csc_defaults(&win->csc);
1844                 tegra_dc_init_lut_defaults(&win->lut);
1845         }
1846
1847         ret = tegra_dc_set(dc, ndev->id);
1848         if (ret < 0) {
1849                 dev_err(&ndev->dev, "can't add dc\n");
1850                 goto err_free_irq;
1851         }
1852
1853         nvhost_set_drvdata(ndev, dc);
1854
1855 #ifdef CONFIG_SWITCH
1856         dc->modeset_switch.name = dev_name(&ndev->dev);
1857         dc->modeset_switch.state = 0;
1858         dc->modeset_switch.print_state = switch_modeset_print_mode;
1859         switch_dev_register(&dc->modeset_switch);
1860 #endif
1861
1862         tegra_dc_feature_register(dc);
1863
1864         if (dc->pdata->default_out)
1865                 tegra_dc_set_out(dc, dc->pdata->default_out);
1866         else
1867                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1868
1869         dc->vblank_syncpt = (dc->ndev->id == 0) ?
1870                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
1871
1872         dc->ext = tegra_dc_ext_register(ndev, dc);
1873         if (IS_ERR_OR_NULL(dc->ext)) {
1874                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
1875                 dc->ext = NULL;
1876         }
1877
1878         mutex_lock(&dc->lock);
1879         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
1880                 _tegra_dc_set_default_videomode(dc);
1881                 dc->enabled = _tegra_dc_enable(dc);
1882         }
1883         mutex_unlock(&dc->lock);
1884
1885         /* interrupt handler must be registered before tegra_fb_register() */
1886         if (request_irq(irq, tegra_dc_irq, 0,
1887                         dev_name(&ndev->dev), dc)) {
1888                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1889                 ret = -EBUSY;
1890                 goto err_put_emc_clk;
1891         }
1892
1893         tegra_dc_create_debugfs(dc);
1894
1895         dev_info(&ndev->dev, "probed\n");
1896
1897         if (dc->pdata->fb) {
1898                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
1899                         unsigned long fmt;
1900                         tegra_dc_writel(dc,
1901                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1902                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1903
1904                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1905                         dc->pdata->fb->bits_per_pixel =
1906                                 tegra_dc_fmt_bpp(fmt);
1907                 }
1908
1909                 mode = tegra_dc_get_override_mode(dc);
1910                 if (mode) {
1911                         dc->pdata->fb->xres = mode->h_active;
1912                         dc->pdata->fb->yres = mode->v_active;
1913                 }
1914
1915                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1916                 if (IS_ERR_OR_NULL(dc->fb))
1917                         dc->fb = NULL;
1918         }
1919
1920         if (dc->out && dc->out->hotplug_init)
1921                 dc->out->hotplug_init();
1922
1923         if (dc->out_ops && dc->out_ops->detect)
1924                 dc->out_ops->detect(dc);
1925         else
1926                 dc->connected = true;
1927
1928         tegra_dc_create_sysfs(&dc->ndev->dev);
1929
1930         return 0;
1931
1932 err_free_irq:
1933         free_irq(irq, dc);
1934 err_put_emc_clk:
1935         clk_put(emc_clk);
1936 err_put_clk:
1937         clk_put(clk);
1938 err_iounmap_reg:
1939         iounmap(base);
1940         if (fb_mem)
1941                 release_resource(fb_mem);
1942 err_release_resource_reg:
1943         release_resource(base_res);
1944 err_free:
1945         kfree(dc);
1946
1947         return ret;
1948 }
1949
1950 static int tegra_dc_remove(struct nvhost_device *ndev)
1951 {
1952         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1953
1954         tegra_dc_remove_sysfs(&dc->ndev->dev);
1955         tegra_dc_remove_debugfs(dc);
1956
1957         if (dc->fb) {
1958                 tegra_fb_unregister(dc->fb);
1959                 if (dc->fb_mem)
1960                         release_resource(dc->fb_mem);
1961         }
1962
1963         tegra_dc_ext_disable(dc->ext);
1964
1965         if (dc->ext)
1966                 tegra_dc_ext_unregister(dc->ext);
1967
1968         if (dc->enabled)
1969                 _tegra_dc_disable(dc);
1970
1971 #ifdef CONFIG_SWITCH
1972         switch_dev_unregister(&dc->modeset_switch);
1973 #endif
1974         free_irq(dc->irq, dc);
1975         clk_put(dc->emc_clk);
1976         clk_put(dc->clk);
1977         iounmap(dc->base);
1978         if (dc->fb_mem)
1979                 release_resource(dc->base_res);
1980         kfree(dc);
1981         tegra_dc_set(NULL, ndev->id);
1982         return 0;
1983 }
1984
1985 #ifdef CONFIG_PM
1986 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
1987 {
1988         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1989
1990         trace_printk("%s:suspend\n", dc->ndev->name);
1991         dev_info(&ndev->dev, "suspend\n");
1992
1993         tegra_dc_ext_disable(dc->ext);
1994
1995         mutex_lock(&dc->lock);
1996
1997         if (dc->out_ops && dc->out_ops->suspend)
1998                 dc->out_ops->suspend(dc);
1999
2000         if (dc->enabled) {
2001                 _tegra_dc_disable(dc);
2002
2003                 dc->suspended = true;
2004         }
2005
2006         if (dc->out && dc->out->postsuspend) {
2007                 dc->out->postsuspend();
2008                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2009                         /*
2010                          * avoid resume event due to voltage falling
2011                          */
2012                         msleep(100);
2013         }
2014
2015         mutex_unlock(&dc->lock);
2016
2017         return 0;
2018 }
2019
2020 static int tegra_dc_resume(struct nvhost_device *ndev)
2021 {
2022         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2023
2024         trace_printk("%s:resume\n", dc->ndev->name);
2025         dev_info(&ndev->dev, "resume\n");
2026
2027         mutex_lock(&dc->lock);
2028         dc->suspended = false;
2029
2030         if (dc->enabled) {
2031                 _tegra_dc_set_default_videomode(dc);
2032                 _tegra_dc_enable(dc);
2033         }
2034
2035         if (dc->out && dc->out->hotplug_init)
2036                 dc->out->hotplug_init();
2037
2038         if (dc->out_ops && dc->out_ops->resume)
2039                 dc->out_ops->resume(dc);
2040         mutex_unlock(&dc->lock);
2041
2042         return 0;
2043 }
2044
2045 #endif /* CONFIG_PM */
2046
2047 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2048 {
2049         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2050
2051         if (!dc || !dc->enabled)
2052                 return;
2053
2054         tegra_dc_blank(dc);
2055         tegra_dc_disable(dc);
2056 }
2057
2058 extern int suspend_set(const char *val, struct kernel_param *kp)
2059 {
2060         if (!strcmp(val, "dump"))
2061                 dump_regs(tegra_dcs[0]);
2062 #ifdef CONFIG_PM
2063         else if (!strcmp(val, "suspend"))
2064                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2065         else if (!strcmp(val, "resume"))
2066                 tegra_dc_resume(tegra_dcs[0]->ndev);
2067 #endif
2068
2069         return 0;
2070 }
2071
2072 extern int suspend_get(char *buffer, struct kernel_param *kp)
2073 {
2074         return 0;
2075 }
2076
2077 int suspend;
2078
2079 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2080
2081 struct nvhost_driver tegra_dc_driver = {
2082         .driver = {
2083                 .name = "tegradc",
2084                 .owner = THIS_MODULE,
2085         },
2086         .probe = tegra_dc_probe,
2087         .remove = tegra_dc_remove,
2088 #ifdef CONFIG_PM
2089         .suspend = tegra_dc_suspend,
2090         .resume = tegra_dc_resume,
2091 #endif
2092         .shutdown = tegra_dc_shutdown,
2093 };
2094
2095 #ifndef MODULE
2096 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2097 {
2098         int i, params[11];
2099         char *p;
2100
2101         for (i = 0; i < ARRAY_SIZE(params); i++) {
2102                 if ((p = strsep(&options, ",")) != NULL) {
2103                         if (*p)
2104                                 params[i] = simple_strtoul(p, &p, 10);
2105                 } else
2106                         return -EINVAL;
2107         }
2108
2109         if ((mode->pclk = params[0]) == 0)
2110                 return -EINVAL;
2111
2112         mode->h_active      = params[1];
2113         mode->v_active      = params[2];
2114         mode->h_ref_to_sync = params[3];
2115         mode->v_ref_to_sync = params[4];
2116         mode->h_sync_width  = params[5];
2117         mode->v_sync_width  = params[6];
2118         mode->h_back_porch  = params[7];
2119         mode->v_back_porch  = params[8];
2120         mode->h_front_porch = params[9];
2121         mode->v_front_porch = params[10];
2122
2123         return 0;
2124 }
2125
2126 static int __init tegra_dc_mode_override(char *str)
2127 {
2128         char *p = str, *options;
2129
2130         if (!p || !*p)
2131                 return -EINVAL;
2132
2133         p = strstr(str, "hdmi:");
2134         if (p) {
2135                 p += 5;
2136                 options = strsep(&p, ";");
2137                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2138                         return -EINVAL;
2139         }
2140
2141         p = strstr(str, "rgb:");
2142         if (p) {
2143                 p += 4;
2144                 options = strsep(&p, ";");
2145                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2146                         return -EINVAL;
2147         }
2148
2149         p = strstr(str, "dsi:");
2150         if (p) {
2151                 p += 4;
2152                 options = strsep(&p, ";");
2153                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2154                         return -EINVAL;
2155         }
2156
2157         return 0;
2158 }
2159
2160 __setup("disp_params=", tegra_dc_mode_override);
2161 #endif
2162
2163 static int __init tegra_dc_module_init(void)
2164 {
2165         int ret = tegra_dc_ext_module_init();
2166         if (ret)
2167                 return ret;
2168         return nvhost_driver_register(&tegra_dc_driver);
2169 }
2170
2171 static void __exit tegra_dc_module_exit(void)
2172 {
2173         nvhost_driver_unregister(&tegra_dc_driver);
2174         tegra_dc_ext_module_exit();
2175 }
2176
2177 module_exit(tegra_dc_module_exit);
2178 module_init(tegra_dc_module_init);