c268b9c306a8b19ca2b5cff3258b5aceb37fa71d
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38
39 #include <mach/clk.h>
40 #include <mach/dc.h>
41 #include <mach/fb.h>
42 #include <mach/mc.h>
43 #include <linux/nvhost.h>
44 #include <mach/latency_allowance.h>
45
46 #include "dc_reg.h"
47 #include "dc_priv.h"
48 #include "overlay.h"
49 #include "nvsd.h"
50
51 #define TEGRA_CRC_LATCHED_DELAY         34
52
53 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
54 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
55 #else
56 /* ignore underflows when on simulation and fpga platform */
57 #define ALL_UF_INT (0)
58 #endif
59
60 static int no_vsync;
61
62 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
63
64 static int use_dynamic_emc = 1;
65
66 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
67
68 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
69
70 DEFINE_MUTEX(tegra_dc_lock);
71 DEFINE_MUTEX(shared_lock);
72
73 static const struct {
74         bool h;
75         bool v;
76 } can_filter[] = {
77         /* Window A has no filtering */
78         { false, false },
79         /* Window B has both H and V filtering */
80         { true,  true  },
81         /* Window C has only H filtering */
82         { false, true  },
83 };
84 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
85 {
86         return can_filter[win->idx].v &&
87                 win->h.full != dfixed_const(win->out_h);
88 }
89 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
90 {
91         return can_filter[win->idx].h &&
92                 win->w.full != dfixed_const(win->out_w);
93 }
94
95 static inline int tegra_dc_fmt_bpp(int fmt)
96 {
97         switch (fmt) {
98         case TEGRA_WIN_FMT_P1:
99                 return 1;
100
101         case TEGRA_WIN_FMT_P2:
102                 return 2;
103
104         case TEGRA_WIN_FMT_P4:
105                 return 4;
106
107         case TEGRA_WIN_FMT_P8:
108                 return 8;
109
110         case TEGRA_WIN_FMT_B4G4R4A4:
111         case TEGRA_WIN_FMT_B5G5R5A:
112         case TEGRA_WIN_FMT_B5G6R5:
113         case TEGRA_WIN_FMT_AB5G5R5:
114                 return 16;
115
116         case TEGRA_WIN_FMT_B8G8R8A8:
117         case TEGRA_WIN_FMT_R8G8B8A8:
118         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
119         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
120                 return 32;
121
122         /* for planar formats, size of the Y plane, 8bit */
123         case TEGRA_WIN_FMT_YCbCr420P:
124         case TEGRA_WIN_FMT_YUV420P:
125         case TEGRA_WIN_FMT_YCbCr422P:
126         case TEGRA_WIN_FMT_YUV422P:
127                 return 8;
128
129         case TEGRA_WIN_FMT_YCbCr422:
130         case TEGRA_WIN_FMT_YUV422:
131         case TEGRA_WIN_FMT_YCbCr422R:
132         case TEGRA_WIN_FMT_YUV422R:
133         case TEGRA_WIN_FMT_YCbCr422RA:
134         case TEGRA_WIN_FMT_YUV422RA:
135                 /* FIXME: need to know the bpp of these formats */
136                 return 0;
137         }
138         return 0;
139 }
140
141 static inline bool tegra_dc_is_yuv_planar(int fmt)
142 {
143         switch (fmt) {
144         case TEGRA_WIN_FMT_YUV420P:
145         case TEGRA_WIN_FMT_YCbCr420P:
146         case TEGRA_WIN_FMT_YCbCr422P:
147         case TEGRA_WIN_FMT_YUV422P:
148                 return true;
149         }
150         return false;
151 }
152
153 #define DUMP_REG(a) do {                        \
154         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
155                  #a, a, tegra_dc_readl(dc, a));               \
156         print(data, buff);                                    \
157         } while (0)
158
159 static void _dump_regs(struct tegra_dc *dc, void *data,
160                        void (* print)(void *data, const char *str))
161 {
162         int i;
163         char buff[256];
164
165         tegra_dc_io_start(dc);
166         clk_enable(dc->clk);
167
168         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
169         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
170         DUMP_REG(DC_CMD_SIGNAL_RAISE);
171         DUMP_REG(DC_CMD_INT_STATUS);
172         DUMP_REG(DC_CMD_INT_MASK);
173         DUMP_REG(DC_CMD_INT_ENABLE);
174         DUMP_REG(DC_CMD_INT_TYPE);
175         DUMP_REG(DC_CMD_INT_POLARITY);
176         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
177         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
178         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
179         DUMP_REG(DC_CMD_STATE_ACCESS);
180         DUMP_REG(DC_CMD_STATE_CONTROL);
181         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
182         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
183
184         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
185         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
186         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
187         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
188         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
189         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
190         DUMP_REG(DC_DISP_REF_TO_SYNC);
191         DUMP_REG(DC_DISP_SYNC_WIDTH);
192         DUMP_REG(DC_DISP_BACK_PORCH);
193         DUMP_REG(DC_DISP_DISP_ACTIVE);
194         DUMP_REG(DC_DISP_FRONT_PORCH);
195         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
196         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
197         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
198         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
199         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
200         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
201         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
202         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
203         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
204         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
205         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
206         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
207         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
208         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
209         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
210         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
211         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
212         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
213         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
214         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
215         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
216         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
217         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
218         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
219         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
220         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
221         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
222         DUMP_REG(DC_DISP_M0_CONTROL);
223         DUMP_REG(DC_DISP_M1_CONTROL);
224         DUMP_REG(DC_DISP_DI_CONTROL);
225         DUMP_REG(DC_DISP_PP_CONTROL);
226         DUMP_REG(DC_DISP_PP_SELECT_A);
227         DUMP_REG(DC_DISP_PP_SELECT_B);
228         DUMP_REG(DC_DISP_PP_SELECT_C);
229         DUMP_REG(DC_DISP_PP_SELECT_D);
230         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
231         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
232         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
233         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
234         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
235         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
236         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
237         DUMP_REG(DC_DISP_BORDER_COLOR);
238         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
239         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
240         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
241         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
242         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
243         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
244         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
245         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
246         DUMP_REG(DC_DISP_CURSOR_POSITION);
247         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
248         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
249         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
250         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
251         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
252         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
253         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
254         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
255         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
256         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
257         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
258         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
259         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
260
261
262         for (i = 0; i < 3; i++) {
263                 print(data, "\n");
264                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
265                 print(data, buff);
266
267                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
268                                 DC_CMD_DISPLAY_WINDOW_HEADER);
269                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
270                 DUMP_REG(DC_WIN_WIN_OPTIONS);
271                 DUMP_REG(DC_WIN_BYTE_SWAP);
272                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
273                 DUMP_REG(DC_WIN_COLOR_DEPTH);
274                 DUMP_REG(DC_WIN_POSITION);
275                 DUMP_REG(DC_WIN_SIZE);
276                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
277                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
278                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
279                 DUMP_REG(DC_WIN_DDA_INCREMENT);
280                 DUMP_REG(DC_WIN_LINE_STRIDE);
281                 DUMP_REG(DC_WIN_BUF_STRIDE);
282                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
283                 DUMP_REG(DC_WIN_BLEND_NOKEY);
284                 DUMP_REG(DC_WIN_BLEND_1WIN);
285                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
286                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
287                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
288                 DUMP_REG(DC_WINBUF_START_ADDR);
289                 DUMP_REG(DC_WINBUF_START_ADDR_U);
290                 DUMP_REG(DC_WINBUF_START_ADDR_V);
291                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
292                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
293                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
294                 DUMP_REG(DC_WIN_CSC_YOF);
295                 DUMP_REG(DC_WIN_CSC_KYRGB);
296                 DUMP_REG(DC_WIN_CSC_KUR);
297                 DUMP_REG(DC_WIN_CSC_KVR);
298                 DUMP_REG(DC_WIN_CSC_KUG);
299                 DUMP_REG(DC_WIN_CSC_KVG);
300                 DUMP_REG(DC_WIN_CSC_KUB);
301                 DUMP_REG(DC_WIN_CSC_KVB);
302         }
303
304         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
305         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
306         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
307         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
308         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
309         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
310         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
311         DUMP_REG(DC_DISP_M1_CONTROL);
312         DUMP_REG(DC_COM_PM1_CONTROL);
313         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
314         DUMP_REG(DC_DISP_SD_CONTROL);
315
316         clk_disable(dc->clk);
317         tegra_dc_io_end(dc);
318 }
319
320 #undef DUMP_REG
321
322 #ifdef DEBUG
323 static void dump_regs_print(void *data, const char *str)
324 {
325         struct tegra_dc *dc = data;
326         dev_dbg(&dc->ndev->dev, "%s", str);
327 }
328
329 static void dump_regs(struct tegra_dc *dc)
330 {
331         _dump_regs(dc, dc, dump_regs_print);
332 }
333 #else /* !DEBUG */
334
335 static void dump_regs(struct tegra_dc *dc) {}
336
337 #endif /* DEBUG */
338
339 #ifdef CONFIG_DEBUG_FS
340
341 static void dbg_regs_print(void *data, const char *str)
342 {
343         struct seq_file *s = data;
344
345         seq_printf(s, "%s", str);
346 }
347
348 #undef DUMP_REG
349
350 static int dbg_dc_show(struct seq_file *s, void *unused)
351 {
352         struct tegra_dc *dc = s->private;
353
354         _dump_regs(dc, s, dbg_regs_print);
355
356         return 0;
357 }
358
359
360 static int dbg_dc_open(struct inode *inode, struct file *file)
361 {
362         return single_open(file, dbg_dc_show, inode->i_private);
363 }
364
365 static const struct file_operations regs_fops = {
366         .open           = dbg_dc_open,
367         .read           = seq_read,
368         .llseek         = seq_lseek,
369         .release        = single_release,
370 };
371
372 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
373 {
374         struct tegra_dc *dc = s->private;
375         struct tegra_dc_mode *m;
376
377         mutex_lock(&dc->lock);
378         m = &dc->mode;
379         seq_printf(s,
380                 "pclk: %d\n"
381                 "h_ref_to_sync: %d\n"
382                 "v_ref_to_sync: %d\n"
383                 "h_sync_width: %d\n"
384                 "v_sync_width: %d\n"
385                 "h_back_porch: %d\n"
386                 "v_back_porch: %d\n"
387                 "h_active: %d\n"
388                 "v_active: %d\n"
389                 "h_front_porch: %d\n"
390                 "v_front_porch: %d\n"
391                 "stereo_mode: %d\n",
392                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
393                 m->h_sync_width, m->v_sync_width,
394                 m->h_back_porch, m->v_back_porch,
395                 m->h_active, m->v_active,
396                 m->h_front_porch, m->v_front_porch,
397                 m->stereo_mode);
398         mutex_unlock(&dc->lock);
399         return 0;
400 }
401
402 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
403 {
404         return single_open(file, dbg_dc_mode_show, inode->i_private);
405 }
406
407 static const struct file_operations mode_fops = {
408         .open           = dbg_dc_mode_open,
409         .read           = seq_read,
410         .llseek         = seq_lseek,
411         .release        = single_release,
412 };
413
414 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
415 {
416         struct tegra_dc *dc = s->private;
417
418         mutex_lock(&dc->lock);
419         seq_printf(s,
420                 "underflows: %llu\n"
421                 "underflows_a: %llu\n"
422                 "underflows_b: %llu\n"
423                 "underflows_c: %llu\n",
424                 dc->stats.underflows,
425                 dc->stats.underflows_a,
426                 dc->stats.underflows_b,
427                 dc->stats.underflows_c);
428         mutex_unlock(&dc->lock);
429
430         return 0;
431 }
432
433 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
434 {
435         return single_open(file, dbg_dc_stats_show, inode->i_private);
436 }
437
438 static const struct file_operations stats_fops = {
439         .open           = dbg_dc_stats_open,
440         .read           = seq_read,
441         .llseek         = seq_lseek,
442         .release        = single_release,
443 };
444
445 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
446 {
447         if (dc->debugdir)
448                 debugfs_remove_recursive(dc->debugdir);
449         dc->debugdir = NULL;
450 }
451
452 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
453 {
454         struct dentry *retval;
455
456         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
457         if (!dc->debugdir)
458                 goto remove_out;
459
460         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
461                 &regs_fops);
462         if (!retval)
463                 goto remove_out;
464
465         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
466                 &mode_fops);
467         if (!retval)
468                 goto remove_out;
469
470         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
471                 &stats_fops);
472         if (!retval)
473                 goto remove_out;
474
475         return;
476 remove_out:
477         dev_err(&dc->ndev->dev, "could not create debugfs\n");
478         tegra_dc_remove_debugfs(dc);
479 }
480
481 #else /* !CONFIG_DEBUGFS */
482 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
483 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
484 #endif /* CONFIG_DEBUGFS */
485
486 static int tegra_dc_set(struct tegra_dc *dc, int index)
487 {
488         int ret = 0;
489
490         mutex_lock(&tegra_dc_lock);
491         if (index >= TEGRA_MAX_DC) {
492                 ret = -EINVAL;
493                 goto out;
494         }
495
496         if (dc != NULL && tegra_dcs[index] != NULL) {
497                 ret = -EBUSY;
498                 goto out;
499         }
500
501         tegra_dcs[index] = dc;
502
503 out:
504         mutex_unlock(&tegra_dc_lock);
505
506         return ret;
507 }
508
509 unsigned int tegra_dc_has_multiple_dc(void)
510 {
511         unsigned int idx;
512         unsigned int cnt = 0;
513         struct tegra_dc *dc;
514
515         mutex_lock(&tegra_dc_lock);
516         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
517                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
518         mutex_unlock(&tegra_dc_lock);
519
520         return (cnt > 1);
521 }
522
523 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
524 {
525         if (idx < TEGRA_MAX_DC)
526                 return tegra_dcs[idx];
527         else
528                 return NULL;
529 }
530 EXPORT_SYMBOL(tegra_dc_get_dc);
531
532 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
533 {
534         if (win >= dc->n_windows)
535                 return NULL;
536
537         return &dc->windows[win];
538 }
539 EXPORT_SYMBOL(tegra_dc_get_window);
540
541 static int get_topmost_window(u32 *depths, unsigned long *wins)
542 {
543         int idx, best = -1;
544
545         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
546                 if (best == -1 || depths[idx] < depths[best])
547                         best = idx;
548         }
549         clear_bit(best, wins);
550         return best;
551 }
552
553 bool tegra_dc_get_connected(struct tegra_dc *dc)
554 {
555         return dc->connected;
556 }
557 EXPORT_SYMBOL(tegra_dc_get_connected);
558
559 static u32 blend_topwin(u32 flags)
560 {
561         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
562                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
563         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
564                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
565         else
566                 return BLEND(NOKEY, FIX, 0xff, 0xff);
567 }
568
569 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
570 {
571         int other;
572
573         for (other = 0; other < DC_N_WINDOWS; other++) {
574                 if (other != idx && (xy-- == 0))
575                         break;
576         }
577         if (BIT(other) & behind_mask)
578                 return blend_topwin(flags[idx]);
579         else if (flags[other])
580                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
581         else
582                 return BLEND(NOKEY, FIX, 0x00, 0x00);
583 }
584
585 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
586 {
587         unsigned long infront_mask;
588         int first;
589
590         infront_mask = ~(behind_mask | BIT(idx));
591         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
592         first = ffs(infront_mask) - 1;
593
594         if (!infront_mask)
595                 return blend_topwin(flags[idx]);
596         else if (behind_mask && first != -1 && flags[first])
597                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
598         else
599                 return BLEND(NOKEY, FIX, 0x0, 0x0);
600 }
601
602 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
603 {
604         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
605
606         while (mask) {
607                 int idx = get_topmost_window(blend->z, &mask);
608
609                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
610                                 DC_CMD_DISPLAY_WINDOW_HEADER);
611                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
612                                 DC_WIN_BLEND_NOKEY);
613                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
614                                 DC_WIN_BLEND_1WIN);
615                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
616                                 DC_WIN_BLEND_2WIN_X);
617                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
618                                 DC_WIN_BLEND_2WIN_Y);
619                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
620                                 DC_WIN_BLEND_3WIN_XY);
621         }
622 }
623
624 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
625 {
626         csc->yof   = 0x00f0;
627         csc->kyrgb = 0x012a;
628         csc->kur   = 0x0000;
629         csc->kvr   = 0x0198;
630         csc->kug   = 0x039b;
631         csc->kvg   = 0x032f;
632         csc->kub   = 0x0204;
633         csc->kvb   = 0x0000;
634 }
635
636 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
637 {
638         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
639         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
640         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
641         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
642         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
643         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
644         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
645         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
646 }
647
648 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
649 {
650         mutex_lock(&dc->lock);
651
652         if (!dc->enabled) {
653                 mutex_unlock(&dc->lock);
654                 return -EFAULT;
655         }
656
657         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
658                         DC_CMD_DISPLAY_WINDOW_HEADER);
659
660         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
661
662         mutex_unlock(&dc->lock);
663
664         return 0;
665 }
666 EXPORT_SYMBOL(tegra_dc_update_csc);
667
668 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
669 {
670         int i;
671         for (i = 0; i < 256; i++)
672                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
673 }
674
675 static int tegra_dc_loop_lut(struct tegra_dc *dc,
676                              struct tegra_dc_win *win,
677                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
678 {
679         struct tegra_dc_lut *lut = &win->lut;
680         struct tegra_dc_lut *global_lut = &dc->fb_lut;
681         int i;
682         for (i = 0; i < 256; i++) {
683
684                 u32 r = (u32)lut->r[i];
685                 u32 g = (u32)lut->g[i];
686                 u32 b = (u32)lut->b[i];
687
688                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
689                         r = (u32)global_lut->r[r];
690                         g = (u32)global_lut->g[g];
691                         b = (u32)global_lut->b[b];
692                 }
693
694                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
695                         return 0;
696         }
697         return 1;
698 }
699
700 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
701 {
702         if (rgb != (i | (i<<8) | (i<<16)))
703                 return 0;
704         return 1;
705 }
706
707 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
708 {
709         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
710         return 1;
711 }
712
713 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
714 {
715         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
716
717         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
718
719         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
720                 val |= CP_ENABLE;
721         else
722                 val &= ~CP_ENABLE;
723
724         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
725 }
726
727 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
728 {
729         struct tegra_dc_win *win = &dc->windows[win_idx];
730
731         mutex_lock(&dc->lock);
732
733         if (!dc->enabled) {
734                 mutex_unlock(&dc->lock);
735                 return -EFAULT;
736         }
737
738         if (fbovr > 0)
739                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
740         else if (fbovr == 0)
741                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
742
743         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
744                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
745         else
746                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
747
748         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
749                         DC_CMD_DISPLAY_WINDOW_HEADER);
750
751         tegra_dc_set_lut(dc, win);
752
753         mutex_unlock(&dc->lock);
754
755         return 0;
756 }
757
758 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
759 {
760         if (win_idx > -1)
761                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
762
763         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
764                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
765                 if (err)
766                         return err;
767         }
768
769         return 0;
770 }
771 EXPORT_SYMBOL(tegra_dc_update_lut);
772
773 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
774 {
775         unsigned i;
776         unsigned v0 = 128;
777         unsigned v1 = 0;
778         /* linear horizontal and vertical filters */
779         for (i = 0; i < 16; i++) {
780                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
781                                 DC_WIN_H_FILTER_P(i));
782
783                 tegra_dc_writel(dc, v0,
784                                 DC_WIN_V_FILTER_P(i));
785                 v0 -= 8;
786                 v1 += 8;
787         }
788 }
789
790 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
791         struct tegra_dc_win *w)
792 {
793         /* windows A, B, C for first and second display */
794         static const enum tegra_la_id la_id_tab[2][3] = {
795                 /* first display */
796                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
797                         TEGRA_LA_DISPLAY_0C },
798                 /* second display */
799                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
800                         TEGRA_LA_DISPLAY_0CB },
801         };
802         /* window B V-filter tap for first and second display. */
803         static const enum tegra_la_id vfilter_tab[2] = {
804                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
805         };
806         unsigned long bw;
807
808         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
809         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
810         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
811
812         bw = w->new_bandwidth;
813
814         /* tegra_dc_get_bandwidth() treats V filter windows as double
815          * bandwidth, but LA has a seperate client for V filter */
816         if (w->idx == 1 && win_use_v_filter(w))
817                 bw /= 2;
818
819         /* our bandwidth is in bytes/sec, but LA takes MBps.
820          * round up bandwidth to 1MBps */
821         bw = bw / 1000000 + 1;
822
823 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
824         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
825         /* if window B, also set the 1B client for the 2-tap V filter. */
826         if (w->idx == 1)
827                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
828 #endif
829
830         w->bandwidth = w->new_bandwidth;
831 }
832
833 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
834                                                    struct tegra_dc_win *b)
835 {
836         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
837                 return 0;
838
839         /* because memory access to load the fifo can overlap, only care
840          * if windows overlap vertically */
841         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
842                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
843 }
844
845 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
846                                                  int n)
847 {
848         unsigned i;
849         unsigned j;
850         unsigned overlap_count;
851         unsigned max_bw = 0;
852
853         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
854                          "inaccurate.\n");
855
856         /* If we had a large number of windows, we would compute adjacency
857          * graph representing 2 window overlaps, find all cliques in the graph,
858          * assign bandwidth to each clique, and then select the clique with
859          * maximum bandwidth. But because we have at most 3 windows,
860          * implementing proper Bron-Kerbosh algorithm would be an overkill,
861          * brute force will suffice.
862          *
863          * Thus: find maximum bandwidth for either single or a pair of windows
864          * and count number of window pair overlaps. If there are three
865          * pairs, all 3 window overlap.
866          */
867
868         overlap_count = 0;
869         for (i = 0; i < n; i++) {
870                 unsigned int bw1;
871
872                 if (wins[i] == NULL)
873                         continue;
874                 bw1 = wins[i]->new_bandwidth;
875                 if (bw1 > max_bw)
876                         /* Single window */
877                         max_bw = bw1;
878
879                 for (j = i + 1; j < n; j++) {
880                         if (wins[j] == NULL)
881                                 continue;
882                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
883                                 unsigned int bw2 = wins[j]->new_bandwidth;
884                                 if (bw1 + bw2 > max_bw)
885                                         /* Window pair overlaps */
886                                         max_bw = bw1 + bw2;
887                                 overlap_count++;
888                         }
889                 }
890         }
891
892         if (overlap_count == 3)
893                 /* All three windows overlap */
894                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
895                          wins[2]->new_bandwidth;
896
897         return max_bw;
898 }
899
900 /*
901  * Calculate peak EMC bandwidth for each enabled window =
902  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
903  * (windows_tiling ? 2 : 1)
904  *
905  *
906  * note:
907  * (*) We use 2 tap V filter, so need double BW if use V filter
908  * (*) Tiling mode on T30 and DDR3 requires double BW
909  */
910 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
911         struct tegra_dc_win *w)
912 {
913         unsigned long ret;
914         int tiled_windows_bw_multiplier;
915         unsigned long bpp;
916
917         if (!WIN_IS_ENABLED(w))
918                 return 0;
919
920         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
921             w->out_w == 0 || w->out_h == 0)
922                 return 0;
923
924         tiled_windows_bw_multiplier =
925                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
926
927         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
928          * but the size reported by tegra_dc_fmt_bpp for the planar version
929          * is of the luma plane's size only. */
930         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
931                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
932         /* perform calculations with most significant bits of pixel clock
933          * to prevent overflow of long. */
934         ret = (unsigned long)(dc->pixel_clk >> 16) *
935                 bpp / 8 *
936                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
937                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
938
939 /*
940  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
941  * will request 147MBps from EMC.
942  */
943         ret = ret * 2 + ret / 10;
944
945         /* if overflowed */
946         if (ret > (1UL << 31))
947                 return ULONG_MAX;
948
949         return ret << 16; /* restore the scaling we did above */
950 }
951
952 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
953 {
954         int i;
955
956         BUG_ON(n > DC_N_WINDOWS);
957
958         /* emc rate and latency allowance both need to know per window
959          * bandwidths */
960         for (i = 0; i < n; i++) {
961                 struct tegra_dc_win *w = windows[i];
962                 if (w)
963                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
964         }
965
966         return tegra_dc_find_max_bandwidth(windows, n);
967 }
968
969 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
970 {
971         unsigned i;
972
973         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
974                 dc->emc_clk_rate = dc->new_emc_clk_rate;
975                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
976         }
977
978         for (i = 0; i < DC_N_WINDOWS; i++) {
979                 struct tegra_dc_win *w = &dc->windows[i];
980                 if (w->bandwidth != w->new_bandwidth)
981                         tegra_dc_set_latency_allowance(dc, w);
982         }
983 }
984
985 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
986 {
987         unsigned long new_rate;
988         struct tegra_dc *dc;
989
990         if (!use_dynamic_emc)
991                 return 0;
992
993         dc = windows[0]->dc;
994
995         /* calculate the new rate based on this POST */
996         new_rate = tegra_dc_get_bandwidth(windows, n);
997         new_rate = EMC_BW_TO_FREQ(new_rate);
998
999         if (tegra_dc_has_multiple_dc())
1000                 new_rate = ULONG_MAX;
1001
1002         dc->new_emc_clk_rate = new_rate;
1003
1004         return 0;
1005 }
1006
1007 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1008                                   bool v, unsigned Bpp)
1009 {
1010         /*
1011          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1012          *           (post_scaled_size_in_pixels - 1)), MAX)
1013          * Where the value of MAX is as follows:
1014          * For V_DDA_INCREMENT: 15.0 (0xF000)
1015          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1016          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1017          */
1018
1019         fixed20_12 out = dfixed_init(out_int);
1020         u32 dda_inc;
1021         int max;
1022
1023         if (v) {
1024                 max = 15;
1025         } else {
1026                 switch (Bpp) {
1027                 default:
1028                         WARN_ON_ONCE(1);
1029                         /* fallthrough */
1030                 case 4:
1031                         max = 4;
1032                         break;
1033                 case 2:
1034                         max = 8;
1035                         break;
1036                 }
1037         }
1038
1039         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1040         in.full -= dfixed_const(1);
1041
1042         dda_inc = dfixed_div(in, out);
1043
1044         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1045
1046         return dda_inc;
1047 }
1048
1049 static inline u32 compute_initial_dda(fixed20_12 in)
1050 {
1051         return dfixed_frac(in);
1052 }
1053
1054 /* does not support updating windows on multiple dcs in one call */
1055 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1056 {
1057         struct tegra_dc *dc;
1058         unsigned long update_mask = GENERAL_ACT_REQ;
1059         unsigned long val;
1060         bool update_blend = false;
1061         int i;
1062
1063         dc = windows[0]->dc;
1064
1065         mutex_lock(&dc->lock);
1066
1067         if (!dc->enabled) {
1068                 mutex_unlock(&dc->lock);
1069                 return -EFAULT;
1070         }
1071
1072         if (no_vsync)
1073                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1074         else
1075                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1076
1077         for (i = 0; i < n; i++) {
1078                 struct tegra_dc_win *win = windows[i];
1079                 unsigned h_dda;
1080                 unsigned v_dda;
1081                 fixed20_12 h_offset, v_offset;
1082                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1083                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1084                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1085                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1086                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1087                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1088                 const bool filter_h = win_use_h_filter(win);
1089                 const bool filter_v = win_use_v_filter(win);
1090
1091                 if (win->z != dc->blend.z[win->idx]) {
1092                         dc->blend.z[win->idx] = win->z;
1093                         update_blend = true;
1094                 }
1095                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1096                         dc->blend.flags[win->idx]) {
1097                         dc->blend.flags[win->idx] =
1098                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1099                         update_blend = true;
1100                 }
1101
1102                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1103                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1104
1105                 if (!no_vsync)
1106                         update_mask |= WIN_A_ACT_REQ << win->idx;
1107
1108                 if (!WIN_IS_ENABLED(win)) {
1109                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1110                         continue;
1111                 }
1112
1113                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1114                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1115
1116                 tegra_dc_writel(dc,
1117                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1118                                 DC_WIN_POSITION);
1119                 tegra_dc_writel(dc,
1120                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1121                                 DC_WIN_SIZE);
1122                 tegra_dc_writel(dc,
1123                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1124                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1125                                 DC_WIN_PRESCALED_SIZE);
1126
1127                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1128                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1129                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1130                                 DC_WIN_DDA_INCREMENT);
1131                 h_dda = compute_initial_dda(win->x);
1132                 v_dda = compute_initial_dda(win->y);
1133                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1134                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1135
1136                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1137                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1138                 tegra_dc_writel(dc,
1139                                 (unsigned long)win->phys_addr,
1140                                 DC_WINBUF_START_ADDR);
1141
1142                 if (!yuvp) {
1143                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1144                 } else {
1145                         tegra_dc_writel(dc,
1146                                         (unsigned long)win->phys_addr_u,
1147                                         DC_WINBUF_START_ADDR_U);
1148                         tegra_dc_writel(dc,
1149                                         (unsigned long)win->phys_addr_v,
1150                                         DC_WINBUF_START_ADDR_V);
1151                         tegra_dc_writel(dc,
1152                                         LINE_STRIDE(win->stride) |
1153                                         UV_LINE_STRIDE(win->stride_uv),
1154                                         DC_WIN_LINE_STRIDE);
1155                 }
1156
1157                 h_offset = win->x;
1158                 if (invert_h) {
1159                         h_offset.full += win->w.full - dfixed_const(1);
1160                 }
1161
1162                 v_offset = win->y;
1163                 if (invert_v) {
1164                         v_offset.full += win->h.full - dfixed_const(1);
1165                 }
1166
1167                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1168                                 DC_WINBUF_ADDR_H_OFFSET);
1169                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1170                                 DC_WINBUF_ADDR_V_OFFSET);
1171
1172                 if (WIN_IS_TILED(win))
1173                         tegra_dc_writel(dc,
1174                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1175                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1176                                         DC_WIN_BUFFER_ADDR_MODE);
1177                 else
1178                         tegra_dc_writel(dc,
1179                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1180                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1181                                         DC_WIN_BUFFER_ADDR_MODE);
1182
1183                 val = WIN_ENABLE;
1184                 if (yuvp)
1185                         val |= CSC_ENABLE;
1186                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1187                         val |= COLOR_EXPAND;
1188
1189                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1190                         val |= CP_ENABLE;
1191
1192                 if (filter_h)
1193                         val |= H_FILTER_ENABLE;
1194                 if (filter_v)
1195                         val |= V_FILTER_ENABLE;
1196
1197                 if (invert_h)
1198                         val |= H_DIRECTION_DECREMENT;
1199                 if (invert_v)
1200                         val |= V_DIRECTION_DECREMENT;
1201
1202                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1203
1204                 win->dirty = no_vsync ? 0 : 1;
1205
1206                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1207                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1208                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1209                         __func__, win->idx, win->z,
1210                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1211                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1212                         win->out_x, win->out_y, win->out_w, win->out_h,
1213                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1214         }
1215
1216         if (update_blend) {
1217                 tegra_dc_set_blending(dc, &dc->blend);
1218                 for (i = 0; i < DC_N_WINDOWS; i++) {
1219                         if (!no_vsync)
1220                                 dc->windows[i].dirty = 1;
1221                         update_mask |= WIN_A_ACT_REQ << i;
1222                 }
1223         }
1224
1225         tegra_dc_set_dynamic_emc(windows, n);
1226
1227         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1228
1229         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1230         if (!no_vsync) {
1231                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1232                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1233                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1234         } else {
1235                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1236                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1237                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1238         }
1239
1240         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1241
1242         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1243                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1244
1245         mutex_unlock(&dc->lock);
1246
1247         return 0;
1248 }
1249 EXPORT_SYMBOL(tegra_dc_update_windows);
1250
1251 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1252 {
1253         return dc->syncpt[i].id;
1254 }
1255 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1256
1257 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1258 {
1259         u32 max;
1260
1261         mutex_lock(&dc->lock);
1262         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1263                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1264         dc->syncpt[i].max = max;
1265         mutex_unlock(&dc->lock);
1266
1267         return max;
1268 }
1269
1270 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1271 {
1272         mutex_lock(&dc->lock);
1273         if ( dc->enabled )
1274                 while (dc->syncpt[i].min < val) {
1275                         dc->syncpt[i].min++;
1276                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1277                                         dc->syncpt[i].id);
1278                 }
1279         mutex_unlock(&dc->lock);
1280 }
1281
1282 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1283                                              int n)
1284 {
1285         int i;
1286
1287         for (i = 0; i < n; i++) {
1288                 if (windows[i]->dirty)
1289                         return false;
1290         }
1291
1292         return true;
1293 }
1294
1295 /* does not support syncing windows on multiple dcs in one call */
1296 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1297 {
1298         if (n < 1 || n > DC_N_WINDOWS)
1299                 return -EINVAL;
1300
1301         if (!windows[0]->dc->enabled)
1302                 return -EFAULT;
1303
1304 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1305         /* Don't want to timeout on simulator */
1306         return wait_event_interruptible(windows[0]->dc->wq,
1307                 tegra_dc_windows_are_clean(windows, n));
1308 #else
1309         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1310                                          tegra_dc_windows_are_clean(windows, n),
1311                                          HZ);
1312 #endif
1313 }
1314 EXPORT_SYMBOL(tegra_dc_sync_windows);
1315
1316 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1317 {
1318 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1319         return clk_get_rate(dc->clk);
1320 #else
1321         return 27000000;
1322 #endif
1323 }
1324
1325 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1326 {
1327         unsigned long rate;
1328         unsigned long div;
1329
1330         rate = tegra_dc_clk_get_rate(dc);
1331
1332         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1333
1334         if (div < 2)
1335                 return 0;
1336
1337         return rate * 2 / div;
1338 }
1339
1340 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1341 {
1342         int pclk;
1343
1344         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1345                 unsigned long rate;
1346                 struct clk *parent_clk =
1347                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1348
1349                 if (clk_get_parent(clk) != parent_clk)
1350                         clk_set_parent(clk, parent_clk);
1351
1352                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1353                         struct clk *base_clk = clk_get_parent(parent_clk);
1354
1355                         /* Assuming either pll_d or pll_d2 is used */
1356                         rate = dc->mode.pclk * 2;
1357
1358                         if (rate != clk_get_rate(base_clk))
1359                                 clk_set_rate(base_clk, rate);
1360                 }
1361         }
1362
1363         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1364                 unsigned long rate;
1365                 struct clk *parent_clk =
1366                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1367                 struct clk *base_clk = clk_get_parent(parent_clk);
1368
1369                 /* needs to match tegra_dc_hdmi_supported_modes[]
1370                 and tegra_pll_d_freq_table[] */
1371                 if (dc->mode.pclk > 70000000)
1372                         rate = 594000000;
1373                 else if (dc->mode.pclk > 25200000)
1374                         rate = 216000000;
1375                 else
1376                         rate = 504000000;
1377
1378                 if (rate != clk_get_rate(base_clk))
1379                         clk_set_rate(base_clk, rate);
1380
1381                 if (clk_get_parent(clk) != parent_clk)
1382                         clk_set_parent(clk, parent_clk);
1383         }
1384
1385         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1386                 unsigned long rate;
1387                 struct clk *parent_clk;
1388                 struct clk *base_clk;
1389
1390                 if (clk == dc->clk) {
1391                         parent_clk = clk_get_sys(NULL,
1392                                         dc->out->parent_clk ? : "pll_d_out0");
1393                         base_clk = clk_get_parent(parent_clk);
1394                         tegra_clk_cfg_ex(base_clk,
1395                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1396                 } else {
1397                         if (dc->pdata->default_out->dsi->dsi_instance) {
1398                                 parent_clk = clk_get_sys(NULL,
1399                                         dc->out->parent_clk ? : "pll_d2_out0");
1400                                 base_clk = clk_get_parent(parent_clk);
1401                                 tegra_clk_cfg_ex(base_clk,
1402                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1403                         } else {
1404                                 parent_clk = clk_get_sys(NULL,
1405                                         dc->out->parent_clk ? : "pll_d_out0");
1406                                 base_clk = clk_get_parent(parent_clk);
1407                                 tegra_clk_cfg_ex(base_clk,
1408                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1409                         }
1410                 }
1411
1412                 rate = dc->mode.pclk;
1413                 if (rate != clk_get_rate(base_clk))
1414                         clk_set_rate(base_clk, rate);
1415
1416                 if (clk_get_parent(clk) != parent_clk)
1417                         clk_set_parent(clk, parent_clk);
1418         }
1419
1420         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1421         tegra_dvfs_set_rate(clk, pclk);
1422 }
1423
1424 /* return non-zero if constraint is violated */
1425 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1426 {
1427         long a, b;
1428
1429         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1430         a = 0;
1431
1432         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1433         b = mode->h_front_porch - 1;
1434
1435         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1436         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1437                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1438         /* check Constraint 1 and 6 */
1439         if (a > b)
1440                 return 1;
1441
1442         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1443         if (mode->h_sync_width < 1)
1444                 return 4;
1445
1446         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1447         if (mode->h_active < 16)
1448                 return 7;
1449
1450         if (href) {
1451                 if (b > a && a % 2)
1452                         *href = a + 1; /* use smallest even value */
1453                 else
1454                         *href = a; /* even or only possible value */
1455         }
1456
1457         return 0;
1458 }
1459
1460 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1461 {
1462         long a;
1463         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1464
1465         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1466         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1467                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1468
1469         /* Constraint 6 */
1470         if (mode->v_front_porch < a + 1)
1471                 a = mode->v_front_porch - 1;
1472
1473         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1474         if (mode->v_sync_width < 1)
1475                 return 4;
1476
1477         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1478         if (mode->v_active < 16)
1479                 return 7;
1480
1481         if (vref)
1482                 *vref = a;
1483         return 0;
1484 }
1485
1486 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1487 {
1488         int ret;
1489         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1490         if (ret)
1491                 return ret;
1492         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1493         if (ret)
1494                 return ret;
1495
1496         return 0;
1497 }
1498
1499 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1500 {
1501         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1502         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1503                 return false;
1504
1505         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1506         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1507                 return false;
1508
1509         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1510          * (vertical blank). */
1511         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1512                 return false;
1513
1514         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1515         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1516                 return false;
1517
1518         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1519         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1520                 return false;
1521
1522         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1523          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1524         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1525                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1526                 return false;
1527
1528         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1529         if (mode->h_active < 16 || mode->v_active < 16)
1530                 return false;
1531
1532         return true;
1533 }
1534
1535 #ifdef DEBUG
1536 /* return in 1000ths of a Hertz */
1537 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1538 {
1539         long h_total, v_total, refresh;
1540         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1541                 m->h_sync_width;
1542         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1543                 m->v_sync_width;
1544         refresh = dc->pixel_clk / h_total;
1545         refresh *= 1000;
1546         refresh /= v_total;
1547         return refresh;
1548 }
1549
1550 static void print_mode(struct tegra_dc *dc,
1551                         const struct tegra_dc_mode *mode, const char *note)
1552 {
1553         if (mode) {
1554                 int refresh = calc_refresh(dc, mode);
1555                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1556                         note ? note : "",
1557                         mode->h_active, mode->v_active,
1558                         refresh / 1000, refresh % 1000,
1559                         mode->pclk);
1560         }
1561 }
1562 #else /* !DEBUG */
1563 static inline void print_mode(struct tegra_dc *dc,
1564                         const struct tegra_dc_mode *mode, const char *note) { }
1565 #endif /* DEBUG */
1566
1567 static inline void enable_dc_irq(unsigned int irq)
1568 {
1569 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1570         enable_irq(irq);
1571 #else
1572         /* Always disable DC interrupts on FPGA. */
1573         disable_irq(irq);
1574 #endif
1575 }
1576
1577 static inline void disable_dc_irq(unsigned int irq)
1578 {
1579         disable_irq(irq);
1580 }
1581
1582 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1583 {
1584         unsigned long val;
1585         unsigned long rate;
1586         unsigned long div;
1587         unsigned long pclk;
1588
1589         print_mode(dc, mode, __func__);
1590
1591         /* use default EMC rate when switching modes */
1592         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1593         tegra_dc_program_bandwidth(dc);
1594
1595         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1596         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1597                         DC_DISP_REF_TO_SYNC);
1598         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1599                         DC_DISP_SYNC_WIDTH);
1600         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1601                         DC_DISP_BACK_PORCH);
1602         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1603                         DC_DISP_DISP_ACTIVE);
1604         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1605                         DC_DISP_FRONT_PORCH);
1606
1607         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1608                         DC_DISP_DATA_ENABLE_OPTIONS);
1609
1610         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1611         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1612                 val |= PIN1_LVS_OUTPUT;
1613         else
1614                 val &= ~PIN1_LVS_OUTPUT;
1615
1616         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1617                 val |= PIN1_LHS_OUTPUT;
1618         else
1619                 val &= ~PIN1_LHS_OUTPUT;
1620         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1621
1622         /* TODO: MIPI/CRT/HDMI clock cals */
1623
1624         val = DISP_DATA_FORMAT_DF1P1C;
1625
1626         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1627                 val |= DISP_DATA_ALIGNMENT_MSB;
1628         else
1629                 val |= DISP_DATA_ALIGNMENT_LSB;
1630
1631         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1632                 val |= DISP_DATA_ORDER_RED_BLUE;
1633         else
1634                 val |= DISP_DATA_ORDER_BLUE_RED;
1635
1636         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1637
1638         rate = tegra_dc_clk_get_rate(dc);
1639
1640         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1641         if (pclk < (mode->pclk / 100 * 99) ||
1642             pclk > (mode->pclk / 100 * 109)) {
1643                 dev_err(&dc->ndev->dev,
1644                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1645                         rate, mode->pclk,
1646                         pclk, (mode->pclk / 100 * 99),
1647                         (mode->pclk / 100 * 109));
1648                 return -EINVAL;
1649         }
1650
1651         div = (rate * 2 / pclk) - 2;
1652
1653         tegra_dc_writel(dc, 0x00010001,
1654                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1655         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1656                         DC_DISP_DISP_CLOCK_CONTROL);
1657
1658         dc->pixel_clk = dc->mode.pclk;
1659
1660         return 0;
1661 }
1662
1663
1664 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1665 {
1666         memcpy(&dc->mode, mode, sizeof(dc->mode));
1667
1668         print_mode(dc, mode, __func__);
1669
1670         return 0;
1671 }
1672 EXPORT_SYMBOL(tegra_dc_set_mode);
1673
1674 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1675                 const struct fb_videomode *fbmode, bool stereo_mode)
1676 {
1677         struct tegra_dc_mode mode;
1678
1679         if (!fbmode->pixclock)
1680                 return -EINVAL;
1681
1682         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1683         mode.h_sync_width = fbmode->hsync_len;
1684         mode.v_sync_width = fbmode->vsync_len;
1685         mode.h_back_porch = fbmode->left_margin;
1686         mode.v_back_porch = fbmode->upper_margin;
1687         mode.h_active = fbmode->xres;
1688         mode.v_active = fbmode->yres;
1689         mode.h_front_porch = fbmode->right_margin;
1690         mode.v_front_porch = fbmode->lower_margin;
1691         mode.stereo_mode = stereo_mode;
1692         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1693                 /* HDMI controller requires h_ref=1, v_ref=1 */
1694                 mode.h_ref_to_sync = 1;
1695                 mode.v_ref_to_sync = 1;
1696         } else {
1697                 calc_ref_to_sync(&mode);
1698         }
1699         if (!check_ref_to_sync(&mode)) {
1700                 dev_err(&dc->ndev->dev,
1701                                 "Display timing doesn't meet restrictions.\n");
1702                 return -EINVAL;
1703         }
1704         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1705                 mode.h_active, mode.v_active, mode.pclk,
1706                 mode.h_ref_to_sync, mode.v_ref_to_sync
1707         );
1708
1709         if (mode.stereo_mode) {
1710                 mode.pclk *= 2;
1711                 /* total v_active = yres*2 + activespace */
1712                 mode.v_active = fbmode->yres*2 +
1713                                 fbmode->vsync_len +
1714                                 fbmode->upper_margin +
1715                                 fbmode->lower_margin;
1716         }
1717
1718         mode.flags = 0;
1719
1720         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1721                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1722
1723         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1724                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1725
1726         return tegra_dc_set_mode(dc, &mode);
1727 }
1728 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1729
1730 void
1731 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1732 {
1733         unsigned int ctrl;
1734         unsigned long out_sel;
1735         unsigned long cmd_state;
1736
1737         mutex_lock(&dc->lock);
1738         if (!dc->enabled) {
1739                 mutex_unlock(&dc->lock);
1740                 return;
1741         }
1742
1743         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1744                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1745                 cfg->clk_select);
1746
1747         /* The new value should be effected immediately */
1748         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1749         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1750
1751         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1752                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1753         else
1754                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1755
1756         switch (cfg->which_pwm) {
1757         case TEGRA_PWM_PM0:
1758                 /* Select the LM0 on PM0 */
1759                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1760                 out_sel &= ~(7 << 0);
1761                 out_sel |= (3 << 0);
1762                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1763                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1764                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1765                 break;
1766         case TEGRA_PWM_PM1:
1767                 /* Select the LM1 on PM1 */
1768                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1769                 out_sel &= ~(7 << 4);
1770                 out_sel |= (3 << 4);
1771                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1772                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1773                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1774                 break;
1775         default:
1776                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1777                 break;
1778         }
1779         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1780         mutex_unlock(&dc->lock);
1781 }
1782 EXPORT_SYMBOL(tegra_dc_config_pwm);
1783
1784 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1785                                 const struct tegra_dc_out_pin *pins,
1786                                 const unsigned int n_pins)
1787 {
1788         unsigned int i;
1789
1790         int name;
1791         int pol;
1792
1793         u32 pol1, pol3;
1794
1795         u32 set1, unset1;
1796         u32 set3, unset3;
1797
1798         set1 = set3 = unset1 = unset3 = 0;
1799
1800         for (i = 0; i < n_pins; i++) {
1801                 name = (pins + i)->name;
1802                 pol  = (pins + i)->pol;
1803
1804                 /* set polarity by name */
1805                 switch (name) {
1806                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1807                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1808                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1809                         else
1810                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1811                         break;
1812                 case TEGRA_DC_OUT_PIN_H_SYNC:
1813                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1814                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1815                         else
1816                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1817                         break;
1818                 case TEGRA_DC_OUT_PIN_V_SYNC:
1819                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1820                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1821                         else
1822                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1823                         break;
1824                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1825                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1826                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1827                         else
1828                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1829                         break;
1830                 default:
1831                         printk("Invalid argument in function %s\n",
1832                                __FUNCTION__);
1833                         break;
1834                 }
1835         }
1836
1837         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1838         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1839
1840         pol1 |= set1;
1841         pol1 &= ~unset1;
1842
1843         pol3 |= set3;
1844         pol3 &= ~unset3;
1845
1846         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1847         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1848 }
1849
1850 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1851 {
1852         dc->out = out;
1853
1854         if (out->n_modes > 0)
1855                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1856
1857         switch (out->type) {
1858         case TEGRA_DC_OUT_RGB:
1859                 dc->out_ops = &tegra_dc_rgb_ops;
1860                 break;
1861
1862         case TEGRA_DC_OUT_HDMI:
1863                 dc->out_ops = &tegra_dc_hdmi_ops;
1864                 break;
1865
1866         case TEGRA_DC_OUT_DSI:
1867                 dc->out_ops = &tegra_dc_dsi_ops;
1868                 break;
1869
1870         default:
1871                 dc->out_ops = NULL;
1872                 break;
1873         }
1874
1875         if (dc->out_ops && dc->out_ops->init)
1876                 dc->out_ops->init(dc);
1877
1878 }
1879
1880 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1881 {
1882         if (dc->out)
1883                 return dc->out->height;
1884         else
1885                 return 0;
1886 }
1887 EXPORT_SYMBOL(tegra_dc_get_out_height);
1888
1889 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1890 {
1891         if (dc->out)
1892                 return dc->out->width;
1893         else
1894                 return 0;
1895 }
1896 EXPORT_SYMBOL(tegra_dc_get_out_width);
1897
1898 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1899 {
1900         if (dc->out && dc->out->max_pixclock)
1901                 return dc->out->max_pixclock;
1902         else
1903                 return 0;
1904 }
1905 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1906
1907 void tegra_dc_enable_crc(struct tegra_dc *dc)
1908 {
1909         u32 val;
1910         tegra_dc_io_start(dc);
1911
1912         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1913                 CRC_ENABLE_ENABLE;
1914         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1915         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1916         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1917 }
1918
1919 void tegra_dc_disable_crc(struct tegra_dc *dc)
1920 {
1921         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1922         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1923         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1924
1925         tegra_dc_io_end(dc);
1926 }
1927
1928 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1929 {
1930         int crc = 0;
1931
1932         if(!dc) {
1933                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1934                 goto crc_error;
1935         }
1936
1937         /* TODO: Replace mdelay with code to sync VBlANK, since
1938          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1939         mdelay(TEGRA_CRC_LATCHED_DELAY);
1940
1941         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1942 crc_error:
1943         return crc;
1944 }
1945
1946 static void tegra_dc_vblank(struct work_struct *work)
1947 {
1948         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1949         bool nvsd_updated = false;
1950
1951         mutex_lock(&dc->lock);
1952
1953         /* update EMC clock if calculated bandwidth has changed */
1954         tegra_dc_program_bandwidth(dc);
1955
1956         /* Update the SD brightness */
1957         if (dc->enabled && dc->out->sd_settings)
1958                 nvsd_updated = nvsd_update_brightness(dc);
1959
1960         mutex_unlock(&dc->lock);
1961
1962         /* Do the actual brightness update outside of the mutex */
1963         if (nvsd_updated && dc->out->sd_settings &&
1964             dc->out->sd_settings->bl_device) {
1965
1966                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1967                 struct backlight_device *bl = platform_get_drvdata(pdev);
1968                 if (bl)
1969                         backlight_update_status(bl);
1970         }
1971 }
1972
1973 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1974 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1975 {
1976         u32 val, i;
1977
1978         /* Check for any underflow reset conditions */
1979         for (i = 0; i < DC_N_WINDOWS; i++) {
1980                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1981                         dc->windows[i].underflows++;
1982
1983 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1984                         if (dc->windows[i].underflows > 4)
1985                                 schedule_work(&dc->reset_work);
1986 #endif
1987                 } else {
1988                         dc->windows[i].underflows = 0;
1989                 }
1990         }
1991
1992         if (!dc->underflow_mask) {
1993                 /* If we have no underflow to check, go ahead
1994                    and disable the interrupt */
1995                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1996                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1997                         val &= ~FRAME_END_INT;
1998                 else
1999                         val &= ~V_BLANK_INT;
2000                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2001         }
2002
2003         /* Clear the underflow mask now that we've checked it. */
2004         dc->underflow_mask = 0;
2005 }
2006
2007 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2008 {
2009         u32 val, i;
2010         u32 completed = 0;
2011         u32 dirty = 0;
2012
2013         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2014         for (i = 0; i < DC_N_WINDOWS; i++) {
2015 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2016                 /* FIXME: this is not needed when the simulator
2017                    clears WIN_x_UPDATE bits as in HW */
2018                 dc->windows[i].dirty = 0;
2019                 completed = 1;
2020 #else
2021                 if (!(val & (WIN_A_UPDATE << i))) {
2022                         dc->windows[i].dirty = 0;
2023                         completed = 1;
2024                 } else {
2025                         dirty = 1;
2026                 }
2027 #endif
2028         }
2029
2030         if (!dirty) {
2031                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2032                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2033                         val &= ~V_BLANK_INT;
2034                 else
2035                         val &= ~FRAME_END_INT;
2036                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2037         }
2038
2039         if (completed) {
2040                 if (!dirty) {
2041                         /* With the last completed window, go ahead
2042                            and enable the vblank interrupt for nvsd. */
2043                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2044                         val |= V_BLANK_INT;
2045                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2046                 }
2047
2048                 wake_up(&dc->wq);
2049         }
2050 }
2051
2052 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2053 {
2054         if (status & V_BLANK_INT) {
2055                 /* Sync up windows. */
2056                 tegra_dc_trigger_windows(dc);
2057
2058                 /* Schedule any additional bottom-half vblank actvities. */
2059                 schedule_work(&dc->vblank_work);
2060         }
2061
2062         /* Check underflow at frame end */
2063         if (status & FRAME_END_INT) {
2064                 tegra_dc_underflow_handler(dc);
2065
2066                 /* Mark the frame_end as complete. */
2067                 if (completion_done(&dc->frame_end_complete))
2068                         complete(&dc->frame_end_complete);
2069         }
2070 }
2071
2072 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2073 {
2074         if (status & V_BLANK_INT) {
2075                 /* Check underflow */
2076                 tegra_dc_underflow_handler(dc);
2077
2078                 /* Schedule any additional bottom-half vblank actvities. */
2079                 schedule_work(&dc->vblank_work);
2080         }
2081
2082         if (status & FRAME_END_INT) {
2083                 /* Mark the frame_end as complete. */
2084                 if (completion_done(&dc->frame_end_complete))
2085                         complete(&dc->frame_end_complete);
2086
2087                 tegra_dc_trigger_windows(dc);
2088         }
2089 }
2090 #endif
2091
2092 /* return an arbitrarily large number if count overflow occurs.
2093  * make it a nice base-10 number to show up in stats output */
2094 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2095 {
2096         unsigned count = tegra_dc_readl(dc, reg);
2097         tegra_dc_writel(dc, 0, reg);
2098         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2099 }
2100
2101 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2102 {
2103 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2104         struct tegra_dc *dc = ptr;
2105         unsigned long status;
2106         unsigned long val;
2107         unsigned long underflow_mask;
2108
2109         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2110         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2111
2112         /*
2113          * Overlays can get thier internal state corrupted during and underflow
2114          * condition.  The only way to fix this state is to reset the DC.
2115          * if we get 4 consecutive frames with underflows, assume we're
2116          * hosed and reset.
2117          */
2118         underflow_mask = status & ALL_UF_INT;
2119
2120         if (underflow_mask) {
2121                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2122                 val |= V_BLANK_INT;
2123                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2124                 dc->underflow_mask |= underflow_mask;
2125                 dc->stats.underflows++;
2126                 if (status & WIN_A_UF_INT)
2127                         dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2128                                 DC_WINBUF_AD_UFLOW_STATUS);
2129                 if (status & WIN_B_UF_INT)
2130                         dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2131                                 DC_WINBUF_BD_UFLOW_STATUS);
2132                 if (status & WIN_C_UF_INT)
2133                         dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2134                                 DC_WINBUF_CD_UFLOW_STATUS);
2135         }
2136
2137         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2138                 tegra_dc_one_shot_irq(dc, status);
2139         else
2140                 tegra_dc_continuous_irq(dc, status);
2141
2142         return IRQ_HANDLED;
2143 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2144         return IRQ_NONE;
2145 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2146 }
2147
2148 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2149 {
2150         u32 color_control;
2151
2152         switch (dc->out->depth) {
2153         case 3:
2154                 color_control = BASE_COLOR_SIZE111;
2155                 break;
2156
2157         case 6:
2158                 color_control = BASE_COLOR_SIZE222;
2159                 break;
2160
2161         case 8:
2162                 color_control = BASE_COLOR_SIZE332;
2163                 break;
2164
2165         case 9:
2166                 color_control = BASE_COLOR_SIZE333;
2167                 break;
2168
2169         case 12:
2170                 color_control = BASE_COLOR_SIZE444;
2171                 break;
2172
2173         case 15:
2174                 color_control = BASE_COLOR_SIZE555;
2175                 break;
2176
2177         case 16:
2178                 color_control = BASE_COLOR_SIZE565;
2179                 break;
2180
2181         case 18:
2182                 color_control = BASE_COLOR_SIZE666;
2183                 break;
2184
2185         default:
2186                 color_control = BASE_COLOR_SIZE888;
2187                 break;
2188         }
2189
2190         switch (dc->out->dither) {
2191         case TEGRA_DC_DISABLE_DITHER:
2192                 color_control |= DITHER_CONTROL_DISABLE;
2193                 break;
2194         case TEGRA_DC_ORDERED_DITHER:
2195                 color_control |= DITHER_CONTROL_ORDERED;
2196                 break;
2197         case TEGRA_DC_ERRDIFF_DITHER:
2198                 /* The line buffer for error-diffusion dither is limited
2199                  * to 1280 pixels per line. This limits the maximum
2200                  * horizontal active area size to 1280 pixels when error
2201                  * diffusion is enabled.
2202                  */
2203                 BUG_ON(dc->mode.h_active > 1280);
2204                 color_control |= DITHER_CONTROL_ERRDIFF;
2205                 break;
2206         }
2207
2208         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2209 }
2210
2211 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2212 {
2213         u32 syncpt_id;
2214
2215         switch (dc->ndev->id) {
2216         case 0:
2217                 switch (idx) {
2218                 case 0:
2219                         syncpt_id = NVSYNCPT_DISP0_A;
2220                         break;
2221                 case 1:
2222                         syncpt_id = NVSYNCPT_DISP0_B;
2223                         break;
2224                 case 2:
2225                         syncpt_id = NVSYNCPT_DISP0_C;
2226                         break;
2227                 default:
2228                         BUG();
2229                         break;
2230                 }
2231                 break;
2232         case 1:
2233                 switch (idx) {
2234                 case 0:
2235                         syncpt_id = NVSYNCPT_DISP1_A;
2236                         break;
2237                 case 1:
2238                         syncpt_id = NVSYNCPT_DISP1_B;
2239                         break;
2240                 case 2:
2241                         syncpt_id = NVSYNCPT_DISP1_C;
2242                         break;
2243                 default:
2244                         BUG();
2245                         break;
2246                 }
2247                 break;
2248         default:
2249                 BUG();
2250                 break;
2251         }
2252
2253         return syncpt_id;
2254 }
2255
2256 static void tegra_dc_init(struct tegra_dc *dc)
2257 {
2258         int i;
2259
2260         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2261         if (dc->ndev->id == 0) {
2262                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2263                                       TEGRA_MC_PRIO_MED);
2264                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2265                                       TEGRA_MC_PRIO_MED);
2266                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2267                                       TEGRA_MC_PRIO_MED);
2268                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2269                                       TEGRA_MC_PRIO_MED);
2270                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2271                                       TEGRA_MC_PRIO_HIGH);
2272         } else if (dc->ndev->id == 1) {
2273                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2274                                       TEGRA_MC_PRIO_MED);
2275                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2276                                       TEGRA_MC_PRIO_MED);
2277                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2278                                       TEGRA_MC_PRIO_MED);
2279                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2280                                       TEGRA_MC_PRIO_MED);
2281                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2282                                       TEGRA_MC_PRIO_HIGH);
2283         }
2284         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2285                         DC_CMD_CONT_SYNCPT_VSYNC);
2286         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2287         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2288         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2289         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2290
2291         /* enable interrupts for vblank, frame_end and underflows */
2292         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2293                 DC_CMD_INT_ENABLE);
2294         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2295
2296         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2297
2298         tegra_dc_set_color_control(dc);
2299         for (i = 0; i < DC_N_WINDOWS; i++) {
2300                 struct tegra_dc_win *win = &dc->windows[i];
2301                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2302                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2303                 tegra_dc_set_csc(dc, &win->csc);
2304                 tegra_dc_set_lut(dc, win);
2305                 tegra_dc_set_scaling_filter(dc);
2306         }
2307
2308
2309         for (i = 0; i < dc->n_windows; i++) {
2310                 u32 syncpt = get_syncpt(dc, i);
2311
2312                 dc->syncpt[i].id = syncpt;
2313
2314                 dc->syncpt[i].min = dc->syncpt[i].max =
2315                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2316         }
2317
2318         print_mode(dc, &dc->mode, __func__);
2319
2320         if (dc->mode.pclk)
2321                 tegra_dc_program_mode(dc, &dc->mode);
2322
2323         /* Initialize SD AFTER the modeset.
2324            nvsd_init handles the sd_settings = NULL case. */
2325         nvsd_init(dc, dc->out->sd_settings);
2326 }
2327
2328 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2329 {
2330         if (dc->out->enable)
2331                 dc->out->enable();
2332
2333         tegra_dc_setup_clk(dc, dc->clk);
2334         clk_enable(dc->clk);
2335         clk_enable(dc->emc_clk);
2336
2337         /* do not accept interrupts during initialization */
2338         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2339         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2340
2341         enable_dc_irq(dc->irq);
2342
2343         tegra_dc_init(dc);
2344
2345         if (dc->out_ops && dc->out_ops->enable)
2346                 dc->out_ops->enable(dc);
2347
2348         if (dc->out->out_pins)
2349                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2350                                             dc->out->n_out_pins);
2351
2352         if (dc->out->postpoweron)
2353                 dc->out->postpoweron();
2354
2355         /* force a full blending update */
2356         dc->blend.z[0] = -1;
2357
2358         tegra_dc_ext_enable(dc->ext);
2359
2360         return true;
2361 }
2362
2363 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2364 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2365 {
2366         if (dc->out->enable)
2367                 dc->out->enable();
2368
2369         tegra_dc_setup_clk(dc, dc->clk);
2370         clk_enable(dc->clk);
2371         clk_enable(dc->emc_clk);
2372
2373         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2374                 mutex_lock(&tegra_dcs[1]->lock);
2375                 disable_irq(tegra_dcs[1]->irq);
2376         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2377                 mutex_lock(&tegra_dcs[0]->lock);
2378                 disable_irq(tegra_dcs[0]->irq);
2379         }
2380
2381         msleep(5);
2382         tegra_periph_reset_assert(dc->clk);
2383         msleep(2);
2384 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2385         tegra_periph_reset_deassert(dc->clk);
2386         msleep(1);
2387 #endif
2388
2389         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2390                 enable_dc_irq(tegra_dcs[1]->irq);
2391                 mutex_unlock(&tegra_dcs[1]->lock);
2392         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2393                 enable_dc_irq(tegra_dcs[0]->irq);
2394                 mutex_unlock(&tegra_dcs[0]->lock);
2395         }
2396
2397         enable_dc_irq(dc->irq);
2398
2399         tegra_dc_init(dc);
2400
2401         if (dc->out_ops && dc->out_ops->enable)
2402                 dc->out_ops->enable(dc);
2403
2404         if (dc->out->out_pins)
2405                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2406                                             dc->out->n_out_pins);
2407
2408         if (dc->out->postpoweron)
2409                 dc->out->postpoweron();
2410
2411         /* force a full blending update */
2412         dc->blend.z[0] = -1;
2413
2414         return true;
2415 }
2416 #endif
2417
2418 static bool _tegra_dc_enable(struct tegra_dc *dc)
2419 {
2420         if (dc->mode.pclk == 0)
2421                 return false;
2422
2423         if (!dc->out)
2424                 return false;
2425
2426         tegra_dc_io_start(dc);
2427
2428         return _tegra_dc_controller_enable(dc);
2429 }
2430
2431 void tegra_dc_enable(struct tegra_dc *dc)
2432 {
2433         mutex_lock(&dc->lock);
2434
2435         if (!dc->enabled)
2436                 dc->enabled = _tegra_dc_enable(dc);
2437
2438         mutex_unlock(&dc->lock);
2439 }
2440
2441 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2442 {
2443         unsigned i;
2444
2445         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2446         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2447         disable_irq(dc->irq);
2448
2449         if (dc->out_ops && dc->out_ops->disable)
2450                 dc->out_ops->disable(dc);
2451
2452         clk_disable(dc->emc_clk);
2453         clk_disable(dc->clk);
2454         tegra_dvfs_set_rate(dc->clk, 0);
2455
2456         if (dc->out && dc->out->disable)
2457                 dc->out->disable();
2458
2459         for (i = 0; i < dc->n_windows; i++) {
2460                 struct tegra_dc_win *w = &dc->windows[i];
2461
2462                 /* reset window bandwidth */
2463                 w->bandwidth = 0;
2464                 w->new_bandwidth = 0;
2465
2466                 /* disable windows */
2467                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2468
2469                 /* flush any pending syncpt waits */
2470                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2471                         dc->syncpt[i].min++;
2472                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2473                                 dc->syncpt[i].id);
2474                 }
2475         }
2476 }
2477
2478 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2479 {
2480 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2481         u32 val;
2482         if (dc->enabled)  {
2483                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2484                 if (enable)
2485                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2486                 else
2487                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2488                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2489         }
2490 #endif
2491 }
2492
2493 bool tegra_dc_stats_get(struct tegra_dc *dc)
2494 {
2495 #if 0 /* right now it is always enabled */
2496         u32 val;
2497         bool res;
2498
2499         if (dc->enabled)  {
2500                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2501                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2502         } else {
2503                 res = false;
2504         }
2505
2506         return res;
2507 #endif
2508         return true;
2509 }
2510
2511 /* make the screen blank by disabling all windows */
2512 void tegra_dc_blank(struct tegra_dc *dc)
2513 {
2514         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2515         unsigned i;
2516
2517         for (i = 0; i < DC_N_WINDOWS; i++) {
2518                 dcwins[i] = tegra_dc_get_window(dc, i);
2519                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2520         }
2521
2522         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2523         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2524 }
2525
2526 static void _tegra_dc_disable(struct tegra_dc *dc)
2527 {
2528         _tegra_dc_controller_disable(dc);
2529         tegra_dc_io_end(dc);
2530 }
2531
2532 void tegra_dc_disable(struct tegra_dc *dc)
2533 {
2534         if (dc->overlay)
2535                 tegra_overlay_disable(dc->overlay);
2536
2537         tegra_dc_ext_disable(dc->ext);
2538
2539         mutex_lock(&dc->lock);
2540
2541         if (dc->enabled) {
2542                 dc->enabled = false;
2543
2544                 if (!dc->suspended)
2545                         _tegra_dc_disable(dc);
2546         }
2547
2548         mutex_unlock(&dc->lock);
2549 }
2550
2551 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2552 static void tegra_dc_reset_worker(struct work_struct *work)
2553 {
2554         struct tegra_dc *dc =
2555                 container_of(work, struct tegra_dc, reset_work);
2556
2557         unsigned long val = 0;
2558
2559         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2560
2561         tegra_dc_ext_disable(dc->ext);
2562
2563         mutex_lock(&shared_lock);
2564         mutex_lock(&dc->lock);
2565
2566         if (dc->enabled == false)
2567                 goto unlock;
2568
2569         dc->enabled = false;
2570
2571         /*
2572          * off host read bus
2573          */
2574         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2575         val &= ~(0x00000100);
2576         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2577
2578         /*
2579          * set DC to STOP mode
2580          */
2581         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2582
2583         msleep(10);
2584
2585         _tegra_dc_controller_disable(dc);
2586
2587         /* _tegra_dc_controller_reset_enable deasserts reset */
2588         _tegra_dc_controller_reset_enable(dc);
2589
2590         dc->enabled = true;
2591 unlock:
2592         mutex_unlock(&dc->lock);
2593         mutex_unlock(&shared_lock);
2594 }
2595 #endif
2596
2597
2598 static int tegra_dc_probe(struct nvhost_device *ndev)
2599 {
2600         struct tegra_dc *dc;
2601         struct clk *clk;
2602         struct clk *emc_clk;
2603         struct resource *res;
2604         struct resource *base_res;
2605         struct resource *fb_mem = NULL;
2606         int ret = 0;
2607         void __iomem *base;
2608         int irq;
2609         int i;
2610
2611         if (!ndev->dev.platform_data) {
2612                 dev_err(&ndev->dev, "no platform data\n");
2613                 return -ENOENT;
2614         }
2615
2616         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2617         if (!dc) {
2618                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2619                 return -ENOMEM;
2620         }
2621
2622         irq = nvhost_get_irq_byname(ndev, "irq");
2623         if (irq <= 0) {
2624                 dev_err(&ndev->dev, "no irq\n");
2625                 ret = -ENOENT;
2626                 goto err_free;
2627         }
2628
2629         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2630         if (!res) {
2631                 dev_err(&ndev->dev, "no mem resource\n");
2632                 ret = -ENOENT;
2633                 goto err_free;
2634         }
2635
2636         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2637         if (!base_res) {
2638                 dev_err(&ndev->dev, "request_mem_region failed\n");
2639                 ret = -EBUSY;
2640                 goto err_free;
2641         }
2642
2643         base = ioremap(res->start, resource_size(res));
2644         if (!base) {
2645                 dev_err(&ndev->dev, "registers can't be mapped\n");
2646                 ret = -EBUSY;
2647                 goto err_release_resource_reg;
2648         }
2649
2650         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2651
2652         clk = clk_get(&ndev->dev, NULL);
2653         if (IS_ERR_OR_NULL(clk)) {
2654                 dev_err(&ndev->dev, "can't get clock\n");
2655                 ret = -ENOENT;
2656                 goto err_iounmap_reg;
2657         }
2658
2659         emc_clk = clk_get(&ndev->dev, "emc");
2660         if (IS_ERR_OR_NULL(emc_clk)) {
2661                 dev_err(&ndev->dev, "can't get emc clock\n");
2662                 ret = -ENOENT;
2663                 goto err_put_clk;
2664         }
2665
2666         dc->clk = clk;
2667         dc->emc_clk = emc_clk;
2668
2669         dc->base_res = base_res;
2670         dc->base = base;
2671         dc->irq = irq;
2672         dc->ndev = ndev;
2673         dc->pdata = ndev->dev.platform_data;
2674
2675         /*
2676          * The emc is a shared clock, it will be set based on
2677          * the requirements for each user on the bus.
2678          */
2679         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2680         clk_set_rate(emc_clk, dc->emc_clk_rate);
2681
2682         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2683                 dc->enabled = true;
2684
2685         mutex_init(&dc->lock);
2686         init_completion(&dc->frame_end_complete);
2687         init_waitqueue_head(&dc->wq);
2688 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2689         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2690 #endif
2691         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2692
2693         tegra_dc_init_lut_defaults(&dc->fb_lut);
2694
2695         dc->n_windows = DC_N_WINDOWS;
2696         for (i = 0; i < dc->n_windows; i++) {
2697                 struct tegra_dc_win *win = &dc->windows[i];
2698                 win->idx = i;
2699                 win->dc = dc;
2700                 tegra_dc_init_csc_defaults(&win->csc);
2701                 tegra_dc_init_lut_defaults(&win->lut);
2702         }
2703
2704         ret = tegra_dc_set(dc, ndev->id);
2705         if (ret < 0) {
2706                 dev_err(&ndev->dev, "can't add dc\n");
2707                 goto err_free_irq;
2708         }
2709
2710         nvhost_set_drvdata(ndev, dc);
2711
2712         if (dc->pdata->default_out)
2713                 tegra_dc_set_out(dc, dc->pdata->default_out);
2714         else
2715                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2716
2717         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2718                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2719
2720         dc->ext = tegra_dc_ext_register(ndev, dc);
2721         if (IS_ERR_OR_NULL(dc->ext)) {
2722                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2723                 dc->ext = NULL;
2724         }
2725
2726         /* interrupt handler must be registered before tegra_fb_register() */
2727         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2728                         dev_name(&ndev->dev), dc)) {
2729                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2730                 ret = -EBUSY;
2731                 goto err_put_emc_clk;
2732         }
2733
2734         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2735         disable_dc_irq(dc->irq);
2736
2737         mutex_lock(&dc->lock);
2738         if (dc->enabled)
2739                 _tegra_dc_enable(dc);
2740         mutex_unlock(&dc->lock);
2741
2742         tegra_dc_create_debugfs(dc);
2743
2744         dev_info(&ndev->dev, "probed\n");
2745
2746         if (dc->pdata->fb) {
2747                 if (dc->pdata->fb->bits_per_pixel == -1) {
2748                         unsigned long fmt;
2749                         tegra_dc_writel(dc,
2750                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2751                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2752
2753                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2754                         dc->pdata->fb->bits_per_pixel =
2755                                 tegra_dc_fmt_bpp(fmt);
2756                 }
2757
2758                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2759                 if (IS_ERR_OR_NULL(dc->fb))
2760                         dc->fb = NULL;
2761         }
2762
2763         if (dc->fb) {
2764                 dc->overlay = tegra_overlay_register(ndev, dc);
2765                 if (IS_ERR_OR_NULL(dc->overlay))
2766                         dc->overlay = NULL;
2767         }
2768
2769         if (dc->out && dc->out->hotplug_init)
2770                 dc->out->hotplug_init();
2771
2772         if (dc->out_ops && dc->out_ops->detect)
2773                 dc->out_ops->detect(dc);
2774         else
2775                 dc->connected = true;
2776
2777         tegra_dc_create_sysfs(&dc->ndev->dev);
2778
2779         return 0;
2780
2781 err_free_irq:
2782         free_irq(irq, dc);
2783 err_put_emc_clk:
2784         clk_put(emc_clk);
2785 err_put_clk:
2786         clk_put(clk);
2787 err_iounmap_reg:
2788         iounmap(base);
2789         if (fb_mem)
2790                 release_resource(fb_mem);
2791 err_release_resource_reg:
2792         release_resource(base_res);
2793 err_free:
2794         kfree(dc);
2795
2796         return ret;
2797 }
2798
2799 static int tegra_dc_remove(struct nvhost_device *ndev)
2800 {
2801         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2802
2803         tegra_dc_remove_sysfs(&dc->ndev->dev);
2804         tegra_dc_remove_debugfs(dc);
2805
2806         if (dc->overlay) {
2807                 tegra_overlay_unregister(dc->overlay);
2808         }
2809
2810         if (dc->fb) {
2811                 tegra_fb_unregister(dc->fb);
2812                 if (dc->fb_mem)
2813                         release_resource(dc->fb_mem);
2814         }
2815
2816         tegra_dc_ext_disable(dc->ext);
2817
2818         if (dc->ext)
2819                 tegra_dc_ext_unregister(dc->ext);
2820
2821         if (dc->enabled)
2822                 _tegra_dc_disable(dc);
2823
2824         free_irq(dc->irq, dc);
2825         clk_put(dc->emc_clk);
2826         clk_put(dc->clk);
2827         iounmap(dc->base);
2828         if (dc->fb_mem)
2829                 release_resource(dc->base_res);
2830         kfree(dc);
2831         tegra_dc_set(NULL, ndev->id);
2832         return 0;
2833 }
2834
2835 #ifdef CONFIG_PM
2836 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2837 {
2838         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2839
2840         dev_info(&ndev->dev, "suspend\n");
2841
2842         if (dc->overlay)
2843                 tegra_overlay_disable(dc->overlay);
2844
2845         tegra_dc_ext_disable(dc->ext);
2846
2847         mutex_lock(&dc->lock);
2848
2849         if (dc->out_ops && dc->out_ops->suspend)
2850                 dc->out_ops->suspend(dc);
2851
2852         if (dc->enabled) {
2853                 _tegra_dc_disable(dc);
2854
2855                 dc->suspended = true;
2856         }
2857
2858         if (dc->out && dc->out->postsuspend) {
2859                 dc->out->postsuspend();
2860                 msleep(100); /* avoid resume event due to voltage falling */
2861         }
2862
2863         mutex_unlock(&dc->lock);
2864
2865         return 0;
2866 }
2867
2868 static int tegra_dc_resume(struct nvhost_device *ndev)
2869 {
2870         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2871
2872         dev_info(&ndev->dev, "resume\n");
2873
2874         mutex_lock(&dc->lock);
2875         dc->suspended = false;
2876
2877         if (dc->enabled)
2878                 _tegra_dc_enable(dc);
2879
2880         if (dc->out && dc->out->hotplug_init)
2881                 dc->out->hotplug_init();
2882
2883         if (dc->out_ops && dc->out_ops->resume)
2884                 dc->out_ops->resume(dc);
2885         mutex_unlock(&dc->lock);
2886
2887         return 0;
2888 }
2889
2890 #endif /* CONFIG_PM */
2891
2892 extern int suspend_set(const char *val, struct kernel_param *kp)
2893 {
2894         if (!strcmp(val, "dump"))
2895                 dump_regs(tegra_dcs[0]);
2896 #ifdef CONFIG_PM
2897         else if (!strcmp(val, "suspend"))
2898                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2899         else if (!strcmp(val, "resume"))
2900                 tegra_dc_resume(tegra_dcs[0]->ndev);
2901 #endif
2902
2903         return 0;
2904 }
2905
2906 extern int suspend_get(char *buffer, struct kernel_param *kp)
2907 {
2908         return 0;
2909 }
2910
2911 int suspend;
2912
2913 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2914
2915 struct nvhost_driver tegra_dc_driver = {
2916         .driver = {
2917                 .name = "tegradc",
2918                 .owner = THIS_MODULE,
2919         },
2920         .probe = tegra_dc_probe,
2921         .remove = tegra_dc_remove,
2922 #ifdef CONFIG_PM
2923         .suspend = tegra_dc_suspend,
2924         .resume = tegra_dc_resume,
2925 #endif
2926 };
2927
2928 static int __init tegra_dc_module_init(void)
2929 {
2930         int ret = tegra_dc_ext_module_init();
2931         if (ret)
2932                 return ret;
2933         return nvhost_driver_register(&tegra_dc_driver);
2934 }
2935
2936 static void __exit tegra_dc_module_exit(void)
2937 {
2938         nvhost_driver_unregister(&tegra_dc_driver);
2939         tegra_dc_ext_module_exit();
2940 }
2941
2942 module_exit(tegra_dc_module_exit);
2943 module_init(tegra_dc_module_init);