tegra: dc: adding max pixclock check for hdmi
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36
37 #include <mach/clk.h>
38 #include <mach/dc.h>
39 #include <mach/fb.h>
40 #include <mach/mc.h>
41 #include <mach/nvhost.h>
42
43 #include "dc_reg.h"
44 #include "dc_priv.h"
45 #include "overlay.h"
46 #include "nvsd.h"
47
48 static int no_vsync;
49
50 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
51
52 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
53
54 DEFINE_MUTEX(tegra_dc_lock);
55 DEFINE_MUTEX(shared_lock);
56
57 static inline int tegra_dc_fmt_bpp(int fmt)
58 {
59         switch (fmt) {
60         case TEGRA_WIN_FMT_P1:
61                 return 1;
62
63         case TEGRA_WIN_FMT_P2:
64                 return 2;
65
66         case TEGRA_WIN_FMT_P4:
67                 return 4;
68
69         case TEGRA_WIN_FMT_P8:
70                 return 8;
71
72         case TEGRA_WIN_FMT_B4G4R4A4:
73         case TEGRA_WIN_FMT_B5G5R5A:
74         case TEGRA_WIN_FMT_B5G6R5:
75         case TEGRA_WIN_FMT_AB5G5R5:
76                 return 16;
77
78         case TEGRA_WIN_FMT_B8G8R8A8:
79         case TEGRA_WIN_FMT_R8G8B8A8:
80         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
81         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
82                 return 32;
83
84         /* for planar formats, size of the Y plane, 8bit */
85         case TEGRA_WIN_FMT_YCbCr420P:
86         case TEGRA_WIN_FMT_YUV420P:
87         case TEGRA_WIN_FMT_YCbCr422P:
88         case TEGRA_WIN_FMT_YUV422P:
89                 return 8;
90
91         case TEGRA_WIN_FMT_YCbCr422:
92         case TEGRA_WIN_FMT_YUV422:
93         case TEGRA_WIN_FMT_YCbCr422R:
94         case TEGRA_WIN_FMT_YUV422R:
95         case TEGRA_WIN_FMT_YCbCr422RA:
96         case TEGRA_WIN_FMT_YUV422RA:
97                 /* FIXME: need to know the bpp of these formats */
98                 return 0;
99         }
100         return 0;
101 }
102
103 static inline bool tegra_dc_is_yuv_planar(int fmt)
104 {
105         switch (fmt) {
106         case TEGRA_WIN_FMT_YUV420P:
107         case TEGRA_WIN_FMT_YCbCr420P:
108         case TEGRA_WIN_FMT_YCbCr422P:
109         case TEGRA_WIN_FMT_YUV422P:
110                 return true;
111         }
112         return false;
113 }
114
115 #define DUMP_REG(a) do {                        \
116         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
117                  #a, a, tegra_dc_readl(dc, a));               \
118         print(data, buff);                                    \
119         } while (0)
120
121 static void _dump_regs(struct tegra_dc *dc, void *data,
122                        void (* print)(void *data, const char *str))
123 {
124         int i;
125         char buff[256];
126
127         tegra_dc_io_start(dc);
128         clk_enable(dc->clk);
129
130         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
131         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
132         DUMP_REG(DC_CMD_SIGNAL_RAISE);
133         DUMP_REG(DC_CMD_INT_STATUS);
134         DUMP_REG(DC_CMD_INT_MASK);
135         DUMP_REG(DC_CMD_INT_ENABLE);
136         DUMP_REG(DC_CMD_INT_TYPE);
137         DUMP_REG(DC_CMD_INT_POLARITY);
138         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
139         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
140         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
141         DUMP_REG(DC_CMD_STATE_ACCESS);
142         DUMP_REG(DC_CMD_STATE_CONTROL);
143         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
144         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
145
146         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
147         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
148         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
149         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
150         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
151         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
152         DUMP_REG(DC_DISP_REF_TO_SYNC);
153         DUMP_REG(DC_DISP_SYNC_WIDTH);
154         DUMP_REG(DC_DISP_BACK_PORCH);
155         DUMP_REG(DC_DISP_DISP_ACTIVE);
156         DUMP_REG(DC_DISP_FRONT_PORCH);
157         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
158         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
159         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
160         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
161         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
162         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
163         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
164         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
165         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
166         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
167         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
168         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
169         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
170         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
171         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
172         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
173         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
174         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
175         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
176         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
177         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
178         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
179         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
180         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
181         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
182         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
183         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
184         DUMP_REG(DC_DISP_M0_CONTROL);
185         DUMP_REG(DC_DISP_M1_CONTROL);
186         DUMP_REG(DC_DISP_DI_CONTROL);
187         DUMP_REG(DC_DISP_PP_CONTROL);
188         DUMP_REG(DC_DISP_PP_SELECT_A);
189         DUMP_REG(DC_DISP_PP_SELECT_B);
190         DUMP_REG(DC_DISP_PP_SELECT_C);
191         DUMP_REG(DC_DISP_PP_SELECT_D);
192         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
193         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
194         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
195         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
196         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
197         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
198         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
199         DUMP_REG(DC_DISP_BORDER_COLOR);
200         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
201         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
202         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
203         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
204         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
205         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
206         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
207         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
208         DUMP_REG(DC_DISP_CURSOR_POSITION);
209         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
210         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
211         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
212         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
213         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
214         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
215         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
216         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
217         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
218         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
219         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
220         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
221         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
222
223
224         for (i = 0; i < 3; i++) {
225                 print(data, "\n");
226                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
227                 print(data, buff);
228
229                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
230                                 DC_CMD_DISPLAY_WINDOW_HEADER);
231                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
232                 DUMP_REG(DC_WIN_WIN_OPTIONS);
233                 DUMP_REG(DC_WIN_BYTE_SWAP);
234                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
235                 DUMP_REG(DC_WIN_COLOR_DEPTH);
236                 DUMP_REG(DC_WIN_POSITION);
237                 DUMP_REG(DC_WIN_SIZE);
238                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
239                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
240                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
241                 DUMP_REG(DC_WIN_DDA_INCREMENT);
242                 DUMP_REG(DC_WIN_LINE_STRIDE);
243                 DUMP_REG(DC_WIN_BUF_STRIDE);
244                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
245                 DUMP_REG(DC_WIN_BLEND_NOKEY);
246                 DUMP_REG(DC_WIN_BLEND_1WIN);
247                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
248                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
249                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
250                 DUMP_REG(DC_WINBUF_START_ADDR);
251                 DUMP_REG(DC_WINBUF_START_ADDR_U);
252                 DUMP_REG(DC_WINBUF_START_ADDR_V);
253                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
254                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
255                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
256                 DUMP_REG(DC_WIN_CSC_YOF);
257                 DUMP_REG(DC_WIN_CSC_KYRGB);
258                 DUMP_REG(DC_WIN_CSC_KUR);
259                 DUMP_REG(DC_WIN_CSC_KVR);
260                 DUMP_REG(DC_WIN_CSC_KUG);
261                 DUMP_REG(DC_WIN_CSC_KVG);
262                 DUMP_REG(DC_WIN_CSC_KUB);
263                 DUMP_REG(DC_WIN_CSC_KVB);
264         }
265
266         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
267         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
268         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
269         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
270         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
271         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
272         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
273         DUMP_REG(DC_DISP_M1_CONTROL);
274         DUMP_REG(DC_COM_PM1_CONTROL);
275         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
276         DUMP_REG(DC_DISP_SD_CONTROL);
277
278         clk_disable(dc->clk);
279         tegra_dc_io_end(dc);
280 }
281
282 #undef DUMP_REG
283
284 #ifdef DEBUG
285 static void dump_regs_print(void *data, const char *str)
286 {
287         struct tegra_dc *dc = data;
288         dev_dbg(&dc->ndev->dev, "%s", str);
289 }
290
291 static void dump_regs(struct tegra_dc *dc)
292 {
293         _dump_regs(dc, dc, dump_regs_print);
294 }
295 #else /* !DEBUG */
296
297 static void dump_regs(struct tegra_dc *dc) {}
298
299 #endif /* DEBUG */
300
301 #ifdef CONFIG_DEBUG_FS
302
303 static void dbg_regs_print(void *data, const char *str)
304 {
305         struct seq_file *s = data;
306
307         seq_printf(s, "%s", str);
308 }
309
310 #undef DUMP_REG
311
312 static int dbg_dc_show(struct seq_file *s, void *unused)
313 {
314         struct tegra_dc *dc = s->private;
315
316         _dump_regs(dc, s, dbg_regs_print);
317
318         return 0;
319 }
320
321
322 static int dbg_dc_open(struct inode *inode, struct file *file)
323 {
324         return single_open(file, dbg_dc_show, inode->i_private);
325 }
326
327 static const struct file_operations regs_fops = {
328         .open           = dbg_dc_open,
329         .read           = seq_read,
330         .llseek         = seq_lseek,
331         .release        = single_release,
332 };
333
334 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
335 {
336         struct tegra_dc *dc = s->private;
337         struct tegra_dc_mode *m;
338
339         mutex_lock(&dc->lock);
340         m = &dc->mode;
341         seq_printf(s,
342                 "pclk: %d\n"
343                 "h_ref_to_sync: %d\n"
344                 "v_ref_to_sync: %d\n"
345                 "h_sync_width: %d\n"
346                 "v_sync_width: %d\n"
347                 "h_back_porch: %d\n"
348                 "v_back_porch: %d\n"
349                 "h_active: %d\n"
350                 "v_active: %d\n"
351                 "h_front_porch: %d\n"
352                 "v_front_porch: %d\n"
353                 "stereo_mode: %d\n",
354                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
355                 m->h_sync_width, m->v_sync_width,
356                 m->h_back_porch, m->v_back_porch,
357                 m->h_active, m->v_active,
358                 m->h_front_porch, m->v_front_porch,
359                 m->stereo_mode);
360         mutex_unlock(&dc->lock);
361         return 0;
362 }
363
364 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
365 {
366         return single_open(file, dbg_dc_mode_show, inode->i_private);
367 }
368
369 static const struct file_operations mode_fops = {
370         .open           = dbg_dc_mode_open,
371         .read           = seq_read,
372         .llseek         = seq_lseek,
373         .release        = single_release,
374 };
375
376 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
377 {
378         struct tegra_dc *dc = s->private;
379
380         mutex_lock(&dc->lock);
381         seq_printf(s,
382                 "underflows: %u\n"
383                 "underflows_a: %u\n"
384                 "underflows_b: %u\n"
385                 "underflows_c: %u\n",
386                 dc->stats.underflows,
387                 dc->stats.underflows_a,
388                 dc->stats.underflows_b,
389                 dc->stats.underflows_c);
390         mutex_unlock(&dc->lock);
391
392         return 0;
393 }
394
395 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
396 {
397         return single_open(file, dbg_dc_stats_show, inode->i_private);
398 }
399
400 static const struct file_operations stats_fops = {
401         .open           = dbg_dc_stats_open,
402         .read           = seq_read,
403         .llseek         = seq_lseek,
404         .release        = single_release,
405 };
406
407 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
408 {
409         if (dc->debugdir)
410                 debugfs_remove_recursive(dc->debugdir);
411         dc->debugdir = NULL;
412 }
413
414 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
415 {
416         struct dentry *retval;
417
418         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
419         if (!dc->debugdir)
420                 goto remove_out;
421
422         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
423                 &regs_fops);
424         if (!retval)
425                 goto remove_out;
426
427         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
428                 &mode_fops);
429         if (!retval)
430                 goto remove_out;
431
432         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
433                 &stats_fops);
434         if (!retval)
435                 goto remove_out;
436
437         return;
438 remove_out:
439         dev_err(&dc->ndev->dev, "could not create debugfs\n");
440         tegra_dc_remove_debugfs(dc);
441 }
442
443 #else /* !CONFIG_DEBUGFS */
444 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
445 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
446 #endif /* CONFIG_DEBUGFS */
447
448 static int tegra_dc_add(struct tegra_dc *dc, int index)
449 {
450         int ret = 0;
451
452         mutex_lock(&tegra_dc_lock);
453         if (index >= TEGRA_MAX_DC) {
454                 ret = -EINVAL;
455                 goto out;
456         }
457
458         if (tegra_dcs[index] != NULL) {
459                 ret = -EBUSY;
460                 goto out;
461         }
462
463         tegra_dcs[index] = dc;
464
465 out:
466         mutex_unlock(&tegra_dc_lock);
467
468         return ret;
469 }
470
471 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
472 {
473         if (idx < TEGRA_MAX_DC)
474                 return tegra_dcs[idx];
475         else
476                 return NULL;
477 }
478 EXPORT_SYMBOL(tegra_dc_get_dc);
479
480 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
481 {
482         if (win >= dc->n_windows)
483                 return NULL;
484
485         return &dc->windows[win];
486 }
487 EXPORT_SYMBOL(tegra_dc_get_window);
488
489 static int get_topmost_window(u32 *depths, unsigned long *wins)
490 {
491         int idx, best = -1;
492
493         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
494                 if (best == -1 || depths[idx] < depths[best])
495                         best = idx;
496         }
497         clear_bit(best, wins);
498         return best;
499 }
500
501 static u32 blend_topwin(u32 flags)
502 {
503         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
504                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
505         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
506                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
507         else
508                 return BLEND(NOKEY, FIX, 0xff, 0xff);
509 }
510
511 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
512 {
513         int other;
514
515         for (other = 0; other < DC_N_WINDOWS; other++) {
516                 if (other != idx && (xy-- == 0))
517                         break;
518         }
519         if (BIT(other) & behind_mask)
520                 return blend_topwin(flags[idx]);
521         else if (flags[other])
522                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
523         else
524                 return BLEND(NOKEY, FIX, 0x00, 0x00);
525 }
526
527 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
528 {
529         unsigned long infront_mask;
530         int first;
531
532         infront_mask = ~(behind_mask | BIT(idx));
533         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
534         first = ffs(infront_mask) - 1;
535
536         if (!infront_mask)
537                 return blend_topwin(flags[idx]);
538         else if (behind_mask && first != -1 && flags[first])
539                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
540         else
541                 return BLEND(NOKEY, FIX, 0x0, 0x0);
542 }
543
544 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
545 {
546         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
547
548         while (mask) {
549                 int idx = get_topmost_window(blend->z, &mask);
550
551                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
552                                 DC_CMD_DISPLAY_WINDOW_HEADER);
553                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
554                                 DC_WIN_BLEND_NOKEY);
555                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
556                                 DC_WIN_BLEND_1WIN);
557                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
558                                 DC_WIN_BLEND_2WIN_X);
559                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
560                                 DC_WIN_BLEND_2WIN_Y);
561                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
562                                 DC_WIN_BLEND_3WIN_XY);
563         }
564 }
565
566 static void tegra_dc_set_csc(struct tegra_dc *dc)
567 {
568         tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
569         tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
570         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
571         tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
572         tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
573         tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
574         tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
575         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
576 }
577
578 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
579 {
580         unsigned i;
581         unsigned v0 = 128;
582         unsigned v1 = 0;
583         /* linear horizontal and vertical filters */
584         for (i = 0; i < 16; i++) {
585                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
586                                 DC_WIN_H_FILTER_P(i));
587
588                 tegra_dc_writel(dc, v0,
589                                 DC_WIN_V_FILTER_P(i));
590                 v0 -= 8;
591                 v1 += 8;
592         }
593 }
594
595 /* does not support updating windows on multiple dcs in one call */
596 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
597 {
598         struct tegra_dc *dc;
599         unsigned long update_mask = GENERAL_ACT_REQ;
600         unsigned long val;
601         bool update_blend = false;
602         int i;
603
604         dc = windows[0]->dc;
605
606         mutex_lock(&dc->lock);
607
608         if (!dc->enabled) {
609                 mutex_unlock(&dc->lock);
610                 return -EFAULT;
611         }
612
613         if (no_vsync)
614                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
615         else
616                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
617
618         for (i = 0; i < n; i++) {
619                 struct tegra_dc_win *win = windows[i];
620                 unsigned h_dda;
621                 unsigned v_dda;
622                 unsigned h_offset;
623                 unsigned v_offset;
624                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
625                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
626                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
627
628                 if (win->z != dc->blend.z[win->idx]) {
629                         dc->blend.z[win->idx] = win->z;
630                         update_blend = true;
631                 }
632                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
633                         dc->blend.flags[win->idx]) {
634                         dc->blend.flags[win->idx] =
635                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
636                         update_blend = true;
637                 }
638
639                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
640                                 DC_CMD_DISPLAY_WINDOW_HEADER);
641
642                 if (!no_vsync)
643                         update_mask |= WIN_A_ACT_REQ << win->idx;
644
645                 if (!(win->flags & TEGRA_WIN_FLAG_ENABLED)) {
646                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
647                         continue;
648                 }
649
650                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
651                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
652
653                 tegra_dc_writel(dc,
654                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
655                                 DC_WIN_POSITION);
656                 tegra_dc_writel(dc,
657                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
658                                 DC_WIN_SIZE);
659                 tegra_dc_writel(dc,
660                                 V_PRESCALED_SIZE(win->h) |
661                                 H_PRESCALED_SIZE(win->w * tegra_dc_fmt_bpp(win->fmt) / 8),
662                                 DC_WIN_PRESCALED_SIZE);
663
664                 h_dda = ((win->w - 1) * 0x1000) / max_t(int, win->out_w - 1, 1);
665                 v_dda = ((win->h - 1) * 0x1000) / max_t(int, win->out_h - 1, 1);
666                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
667                                 DC_WIN_DDA_INCREMENT);
668                 tegra_dc_writel(dc, 0, DC_WIN_H_INITIAL_DDA);
669                 tegra_dc_writel(dc, 0, DC_WIN_V_INITIAL_DDA);
670
671                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
672                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
673                 tegra_dc_writel(dc,
674                                 (unsigned long)win->phys_addr +
675                                 (unsigned long)win->offset,
676                                 DC_WINBUF_START_ADDR);
677
678                 if (!yuvp) {
679                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
680                 } else {
681                         tegra_dc_writel(dc,
682                                         (unsigned long)win->phys_addr +
683                                         (unsigned long)win->offset_u,
684                                         DC_WINBUF_START_ADDR_U);
685                         tegra_dc_writel(dc,
686                                         (unsigned long)win->phys_addr +
687                                         (unsigned long)win->offset_v,
688                                         DC_WINBUF_START_ADDR_V);
689                         tegra_dc_writel(dc,
690                                         LINE_STRIDE(win->stride) |
691                                         UV_LINE_STRIDE(win->stride_uv),
692                                         DC_WIN_LINE_STRIDE);
693                 }
694
695                 h_offset = win->x;
696                 if (invert_h) {
697                         h_offset += win->w - 1;
698                 }
699                 h_offset *= tegra_dc_fmt_bpp(win->fmt) / 8;
700
701                 v_offset = win->y;
702                 if (invert_v) {
703                         v_offset += win->h - 1;
704                 }
705
706                 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
707                 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
708
709                 if (win->flags & TEGRA_WIN_FLAG_TILED)
710                         tegra_dc_writel(dc,
711                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
712                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
713                                         DC_WIN_BUFFER_ADDR_MODE);
714                 else
715                         tegra_dc_writel(dc,
716                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
717                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
718                                         DC_WIN_BUFFER_ADDR_MODE);
719
720                 val = WIN_ENABLE;
721                 if (yuvp)
722                         val |= CSC_ENABLE;
723                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
724                         val |= COLOR_EXPAND;
725
726                 if (win->w != win->out_w)
727                         val |= H_FILTER_ENABLE;
728                 if (win->h != win->out_h)
729                         val |= V_FILTER_ENABLE;
730
731                 if (invert_h)
732                         val |= H_DIRECTION_DECREMENT;
733                 if (invert_v)
734                         val |= V_DIRECTION_DECREMENT;
735
736                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
737
738                 win->dirty = no_vsync ? 0 : 1;
739         }
740
741         if (update_blend) {
742                 tegra_dc_set_blending(dc, &dc->blend);
743                 for (i = 0; i < DC_N_WINDOWS; i++) {
744                         if (!no_vsync)
745                                 dc->windows[i].dirty = 1;
746                         update_mask |= WIN_A_ACT_REQ << i;
747                 }
748         }
749
750         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
751
752         if (!no_vsync) {
753                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
754                 val |= FRAME_END_INT;
755                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
756
757                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
758                 val |= FRAME_END_INT;
759                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
760         }
761
762         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768 EXPORT_SYMBOL(tegra_dc_update_windows);
769
770 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc)
771 {
772         return dc->syncpt_id;
773 }
774 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
775
776 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc)
777 {
778         u32 max;
779
780         mutex_lock(&dc->lock);
781         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt, dc->syncpt_id,
782                                         ((dc->enabled) ? 1 : 0) );
783         dc->syncpt_max = max;
784         mutex_unlock(&dc->lock);
785
786         return max;
787 }
788
789 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val)
790 {
791         mutex_lock(&dc->lock);
792         if ( dc->enabled )
793                 while (dc->syncpt_min < val) {
794                         dc->syncpt_min++;
795                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
796                                 dc->syncpt_id);
797                 }
798         mutex_unlock(&dc->lock);
799 }
800
801 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
802                                              int n)
803 {
804         int i;
805
806         for (i = 0; i < n; i++) {
807                 if (windows[i]->dirty)
808                         return false;
809         }
810
811         return true;
812 }
813
814 /* does not support syncing windows on multiple dcs in one call */
815 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
816 {
817         if (n < 1 || n > DC_N_WINDOWS)
818                 return -EINVAL;
819
820         if (!windows[0]->dc->enabled)
821                 return -EFAULT;
822
823         return wait_event_interruptible_timeout(windows[0]->dc->wq,
824                                          tegra_dc_windows_are_clean(windows, n),
825                                          HZ);
826 }
827 EXPORT_SYMBOL(tegra_dc_sync_windows);
828
829 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
830 {
831 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
832         return 27000000;
833 #else
834         return clk_get_rate(dc->clk);
835 #endif
836 }
837
838 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
839 {
840         unsigned long rate;
841         unsigned long div;
842
843         rate = tegra_dc_clk_get_rate(dc);
844
845         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
846
847         if (div < 2)
848                 return 0;
849
850         return rate * 2 / div;
851 }
852
853 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
854 {
855         int pclk;
856
857         if (dc->out->type == TEGRA_DC_OUT_RGB) {
858                 struct clk *parent_clk =
859                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
860
861                 if (clk_get_parent(clk) != parent_clk)
862                         clk_set_parent(clk, parent_clk);
863         }
864
865         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
866                 unsigned long rate;
867                 struct clk *pll_d_out0_clk =
868                         clk_get_sys(NULL, "pll_d_out0");
869                 struct clk *pll_d_clk =
870                         clk_get_sys(NULL, "pll_d");
871
872                 if (dc->mode.pclk > 70000000)
873                         rate = 594000000;
874                 else
875                         rate = 216000000;
876
877                 if (rate != clk_get_rate(pll_d_clk))
878                         clk_set_rate(pll_d_clk, rate);
879
880                 if (clk_get_parent(clk) != pll_d_out0_clk)
881                         clk_set_parent(clk, pll_d_out0_clk);
882         }
883
884         if (dc->out->type == TEGRA_DC_OUT_DSI) {
885                 unsigned long rate;
886                 struct clk *pll_d_out0_clk;
887                 struct clk *pll_d_clk;
888
889                 if (clk == dc->clk) {
890                         pll_d_out0_clk = clk_get_sys(NULL, "pll_d_out0");
891                         pll_d_clk = clk_get_sys(NULL, "pll_d");
892                 } else {
893                         if (dc->pdata->default_out->dsi->dsi_instance) {
894                                 pll_d_out0_clk = clk_get_sys(NULL, "pll_d2_out0");
895                                 pll_d_clk = clk_get_sys(NULL, "pll_d2");
896                                 tegra_clk_cfg_ex(pll_d_clk, TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
897                         } else {
898                                 pll_d_out0_clk = clk_get_sys(NULL, "pll_d_out0");
899                                 pll_d_clk = clk_get_sys(NULL, "pll_d");
900                         }
901                 }
902
903                 rate = dc->mode.pclk;
904                 if (rate != clk_get_rate(pll_d_clk))
905                         clk_set_rate(pll_d_clk, rate);
906
907                 if (clk_get_parent(clk) != pll_d_out0_clk)
908                         clk_set_parent(clk, pll_d_out0_clk);
909         }
910
911         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
912         tegra_dvfs_set_rate(clk, pclk);
913 }
914
915 /* return non-zero if constraint is violated */
916 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
917 {
918         long a, b;
919
920         /* Constraint 5: H_REF_TO_SYNC >= 0 */
921         a = 0;
922
923         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
924         b = mode->h_front_porch - 1;
925
926         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
927         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
928                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
929         /* check Constraint 1 and 6 */
930         if (a > b)
931                 return 1;
932
933         /* Constraint 4: H_SYNC_WIDTH >= 1 */
934         if (mode->h_sync_width < 1)
935                 return 4;
936
937         /* Constraint 7: H_DISP_ACTIVE >= 16 */
938         if (mode->h_active < 16)
939                 return 7;
940
941         if (href) {
942                 if (b > a && a % 2)
943                         *href = a + 1; /* use smallest even value */
944                 else
945                         *href = a; /* even or only possible value */
946         }
947
948         return 0;
949 }
950
951 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
952 {
953         long a;
954         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
955
956         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
957         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
958                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
959
960         /* Constraint 6 */
961         if (mode->v_front_porch < a + 1)
962                 a = mode->v_front_porch - 1;
963
964         /* Constraint 4: V_SYNC_WIDTH >= 1 */
965         if (mode->v_sync_width < 1)
966                 return 4;
967
968         /* Constraint 7: V_DISP_ACTIVE >= 16 */
969         if (mode->v_active < 16)
970                 return 7;
971
972         if (vref)
973                 *vref = a;
974         return 0;
975 }
976
977 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
978 {
979         int ret;
980         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
981         if (ret)
982                 return ret;
983         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
984         if (ret)
985                 return ret;
986
987         return 0;
988 }
989
990 #ifdef DEBUG
991 /* return in 1000ths of a Hertz */
992 static int calc_refresh(const struct tegra_dc_mode *m)
993 {
994         long h_total, v_total, refresh;
995         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
996                 m->h_sync_width;
997         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
998                 m->v_sync_width;
999         refresh = m->pclk / h_total;
1000         refresh *= 1000;
1001         refresh /= v_total;
1002         return refresh;
1003 }
1004
1005 static void print_mode(struct tegra_dc *dc,
1006                         const struct tegra_dc_mode *mode, const char *note)
1007 {
1008         if (mode) {
1009                 int refresh = calc_refresh(mode);
1010                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1011                         note ? note : "",
1012                         mode->h_active, mode->v_active,
1013                         refresh / 1000, refresh % 1000,
1014                         mode->pclk);
1015         }
1016 }
1017 #else /* !DEBUG */
1018 static inline void print_mode(struct tegra_dc *dc,
1019                         const struct tegra_dc_mode *mode, const char *note) { }
1020 #endif /* DEBUG */
1021
1022 static inline void enable_dc_irq(unsigned int irq)
1023 {
1024 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1025         /* Always disable DC interrupts on FPGA. */
1026         disable_irq(irq);
1027 #else
1028         enable_irq(irq);
1029 #endif
1030 }
1031
1032 static inline void disable_dc_irq(unsigned int irq)
1033 {
1034         disable_irq(irq);
1035 }
1036
1037 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1038 {
1039         unsigned long val;
1040         unsigned long rate;
1041         unsigned long div;
1042         unsigned long pclk;
1043
1044         print_mode(dc, mode, __func__);
1045
1046         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1047         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1048                         DC_DISP_REF_TO_SYNC);
1049         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1050                         DC_DISP_SYNC_WIDTH);
1051         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1052                         DC_DISP_BACK_PORCH);
1053         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1054                         DC_DISP_DISP_ACTIVE);
1055         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1056                         DC_DISP_FRONT_PORCH);
1057
1058         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1059                         DC_DISP_DATA_ENABLE_OPTIONS);
1060
1061         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1062         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1063                 val |= PIN1_LVS_OUTPUT;
1064         else
1065                 val &= ~PIN1_LVS_OUTPUT;
1066
1067         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1068                 val |= PIN1_LHS_OUTPUT;
1069         else
1070                 val &= ~PIN1_LHS_OUTPUT;
1071         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1072
1073         /* TODO: MIPI/CRT/HDMI clock cals */
1074
1075         val = DISP_DATA_FORMAT_DF1P1C;
1076
1077         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1078                 val |= DISP_DATA_ALIGNMENT_MSB;
1079         else
1080                 val |= DISP_DATA_ALIGNMENT_LSB;
1081
1082         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1083                 val |= DISP_DATA_ORDER_RED_BLUE;
1084         else
1085                 val |= DISP_DATA_ORDER_BLUE_RED;
1086
1087         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1088
1089         rate = tegra_dc_clk_get_rate(dc);
1090
1091         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1092         if (pclk < (mode->pclk / 100 * 99) ||
1093             pclk > (mode->pclk / 100 * 109)) {
1094                 dev_err(&dc->ndev->dev,
1095                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1096                         rate, mode->pclk,
1097                         pclk, (mode->pclk / 100 * 99),
1098                         (mode->pclk / 100 * 109));
1099                 return -EINVAL;
1100         }
1101
1102         div = (rate * 2 / pclk) - 2;
1103
1104         tegra_dc_writel(dc, 0x00010001,
1105                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1106         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1107                         DC_DISP_DISP_CLOCK_CONTROL);
1108
1109         return 0;
1110 }
1111
1112
1113 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1114 {
1115         memcpy(&dc->mode, mode, sizeof(dc->mode));
1116
1117         print_mode(dc, mode, __func__);
1118
1119         return 0;
1120 }
1121 EXPORT_SYMBOL(tegra_dc_set_mode);
1122
1123 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1124                 const struct fb_videomode *fbmode, bool stereo_mode)
1125 {
1126         struct tegra_dc_mode mode;
1127
1128         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1129         mode.h_sync_width = fbmode->hsync_len;
1130         mode.v_sync_width = fbmode->vsync_len;
1131         mode.h_back_porch = fbmode->left_margin;
1132         mode.v_back_porch = fbmode->upper_margin;
1133         mode.h_active = fbmode->xres;
1134         mode.v_active = fbmode->yres;
1135         mode.h_front_porch = fbmode->right_margin;
1136         mode.v_front_porch = fbmode->lower_margin;
1137         mode.stereo_mode = stereo_mode;
1138         if (calc_ref_to_sync(&mode)) {
1139                 dev_err(&dc->ndev->dev, "bad href/vref values, overriding.\n");
1140                 mode.h_ref_to_sync = 11;
1141                 mode.v_ref_to_sync = 1;
1142         }
1143         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1144                 mode.h_active, mode.v_active, mode.pclk,
1145                 mode.h_ref_to_sync, mode.v_ref_to_sync
1146         );
1147
1148         if (mode.stereo_mode) {
1149                 mode.pclk *= 2;
1150                 /* total v_active = yres*2 + activespace */
1151                 mode.v_active = fbmode->yres*2 +
1152                                 fbmode->vsync_len +
1153                                 fbmode->upper_margin +
1154                                 fbmode->lower_margin;
1155         }
1156
1157         mode.flags = 0;
1158
1159         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1160                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1161
1162         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1163                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1164
1165         return tegra_dc_set_mode(dc, &mode);
1166 }
1167 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1168
1169 void
1170 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1171 {
1172         unsigned int ctrl;
1173         unsigned long out_sel;
1174         unsigned long cmd_state;
1175
1176         mutex_lock(&dc->lock);
1177         if (!dc->enabled) {
1178                 mutex_unlock(&dc->lock);
1179                 return;
1180         }
1181
1182         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1183                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1184                 cfg->clk_select);
1185
1186         /* The new value should be effected immediately */
1187         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1188         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1189
1190         switch (cfg->which_pwm) {
1191         case TEGRA_PWM_PM0:
1192                 /* Select the LM0 on PM0 */
1193                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1194                 out_sel &= ~(7 << 0);
1195                 out_sel |= (3 << 0);
1196                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1197                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1198                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1199                 break;
1200         case TEGRA_PWM_PM1:
1201                 /* Select the LM1 on PM1 */
1202                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1203                 out_sel &= ~(7 << 4);
1204                 out_sel |= (3 << 4);
1205                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1206                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1207                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1208                 break;
1209         default:
1210                 dev_err(&dc->ndev->dev, "Error\n");
1211                 break;
1212         }
1213         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1214         mutex_unlock(&dc->lock);
1215 }
1216 EXPORT_SYMBOL(tegra_dc_config_pwm);
1217
1218 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1219                                 const struct tegra_dc_out_pin *pins,
1220                                 const unsigned int n_pins)
1221 {
1222         unsigned int i;
1223
1224         int name;
1225         int pol;
1226
1227         u32 pol1, pol3;
1228
1229         u32 set1, unset1;
1230         u32 set3, unset3;
1231
1232         set1 = set3 = unset1 = unset3 = 0;
1233
1234         for (i = 0; i < n_pins; i++) {
1235                 name = (pins + i)->name;
1236                 pol  = (pins + i)->pol;
1237
1238                 /* set polarity by name */
1239                 switch (name) {
1240                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1241                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1242                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1243                         else
1244                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1245                         break;
1246                 case TEGRA_DC_OUT_PIN_H_SYNC:
1247                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1248                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1249                         else
1250                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1251                         break;
1252                 case TEGRA_DC_OUT_PIN_V_SYNC:
1253                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1254                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1255                         else
1256                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1257                         break;
1258                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1259                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1260                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1261                         else
1262                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1263                         break;
1264                 default:
1265                         printk("Invalid argument in function %s\n",
1266                                __FUNCTION__);
1267                         break;
1268                 }
1269         }
1270
1271         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1272         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1273
1274         pol1 |= set1;
1275         pol1 &= ~unset1;
1276
1277         pol3 |= set3;
1278         pol3 &= ~unset3;
1279
1280         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1281         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1282 }
1283
1284 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1285 {
1286         dc->out = out;
1287
1288         if (out->n_modes > 0)
1289                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1290
1291         switch (out->type) {
1292         case TEGRA_DC_OUT_RGB:
1293                 dc->out_ops = &tegra_dc_rgb_ops;
1294                 break;
1295
1296         case TEGRA_DC_OUT_HDMI:
1297                 dc->out_ops = &tegra_dc_hdmi_ops;
1298                 break;
1299
1300         case TEGRA_DC_OUT_DSI:
1301                 dc->out_ops = &tegra_dc_dsi_ops;
1302                 break;
1303
1304         default:
1305                 dc->out_ops = NULL;
1306                 break;
1307         }
1308
1309         if (dc->out_ops && dc->out_ops->init)
1310                 dc->out_ops->init(dc);
1311
1312 }
1313
1314 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1315 {
1316         if (dc->out)
1317                 return dc->out->height;
1318         else
1319                 return 0;
1320 }
1321 EXPORT_SYMBOL(tegra_dc_get_out_height);
1322
1323 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1324 {
1325         if (dc->out)
1326                 return dc->out->width;
1327         else
1328                 return 0;
1329 }
1330 EXPORT_SYMBOL(tegra_dc_get_out_width);
1331
1332 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1333 {
1334         if (dc->out && dc->out->max_pixclock)
1335                 return dc->out->max_pixclock;
1336         else
1337                 return 0;
1338 }
1339 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1340
1341 static void tegra_dc_vblank(struct work_struct *work)
1342 {
1343         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1344         bool nvsd_updated = false;
1345
1346         mutex_lock(&dc->lock);
1347
1348         /* Update the SD brightness */
1349         nvsd_updated = nvsd_update_brightness(dc);
1350
1351         mutex_unlock(&dc->lock);
1352
1353         /* Do the actual brightness update outside of the mutex */
1354         if (nvsd_updated && dc->out->sd_settings &&
1355             dc->out->sd_settings->bl_device) {
1356
1357                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1358                 struct backlight_device *bl = platform_get_drvdata(pdev);
1359                 if (bl)
1360                         backlight_update_status(bl);
1361         }
1362 }
1363
1364 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1365 {
1366 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1367         struct tegra_dc *dc = ptr;
1368         unsigned long status;
1369         unsigned long val;
1370         unsigned long underflow_mask;
1371         int i;
1372
1373         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1374         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1375
1376         /*
1377          * Overlays can get thier internal state corrupted during and underflow
1378          * condition.  The only way to fix this state is to reset the DC.
1379          * if we get 4 consecutive frames with underflows, assume we're
1380          * hosed and reset.
1381          */
1382         underflow_mask = status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1383
1384         if (underflow_mask) {
1385                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1386                 val |= V_BLANK_INT;
1387                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1388                 dc->underflow_mask |= underflow_mask;
1389                 dc->stats.underflows++;
1390                 if (status & WIN_A_UF_INT)
1391                         dc->stats.underflows_a++;
1392                 if (status & WIN_B_UF_INT)
1393                         dc->stats.underflows_b++;
1394                 if (status & WIN_C_UF_INT)
1395                         dc->stats.underflows_c++;
1396         }
1397
1398         if (status & V_BLANK_INT) {
1399                 int i;
1400
1401                 /* Check for any underflow reset conditions */
1402                 for (i = 0; i< DC_N_WINDOWS; i++) {
1403                         if (dc->underflow_mask & (WIN_A_UF_INT <<i)) {
1404                                 dc->windows[i].underflows++;
1405
1406 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1407                                 if (dc->windows[i].underflows > 4)
1408                                         schedule_work(&dc->reset_work);
1409 #endif
1410                         } else {
1411                                 dc->windows[i].underflows = 0;
1412                         }
1413                 }
1414
1415                 if (!dc->underflow_mask) {
1416                         /* If we have no underflow to check, go ahead
1417                            and disable the interrupt */
1418                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1419                         val &= ~V_BLANK_INT;
1420                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1421                 }
1422
1423                 /* Clear the underflow mask now that we've checked it. */
1424                 dc->underflow_mask = 0;
1425
1426                 /* Schedule any additional bottom-half vblank actvities. */
1427                 schedule_work(&dc->vblank_work);
1428
1429                 /* Mark the vblank as complete. */
1430                 complete(&dc->vblank_complete);
1431         }
1432
1433         if (status & FRAME_END_INT) {
1434                 int completed = 0;
1435                 int dirty = 0;
1436
1437                 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1438                 for (i = 0; i < DC_N_WINDOWS; i++) {
1439                         if (!(val & (WIN_A_UPDATE << i))) {
1440                                 dc->windows[i].dirty = 0;
1441                                 completed = 1;
1442                         } else {
1443                                 dirty = 1;
1444                         }
1445                 }
1446
1447                 if (!dirty) {
1448                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1449                         val &= ~FRAME_END_INT;
1450                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1451                 }
1452
1453                 if (completed) {
1454                         if (!dirty) {
1455                                 /* With the last completed window, go ahead
1456                                    and enable the vblank interrupt for nvsd. */
1457                                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1458                                 val |= V_BLANK_INT;
1459                                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1460
1461                                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1462                                 val |= V_BLANK_INT;
1463                                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1464                         }
1465
1466                         /* Wake up the workqueue regardless. */
1467                         wake_up(&dc->wq);
1468                 }
1469         }
1470
1471         return IRQ_HANDLED;
1472 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1473         return IRQ_NONE;
1474 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1475 }
1476
1477 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1478 {
1479         u32 color_control;
1480
1481         switch (dc->out->depth) {
1482         case 3:
1483                 color_control = BASE_COLOR_SIZE111;
1484                 break;
1485
1486         case 6:
1487                 color_control = BASE_COLOR_SIZE222;
1488                 break;
1489
1490         case 8:
1491                 color_control = BASE_COLOR_SIZE332;
1492                 break;
1493
1494         case 9:
1495                 color_control = BASE_COLOR_SIZE333;
1496                 break;
1497
1498         case 12:
1499                 color_control = BASE_COLOR_SIZE444;
1500                 break;
1501
1502         case 15:
1503                 color_control = BASE_COLOR_SIZE555;
1504                 break;
1505
1506         case 16:
1507                 color_control = BASE_COLOR_SIZE565;
1508                 break;
1509
1510         case 18:
1511                 color_control = BASE_COLOR_SIZE666;
1512                 break;
1513
1514         default:
1515                 color_control = BASE_COLOR_SIZE888;
1516                 break;
1517         }
1518
1519         switch (dc->out->dither) {
1520         case TEGRA_DC_DISABLE_DITHER:
1521                 color_control |= DITHER_CONTROL_DISABLE;
1522                 break;
1523         case TEGRA_DC_ORDERED_DITHER:
1524                 color_control |= DITHER_CONTROL_ORDERED;
1525                 break;
1526         case TEGRA_DC_ERRDIFF_DITHER:
1527                 /* The line buffer for error-diffusion dither is limited
1528                  * to 640 pixels per line. This limits the maximum
1529                  * horizontal active area size to 640 pixels when error
1530                  * diffusion is enabled.
1531                  */
1532                 BUG_ON(dc->mode.h_active > 640);
1533                 color_control |= DITHER_CONTROL_ERRDIFF;
1534                 break;
1535         }
1536
1537         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1538 }
1539
1540 static void tegra_dc_init(struct tegra_dc *dc)
1541 {
1542         u32 disp_syncpt = 0;
1543         u32 vblank_syncpt = 0;
1544         int i;
1545
1546         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1547         if (dc->ndev->id == 0) {
1548                 disp_syncpt = NVSYNCPT_DISP0;
1549                 vblank_syncpt = NVSYNCPT_VBLANK0;
1550
1551                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1552                                       TEGRA_MC_PRIO_MED);
1553                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1554                                       TEGRA_MC_PRIO_MED);
1555                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1556                                       TEGRA_MC_PRIO_MED);
1557                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1558                                       TEGRA_MC_PRIO_MED);
1559                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1560                                       TEGRA_MC_PRIO_HIGH);
1561         } else if (dc->ndev->id == 1) {
1562                 disp_syncpt = NVSYNCPT_DISP1;
1563                 vblank_syncpt = NVSYNCPT_VBLANK1;
1564
1565                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1566                                       TEGRA_MC_PRIO_MED);
1567                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1568                                       TEGRA_MC_PRIO_MED);
1569                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1570                                       TEGRA_MC_PRIO_MED);
1571                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1572                                       TEGRA_MC_PRIO_MED);
1573                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1574                                       TEGRA_MC_PRIO_HIGH);
1575         }
1576         tegra_dc_writel(dc, 0x00000100 | vblank_syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1577         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1578         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1579         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1580         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1581
1582         tegra_dc_writel(dc, (FRAME_END_INT |
1583                              V_BLANK_INT |
1584                              WIN_A_UF_INT |
1585                              WIN_B_UF_INT |
1586                              WIN_C_UF_INT), DC_CMD_INT_MASK);
1587         tegra_dc_writel(dc, (WIN_A_UF_INT |
1588                              WIN_B_UF_INT |
1589                              WIN_C_UF_INT), DC_CMD_INT_ENABLE);
1590
1591         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1592
1593         tegra_dc_set_color_control(dc);
1594         for (i = 0; i < DC_N_WINDOWS; i++) {
1595                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1596                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1597                 tegra_dc_set_csc(dc);
1598                 tegra_dc_set_scaling_filter(dc);
1599         }
1600
1601
1602         dc->syncpt_id = disp_syncpt;
1603
1604         dc->syncpt_min = dc->syncpt_max =
1605                 nvhost_syncpt_read(&dc->ndev->host->syncpt, disp_syncpt);
1606
1607         print_mode(dc, &dc->mode, __func__);
1608
1609         if (dc->mode.pclk)
1610                 tegra_dc_program_mode(dc, &dc->mode);
1611
1612         /* Initialize SD AFTER the modeset.
1613            nvsd_init handles the sd_settings = NULL case. */
1614         nvsd_init(dc, dc->out->sd_settings);
1615 }
1616
1617 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1618 {
1619         if (dc->out->enable)
1620                 dc->out->enable();
1621
1622         tegra_dc_setup_clk(dc, dc->clk);
1623         tegra_periph_reset_assert(dc->clk);
1624         clk_enable(dc->clk);
1625         clk_enable(dc->emc_clk);
1626         enable_dc_irq(dc->irq);
1627
1628         tegra_dc_init(dc);
1629
1630         if (dc->out_ops && dc->out_ops->enable)
1631                 dc->out_ops->enable(dc);
1632
1633         if (dc->out->out_pins)
1634                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1635                                             dc->out->n_out_pins);
1636
1637         if (dc->out->postpoweron)
1638                 dc->out->postpoweron();
1639
1640         /* force a full blending update */
1641         dc->blend.z[0] = -1;
1642
1643         return true;
1644 }
1645
1646 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1647 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1648 {
1649         if (dc->out->enable)
1650                 dc->out->enable();
1651
1652         tegra_dc_setup_clk(dc, dc->clk);
1653         clk_enable(dc->clk);
1654         clk_enable(dc->emc_clk);
1655
1656         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1657                 mutex_lock(&tegra_dcs[1]->lock);
1658                 disable_irq(tegra_dcs[1]->irq);
1659         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1660                 mutex_lock(&tegra_dcs[0]->lock);
1661                 disable_irq(tegra_dcs[0]->irq);
1662         }
1663
1664         msleep(5);
1665         tegra_periph_reset_assert(dc->clk);
1666         msleep(2);
1667 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1668         tegra_periph_reset_deassert(dc->clk);
1669         msleep(1);
1670 #endif
1671
1672         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1673                 enable_dc_irq(tegra_dcs[1]->irq);
1674                 mutex_unlock(&tegra_dcs[1]->lock);
1675         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1676                 enable_dc_irq(tegra_dcs[0]->irq);
1677                 mutex_unlock(&tegra_dcs[0]->lock);
1678         }
1679
1680         enable_dc_irq(dc->irq);
1681
1682         tegra_dc_init(dc);
1683
1684         if (dc->out_ops && dc->out_ops->enable)
1685                 dc->out_ops->enable(dc);
1686
1687         if (dc->out->out_pins)
1688                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1689                                             dc->out->n_out_pins);
1690
1691         if (dc->out->postpoweron)
1692                 dc->out->postpoweron();
1693
1694         /* force a full blending update */
1695         dc->blend.z[0] = -1;
1696
1697         return true;
1698 }
1699 #endif
1700
1701 static bool _tegra_dc_enable(struct tegra_dc *dc)
1702 {
1703         if (dc->mode.pclk == 0)
1704                 return false;
1705
1706         if (!dc->out)
1707                 return false;
1708
1709         tegra_dc_io_start(dc);
1710
1711         return _tegra_dc_controller_enable(dc);
1712 }
1713
1714 void tegra_dc_enable(struct tegra_dc *dc)
1715 {
1716         mutex_lock(&dc->lock);
1717
1718         if (!dc->enabled)
1719                 dc->enabled = _tegra_dc_enable(dc);
1720
1721         mutex_unlock(&dc->lock);
1722 }
1723
1724 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1725 {
1726         disable_irq(dc->irq);
1727
1728         if (dc->out_ops && dc->out_ops->disable)
1729                 dc->out_ops->disable(dc);
1730
1731         clk_disable(dc->emc_clk);
1732         clk_disable(dc->clk);
1733         tegra_dvfs_set_rate(dc->clk, 0);
1734
1735         if (dc->out && dc->out->disable)
1736                 dc->out->disable();
1737
1738         /* flush any pending syncpt waits */
1739         while (dc->syncpt_min < dc->syncpt_max) {
1740                 dc->syncpt_min++;
1741                 nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt, dc->syncpt_id);
1742         }
1743 }
1744
1745 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1746 {
1747 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1748         u32 val;
1749         if (dc->enabled)  {
1750                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1751                 if (enable)
1752                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1753                 else
1754                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1755                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1756         }
1757 #endif
1758 }
1759
1760 bool tegra_dc_stats_get(struct tegra_dc *dc)
1761 {
1762 #if 0 /* right now it is always enabled */
1763         u32 val;
1764         bool res;
1765
1766         if (dc->enabled)  {
1767                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1768                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1769         } else {
1770                 res = false;
1771         }
1772
1773         return res;
1774 #endif
1775         return true;
1776 }
1777
1778 static void _tegra_dc_disable(struct tegra_dc *dc)
1779 {
1780         _tegra_dc_controller_disable(dc);
1781         tegra_dc_io_end(dc);
1782 }
1783
1784 void tegra_dc_disable(struct tegra_dc *dc)
1785 {
1786         if (dc->overlay)
1787                 tegra_overlay_disable(dc->overlay);
1788
1789         mutex_lock(&dc->lock);
1790
1791         if (dc->enabled) {
1792                 dc->enabled = false;
1793
1794                 if (!dc->suspended)
1795                         _tegra_dc_disable(dc);
1796         }
1797
1798         mutex_unlock(&dc->lock);
1799 }
1800
1801 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1802 static void tegra_dc_reset_worker(struct work_struct *work)
1803 {
1804         struct tegra_dc *dc =
1805                 container_of(work, struct tegra_dc, reset_work);
1806
1807         unsigned long val = 0;
1808
1809         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
1810
1811         mutex_lock(&shared_lock);
1812         mutex_lock(&dc->lock);
1813
1814         if (dc->enabled == false)
1815                 goto unlock;
1816
1817         dc->enabled = false;
1818
1819         /*
1820          * off host read bus
1821          */
1822         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1823         val &= ~(0x00000100);
1824         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1825
1826         /*
1827          * set DC to STOP mode
1828          */
1829         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1830
1831         msleep(10);
1832
1833         _tegra_dc_controller_disable(dc);
1834
1835         /* _tegra_dc_controller_reset_enable deasserts reset */
1836         _tegra_dc_controller_reset_enable(dc);
1837
1838         dc->enabled = true;
1839 unlock:
1840         mutex_unlock(&dc->lock);
1841         mutex_unlock(&shared_lock);
1842 }
1843 #endif
1844
1845
1846 static int tegra_dc_probe(struct nvhost_device *ndev)
1847 {
1848         struct tegra_dc *dc;
1849         struct clk *clk;
1850         struct clk *emc_clk;
1851         struct resource *res;
1852         struct resource *base_res;
1853         struct resource *fb_mem = NULL;
1854         int ret = 0;
1855         void __iomem *base;
1856         int irq;
1857         int i;
1858         unsigned long emc_clk_rate;
1859
1860         if (!ndev->dev.platform_data) {
1861                 dev_err(&ndev->dev, "no platform data\n");
1862                 return -ENOENT;
1863         }
1864
1865         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1866         if (!dc) {
1867                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1868                 return -ENOMEM;
1869         }
1870
1871         irq = nvhost_get_irq_byname(ndev, "irq");
1872         if (irq <= 0) {
1873                 dev_err(&ndev->dev, "no irq\n");
1874                 ret = -ENOENT;
1875                 goto err_free;
1876         }
1877
1878         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1879         if (!res) {
1880                 dev_err(&ndev->dev, "no mem resource\n");
1881                 ret = -ENOENT;
1882                 goto err_free;
1883         }
1884
1885         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
1886         if (!base_res) {
1887                 dev_err(&ndev->dev, "request_mem_region failed\n");
1888                 ret = -EBUSY;
1889                 goto err_free;
1890         }
1891
1892         base = ioremap(res->start, resource_size(res));
1893         if (!base) {
1894                 dev_err(&ndev->dev, "registers can't be mapped\n");
1895                 ret = -EBUSY;
1896                 goto err_release_resource_reg;
1897         }
1898
1899         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1900
1901         clk = clk_get(&ndev->dev, NULL);
1902         if (IS_ERR_OR_NULL(clk)) {
1903                 dev_err(&ndev->dev, "can't get clock\n");
1904                 ret = -ENOENT;
1905                 goto err_iounmap_reg;
1906         }
1907
1908         emc_clk = clk_get(&ndev->dev, "emc");
1909         if (IS_ERR_OR_NULL(emc_clk)) {
1910                 dev_err(&ndev->dev, "can't get emc clock\n");
1911                 ret = -ENOENT;
1912                 goto err_put_clk;
1913         }
1914
1915         dc->clk = clk;
1916         dc->emc_clk = emc_clk;
1917         dc->base_res = base_res;
1918         dc->base = base;
1919         dc->irq = irq;
1920         dc->ndev = ndev;
1921         dc->pdata = ndev->dev.platform_data;
1922
1923         /*
1924          * The emc is a shared clock, it will be set based on
1925          * the requirements for each user on the bus.
1926          */
1927         emc_clk_rate = dc->pdata->emc_clk_rate;
1928         clk_set_rate(emc_clk, emc_clk_rate ? emc_clk_rate : ULONG_MAX);
1929
1930         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
1931                 dc->enabled = true;
1932
1933         mutex_init(&dc->lock);
1934         init_completion(&dc->vblank_complete);
1935         init_waitqueue_head(&dc->wq);
1936 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1937         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1938 #endif
1939         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1940
1941         dc->n_windows = DC_N_WINDOWS;
1942         for (i = 0; i < dc->n_windows; i++) {
1943                 dc->windows[i].idx = i;
1944                 dc->windows[i].dc = dc;
1945         }
1946
1947         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
1948                         dev_name(&ndev->dev), dc)) {
1949                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1950                 ret = -EBUSY;
1951                 goto err_put_emc_clk;
1952         }
1953
1954         /* hack to balance enable_irq calls in _tegra_dc_enable() */
1955         disable_dc_irq(dc->irq);
1956
1957         ret = tegra_dc_add(dc, ndev->id);
1958         if (ret < 0) {
1959                 dev_err(&ndev->dev, "can't add dc\n");
1960                 goto err_free_irq;
1961         }
1962
1963         nvhost_set_drvdata(ndev, dc);
1964
1965         if (dc->pdata->default_out)
1966                 tegra_dc_set_out(dc, dc->pdata->default_out);
1967         else
1968                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1969
1970         mutex_lock(&dc->lock);
1971         if (dc->enabled)
1972                 _tegra_dc_enable(dc);
1973         mutex_unlock(&dc->lock);
1974
1975         tegra_dc_create_debugfs(dc);
1976
1977         dev_info(&ndev->dev, "probed\n");
1978
1979         if (dc->pdata->fb) {
1980                 if (dc->pdata->fb->bits_per_pixel == -1) {
1981                         unsigned long fmt;
1982                         tegra_dc_writel(dc,
1983                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1984                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1985
1986                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1987                         dc->pdata->fb->bits_per_pixel =
1988                                 tegra_dc_fmt_bpp(fmt);
1989                 }
1990
1991                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1992                 if (IS_ERR_OR_NULL(dc->fb))
1993                         dc->fb = NULL;
1994         }
1995
1996         if (dc->fb) {
1997                 dc->overlay = tegra_overlay_register(ndev, dc);
1998                 if (IS_ERR_OR_NULL(dc->overlay))
1999                         dc->overlay = NULL;
2000         }
2001
2002         if (dc->out && dc->out->hotplug_init)
2003                 dc->out->hotplug_init();
2004
2005         if (dc->out_ops && dc->out_ops->detect)
2006                 dc->out_ops->detect(dc);
2007
2008         tegra_dc_create_sysfs(&dc->ndev->dev);
2009
2010         return 0;
2011
2012 err_free_irq:
2013         free_irq(irq, dc);
2014 err_put_emc_clk:
2015         clk_put(emc_clk);
2016 err_put_clk:
2017         clk_put(clk);
2018 err_iounmap_reg:
2019         iounmap(base);
2020         if (fb_mem)
2021                 release_resource(fb_mem);
2022 err_release_resource_reg:
2023         release_resource(base_res);
2024 err_free:
2025         kfree(dc);
2026
2027         return ret;
2028 }
2029
2030 static int tegra_dc_remove(struct nvhost_device *ndev)
2031 {
2032         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2033
2034         tegra_dc_remove_sysfs(&dc->ndev->dev);
2035         tegra_dc_remove_debugfs(dc);
2036
2037         if (dc->overlay) {
2038                 tegra_overlay_unregister(dc->overlay);
2039         }
2040
2041         if (dc->fb) {
2042                 tegra_fb_unregister(dc->fb);
2043                 if (dc->fb_mem)
2044                         release_resource(dc->fb_mem);
2045         }
2046
2047
2048         if (dc->enabled)
2049                 _tegra_dc_disable(dc);
2050
2051         free_irq(dc->irq, dc);
2052         clk_put(dc->emc_clk);
2053         clk_put(dc->clk);
2054         iounmap(dc->base);
2055         if (dc->fb_mem)
2056                 release_resource(dc->base_res);
2057         kfree(dc);
2058         return 0;
2059 }
2060
2061 #ifdef CONFIG_PM
2062 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2063 {
2064         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2065
2066         dev_info(&ndev->dev, "suspend\n");
2067
2068         if (dc->overlay)
2069                 tegra_overlay_disable(dc->overlay);
2070
2071         mutex_lock(&dc->lock);
2072
2073         if (dc->out_ops && dc->out_ops->suspend)
2074                 dc->out_ops->suspend(dc);
2075
2076         if (dc->enabled) {
2077                 tegra_fb_suspend(dc->fb);
2078                 _tegra_dc_disable(dc);
2079
2080                 dc->suspended = true;
2081         }
2082
2083         if (dc->out && dc->out->postsuspend) {
2084                 dc->out->postsuspend();
2085                 msleep(100); /* avoid resume event due to voltage falling */
2086         }
2087
2088         mutex_unlock(&dc->lock);
2089
2090         return 0;
2091 }
2092
2093 static int tegra_dc_resume(struct nvhost_device *ndev)
2094 {
2095         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2096
2097         dev_info(&ndev->dev, "resume\n");
2098
2099         mutex_lock(&dc->lock);
2100         dc->suspended = false;
2101
2102         if (dc->enabled)
2103                 _tegra_dc_enable(dc);
2104
2105         if (dc->out && dc->out->hotplug_init)
2106                 dc->out->hotplug_init();
2107
2108         if (dc->out_ops && dc->out_ops->resume)
2109                 dc->out_ops->resume(dc);
2110         mutex_unlock(&dc->lock);
2111
2112         return 0;
2113 }
2114
2115 #endif /* CONFIG_PM */
2116
2117 extern int suspend_set(const char *val, struct kernel_param *kp)
2118 {
2119         if (!strcmp(val, "dump"))
2120                 dump_regs(tegra_dcs[0]);
2121 #ifdef CONFIG_PM
2122         else if (!strcmp(val, "suspend"))
2123                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2124         else if (!strcmp(val, "resume"))
2125                 tegra_dc_resume(tegra_dcs[0]->ndev);
2126 #endif
2127
2128         return 0;
2129 }
2130
2131 extern int suspend_get(char *buffer, struct kernel_param *kp)
2132 {
2133         return 0;
2134 }
2135
2136 int suspend;
2137
2138 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2139
2140 struct nvhost_driver tegra_dc_driver = {
2141         .driver = {
2142                 .name = "tegradc",
2143                 .owner = THIS_MODULE,
2144         },
2145         .probe = tegra_dc_probe,
2146         .remove = tegra_dc_remove,
2147 #ifdef CONFIG_PM
2148         .suspend = tegra_dc_suspend,
2149         .resume = tegra_dc_resume,
2150 #endif
2151 };
2152
2153 static int __init tegra_dc_module_init(void)
2154 {
2155         return nvhost_driver_register(&tegra_dc_driver);
2156 }
2157
2158 static void __exit tegra_dc_module_exit(void)
2159 {
2160         nvhost_driver_unregister(&tegra_dc_driver);
2161 }
2162
2163 module_exit(tegra_dc_module_exit);
2164 module_init(tegra_dc_module_init);