video: tegra: add device tree support for DC
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2013, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43 #include <linux/of_irq.h>
44 #include <linux/of_address.h>
45
46 #define CREATE_TRACE_POINTS
47 #include <trace/events/display.h>
48
49 #include <mach/clk.h>
50 #include <mach/dc.h>
51 #include <mach/fb.h>
52 #include <mach/mc.h>
53 #include <linux/nvhost.h>
54 #include <mach/latency_allowance.h>
55 #include <mach/iomap.h>
56
57 #include "dc_reg.h"
58 #include "dc_config.h"
59 #include "dc_priv.h"
60 #include "dev.h"
61 #include "nvsd.h"
62
63 #define TEGRA_CRC_LATCHED_DELAY         34
64
65 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
66 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
67
68 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
69         .refresh = 60,
70         .xres = 640,
71         .yres = 480,
72         .pixclock = KHZ2PICOS(25200),
73         .hsync_len = 96,        /* h_sync_width */
74         .vsync_len = 2,         /* v_sync_width */
75         .left_margin = 48,      /* h_back_porch */
76         .upper_margin = 33,     /* v_back_porch */
77         .right_margin = 16,     /* h_front_porch */
78         .lower_margin = 10,     /* v_front_porch */
79         .vmode = 0,
80         .sync = 0,
81 };
82
83 static struct tegra_dc_mode override_disp_mode[3];
84
85 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
86
87 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
88
89 DEFINE_MUTEX(tegra_dc_lock);
90 DEFINE_MUTEX(shared_lock);
91
92 static const struct {
93         bool h;
94         bool v;
95 } can_filter[] = {
96         /* Window A has no filtering */
97         { false, false },
98         /* Window B has both H and V filtering */
99         { true,  true  },
100         /* Window C has only H filtering */
101         { false, true  },
102 };
103
104 #ifdef CONFIG_TEGRA_DC_CMU
105 static struct tegra_dc_cmu default_cmu = {
106         /* lut1 maps sRGB to linear space. */
107         {
108                 0,    1,    2,    4,    5,    6,    7,    9,
109                 10,   11,   12,   14,   15,   16,   18,   20,
110                 21,   23,   25,   27,   29,   31,   33,   35,
111                 37,   40,   42,   45,   48,   50,   53,   56,
112                 59,   62,   66,   69,   72,   76,   79,   83,
113                 87,   91,   95,   99,   103,  107,  112,  116,
114                 121,  126,  131,  136,  141,  146,  151,  156,
115                 162,  168,  173,  179,  185,  191,  197,  204,
116                 210,  216,  223,  230,  237,  244,  251,  258,
117                 265,  273,  280,  288,  296,  304,  312,  320,
118                 329,  337,  346,  354,  363,  372,  381,  390,
119                 400,  409,  419,  428,  438,  448,  458,  469,
120                 479,  490,  500,  511,  522,  533,  544,  555,
121                 567,  578,  590,  602,  614,  626,  639,  651,
122                 664,  676,  689,  702,  715,  728,  742,  755,
123                 769,  783,  797,  811,  825,  840,  854,  869,
124                 884,  899,  914,  929,  945,  960,  976,  992,
125                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
126                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
127                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
128                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
129                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
130                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
131                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
132                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
133                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
134                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
135                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
136                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
137                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
138                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
139                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
140         },
141         /* csc */
142         {
143                 0x100, 0x0,   0x0,
144                 0x0,   0x100, 0x0,
145                 0x0,   0x0,   0x100,
146         },
147         /* lut2 maps linear space to sRGB*/
148         {
149                 0,    1,    2,    2,    3,    4,    5,    6,
150                 6,    7,    8,    9,    10,   10,   11,   12,
151                 13,   13,   14,   15,   15,   16,   16,   17,
152                 18,   18,   19,   19,   20,   20,   21,   21,
153                 22,   22,   23,   23,   23,   24,   24,   25,
154                 25,   25,   26,   26,   27,   27,   27,   28,
155                 28,   29,   29,   29,   30,   30,   30,   31,
156                 31,   31,   32,   32,   32,   33,   33,   33,
157                 34,   34,   34,   34,   35,   35,   35,   36,
158                 36,   36,   37,   37,   37,   37,   38,   38,
159                 38,   38,   39,   39,   39,   40,   40,   40,
160                 40,   41,   41,   41,   41,   42,   42,   42,
161                 42,   43,   43,   43,   43,   43,   44,   44,
162                 44,   44,   45,   45,   45,   45,   46,   46,
163                 46,   46,   46,   47,   47,   47,   47,   48,
164                 48,   48,   48,   48,   49,   49,   49,   49,
165                 49,   50,   50,   50,   50,   50,   51,   51,
166                 51,   51,   51,   52,   52,   52,   52,   52,
167                 53,   53,   53,   53,   53,   54,   54,   54,
168                 54,   54,   55,   55,   55,   55,   55,   55,
169                 56,   56,   56,   56,   56,   57,   57,   57,
170                 57,   57,   57,   58,   58,   58,   58,   58,
171                 58,   59,   59,   59,   59,   59,   59,   60,
172                 60,   60,   60,   60,   60,   61,   61,   61,
173                 61,   61,   61,   62,   62,   62,   62,   62,
174                 62,   63,   63,   63,   63,   63,   63,   64,
175                 64,   64,   64,   64,   64,   64,   65,   65,
176                 65,   65,   65,   65,   66,   66,   66,   66,
177                 66,   66,   66,   67,   67,   67,   67,   67,
178                 67,   67,   68,   68,   68,   68,   68,   68,
179                 68,   69,   69,   69,   69,   69,   69,   69,
180                 70,   70,   70,   70,   70,   70,   70,   71,
181                 71,   71,   71,   71,   71,   71,   72,   72,
182                 72,   72,   72,   72,   72,   72,   73,   73,
183                 73,   73,   73,   73,   73,   74,   74,   74,
184                 74,   74,   74,   74,   74,   75,   75,   75,
185                 75,   75,   75,   75,   75,   76,   76,   76,
186                 76,   76,   76,   76,   77,   77,   77,   77,
187                 77,   77,   77,   77,   78,   78,   78,   78,
188                 78,   78,   78,   78,   78,   79,   79,   79,
189                 79,   79,   79,   79,   79,   80,   80,   80,
190                 80,   80,   80,   80,   80,   81,   81,   81,
191                 81,   81,   81,   81,   81,   81,   82,   82,
192                 82,   82,   82,   82,   82,   82,   83,   83,
193                 83,   83,   83,   83,   83,   83,   83,   84,
194                 84,   84,   84,   84,   84,   84,   84,   84,
195                 85,   85,   85,   85,   85,   85,   85,   85,
196                 85,   86,   86,   86,   86,   86,   86,   86,
197                 86,   86,   87,   87,   87,   87,   87,   87,
198                 87,   87,   87,   88,   88,   88,   88,   88,
199                 88,   88,   88,   88,   88,   89,   89,   89,
200                 89,   89,   89,   89,   89,   89,   90,   90,
201                 90,   90,   90,   90,   90,   90,   90,   90,
202                 91,   91,   91,   91,   91,   91,   91,   91,
203                 91,   91,   92,   92,   92,   92,   92,   92,
204                 92,   92,   92,   92,   93,   93,   93,   93,
205                 93,   93,   93,   93,   93,   93,   94,   94,
206                 94,   94,   94,   94,   94,   94,   94,   94,
207                 95,   95,   95,   95,   95,   95,   95,   95,
208                 95,   95,   96,   96,   96,   96,   96,   96,
209                 96,   96,   96,   96,   96,   97,   97,   97,
210                 97,   97,   97,   97,   97,   97,   97,   98,
211                 98,   98,   98,   98,   98,   98,   98,   98,
212                 98,   98,   99,   99,   99,   99,   99,   99,
213                 99,   100,  101,  101,  102,  103,  103,  104,
214                 105,  105,  106,  107,  107,  108,  109,  109,
215                 110,  111,  111,  112,  113,  113,  114,  115,
216                 115,  116,  116,  117,  118,  118,  119,  119,
217                 120,  120,  121,  122,  122,  123,  123,  124,
218                 124,  125,  126,  126,  127,  127,  128,  128,
219                 129,  129,  130,  130,  131,  131,  132,  132,
220                 133,  133,  134,  134,  135,  135,  136,  136,
221                 137,  137,  138,  138,  139,  139,  140,  140,
222                 141,  141,  142,  142,  143,  143,  144,  144,
223                 145,  145,  145,  146,  146,  147,  147,  148,
224                 148,  149,  149,  150,  150,  150,  151,  151,
225                 152,  152,  153,  153,  153,  154,  154,  155,
226                 155,  156,  156,  156,  157,  157,  158,  158,
227                 158,  159,  159,  160,  160,  160,  161,  161,
228                 162,  162,  162,  163,  163,  164,  164,  164,
229                 165,  165,  166,  166,  166,  167,  167,  167,
230                 168,  168,  169,  169,  169,  170,  170,  170,
231                 171,  171,  172,  172,  172,  173,  173,  173,
232                 174,  174,  174,  175,  175,  176,  176,  176,
233                 177,  177,  177,  178,  178,  178,  179,  179,
234                 179,  180,  180,  180,  181,  181,  182,  182,
235                 182,  183,  183,  183,  184,  184,  184,  185,
236                 185,  185,  186,  186,  186,  187,  187,  187,
237                 188,  188,  188,  189,  189,  189,  189,  190,
238                 190,  190,  191,  191,  191,  192,  192,  192,
239                 193,  193,  193,  194,  194,  194,  195,  195,
240                 195,  196,  196,  196,  196,  197,  197,  197,
241                 198,  198,  198,  199,  199,  199,  200,  200,
242                 200,  200,  201,  201,  201,  202,  202,  202,
243                 202,  203,  203,  203,  204,  204,  204,  205,
244                 205,  205,  205,  206,  206,  206,  207,  207,
245                 207,  207,  208,  208,  208,  209,  209,  209,
246                 209,  210,  210,  210,  211,  211,  211,  211,
247                 212,  212,  212,  213,  213,  213,  213,  214,
248                 214,  214,  214,  215,  215,  215,  216,  216,
249                 216,  216,  217,  217,  217,  217,  218,  218,
250                 218,  219,  219,  219,  219,  220,  220,  220,
251                 220,  221,  221,  221,  221,  222,  222,  222,
252                 223,  223,  223,  223,  224,  224,  224,  224,
253                 225,  225,  225,  225,  226,  226,  226,  226,
254                 227,  227,  227,  227,  228,  228,  228,  228,
255                 229,  229,  229,  229,  230,  230,  230,  230,
256                 231,  231,  231,  231,  232,  232,  232,  232,
257                 233,  233,  233,  233,  234,  234,  234,  234,
258                 235,  235,  235,  235,  236,  236,  236,  236,
259                 237,  237,  237,  237,  238,  238,  238,  238,
260                 239,  239,  239,  239,  240,  240,  240,  240,
261                 240,  241,  241,  241,  241,  242,  242,  242,
262                 242,  243,  243,  243,  243,  244,  244,  244,
263                 244,  244,  245,  245,  245,  245,  246,  246,
264                 246,  246,  247,  247,  247,  247,  247,  248,
265                 248,  248,  248,  249,  249,  249,  249,  249,
266                 250,  250,  250,  250,  251,  251,  251,  251,
267                 251,  252,  252,  252,  252,  253,  253,  253,
268                 253,  253,  254,  254,  254,  254,  255,  255,
269         },
270 };
271 #endif
272
273 void tegra_dc_clk_enable(struct tegra_dc *dc)
274 {
275         if (!tegra_is_clk_enabled(dc->clk)) {
276                 clk_prepare_enable(dc->clk);
277                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
278         }
279 }
280
281 void tegra_dc_clk_disable(struct tegra_dc *dc)
282 {
283         if (tegra_is_clk_enabled(dc->clk)) {
284                 clk_disable_unprepare(dc->clk);
285                 tegra_dvfs_set_rate(dc->clk, 0);
286         }
287 }
288
289 void tegra_dc_get(struct tegra_dc *dc)
290 {
291         tegra_dc_io_start(dc);
292
293         /* extra reference to dc clk */
294         clk_prepare_enable(dc->clk);
295 }
296
297 void tegra_dc_put(struct tegra_dc *dc)
298 {
299         /* balance extra dc clk reference */
300         clk_disable_unprepare(dc->clk);
301
302         tegra_dc_io_end(dc);
303 }
304
305 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
306 {
307         tegra_dc_get(dc);
308         if (dc->out_ops && dc->out_ops->hold)
309                 dc->out_ops->hold(dc);
310 }
311
312 void tegra_dc_release_dc_out(struct tegra_dc *dc)
313 {
314         if (dc->out_ops && dc->out_ops->release)
315                 dc->out_ops->release(dc);
316         tegra_dc_put(dc);
317 }
318
319 #define DUMP_REG(a) do {                        \
320         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
321                  #a, a, tegra_dc_readl(dc, a));               \
322         print(data, buff);                                    \
323         } while (0)
324
325 static void _dump_regs(struct tegra_dc *dc, void *data,
326                        void (* print)(void *data, const char *str))
327 {
328         int i;
329         char buff[256];
330
331         mutex_lock(&dc->lock);
332         tegra_dc_get(dc);
333
334         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
335         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
336         DUMP_REG(DC_CMD_SIGNAL_RAISE);
337         DUMP_REG(DC_CMD_INT_STATUS);
338         DUMP_REG(DC_CMD_INT_MASK);
339         DUMP_REG(DC_CMD_INT_ENABLE);
340         DUMP_REG(DC_CMD_INT_TYPE);
341         DUMP_REG(DC_CMD_INT_POLARITY);
342         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
343         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
344         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
345         DUMP_REG(DC_CMD_STATE_ACCESS);
346         DUMP_REG(DC_CMD_STATE_CONTROL);
347         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
348         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
349
350         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
351         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
352         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
353         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
354         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
355         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
356         DUMP_REG(DC_DISP_REF_TO_SYNC);
357         DUMP_REG(DC_DISP_SYNC_WIDTH);
358         DUMP_REG(DC_DISP_BACK_PORCH);
359         DUMP_REG(DC_DISP_DISP_ACTIVE);
360         DUMP_REG(DC_DISP_FRONT_PORCH);
361         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
362         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
363         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
364         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
365         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
366         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
367         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
368         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
369         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
370         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
371         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
372         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
373         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
374         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
375         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
376         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
377         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
378         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
379         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
380         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
381         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
382         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
383         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
384         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
385         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
386         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
387         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
388         DUMP_REG(DC_DISP_M0_CONTROL);
389         DUMP_REG(DC_DISP_M1_CONTROL);
390         DUMP_REG(DC_DISP_DI_CONTROL);
391         DUMP_REG(DC_DISP_PP_CONTROL);
392         DUMP_REG(DC_DISP_PP_SELECT_A);
393         DUMP_REG(DC_DISP_PP_SELECT_B);
394         DUMP_REG(DC_DISP_PP_SELECT_C);
395         DUMP_REG(DC_DISP_PP_SELECT_D);
396         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
397         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
398         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
399         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
400         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
401         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
402         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
403         DUMP_REG(DC_DISP_BORDER_COLOR);
404         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
405         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
406         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
407         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
408         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
409         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
410         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
411         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
412         DUMP_REG(DC_DISP_CURSOR_POSITION);
413         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
414         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
415         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
416         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
417         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
418         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
419         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
420         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
421         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
422         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
423 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
424         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
425 #endif
426         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
427         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
428
429
430         for (i = 0; i < 3; i++) {
431                 print(data, "\n");
432                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
433                 print(data, buff);
434
435                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
436                                 DC_CMD_DISPLAY_WINDOW_HEADER);
437                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
438                 DUMP_REG(DC_WIN_WIN_OPTIONS);
439                 DUMP_REG(DC_WIN_BYTE_SWAP);
440                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
441                 DUMP_REG(DC_WIN_COLOR_DEPTH);
442                 DUMP_REG(DC_WIN_POSITION);
443                 DUMP_REG(DC_WIN_SIZE);
444                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
445                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
446                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
447                 DUMP_REG(DC_WIN_DDA_INCREMENT);
448                 DUMP_REG(DC_WIN_LINE_STRIDE);
449 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
450                 DUMP_REG(DC_WIN_BUF_STRIDE);
451                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
452 #endif
453                 DUMP_REG(DC_WIN_BLEND_NOKEY);
454                 DUMP_REG(DC_WIN_BLEND_1WIN);
455                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
456                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
457                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
458                 DUMP_REG(DC_WINBUF_START_ADDR);
459                 DUMP_REG(DC_WINBUF_START_ADDR_U);
460                 DUMP_REG(DC_WINBUF_START_ADDR_V);
461                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
462                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
463                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
464                 DUMP_REG(DC_WIN_CSC_YOF);
465                 DUMP_REG(DC_WIN_CSC_KYRGB);
466                 DUMP_REG(DC_WIN_CSC_KUR);
467                 DUMP_REG(DC_WIN_CSC_KVR);
468                 DUMP_REG(DC_WIN_CSC_KUG);
469                 DUMP_REG(DC_WIN_CSC_KVG);
470                 DUMP_REG(DC_WIN_CSC_KUB);
471                 DUMP_REG(DC_WIN_CSC_KVB);
472         }
473
474         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
475         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
476         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
477         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
478         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
479         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
480         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
481         DUMP_REG(DC_DISP_M1_CONTROL);
482         DUMP_REG(DC_COM_PM1_CONTROL);
483         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
484         DUMP_REG(DC_DISP_SD_CONTROL);
485 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
486         DUMP_REG(DC_COM_CMU_CSC_KRR);
487         DUMP_REG(DC_COM_CMU_CSC_KGR);
488         DUMP_REG(DC_COM_CMU_CSC_KBR);
489         DUMP_REG(DC_COM_CMU_CSC_KRG);
490         DUMP_REG(DC_COM_CMU_CSC_KGG);
491         DUMP_REG(DC_COM_CMU_CSC_KBR);
492         DUMP_REG(DC_COM_CMU_CSC_KRB);
493         DUMP_REG(DC_COM_CMU_CSC_KGB);
494         DUMP_REG(DC_COM_CMU_CSC_KBB);
495 #endif
496
497         tegra_dc_put(dc);
498         mutex_unlock(&dc->lock);
499 }
500
501 #undef DUMP_REG
502
503 #ifdef DEBUG
504 static void dump_regs_print(void *data, const char *str)
505 {
506         struct tegra_dc *dc = data;
507         dev_dbg(&dc->ndev->dev, "%s", str);
508 }
509
510 static void dump_regs(struct tegra_dc *dc)
511 {
512         _dump_regs(dc, dc, dump_regs_print);
513 }
514 #else /* !DEBUG */
515
516 static void dump_regs(struct tegra_dc *dc) {}
517
518 #endif /* DEBUG */
519
520 #ifdef CONFIG_DEBUG_FS
521
522 static void dbg_regs_print(void *data, const char *str)
523 {
524         struct seq_file *s = data;
525
526         seq_printf(s, "%s", str);
527 }
528
529 #undef DUMP_REG
530
531 static int dbg_dc_show(struct seq_file *s, void *unused)
532 {
533         struct tegra_dc *dc = s->private;
534
535         _dump_regs(dc, s, dbg_regs_print);
536
537         return 0;
538 }
539
540
541 static int dbg_dc_open(struct inode *inode, struct file *file)
542 {
543         return single_open(file, dbg_dc_show, inode->i_private);
544 }
545
546 static const struct file_operations regs_fops = {
547         .open           = dbg_dc_open,
548         .read           = seq_read,
549         .llseek         = seq_lseek,
550         .release        = single_release,
551 };
552
553 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
554 {
555         struct tegra_dc *dc = s->private;
556         struct tegra_dc_mode *m;
557
558         mutex_lock(&dc->lock);
559         m = &dc->mode;
560         seq_printf(s,
561                 "pclk: %d\n"
562                 "h_ref_to_sync: %d\n"
563                 "v_ref_to_sync: %d\n"
564                 "h_sync_width: %d\n"
565                 "v_sync_width: %d\n"
566                 "h_back_porch: %d\n"
567                 "v_back_porch: %d\n"
568                 "h_active: %d\n"
569                 "v_active: %d\n"
570                 "h_front_porch: %d\n"
571                 "v_front_porch: %d\n"
572                 "stereo_mode: %d\n",
573                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
574                 m->h_sync_width, m->v_sync_width,
575                 m->h_back_porch, m->v_back_porch,
576                 m->h_active, m->v_active,
577                 m->h_front_porch, m->v_front_porch,
578                 m->stereo_mode);
579         mutex_unlock(&dc->lock);
580         return 0;
581 }
582
583 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
584 {
585         return single_open(file, dbg_dc_mode_show, inode->i_private);
586 }
587
588 static const struct file_operations mode_fops = {
589         .open           = dbg_dc_mode_open,
590         .read           = seq_read,
591         .llseek         = seq_lseek,
592         .release        = single_release,
593 };
594
595 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
596 {
597         struct tegra_dc *dc = s->private;
598
599         mutex_lock(&dc->lock);
600         seq_printf(s,
601                 "underflows: %llu\n"
602                 "underflows_a: %llu\n"
603                 "underflows_b: %llu\n"
604                 "underflows_c: %llu\n",
605                 dc->stats.underflows,
606                 dc->stats.underflows_a,
607                 dc->stats.underflows_b,
608                 dc->stats.underflows_c);
609         mutex_unlock(&dc->lock);
610
611         return 0;
612 }
613
614 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
615 {
616         return single_open(file, dbg_dc_stats_show, inode->i_private);
617 }
618
619 static const struct file_operations stats_fops = {
620         .open           = dbg_dc_stats_open,
621         .read           = seq_read,
622         .llseek         = seq_lseek,
623         .release        = single_release,
624 };
625
626 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
627 {
628         if (dc->debugdir)
629                 debugfs_remove_recursive(dc->debugdir);
630         dc->debugdir = NULL;
631 }
632
633 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
634 {
635         struct dentry *retval;
636
637         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
638         if (!dc->debugdir)
639                 goto remove_out;
640
641         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
642                 &regs_fops);
643         if (!retval)
644                 goto remove_out;
645
646         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
647                 &mode_fops);
648         if (!retval)
649                 goto remove_out;
650
651         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
652                 &stats_fops);
653         if (!retval)
654                 goto remove_out;
655
656         return;
657 remove_out:
658         dev_err(&dc->ndev->dev, "could not create debugfs\n");
659         tegra_dc_remove_debugfs(dc);
660 }
661
662 #else /* !CONFIG_DEBUGFS */
663 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
664 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
665 #endif /* CONFIG_DEBUGFS */
666
667 static int tegra_dc_set(struct tegra_dc *dc, int index)
668 {
669         int ret = 0;
670
671         mutex_lock(&tegra_dc_lock);
672         if (index >= TEGRA_MAX_DC) {
673                 ret = -EINVAL;
674                 goto out;
675         }
676
677         if (dc != NULL && tegra_dcs[index] != NULL) {
678                 ret = -EBUSY;
679                 goto out;
680         }
681
682         tegra_dcs[index] = dc;
683
684 out:
685         mutex_unlock(&tegra_dc_lock);
686
687         return ret;
688 }
689
690 unsigned int tegra_dc_has_multiple_dc(void)
691 {
692         unsigned int idx;
693         unsigned int cnt = 0;
694         struct tegra_dc *dc;
695
696         mutex_lock(&tegra_dc_lock);
697         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
698                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
699         mutex_unlock(&tegra_dc_lock);
700
701         return (cnt > 1);
702 }
703
704 /* get the stride size of a window.
705  * return: stride size in bytes for window win. or 0 if unavailble. */
706 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
707 {
708         u32 stride;
709
710         if (!dc->enabled)
711                 return 0;
712         BUG_ON(win > DC_N_WINDOWS);
713         mutex_lock(&dc->lock);
714         tegra_dc_get(dc);
715         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
716                 DC_CMD_DISPLAY_WINDOW_HEADER);
717         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
718         tegra_dc_put(dc);
719         mutex_unlock(&dc->lock);
720         return GET_LINE_STRIDE(stride);
721 }
722 EXPORT_SYMBOL(tegra_dc_get_stride);
723
724 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
725 {
726         if (idx < TEGRA_MAX_DC)
727                 return tegra_dcs[idx];
728         else
729                 return NULL;
730 }
731 EXPORT_SYMBOL(tegra_dc_get_dc);
732
733 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
734 {
735         if (win >= dc->n_windows)
736                 return NULL;
737
738         return &dc->windows[win];
739 }
740 EXPORT_SYMBOL(tegra_dc_get_window);
741
742 bool tegra_dc_get_connected(struct tegra_dc *dc)
743 {
744         return dc->connected;
745 }
746 EXPORT_SYMBOL(tegra_dc_get_connected);
747
748 bool tegra_dc_hpd(struct tegra_dc *dc)
749 {
750         int sense;
751         int level;
752         int hpd;
753
754         if (WARN_ON(!dc || !dc->out))
755                 return false;
756
757         if (dc->out->hotplug_state != 0) {
758                 if (dc->out->hotplug_state == 1) /* force on */
759                         return true;
760                 if (dc->out->hotplug_state == -1) /* force off */
761                         return false;
762         }
763         level = gpio_get_value(dc->out->hotplug_gpio);
764
765         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
766
767         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
768                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
769
770         if (dc->out->hotplug_report)
771                 dc->out->hotplug_report(hpd);
772
773         return hpd;
774 }
775 EXPORT_SYMBOL(tegra_dc_hpd);
776
777 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
778 {
779         unsigned i;
780         unsigned v0 = 128;
781         unsigned v1 = 0;
782
783         /* linear horizontal and vertical filters */
784         for (i = 0; i < 16; i++) {
785                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
786                                 DC_WIN_H_FILTER_P(i));
787
788                 tegra_dc_writel(dc, v0,
789                                 DC_WIN_V_FILTER_P(i));
790                 v0 -= 8;
791                 v1 += 8;
792         }
793 }
794
795 #ifdef CONFIG_TEGRA_DC_CMU
796 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
797                                         struct tegra_dc_cmu *src_cmu)
798 {
799         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
800 }
801
802 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
803 {
804         u32 val;
805         u32 i;
806
807         for (i = 0; i < 256; i++) {
808                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
809                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
810         }
811
812         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
813         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
814         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
815         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
816         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
817         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
818         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
819         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
820         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
821
822         for (i = 0; i < 960; i++) {
823                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
824                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
825         }
826 }
827
828 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
829 {
830         u32 val;
831         u32 i;
832         bool flags;
833
834         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
835         if (val & CMU_ENABLE)
836                 flags = true;
837
838         val &= ~CMU_ENABLE;
839         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
840         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
841         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
842
843         /*TODO: Sync up with frame end */
844         mdelay(20);
845
846         for (i = 0; i < 256; i++) {
847                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
848                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
849                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
850                 cmu->lut1[i] = LUT1_READ_DATA(val);
851         }
852
853         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
854         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
855         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
856         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
857         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
858         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
859         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
860         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
861         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
862
863         for (i = 0; i < 960; i++) {
864                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
865                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
866                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
867                 cmu->lut2[i] = LUT2_READ_DATA(val);
868         }
869 }
870 EXPORT_SYMBOL(tegra_dc_get_cmu);
871
872 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
873 {
874         u32 val;
875
876         if (dc->pdata->cmu_enable) {
877                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
878         } else {
879                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
880                 return 0;
881         }
882
883         if (cmu != &dc->cmu) {
884                 tegra_dc_cache_cmu(&dc->cmu, cmu);
885
886                 /* Disable CMU */
887                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
888                 if (val & CMU_ENABLE) {
889                         val &= ~CMU_ENABLE;
890                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
891                         val = GENERAL_UPDATE;
892                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
893                         val = GENERAL_ACT_REQ;
894                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
895                         /*TODO: Sync up with vsync */
896                         mdelay(20);
897                 }
898
899                 tegra_dc_set_cmu(dc, &dc->cmu);
900         }
901
902         return 0;
903 }
904
905 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
906 {
907         int ret;
908
909         mutex_lock(&dc->lock);
910         if (!dc->enabled) {
911                 mutex_unlock(&dc->lock);
912                 return 0;
913         }
914
915         tegra_dc_get(dc);
916
917         ret = _tegra_dc_update_cmu(dc, cmu);
918         tegra_dc_set_color_control(dc);
919
920         tegra_dc_put(dc);
921         mutex_unlock(&dc->lock);
922
923         return ret;
924 }
925 EXPORT_SYMBOL(tegra_dc_update_cmu);
926
927 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
928 {
929         dc->pdata->cmu_enable = cmu_enable;
930         if (dc->pdata->cmu)
931                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
932         else
933                 tegra_dc_update_cmu(dc, &default_cmu);
934 }
935 #else
936 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
937 #define tegra_dc_set_cmu(dc, cmu)
938 #define tegra_dc_update_cmu(dc, cmu)
939 #endif
940
941 /* disable_irq() blocks until handler completes, calling this function while
942  * holding dc->lock can deadlock. */
943 static inline void disable_dc_irq(const struct tegra_dc *dc)
944 {
945         disable_irq(dc->irq);
946 }
947
948 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
949 {
950         return dc->syncpt[i].id;
951 }
952 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
953
954 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
955 {
956         u32 max;
957
958         mutex_lock(&dc->lock);
959         tegra_dc_get(dc);
960         max = nvhost_syncpt_incr_max_ext(dc->ndev,
961                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
962         dc->syncpt[i].max = max;
963         tegra_dc_put(dc);
964         mutex_unlock(&dc->lock);
965
966         return max;
967 }
968
969 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
970 {
971         mutex_lock(&dc->lock);
972         if (dc->enabled) {
973                 tegra_dc_get(dc);
974                 while (dc->syncpt[i].min < val) {
975                         dc->syncpt[i].min++;
976                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
977                 }
978                 tegra_dc_put(dc);
979         }
980         mutex_unlock(&dc->lock);
981 }
982
983 void
984 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
985 {
986         unsigned int ctrl;
987         unsigned long out_sel;
988         unsigned long cmd_state;
989
990         mutex_lock(&dc->lock);
991         if (!dc->enabled) {
992                 mutex_unlock(&dc->lock);
993                 return;
994         }
995
996         tegra_dc_get(dc);
997
998         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
999                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1000                 cfg->clk_select);
1001
1002         /* The new value should be effected immediately */
1003         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1004         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1005
1006         switch (cfg->which_pwm) {
1007         case TEGRA_PWM_PM0:
1008                 /* Select the LM0 on PM0 */
1009                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1010                 out_sel &= ~(7 << 0);
1011                 out_sel |= (3 << 0);
1012                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1013                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1014                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1015                 break;
1016         case TEGRA_PWM_PM1:
1017                 /* Select the LM1 on PM1 */
1018                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1019                 out_sel &= ~(7 << 4);
1020                 out_sel |= (3 << 4);
1021                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1022                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1023                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1024                 break;
1025         default:
1026                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1027                 break;
1028         }
1029         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1030         tegra_dc_put(dc);
1031         mutex_unlock(&dc->lock);
1032 }
1033 EXPORT_SYMBOL(tegra_dc_config_pwm);
1034
1035 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1036                                 const struct tegra_dc_out_pin *pins,
1037                                 const unsigned int n_pins)
1038 {
1039         unsigned int i;
1040
1041         int name;
1042         int pol;
1043
1044         u32 pol1, pol3;
1045
1046         u32 set1, unset1;
1047         u32 set3, unset3;
1048
1049         set1 = set3 = unset1 = unset3 = 0;
1050
1051         for (i = 0; i < n_pins; i++) {
1052                 name = (pins + i)->name;
1053                 pol  = (pins + i)->pol;
1054
1055                 /* set polarity by name */
1056                 switch (name) {
1057                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1058                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1059                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1060                         else
1061                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1062                         break;
1063                 case TEGRA_DC_OUT_PIN_H_SYNC:
1064                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1065                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1066                         else
1067                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1068                         break;
1069                 case TEGRA_DC_OUT_PIN_V_SYNC:
1070                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1071                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1072                         else
1073                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1074                         break;
1075                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1076                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1077                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1078                         else
1079                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1080                         break;
1081                 default:
1082                         printk("Invalid argument in function %s\n",
1083                                __FUNCTION__);
1084                         break;
1085                 }
1086         }
1087
1088         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1089         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1090
1091         pol1 |= set1;
1092         pol1 &= ~unset1;
1093
1094         pol3 |= set3;
1095         pol3 &= ~unset3;
1096
1097         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1098         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1099 }
1100
1101 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1102 {
1103         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1104                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1105                 dc->out->type == TEGRA_DC_OUT_DSI)
1106                 return override_disp_mode[dc->out->type].pclk ?
1107                         &override_disp_mode[dc->out->type] : NULL;
1108         else
1109                 return NULL;
1110 }
1111
1112 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1113 {
1114         struct tegra_dc_mode *mode;
1115
1116         dc->out = out;
1117         mode = tegra_dc_get_override_mode(dc);
1118
1119         if (mode)
1120                 tegra_dc_set_mode(dc, mode);
1121         else if (out->n_modes > 0)
1122                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1123
1124         switch (out->type) {
1125         case TEGRA_DC_OUT_RGB:
1126                 dc->out_ops = &tegra_dc_rgb_ops;
1127                 break;
1128
1129         case TEGRA_DC_OUT_HDMI:
1130                 dc->out_ops = &tegra_dc_hdmi_ops;
1131                 break;
1132
1133         case TEGRA_DC_OUT_DSI:
1134                 dc->out_ops = &tegra_dc_dsi_ops;
1135                 break;
1136
1137         default:
1138                 dc->out_ops = NULL;
1139                 break;
1140         }
1141
1142         if (dc->out_ops && dc->out_ops->init)
1143                 dc->out_ops->init(dc);
1144 }
1145
1146 /* returns on error: -EINVAL
1147  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1148 int tegra_dc_get_out(const struct tegra_dc *dc)
1149 {
1150         if (dc && dc->out)
1151                 return dc->out->type;
1152         return -EINVAL;
1153 }
1154
1155 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1156 {
1157         if (dc->out)
1158                 return dc->out->height;
1159         else
1160                 return 0;
1161 }
1162 EXPORT_SYMBOL(tegra_dc_get_out_height);
1163
1164 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1165 {
1166         if (dc->out)
1167                 return dc->out->width;
1168         else
1169                 return 0;
1170 }
1171 EXPORT_SYMBOL(tegra_dc_get_out_width);
1172
1173 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1174 {
1175         if (dc->out && dc->out->max_pixclock)
1176                 return dc->out->max_pixclock;
1177         else
1178                 return 0;
1179 }
1180 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1181
1182 void tegra_dc_enable_crc(struct tegra_dc *dc)
1183 {
1184         u32 val;
1185
1186         mutex_lock(&dc->lock);
1187         tegra_dc_get(dc);
1188
1189         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1190                 CRC_ENABLE_ENABLE;
1191         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1192         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1193         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1194         tegra_dc_put(dc);
1195         mutex_unlock(&dc->lock);
1196 }
1197
1198 void tegra_dc_disable_crc(struct tegra_dc *dc)
1199 {
1200         mutex_lock(&dc->lock);
1201         tegra_dc_get(dc);
1202         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1203         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1204         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1205
1206         tegra_dc_put(dc);
1207         mutex_unlock(&dc->lock);
1208 }
1209
1210 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1211 {
1212         int crc = 0;
1213
1214         if (!dc) {
1215                 pr_err("Failed to get dc: NULL parameter.\n");
1216                 goto crc_error;
1217         }
1218
1219 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1220         /* TODO: Replace mdelay with code to sync VBlANK, since
1221          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1222         mdelay(TEGRA_CRC_LATCHED_DELAY);
1223 #endif
1224
1225         mutex_lock(&dc->lock);
1226         tegra_dc_get(dc);
1227         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1228         tegra_dc_put(dc);
1229         mutex_unlock(&dc->lock);
1230 crc_error:
1231         return crc;
1232 }
1233
1234 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1235 {
1236 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1237         u32 val;
1238
1239         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1240         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1241             return true;
1242 #endif
1243         return false;
1244 }
1245
1246 static inline void enable_dc_irq(const struct tegra_dc *dc)
1247 {
1248 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1249         enable_irq(dc->irq);
1250 #else
1251         /* Always disable DC interrupts on FPGA. */
1252         disable_irq(dc->irq);
1253 #endif
1254 }
1255
1256 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1257 {
1258         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1259                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1260 }
1261
1262 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1263 {
1264         int ret = -ENOTTY;
1265
1266         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1267                 return ret;
1268
1269         /*
1270          * Logic is as follows
1271          * a) Indicate we need a vblank.
1272          * b) Wait for completion to be signalled from isr.
1273          * c) Initialize completion for next iteration.
1274          */
1275
1276         mutex_lock(&dc->one_shot_lp_lock);
1277         tegra_dc_get(dc);
1278         dc->out->user_needs_vblank = true;
1279         tegra_dc_unmask_interrupt(dc, MSF_INT);
1280
1281         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1282         init_completion(&dc->out->user_vblank_comp);
1283         tegra_dc_mask_interrupt(dc, MSF_INT);
1284         tegra_dc_put(dc);
1285         mutex_unlock(&dc->one_shot_lp_lock);
1286
1287         return ret;
1288 }
1289
1290 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1291 {
1292         /* Do the actual brightness update outside of the mutex dc->lock */
1293         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1294                 dc->out->sd_settings->bl_device_name) {
1295                 char *bl_device_name =
1296                         dc->out->sd_settings->bl_device_name;
1297                 dc->out->sd_settings->bl_device =
1298                         get_backlight_device_by_name(bl_device_name);
1299         }
1300
1301         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1302                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1303                 backlight_update_status(bl);
1304         }
1305 }
1306
1307 static void tegra_dc_vblank(struct work_struct *work)
1308 {
1309         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1310         bool nvsd_updated = false;
1311
1312         mutex_lock(&dc->lock);
1313
1314         if (!dc->enabled) {
1315                 mutex_unlock(&dc->lock);
1316                 return;
1317         }
1318
1319         tegra_dc_get(dc);
1320         /* use the new frame's bandwidth setting instead of max(current, new),
1321          * skip this if we're using tegra_dc_one_shot_worker() */
1322         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1323                 tegra_dc_program_bandwidth(dc, true);
1324
1325         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1326         if (!tegra_dc_windows_are_dirty(dc))
1327                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1328
1329         /* Update the SD brightness */
1330         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1331                 nvsd_updated = nvsd_update_brightness(dc);
1332                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1333                  * V_BLANK_NVSD bit of vblank ref-count. */
1334                 if (nvsd_updated) {
1335                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1336                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1337                 } else {
1338                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1339                 }
1340         }
1341
1342         /* Mask vblank interrupt if ref-count is zero. */
1343         if (!dc->vblank_ref_count)
1344                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1345
1346         tegra_dc_put(dc);
1347         mutex_unlock(&dc->lock);
1348
1349         /* Do the actual brightness update outside of the mutex dc->lock */
1350         if (nvsd_updated)
1351                 tegra_dc_prism_update_backlight(dc);
1352 }
1353
1354 static void tegra_dc_one_shot_worker(struct work_struct *work)
1355 {
1356         struct tegra_dc *dc = container_of(
1357                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1358         mutex_lock(&dc->lock);
1359
1360         /* memory client has gone idle */
1361         tegra_dc_clear_bandwidth(dc);
1362
1363         if (dc->out_ops && dc->out_ops->idle) {
1364                 tegra_dc_io_start(dc);
1365                 dc->out_ops->idle(dc);
1366                 tegra_dc_io_end(dc);
1367         }
1368
1369         mutex_unlock(&dc->lock);
1370 }
1371
1372 /* return an arbitrarily large number if count overflow occurs.
1373  * make it a nice base-10 number to show up in stats output */
1374 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1375 {
1376         unsigned count = tegra_dc_readl(dc, reg);
1377
1378         tegra_dc_writel(dc, 0, reg);
1379         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1380 }
1381
1382 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1383 {
1384         int i;
1385
1386         dc->stats.underflows++;
1387         if (dc->underflow_mask & WIN_A_UF_INT)
1388                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1389                         DC_WINBUF_AD_UFLOW_STATUS);
1390         if (dc->underflow_mask & WIN_B_UF_INT)
1391                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1392                         DC_WINBUF_BD_UFLOW_STATUS);
1393         if (dc->underflow_mask & WIN_C_UF_INT)
1394                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1395                         DC_WINBUF_CD_UFLOW_STATUS);
1396
1397         /* Check for any underflow reset conditions */
1398         for (i = 0; i < DC_N_WINDOWS; i++) {
1399                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1400                         dc->windows[i].underflows++;
1401
1402 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1403                         if (dc->windows[i].underflows > 4) {
1404                                 schedule_work(&dc->reset_work);
1405                                 /* reset counter */
1406                                 dc->windows[i].underflows = 0;
1407                                 trace_display_reset(dc);
1408                         }
1409 #endif
1410 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1411                         if (dc->windows[i].underflows > 4) {
1412                                 trace_display_reset(dc);
1413                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1414                                                 DC_DISP_DISP_MISC_CONTROL);
1415                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1416                                                 DC_CMD_STATE_CONTROL);
1417                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1418                                                 DC_CMD_STATE_CONTROL);
1419
1420                                 tegra_dc_writel(dc, 0,
1421                                                 DC_DISP_DISP_MISC_CONTROL);
1422                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1423                                                 DC_CMD_STATE_CONTROL);
1424                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1425                                                 DC_CMD_STATE_CONTROL);
1426                         }
1427 #endif
1428                 } else {
1429                         dc->windows[i].underflows = 0;
1430                 }
1431         }
1432
1433         /* Clear the underflow mask now that we've checked it. */
1434         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1435         dc->underflow_mask = 0;
1436         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1437         trace_underflow(dc);
1438 }
1439
1440 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1441 static void tegra_dc_vpulse2(struct work_struct *work)
1442 {
1443         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1444         bool nvsd_updated = false;
1445
1446         mutex_lock(&dc->lock);
1447
1448         if (!dc->enabled) {
1449                 mutex_unlock(&dc->lock);
1450                 return;
1451         }
1452
1453         tegra_dc_get(dc);
1454
1455         /* Clear the V_PULSE2_FLIP if no update */
1456         if (!tegra_dc_windows_are_dirty(dc))
1457                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1458
1459         /* Update the SD brightness */
1460         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1461                 nvsd_updated = nvsd_update_brightness(dc);
1462                 if (nvsd_updated) {
1463                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1464                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1465                 } else {
1466                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1467                 }
1468         }
1469
1470         /* Mask vpulse2 interrupt if ref-count is zero. */
1471         if (!dc->vpulse2_ref_count)
1472                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1473
1474         tegra_dc_put(dc);
1475         mutex_unlock(&dc->lock);
1476
1477         /* Do the actual brightness update outside of the mutex dc->lock */
1478         if (nvsd_updated)
1479                 tegra_dc_prism_update_backlight(dc);
1480 }
1481 #endif
1482
1483 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1484 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1485 {
1486         /* pending user vblank, so wakeup */
1487         if ((status & (V_BLANK_INT | MSF_INT)) &&
1488             (dc->out->user_needs_vblank)) {
1489                 dc->out->user_needs_vblank = false;
1490                 complete(&dc->out->user_vblank_comp);
1491         }
1492
1493         if (status & V_BLANK_INT) {
1494                 /* Sync up windows. */
1495                 tegra_dc_trigger_windows(dc);
1496
1497                 /* Schedule any additional bottom-half vblank actvities. */
1498                 queue_work(system_freezable_wq, &dc->vblank_work);
1499         }
1500
1501         if (status & FRAME_END_INT) {
1502                 /* Mark the frame_end as complete. */
1503                 if (!completion_done(&dc->frame_end_complete))
1504                         complete(&dc->frame_end_complete);
1505         }
1506
1507 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1508         if (status & V_PULSE2_INT)
1509                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1510 #endif
1511 }
1512
1513 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1514 {
1515         /* Schedule any additional bottom-half vblank actvities. */
1516         if (status & V_BLANK_INT)
1517                 queue_work(system_freezable_wq, &dc->vblank_work);
1518
1519         if (status & FRAME_END_INT) {
1520                 struct timespec tm = CURRENT_TIME;
1521                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1522                 wake_up(&dc->timestamp_wq);
1523
1524                 /* Mark the frame_end as complete. */
1525                 if (!completion_done(&dc->frame_end_complete))
1526                         complete(&dc->frame_end_complete);
1527
1528                 tegra_dc_trigger_windows(dc);
1529         }
1530
1531 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1532         if (status & V_PULSE2_INT)
1533                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1534 #endif
1535 }
1536
1537 /* XXX: Not sure if we limit look ahead to 1 frame */
1538 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1539 {
1540         BUG_ON(!dc->frametime_ns);
1541         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1542 }
1543
1544 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1545 {
1546         BUG_ON(!dc->frametime_ns);
1547         return (((new_ts - old_ts) > dc->frametime_ns)
1548                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1549                         != div_s64((old_ts - dc->frame_end_timestamp),
1550                                 dc->frametime_ns)));
1551 }
1552 #endif
1553
1554 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1555 {
1556 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1557         struct tegra_dc *dc = ptr;
1558         unsigned long status;
1559         unsigned long underflow_mask;
1560         u32 val;
1561         int need_disable = 0;
1562
1563         mutex_lock(&dc->lock);
1564         if (!dc->enabled || !tegra_dc_is_powered(dc)) {
1565                 mutex_unlock(&dc->lock);
1566                 return IRQ_HANDLED;
1567         }
1568
1569         tegra_dc_get(dc);
1570
1571         if (!nvhost_module_powered_ext(dc->ndev)) {
1572                 WARN(1, "IRQ when DC not powered!\n");
1573                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1574                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1575                 tegra_dc_put(dc);
1576                 mutex_unlock(&dc->lock);
1577                 return IRQ_HANDLED;
1578         }
1579
1580         /* clear all status flags except underflow, save those for the worker */
1581         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1582         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1583         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1584         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1585
1586         /*
1587          * Overlays can get thier internal state corrupted during and underflow
1588          * condition.  The only way to fix this state is to reset the DC.
1589          * if we get 4 consecutive frames with underflows, assume we're
1590          * hosed and reset.
1591          */
1592         underflow_mask = status & ALL_UF_INT;
1593
1594         /* Check underflow */
1595         if (underflow_mask) {
1596                 dc->underflow_mask |= underflow_mask;
1597                 schedule_delayed_work(&dc->underflow_work,
1598                         msecs_to_jiffies(1));
1599         }
1600
1601         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1602                 tegra_dc_one_shot_irq(dc, status);
1603         else
1604                 tegra_dc_continuous_irq(dc, status);
1605
1606         /* update video mode if it has changed since the last frame */
1607         if (status & (FRAME_END_INT | V_BLANK_INT))
1608                 if (tegra_dc_update_mode(dc))
1609                         need_disable = 1; /* force display off on error */
1610
1611         tegra_dc_put(dc);
1612         mutex_unlock(&dc->lock);
1613
1614         if (need_disable)
1615                 tegra_dc_disable(dc);
1616         return IRQ_HANDLED;
1617 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1618         return IRQ_NONE;
1619 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1620 }
1621
1622 void tegra_dc_set_color_control(struct tegra_dc *dc)
1623 {
1624         u32 color_control;
1625
1626         switch (dc->out->depth) {
1627         case 3:
1628                 color_control = BASE_COLOR_SIZE111;
1629                 break;
1630
1631         case 6:
1632                 color_control = BASE_COLOR_SIZE222;
1633                 break;
1634
1635         case 8:
1636                 color_control = BASE_COLOR_SIZE332;
1637                 break;
1638
1639         case 9:
1640                 color_control = BASE_COLOR_SIZE333;
1641                 break;
1642
1643         case 12:
1644                 color_control = BASE_COLOR_SIZE444;
1645                 break;
1646
1647         case 15:
1648                 color_control = BASE_COLOR_SIZE555;
1649                 break;
1650
1651         case 16:
1652                 color_control = BASE_COLOR_SIZE565;
1653                 break;
1654
1655         case 18:
1656                 color_control = BASE_COLOR_SIZE666;
1657                 break;
1658
1659         default:
1660                 color_control = BASE_COLOR_SIZE888;
1661                 break;
1662         }
1663
1664         switch (dc->out->dither) {
1665         case TEGRA_DC_DISABLE_DITHER:
1666                 color_control |= DITHER_CONTROL_DISABLE;
1667                 break;
1668         case TEGRA_DC_ORDERED_DITHER:
1669                 color_control |= DITHER_CONTROL_ORDERED;
1670                 break;
1671         case TEGRA_DC_ERRDIFF_DITHER:
1672                 /* The line buffer for error-diffusion dither is limited
1673                  * to 1280 pixels per line. This limits the maximum
1674                  * horizontal active area size to 1280 pixels when error
1675                  * diffusion is enabled.
1676                  */
1677                 BUG_ON(dc->mode.h_active > 1280);
1678                 color_control |= DITHER_CONTROL_ERRDIFF;
1679                 break;
1680         }
1681
1682 #ifdef CONFIG_TEGRA_DC_CMU
1683         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1684                 color_control |= CMU_ENABLE;
1685 #endif
1686
1687         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1688 }
1689
1690 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1691 {
1692         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1693                 return dc->win_syncpt[idx];
1694         BUG();
1695 }
1696
1697 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1698 {
1699 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1700         u32 start, end;
1701         unsigned long val;
1702
1703         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1704         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1705
1706         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1707                 dc->mode.v_back_porch + dc->mode.v_active;
1708         end = start + 1;
1709         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1710         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1711
1712         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1713         val |= V_PULSE2_INT;
1714         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1715
1716         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1717         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1718 #endif
1719 }
1720
1721 static int tegra_dc_init(struct tegra_dc *dc)
1722 {
1723         int i;
1724         int int_enable;
1725
1726         tegra_dc_io_start(dc);
1727         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1728         if (dc->ndev->id == 0) {
1729                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1730                                       TEGRA_MC_PRIO_MED);
1731                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1732                                       TEGRA_MC_PRIO_MED);
1733                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1734                                       TEGRA_MC_PRIO_MED);
1735 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1736                 /* only present on Tegra2 and 3 */
1737                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1738                                       TEGRA_MC_PRIO_MED);
1739 #endif
1740                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1741                                       TEGRA_MC_PRIO_HIGH);
1742         } else if (dc->ndev->id == 1) {
1743                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1744                                       TEGRA_MC_PRIO_MED);
1745                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1746                                       TEGRA_MC_PRIO_MED);
1747                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1748                                       TEGRA_MC_PRIO_MED);
1749 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1750                 /* only present on Tegra2 and 3 */
1751                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1752                                       TEGRA_MC_PRIO_MED);
1753 #endif
1754                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1755                                       TEGRA_MC_PRIO_HIGH);
1756         }
1757         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1758                         DC_CMD_CONT_SYNCPT_VSYNC);
1759
1760         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1761         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1762         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1763         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1764 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1765         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1766 #endif
1767         /* enable interrupts for vblank, frame_end and underflows */
1768         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1769         /* for panels with one-shot mode enable tearing effect interrupt */
1770         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1771                 int_enable |= MSF_INT;
1772
1773         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1774         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1775         tegra_dc_init_vpulse2_int(dc);
1776
1777         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1778
1779 #ifdef CONFIG_TEGRA_DC_CMU
1780         if (dc->pdata->cmu)
1781                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1782         else
1783                 _tegra_dc_update_cmu(dc, &default_cmu);
1784 #endif
1785         tegra_dc_set_color_control(dc);
1786         for (i = 0; i < DC_N_WINDOWS; i++) {
1787                 struct tegra_dc_win *win = &dc->windows[i];
1788                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1789                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1790                 tegra_dc_set_csc(dc, &win->csc);
1791                 tegra_dc_set_lut(dc, win);
1792                 tegra_dc_set_scaling_filter(dc);
1793         }
1794
1795         for (i = 0; i < dc->n_windows; i++) {
1796                 u32 syncpt = get_syncpt(dc, i);
1797
1798                 dc->syncpt[i].id = syncpt;
1799
1800                 dc->syncpt[i].min = dc->syncpt[i].max =
1801                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1802         }
1803
1804         trace_display_mode(dc, &dc->mode);
1805
1806         if (dc->mode.pclk) {
1807                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1808                         tegra_dc_io_end(dc);
1809                         return -EINVAL;
1810                 }
1811         }
1812
1813         /* Initialize SD AFTER the modeset.
1814            nvsd_init handles the sd_settings = NULL case. */
1815         nvsd_init(dc, dc->out->sd_settings);
1816
1817         tegra_dc_io_end(dc);
1818
1819         return 0;
1820 }
1821
1822 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1823 {
1824         int failed_init = 0;
1825
1826         tegra_dc_unpowergate_locked(dc);
1827
1828         if (dc->out->enable)
1829                 dc->out->enable(&dc->ndev->dev);
1830
1831         tegra_dc_setup_clk(dc, dc->clk);
1832         tegra_dc_clk_enable(dc);
1833         tegra_dc_io_start(dc);
1834
1835         tegra_dc_power_on(dc);
1836
1837         /* do not accept interrupts during initialization */
1838         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1839
1840         enable_dc_irq(dc);
1841
1842         failed_init = tegra_dc_init(dc);
1843         if (failed_init) {
1844                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1845                 disable_irq_nosync(dc->irq);
1846                 tegra_dc_clear_bandwidth(dc);
1847                 tegra_dc_clk_disable(dc);
1848                 if (dc->out && dc->out->disable)
1849                         dc->out->disable();
1850                 tegra_dc_io_end(dc);
1851                 return false;
1852         }
1853
1854         if (dc->out_ops && dc->out_ops->enable)
1855                 dc->out_ops->enable(dc);
1856
1857         /* force a full blending update */
1858         dc->blend.z[0] = -1;
1859
1860         tegra_dc_ext_enable(dc->ext);
1861
1862         trace_display_enable(dc);
1863
1864         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1865         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1866
1867         if (dc->out->postpoweron)
1868                 dc->out->postpoweron(&dc->ndev->dev);
1869
1870         if (dc->out_ops && dc->out_ops->postpoweron)
1871                 dc->out_ops->postpoweron(dc);
1872
1873         tegra_log_resume_time();
1874
1875         tegra_dc_io_end(dc);
1876         return true;
1877 }
1878
1879 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1880 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1881 {
1882         bool ret = true;
1883
1884         if (dc->out->enable)
1885                 dc->out->enable(&dc->ndev->dev);
1886
1887         tegra_dc_setup_clk(dc, dc->clk);
1888         tegra_dc_clk_enable(dc);
1889
1890         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1891                 mutex_lock(&tegra_dcs[1]->lock);
1892                 disable_irq_nosync(tegra_dcs[1]->irq);
1893         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1894                 mutex_lock(&tegra_dcs[0]->lock);
1895                 disable_irq_nosync(tegra_dcs[0]->irq);
1896         }
1897
1898         msleep(5);
1899         tegra_periph_reset_assert(dc->clk);
1900         msleep(2);
1901 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1902         tegra_periph_reset_deassert(dc->clk);
1903         msleep(1);
1904 #endif
1905
1906         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1907                 enable_dc_irq(tegra_dcs[1]);
1908                 mutex_unlock(&tegra_dcs[1]->lock);
1909         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1910                 enable_dc_irq(tegra_dcs[0]);
1911                 mutex_unlock(&tegra_dcs[0]->lock);
1912         }
1913
1914         enable_dc_irq(dc);
1915
1916         if (tegra_dc_init(dc)) {
1917                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1918                 ret = false;
1919         }
1920
1921         if (dc->out_ops && dc->out_ops->enable)
1922                 dc->out_ops->enable(dc);
1923
1924         if (dc->out->postpoweron)
1925                 dc->out->postpoweron();
1926
1927         /* force a full blending update */
1928         dc->blend.z[0] = -1;
1929
1930         tegra_dc_ext_enable(dc->ext);
1931
1932         if (!ret) {
1933                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1934                 _tegra_dc_controller_disable(dc);
1935         }
1936
1937         trace_display_reset(dc);
1938         return ret;
1939 }
1940 #endif
1941
1942 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1943 {
1944         if (dc->mode.pclk == 0) {
1945                 switch (dc->out->type) {
1946                 case TEGRA_DC_OUT_HDMI:
1947                 /* DC enable called but no videomode is loaded.
1948                      Check if HDMI is connected, then set fallback mdoe */
1949                 if (tegra_dc_hpd(dc)) {
1950                         return tegra_dc_set_fb_mode(dc,
1951                                         &tegra_dc_hdmi_fallback_mode, 0);
1952                 } else
1953                         return false;
1954
1955                 break;
1956
1957                 /* Do nothing for other outputs for now */
1958                 case TEGRA_DC_OUT_RGB:
1959
1960                 case TEGRA_DC_OUT_DSI:
1961
1962                 default:
1963                         return false;
1964                 }
1965         }
1966
1967         return false;
1968 }
1969
1970 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1971 {
1972         return _tegra_dc_set_default_videomode(dc);
1973 }
1974
1975 static bool _tegra_dc_enable(struct tegra_dc *dc)
1976 {
1977         if (dc->mode.pclk == 0)
1978                 return false;
1979
1980         if (!dc->out)
1981                 return false;
1982
1983         if (dc->enabled)
1984                 return true;
1985
1986         if (!_tegra_dc_controller_enable(dc))
1987                 return false;
1988
1989         return true;
1990 }
1991
1992 void tegra_dc_enable(struct tegra_dc *dc)
1993 {
1994         mutex_lock(&dc->lock);
1995
1996         if (!dc->enabled)
1997                 dc->enabled = _tegra_dc_enable(dc);
1998
1999         mutex_unlock(&dc->lock);
2000         trace_display_mode(dc, &dc->mode);
2001 }
2002
2003 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2004 {
2005         unsigned i;
2006
2007         tegra_dc_get(dc);
2008
2009         if (dc->out && dc->out->prepoweroff)
2010                 dc->out->prepoweroff();
2011
2012         if (dc->out_ops && dc->out_ops->disable)
2013                 dc->out_ops->disable(dc);
2014
2015         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2016
2017         disable_irq_nosync(dc->irq);
2018
2019         tegra_dc_clear_bandwidth(dc);
2020
2021         if (dc->out && dc->out->disable)
2022                 dc->out->disable();
2023
2024         for (i = 0; i < dc->n_windows; i++) {
2025                 struct tegra_dc_win *w = &dc->windows[i];
2026
2027                 /* reset window bandwidth */
2028                 w->bandwidth = 0;
2029                 w->new_bandwidth = 0;
2030
2031                 /* disable windows */
2032                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2033
2034                 /* set window physical address to invalid*/
2035                 w->phys_addr = 0;
2036
2037                 /* flush any pending syncpt waits */
2038                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2039                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2040                                 dc->syncpt[i].min, dc->syncpt[i].max);
2041                         dc->syncpt[i].min++;
2042                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2043                 }
2044         }
2045         trace_display_disable(dc);
2046
2047         if (dc->out_ops && dc->out_ops->postpoweroff)
2048                 dc->out_ops->postpoweroff(dc);
2049
2050         tegra_dc_clk_disable(dc);
2051         tegra_dc_put(dc);
2052 }
2053
2054 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2055 {
2056 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2057         u32 val;
2058         if (dc->enabled)  {
2059                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2060                 if (enable)
2061                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2062                 else
2063                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2064                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2065         }
2066 #endif
2067 }
2068
2069 bool tegra_dc_stats_get(struct tegra_dc *dc)
2070 {
2071 #if 0 /* right now it is always enabled */
2072         u32 val;
2073         bool res;
2074
2075         if (dc->enabled)  {
2076                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2077                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2078         } else {
2079                 res = false;
2080         }
2081
2082         return res;
2083 #endif
2084         return true;
2085 }
2086
2087 /* make the screen blank by disabling all windows */
2088 void tegra_dc_blank(struct tegra_dc *dc)
2089 {
2090         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2091         unsigned i;
2092
2093         for (i = 0; i < DC_N_WINDOWS; i++) {
2094                 dcwins[i] = tegra_dc_get_window(dc, i);
2095                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2096         }
2097
2098         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2099         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2100 }
2101
2102 static void _tegra_dc_disable(struct tegra_dc *dc)
2103 {
2104         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2105                 mutex_lock(&dc->one_shot_lock);
2106                 cancel_delayed_work_sync(&dc->one_shot_work);
2107         }
2108
2109         tegra_dc_io_start(dc);
2110         _tegra_dc_controller_disable(dc);
2111         tegra_dc_io_end(dc);
2112
2113         tegra_dc_powergate_locked(dc);
2114
2115         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2116                 mutex_unlock(&dc->one_shot_lock);
2117
2118         /*
2119          * We will need to reinitialize the display the next time panel
2120          * is enabled.
2121          */
2122         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2123
2124         tegra_log_suspend_time();
2125 }
2126
2127 void tegra_dc_disable(struct tegra_dc *dc)
2128 {
2129         tegra_dc_ext_disable(dc->ext);
2130
2131         /* it's important that new underflow work isn't scheduled before the
2132          * lock is acquired. */
2133         cancel_delayed_work_sync(&dc->underflow_work);
2134
2135         mutex_lock(&dc->lock);
2136
2137         if (dc->enabled) {
2138                 dc->enabled = false;
2139
2140                 if (!dc->suspended)
2141                         _tegra_dc_disable(dc);
2142         }
2143
2144 #ifdef CONFIG_SWITCH
2145         switch_set_state(&dc->modeset_switch, 0);
2146 #endif
2147
2148         mutex_unlock(&dc->lock);
2149         synchronize_irq(dc->irq);
2150         trace_display_mode(dc, &dc->mode);
2151 }
2152
2153 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2154 static void tegra_dc_reset_worker(struct work_struct *work)
2155 {
2156         struct tegra_dc *dc =
2157                 container_of(work, struct tegra_dc, reset_work);
2158
2159         unsigned long val = 0;
2160
2161         mutex_lock(&shared_lock);
2162
2163         dev_warn(&dc->ndev->dev,
2164                 "overlay stuck in underflow state.  resetting.\n");
2165
2166         tegra_dc_ext_disable(dc->ext);
2167
2168         mutex_lock(&dc->lock);
2169
2170         if (dc->enabled == false)
2171                 goto unlock;
2172
2173         dc->enabled = false;
2174
2175         /*
2176          * off host read bus
2177          */
2178         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2179         val &= ~(0x00000100);
2180         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2181
2182         /*
2183          * set DC to STOP mode
2184          */
2185         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2186
2187         msleep(10);
2188
2189         _tegra_dc_controller_disable(dc);
2190
2191         /* _tegra_dc_controller_reset_enable deasserts reset */
2192         _tegra_dc_controller_reset_enable(dc);
2193
2194         dc->enabled = true;
2195
2196         /* reopen host read bus */
2197         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2198         val &= ~(0x00000100);
2199         val |= 0x100;
2200         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2201
2202 unlock:
2203         mutex_unlock(&dc->lock);
2204         mutex_unlock(&shared_lock);
2205         trace_display_reset(dc);
2206 }
2207 #endif
2208
2209 static void tegra_dc_underflow_worker(struct work_struct *work)
2210 {
2211         struct tegra_dc *dc = container_of(
2212                 to_delayed_work(work), struct tegra_dc, underflow_work);
2213
2214         mutex_lock(&dc->lock);
2215         tegra_dc_get(dc);
2216
2217         if (dc->enabled) {
2218                 tegra_dc_underflow_handler(dc);
2219         }
2220         tegra_dc_put(dc);
2221         mutex_unlock(&dc->lock);
2222 }
2223
2224 #ifdef CONFIG_SWITCH
2225 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2226 {
2227         struct tegra_dc *dc =
2228                 container_of(sdev, struct tegra_dc, modeset_switch);
2229
2230         if (!sdev->state)
2231                 return sprintf(buf, "offline\n");
2232
2233         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2234 }
2235 #endif
2236
2237 static void tegra_dc_add_modes(struct tegra_dc *dc)
2238 {
2239         struct fb_monspecs specs;
2240         int i;
2241
2242         memset(&specs, 0, sizeof(specs));
2243         specs.max_x = dc->mode.h_active * 1000;
2244         specs.max_y = dc->mode.v_active * 1000;
2245         specs.modedb_len = dc->out->n_modes;
2246         specs.modedb = kzalloc(specs.modedb_len *
2247                 sizeof(struct fb_videomode), GFP_KERNEL);
2248         if (specs.modedb == NULL) {
2249                 dev_err(&dc->ndev->dev, "modedb allocation failed\n");
2250                 return;
2251         }
2252         for (i = 0; i < dc->out->n_modes; i++)
2253                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2254                         &dc->out->modes[i]);
2255         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2256 }
2257
2258 static int tegra_dc_probe(struct platform_device *ndev)
2259 {
2260         struct tegra_dc *dc;
2261         struct tegra_dc_mode *mode;
2262         struct tegra_dc_platform_data *dt_pdata = NULL;
2263         struct tegra_dc_platform_data *temp_pdata;
2264         struct of_tegra_dc_data *of_pdata = NULL;
2265         struct clk *clk;
2266         struct device_node *np = ndev->dev.of_node;
2267         struct clk *emc_clk;
2268         struct resource *res;
2269         struct resource dt_res;
2270         struct resource *base_res;
2271         struct resource *fb_mem = NULL;
2272         int ret = 0;
2273         void __iomem *base;
2274         int irq;
2275         int i;
2276
2277         if (!ndev->dev.platform_data) {
2278                 dev_err(&ndev->dev, "no platform data\n");
2279                 return -ENOENT;
2280         }
2281
2282         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2283         if (!dc) {
2284                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2285                 return -ENOMEM;
2286         }
2287
2288         if (np) {
2289                 dt_pdata = of_dc_parse_platform_data(ndev);
2290                 if (dt_pdata == NULL)
2291                         goto err_free;
2292
2293 #ifdef CONFIG_OF
2294                 irq = of_irq_to_resource(np, 0, NULL);
2295                 if (!irq)
2296                         goto err_free;
2297 #endif
2298
2299                 ret = of_address_to_resource(np, 0, &dt_res);
2300                 if (ret)
2301                         goto err_free;
2302
2303                 if (dt_res.start == TEGRA_DISPLAY_BASE)
2304                         ndev->id = 0;
2305                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
2306                         ndev->id = 1;
2307                 else
2308                         goto err_free;
2309
2310                 res = &dt_res;
2311         } else {
2312                 irq = platform_get_irq_byname(ndev, "irq");
2313                 if (irq <= 0) {
2314                         dev_err(&ndev->dev, "no irq\n");
2315                         ret = -ENOENT;
2316                         goto err_free;
2317                 }
2318
2319                 res = platform_get_resource_byname(ndev,
2320                         IORESOURCE_MEM, "regs");
2321                 if (!res) {
2322                         dev_err(&ndev->dev, "no mem resource\n");
2323                         ret = -ENOENT;
2324                         goto err_free;
2325                 }
2326         }
2327
2328         base_res = request_mem_region(res->start, resource_size(res),
2329                 ndev->name);
2330         if (!base_res) {
2331                 dev_err(&ndev->dev, "request_mem_region failed\n");
2332                 ret = -EBUSY;
2333                 goto err_free;
2334         }
2335
2336         base = ioremap(res->start, resource_size(res));
2337         if (!base) {
2338                 dev_err(&ndev->dev, "registers can't be mapped\n");
2339                 ret = -EBUSY;
2340                 goto err_release_resource_reg;
2341         }
2342         if (TEGRA_DISPLAY_BASE == res->start) {
2343                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2344                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2345                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2346                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2347                 /* This code assumes DISB depends on DISA. DC's powergate
2348                  * code will have to change if dependency is removed */
2349                 if (dc->out && dc->out->type == TEGRA_DC_OUT_HDMI)
2350                         dc->powergate_id = TEGRA_POWERGATE_DISB;
2351                 else
2352                         dc->powergate_id = TEGRA_POWERGATE_DISA;
2353         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2354                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2355                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2356                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2357                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2358                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2359         } else {
2360                 dev_err(&ndev->dev,
2361                         "Unknown base address %#08x: unable to assign syncpt\n",
2362                         res->start);
2363         }
2364
2365         if (np) {
2366                 temp_pdata = (struct tegra_dc_platform_data *)
2367                         ndev->dev.platform_data;
2368                 of_pdata = &(temp_pdata->of_data);
2369                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
2370                 if (fb_mem == NULL) {
2371                         ret = -ENOMEM;
2372                         goto err_iounmap_reg;
2373                 }
2374                 fb_mem->name = "fbmem";
2375                 fb_mem->flags = IORESOURCE_MEM;
2376                 fb_mem->start = (resource_size_t) of_pdata->fb_start;
2377                 fb_mem->end = fb_mem->start +
2378                         (resource_size_t)of_pdata->fb_size - 1;
2379         } else {
2380                 fb_mem = platform_get_resource_byname(ndev,
2381                         IORESOURCE_MEM, "fbmem");
2382         }
2383
2384         clk = clk_get(&ndev->dev, NULL);
2385         if (IS_ERR_OR_NULL(clk)) {
2386                 dev_err(&ndev->dev, "can't get clock\n");
2387                 ret = -ENOENT;
2388                 goto err_iounmap_reg;
2389         }
2390
2391         emc_clk = clk_get(&ndev->dev, "emc");
2392         if (IS_ERR_OR_NULL(emc_clk)) {
2393                 dev_err(&ndev->dev, "can't get emc clock\n");
2394                 ret = -ENOENT;
2395                 goto err_put_clk;
2396         }
2397
2398         dc->clk = clk;
2399         dc->emc_clk = emc_clk;
2400         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2401         /* Initialize one shot work delay, it will be assigned by dsi
2402          * according to refresh rate later. */
2403         dc->one_shot_delay_ms = 40;
2404
2405         dc->base_res = base_res;
2406         dc->base = base;
2407         dc->irq = irq;
2408         dc->ndev = ndev;
2409
2410         if (!np)
2411                 dc->pdata = ndev->dev.platform_data;
2412         else
2413                 dc->pdata = dt_pdata;
2414
2415         /*
2416          * The emc is a shared clock, it will be set based on
2417          * the requirements for each user on the bus.
2418          */
2419         dc->emc_clk_rate = 0;
2420
2421         mutex_init(&dc->lock);
2422         mutex_init(&dc->one_shot_lock);
2423         mutex_init(&dc->one_shot_lp_lock);
2424         init_completion(&dc->frame_end_complete);
2425         init_waitqueue_head(&dc->wq);
2426         init_waitqueue_head(&dc->timestamp_wq);
2427 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2428         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2429 #endif
2430         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2431         dc->vblank_ref_count = 0;
2432 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2433         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2434 #endif
2435         dc->vpulse2_ref_count = 0;
2436         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2437         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2438
2439         tegra_dc_init_lut_defaults(&dc->fb_lut);
2440
2441         dc->n_windows = DC_N_WINDOWS;
2442         for (i = 0; i < dc->n_windows; i++) {
2443                 struct tegra_dc_win *win = &dc->windows[i];
2444                 win->idx = i;
2445                 win->dc = dc;
2446                 tegra_dc_init_csc_defaults(&win->csc);
2447                 tegra_dc_init_lut_defaults(&win->lut);
2448         }
2449
2450         ret = tegra_dc_set(dc, ndev->id);
2451         if (ret < 0) {
2452                 dev_err(&ndev->dev, "can't add dc\n");
2453                 goto err_put_emc_clk;
2454         }
2455
2456         platform_set_drvdata(ndev, dc);
2457
2458 #ifdef CONFIG_SWITCH
2459         dc->modeset_switch.name = dev_name(&ndev->dev);
2460         dc->modeset_switch.state = 0;
2461         dc->modeset_switch.print_state = switch_modeset_print_mode;
2462         ret = switch_dev_register(&dc->modeset_switch);
2463         if (ret < 0)
2464                 dev_err(&ndev->dev, "failed to register switch driver\n");
2465 #endif
2466
2467         tegra_dc_feature_register(dc);
2468
2469         if (dc->pdata->default_out)
2470                 tegra_dc_set_out(dc, dc->pdata->default_out);
2471         else
2472                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2473         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2474
2475         dc->ext = tegra_dc_ext_register(ndev, dc);
2476         if (IS_ERR_OR_NULL(dc->ext)) {
2477                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2478                 dc->ext = NULL;
2479         }
2480
2481         /* interrupt handler must be registered before tegra_fb_register() */
2482         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2483                         dev_name(&ndev->dev), dc)) {
2484                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2485                 ret = -EBUSY;
2486                 goto err_disable_dc;
2487         }
2488         disable_dc_irq(dc);
2489
2490         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2491                 _tegra_dc_set_default_videomode(dc);
2492                 dc->enabled = _tegra_dc_enable(dc);
2493         }
2494
2495         tegra_dc_create_debugfs(dc);
2496
2497         dev_info(&ndev->dev, "probed\n");
2498
2499         if (dc->pdata->fb) {
2500                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2501                         unsigned long fmt;
2502                         tegra_dc_writel(dc,
2503                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2504                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2505
2506                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2507                         dc->pdata->fb->bits_per_pixel =
2508                                 tegra_dc_fmt_bpp(fmt);
2509                 }
2510
2511                 mode = tegra_dc_get_override_mode(dc);
2512                 if (mode) {
2513                         dc->pdata->fb->xres = mode->h_active;
2514                         dc->pdata->fb->yres = mode->v_active;
2515                 }
2516
2517                 tegra_dc_io_start(dc);
2518                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2519                 tegra_dc_io_end(dc);
2520                 if (IS_ERR_OR_NULL(dc->fb)) {
2521                         dc->fb = NULL;
2522                         dev_err(&ndev->dev, "failed to register fb\n");
2523                         goto err_remove_debugfs;
2524                 }
2525         }
2526
2527         if (dc->out && dc->out->n_modes)
2528                 tegra_dc_add_modes(dc);
2529
2530         tegra_dc_hotplug_init(dc);
2531
2532         if (dc->out_ops && dc->out_ops->detect)
2533                 dc->out_ops->detect(dc);
2534         else
2535                 dc->connected = true;
2536
2537         /* Powergate display module when it's unconnected. */
2538         if (!tegra_dc_get_connected(dc))
2539                 tegra_dc_powergate_locked(dc);
2540
2541         tegra_dc_create_sysfs(&dc->ndev->dev);
2542
2543         return 0;
2544
2545 err_remove_debugfs:
2546         tegra_dc_remove_debugfs(dc);
2547         free_irq(irq, dc);
2548 err_disable_dc:
2549         if (dc->ext) {
2550                 tegra_dc_ext_disable(dc->ext);
2551                 tegra_dc_ext_unregister(dc->ext);
2552         }
2553         mutex_lock(&dc->lock);
2554         if (dc->enabled)
2555                 _tegra_dc_disable(dc);
2556         dc->enabled = false;
2557         mutex_unlock(&dc->lock);
2558 #ifdef CONFIG_SWITCH
2559         switch_dev_unregister(&dc->modeset_switch);
2560 #endif
2561 err_put_emc_clk:
2562         clk_put(emc_clk);
2563 err_put_clk:
2564         clk_put(clk);
2565 err_iounmap_reg:
2566         iounmap(base);
2567         if (fb_mem) {
2568                 if (!np)
2569                         release_resource(fb_mem);
2570                 else
2571                         kfree(fb_mem);
2572         }
2573 err_release_resource_reg:
2574         release_resource(base_res);
2575 err_free:
2576         kfree(dc);
2577
2578         return ret;
2579 }
2580
2581 static int __devexit tegra_dc_remove(struct platform_device *ndev)
2582 {
2583         struct tegra_dc *dc = platform_get_drvdata(ndev);
2584         struct device_node *np = ndev->dev.of_node;
2585
2586         tegra_dc_remove_sysfs(&dc->ndev->dev);
2587         tegra_dc_remove_debugfs(dc);
2588
2589         if (dc->fb) {
2590                 tegra_fb_unregister(dc->fb);
2591                 if (dc->fb_mem) {
2592                         if (!np)
2593                                 release_resource(dc->fb_mem);
2594                         else
2595                                 kfree(dc->fb_mem);
2596                 }
2597         }
2598
2599         tegra_dc_ext_disable(dc->ext);
2600
2601         if (dc->ext)
2602                 tegra_dc_ext_unregister(dc->ext);
2603
2604         mutex_lock(&dc->lock);
2605         if (dc->enabled)
2606                 _tegra_dc_disable(dc);
2607         dc->enabled = false;
2608         mutex_unlock(&dc->lock);
2609         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2610
2611 #ifdef CONFIG_SWITCH
2612         switch_dev_unregister(&dc->modeset_switch);
2613 #endif
2614         free_irq(dc->irq, dc);
2615         clk_put(dc->emc_clk);
2616         clk_put(dc->clk);
2617         iounmap(dc->base);
2618         if (dc->fb_mem)
2619                 release_resource(dc->base_res);
2620         kfree(dc);
2621         tegra_dc_set(NULL, ndev->id);
2622
2623         return 0;
2624 }
2625
2626 #ifdef CONFIG_PM
2627 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2628 {
2629         struct tegra_dc *dc = platform_get_drvdata(ndev);
2630
2631         trace_display_suspend(dc);
2632         dev_info(&ndev->dev, "suspend\n");
2633
2634         tegra_dc_ext_disable(dc->ext);
2635
2636         mutex_lock(&dc->lock);
2637         tegra_dc_io_start(dc);
2638
2639         if (dc->out_ops && dc->out_ops->suspend)
2640                 dc->out_ops->suspend(dc);
2641
2642         if (dc->enabled) {
2643                 _tegra_dc_disable(dc);
2644
2645                 dc->suspended = true;
2646         }
2647
2648         if (dc->out && dc->out->postsuspend)
2649                 dc->out->postsuspend();
2650
2651         tegra_dc_io_end(dc);
2652         mutex_unlock(&dc->lock);
2653         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2654
2655         return 0;
2656 }
2657
2658 static int tegra_dc_resume(struct platform_device *ndev)
2659 {
2660         struct tegra_dc *dc = platform_get_drvdata(ndev);
2661
2662         trace_display_resume(dc);
2663         dev_info(&ndev->dev, "resume\n");
2664
2665         mutex_lock(&dc->lock);
2666         dc->suspended = false;
2667
2668         /* To pan the fb on resume */
2669         tegra_fb_pan_display_reset(dc->fb);
2670
2671         if (dc->enabled) {
2672                 dc->enabled = false;
2673                 _tegra_dc_set_default_videomode(dc);
2674                 dc->enabled = _tegra_dc_enable(dc);
2675         }
2676
2677         if (dc->out_ops && dc->out_ops->resume)
2678                 dc->out_ops->resume(dc);
2679         mutex_unlock(&dc->lock);
2680
2681         return 0;
2682 }
2683
2684 #endif /* CONFIG_PM */
2685
2686 static void tegra_dc_shutdown(struct platform_device *ndev)
2687 {
2688         struct tegra_dc *dc = platform_get_drvdata(ndev);
2689
2690         if (!dc || !dc->enabled)
2691                 return;
2692
2693         tegra_dc_disable(dc);
2694 }
2695
2696 extern int suspend_set(const char *val, struct kernel_param *kp)
2697 {
2698         if (!strcmp(val, "dump"))
2699                 dump_regs(tegra_dcs[0]);
2700 #ifdef CONFIG_PM
2701         else if (!strcmp(val, "suspend"))
2702                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2703         else if (!strcmp(val, "resume"))
2704                 tegra_dc_resume(tegra_dcs[0]->ndev);
2705 #endif
2706
2707         return 0;
2708 }
2709
2710 extern int suspend_get(char *buffer, struct kernel_param *kp)
2711 {
2712         return 0;
2713 }
2714
2715 int suspend;
2716
2717 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2718
2719
2720 #ifdef CONFIG_OF
2721 static struct of_device_id tegra_display_of_match[] __devinitdata = {
2722         {.compatible = "nvidia,tegra114-dc", },
2723         { },
2724 };
2725 #endif
2726
2727 struct platform_driver tegra_dc_driver = {
2728         .driver = {
2729                 .name = "tegradc",
2730                 .owner = THIS_MODULE,
2731 #ifdef CONFIG_OF
2732                 .of_match_table = tegra_display_of_match,
2733 #endif
2734         },
2735         .probe = tegra_dc_probe,
2736         .remove = tegra_dc_remove,
2737 #ifdef CONFIG_PM
2738         .suspend = tegra_dc_suspend,
2739         .resume = tegra_dc_resume,
2740 #endif
2741         .shutdown = tegra_dc_shutdown,
2742 };
2743
2744 #ifndef MODULE
2745 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2746 {
2747         int i, params[11];
2748         char *p;
2749
2750         for (i = 0; i < ARRAY_SIZE(params); i++) {
2751                 if ((p = strsep(&options, ",")) != NULL) {
2752                         if (*p)
2753                                 params[i] = simple_strtoul(p, &p, 10);
2754                 } else
2755                         return -EINVAL;
2756         }
2757
2758         if ((mode->pclk = params[0]) == 0)
2759                 return -EINVAL;
2760
2761         mode->h_active      = params[1];
2762         mode->v_active      = params[2];
2763         mode->h_ref_to_sync = params[3];
2764         mode->v_ref_to_sync = params[4];
2765         mode->h_sync_width  = params[5];
2766         mode->v_sync_width  = params[6];
2767         mode->h_back_porch  = params[7];
2768         mode->v_back_porch  = params[8];
2769         mode->h_front_porch = params[9];
2770         mode->v_front_porch = params[10];
2771
2772         return 0;
2773 }
2774
2775 static int __init tegra_dc_mode_override(char *str)
2776 {
2777         char *p = str, *options;
2778
2779         if (!p || !*p)
2780                 return -EINVAL;
2781
2782         p = strstr(str, "hdmi:");
2783         if (p) {
2784                 p += 5;
2785                 options = strsep(&p, ";");
2786                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2787                         return -EINVAL;
2788         }
2789
2790         p = strstr(str, "rgb:");
2791         if (p) {
2792                 p += 4;
2793                 options = strsep(&p, ";");
2794                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2795                         return -EINVAL;
2796         }
2797
2798         p = strstr(str, "dsi:");
2799         if (p) {
2800                 p += 4;
2801                 options = strsep(&p, ";");
2802                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2803                         return -EINVAL;
2804         }
2805
2806         return 0;
2807 }
2808
2809 __setup("disp_params=", tegra_dc_mode_override);
2810 #endif
2811
2812 static int __init tegra_dc_module_init(void)
2813 {
2814         int ret = tegra_dc_ext_module_init();
2815         if (ret)
2816                 return ret;
2817         return platform_driver_register(&tegra_dc_driver);
2818 }
2819
2820 static void __exit tegra_dc_module_exit(void)
2821 {
2822         platform_driver_unregister(&tegra_dc_driver);
2823         tegra_dc_ext_module_exit();
2824 }
2825
2826 module_exit(tegra_dc_module_exit);
2827 module_init(tegra_dc_module_init);