drivers/video/tegra/dc/dc.c

   1 /*
   2  * drivers/video/tegra/dc/dc.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (C) 2010-2011 NVIDIA Corporation
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/mutex.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/workqueue.h>
  32 #include <linux/ktime.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/backlight.h>
  36 #include <video/tegrafb.h>
  37 #include <drm/drm_fixed.h>
  38
  39 #include <mach/clk.h>
  40 #include <mach/dc.h>
  41 #include <mach/fb.h>
  42 #include <mach/mc.h>
  43 #include <linux/nvhost.h>
  44 #include <mach/latency_allowance.h>
  45
  46 #include "dc_reg.h"
  47 #include "dc_priv.h"
  48 #include "overlay.h"
  49 #include "nvsd.h"
  50
  51 #define TEGRA_CRC_LATCHED_DELAY         34
  52
  53 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
  54 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
  55 #else
  56 /* ignore underflows when on simulation and fpga platform */
  57 #define ALL_UF_INT (0)
  58 #endif
  59
  60 static int no_vsync;
  61
  62 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
  63
  64 static int use_dynamic_emc = 1;
  65
  66 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
  67
  68 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
  69
  70 DEFINE_MUTEX(tegra_dc_lock);
  71 DEFINE_MUTEX(shared_lock);
  72
  73 static const struct {
  74         bool h;
  75         bool v;
  76 } can_filter[] = {
  77         /* Window A has no filtering */
  78         { false, false },
  79         /* Window B has both H and V filtering */
  80         { true,  true  },
  81         /* Window C has only H filtering */
  82         { false, true  },
  83 };
  84 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
  85 {
  86         return can_filter[win->idx].v &&
  87                 win->h.full != dfixed_const(win->out_h);
  88 }
  89 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
  90 {
  91         return can_filter[win->idx].h &&
  92                 win->w.full != dfixed_const(win->out_w);
  93 }
  94
  95 static inline int tegra_dc_fmt_bpp(int fmt)
  96 {
  97         switch (fmt) {
  98         case TEGRA_WIN_FMT_P1:
  99                 return 1;
 100
 101         case TEGRA_WIN_FMT_P2:
 102                 return 2;
 103
 104         case TEGRA_WIN_FMT_P4:
 105                 return 4;
 106
 107         case TEGRA_WIN_FMT_P8:
 108                 return 8;
 109
 110         case TEGRA_WIN_FMT_B4G4R4A4:
 111         case TEGRA_WIN_FMT_B5G5R5A:
 112         case TEGRA_WIN_FMT_B5G6R5:
 113         case TEGRA_WIN_FMT_AB5G5R5:
 114                 return 16;
 115
 116         case TEGRA_WIN_FMT_B8G8R8A8:
 117         case TEGRA_WIN_FMT_R8G8B8A8:
 118         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
 119         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
 120                 return 32;
 121
 122         /* for planar formats, size of the Y plane, 8bit */
 123         case TEGRA_WIN_FMT_YCbCr420P:
 124         case TEGRA_WIN_FMT_YUV420P:
 125         case TEGRA_WIN_FMT_YCbCr422P:
 126         case TEGRA_WIN_FMT_YUV422P:
 127                 return 8;
 128
 129         case TEGRA_WIN_FMT_YCbCr422:
 130         case TEGRA_WIN_FMT_YUV422:
 131         case TEGRA_WIN_FMT_YCbCr422R:
 132         case TEGRA_WIN_FMT_YUV422R:
 133         case TEGRA_WIN_FMT_YCbCr422RA:
 134         case TEGRA_WIN_FMT_YUV422RA:
 135                 /* FIXME: need to know the bpp of these formats */
 136                 return 0;
 137         }
 138         return 0;
 139 }
 140
 141 static inline bool tegra_dc_is_yuv_planar(int fmt)
 142 {
 143         switch (fmt) {
 144         case TEGRA_WIN_FMT_YUV420P:
 145         case TEGRA_WIN_FMT_YCbCr420P:
 146         case TEGRA_WIN_FMT_YCbCr422P:
 147         case TEGRA_WIN_FMT_YUV422P:
 148                 return true;
 149         }
 150         return false;
 151 }
 152
 153 #define DUMP_REG(a) do {                        \
 154         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
 155                  #a, a, tegra_dc_readl(dc, a));               \
 156         print(data, buff);                                    \
 157         } while (0)
 158
 159 static void _dump_regs(struct tegra_dc *dc, void *data,
 160                        void (* print)(void *data, const char *str))
 161 {
 162         int i;
 163         char buff[256];
 164
 165         tegra_dc_io_start(dc);
 166         clk_enable(dc->clk);
 167
 168         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 169         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 170         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 171         DUMP_REG(DC_CMD_INT_STATUS);
 172         DUMP_REG(DC_CMD_INT_MASK);
 173         DUMP_REG(DC_CMD_INT_ENABLE);
 174         DUMP_REG(DC_CMD_INT_TYPE);
 175         DUMP_REG(DC_CMD_INT_POLARITY);
 176         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 177         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 178         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 179         DUMP_REG(DC_CMD_STATE_ACCESS);
 180         DUMP_REG(DC_CMD_STATE_CONTROL);
 181         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 182         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 183
 184         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 185         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 186         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 187         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
 188         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
 189         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 190         DUMP_REG(DC_DISP_REF_TO_SYNC);
 191         DUMP_REG(DC_DISP_SYNC_WIDTH);
 192         DUMP_REG(DC_DISP_BACK_PORCH);
 193         DUMP_REG(DC_DISP_DISP_ACTIVE);
 194         DUMP_REG(DC_DISP_FRONT_PORCH);
 195         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 196         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 197         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 198         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 199         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 200         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 201         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 202         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 203         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 204         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 205         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 206         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 207         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 208         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 209         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 210         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 211         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 212         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 213         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 214         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 215         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 216         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 217         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 218         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 219         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 220         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 221         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 222         DUMP_REG(DC_DISP_M0_CONTROL);
 223         DUMP_REG(DC_DISP_M1_CONTROL);
 224         DUMP_REG(DC_DISP_DI_CONTROL);
 225         DUMP_REG(DC_DISP_PP_CONTROL);
 226         DUMP_REG(DC_DISP_PP_SELECT_A);
 227         DUMP_REG(DC_DISP_PP_SELECT_B);
 228         DUMP_REG(DC_DISP_PP_SELECT_C);
 229         DUMP_REG(DC_DISP_PP_SELECT_D);
 230         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 231         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 232         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 233         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 234         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 235         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 236         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 237         DUMP_REG(DC_DISP_BORDER_COLOR);
 238         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 239         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 240         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 241         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 242         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 243         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 244         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 245         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 246         DUMP_REG(DC_DISP_CURSOR_POSITION);
 247         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 248         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 249         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 250         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 251         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 252         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 253         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 254         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 255         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 256         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
 257         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 258         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 259         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 260
 261
 262         for (i = 0; i < 3; i++) {
 263                 print(data, "\n");
 264                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
 265                 print(data, buff);
 266
 267                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
 268                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 269                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 270                 DUMP_REG(DC_WIN_WIN_OPTIONS);
 271                 DUMP_REG(DC_WIN_BYTE_SWAP);
 272                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
 273                 DUMP_REG(DC_WIN_COLOR_DEPTH);
 274                 DUMP_REG(DC_WIN_POSITION);
 275                 DUMP_REG(DC_WIN_SIZE);
 276                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
 277                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
 278                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
 279                 DUMP_REG(DC_WIN_DDA_INCREMENT);
 280                 DUMP_REG(DC_WIN_LINE_STRIDE);
 281                 DUMP_REG(DC_WIN_BUF_STRIDE);
 282                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 283                 DUMP_REG(DC_WIN_BLEND_NOKEY);
 284                 DUMP_REG(DC_WIN_BLEND_1WIN);
 285                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
 286                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 287                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 288                 DUMP_REG(DC_WINBUF_START_ADDR);
 289                 DUMP_REG(DC_WINBUF_START_ADDR_U);
 290                 DUMP_REG(DC_WINBUF_START_ADDR_V);
 291                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 292                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 293                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 294                 DUMP_REG(DC_WIN_CSC_YOF);
 295                 DUMP_REG(DC_WIN_CSC_KYRGB);
 296                 DUMP_REG(DC_WIN_CSC_KUR);
 297                 DUMP_REG(DC_WIN_CSC_KVR);
 298                 DUMP_REG(DC_WIN_CSC_KUG);
 299                 DUMP_REG(DC_WIN_CSC_KVG);
 300                 DUMP_REG(DC_WIN_CSC_KUB);
 301                 DUMP_REG(DC_WIN_CSC_KVB);
 302         }
 303
 304         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 305         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
 306         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
 307         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
 308         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
 309         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
 310         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 311         DUMP_REG(DC_DISP_M1_CONTROL);
 312         DUMP_REG(DC_COM_PM1_CONTROL);
 313         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
 314         DUMP_REG(DC_DISP_SD_CONTROL);
 315
 316         clk_disable(dc->clk);
 317         tegra_dc_io_end(dc);
 318 }
 319
 320 #undef DUMP_REG
 321
 322 #ifdef DEBUG
 323 static void dump_regs_print(void *data, const char *str)
 324 {
 325         struct tegra_dc *dc = data;
 326         dev_dbg(&dc->ndev->dev, "%s", str);
 327 }
 328
 329 static void dump_regs(struct tegra_dc *dc)
 330 {
 331         _dump_regs(dc, dc, dump_regs_print);
 332 }
 333 #else /* !DEBUG */
 334
 335 static void dump_regs(struct tegra_dc *dc) {}
 336
 337 #endif /* DEBUG */
 338
 339 #ifdef CONFIG_DEBUG_FS
 340
 341 static void dbg_regs_print(void *data, const char *str)
 342 {
 343         struct seq_file *s = data;
 344
 345         seq_printf(s, "%s", str);
 346 }
 347
 348 #undef DUMP_REG
 349
 350 static int dbg_dc_show(struct seq_file *s, void *unused)
 351 {
 352         struct tegra_dc *dc = s->private;
 353
 354         _dump_regs(dc, s, dbg_regs_print);
 355
 356         return 0;
 357 }
 358
 359
 360 static int dbg_dc_open(struct inode *inode, struct file *file)
 361 {
 362         return single_open(file, dbg_dc_show, inode->i_private);
 363 }
 364
 365 static const struct file_operations regs_fops = {
 366         .open           = dbg_dc_open,
 367         .read           = seq_read,
 368         .llseek         = seq_lseek,
 369         .release        = single_release,
 370 };
 371
 372 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
 373 {
 374         struct tegra_dc *dc = s->private;
 375         struct tegra_dc_mode *m;
 376
 377         mutex_lock(&dc->lock);
 378         m = &dc->mode;
 379         seq_printf(s,
 380                 "pclk: %d\n"
 381                 "h_ref_to_sync: %d\n"
 382                 "v_ref_to_sync: %d\n"
 383                 "h_sync_width: %d\n"
 384                 "v_sync_width: %d\n"
 385                 "h_back_porch: %d\n"
 386                 "v_back_porch: %d\n"
 387                 "h_active: %d\n"
 388                 "v_active: %d\n"
 389                 "h_front_porch: %d\n"
 390                 "v_front_porch: %d\n"
 391                 "stereo_mode: %d\n",
 392                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
 393                 m->h_sync_width, m->v_sync_width,
 394                 m->h_back_porch, m->v_back_porch,
 395                 m->h_active, m->v_active,
 396                 m->h_front_porch, m->v_front_porch,
 397                 m->stereo_mode);
 398         mutex_unlock(&dc->lock);
 399         return 0;
 400 }
 401
 402 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
 403 {
 404         return single_open(file, dbg_dc_mode_show, inode->i_private);
 405 }
 406
 407 static const struct file_operations mode_fops = {
 408         .open           = dbg_dc_mode_open,
 409         .read           = seq_read,
 410         .llseek         = seq_lseek,
 411         .release        = single_release,
 412 };
 413
 414 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
 415 {
 416         struct tegra_dc *dc = s->private;
 417
 418         mutex_lock(&dc->lock);
 419         seq_printf(s,
 420                 "underflows: %llu\n"
 421                 "underflows_a: %llu\n"
 422                 "underflows_b: %llu\n"
 423                 "underflows_c: %llu\n",
 424                 dc->stats.underflows,
 425                 dc->stats.underflows_a,
 426                 dc->stats.underflows_b,
 427                 dc->stats.underflows_c);
 428         mutex_unlock(&dc->lock);
 429
 430         return 0;
 431 }
 432
 433 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
 434 {
 435         return single_open(file, dbg_dc_stats_show, inode->i_private);
 436 }
 437
 438 static const struct file_operations stats_fops = {
 439         .open           = dbg_dc_stats_open,
 440         .read           = seq_read,
 441         .llseek         = seq_lseek,
 442         .release        = single_release,
 443 };
 444
 445 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
 446 {
 447         if (dc->debugdir)
 448                 debugfs_remove_recursive(dc->debugdir);
 449         dc->debugdir = NULL;
 450 }
 451
 452 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
 453 {
 454         struct dentry *retval;
 455
 456         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
 457         if (!dc->debugdir)
 458                 goto remove_out;
 459
 460         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
 461                 &regs_fops);
 462         if (!retval)
 463                 goto remove_out;
 464
 465         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
 466                 &mode_fops);
 467         if (!retval)
 468                 goto remove_out;
 469
 470         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
 471                 &stats_fops);
 472         if (!retval)
 473                 goto remove_out;
 474
 475         return;
 476 remove_out:
 477         dev_err(&dc->ndev->dev, "could not create debugfs\n");
 478         tegra_dc_remove_debugfs(dc);
 479 }
 480
 481 #else /* !CONFIG_DEBUGFS */
 482 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
 483 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
 484 #endif /* CONFIG_DEBUGFS */
 485
 486 static int tegra_dc_set(struct tegra_dc *dc, int index)
 487 {
 488         int ret = 0;
 489
 490         mutex_lock(&tegra_dc_lock);
 491         if (index >= TEGRA_MAX_DC) {
 492                 ret = -EINVAL;
 493                 goto out;
 494         }
 495
 496         if (dc != NULL && tegra_dcs[index] != NULL) {
 497                 ret = -EBUSY;
 498                 goto out;
 499         }
 500
 501         tegra_dcs[index] = dc;
 502
 503 out:
 504         mutex_unlock(&tegra_dc_lock);
 505
 506         return ret;
 507 }
 508
 509 unsigned int tegra_dc_has_multiple_dc(void)
 510 {
 511         unsigned int idx;
 512         unsigned int cnt = 0;
 513         struct tegra_dc *dc;
 514
 515         mutex_lock(&tegra_dc_lock);
 516         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
 517                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
 518         mutex_unlock(&tegra_dc_lock);
 519
 520         return (cnt > 1);
 521 }
 522
 523 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
 524 {
 525         if (idx < TEGRA_MAX_DC)
 526                 return tegra_dcs[idx];
 527         else
 528                 return NULL;
 529 }
 530 EXPORT_SYMBOL(tegra_dc_get_dc);
 531
 532 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
 533 {
 534         if (win >= dc->n_windows)
 535                 return NULL;
 536
 537         return &dc->windows[win];
 538 }
 539 EXPORT_SYMBOL(tegra_dc_get_window);
 540
 541 static int get_topmost_window(u32 *depths, unsigned long *wins)
 542 {
 543         int idx, best = -1;
 544
 545         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
 546                 if (best == -1 || depths[idx] < depths[best])
 547                         best = idx;
 548         }
 549         clear_bit(best, wins);
 550         return best;
 551 }
 552
 553 bool tegra_dc_get_connected(struct tegra_dc *dc)
 554 {
 555         return dc->connected;
 556 }
 557 EXPORT_SYMBOL(tegra_dc_get_connected);
 558
 559 static u32 blend_topwin(u32 flags)
 560 {
 561         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
 562                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
 563         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
 564                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
 565         else
 566                 return BLEND(NOKEY, FIX, 0xff, 0xff);
 567 }
 568
 569 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
 570 {
 571         int other;
 572
 573         for (other = 0; other < DC_N_WINDOWS; other++) {
 574                 if (other != idx && (xy-- == 0))
 575                         break;
 576         }
 577         if (BIT(other) & behind_mask)
 578                 return blend_topwin(flags[idx]);
 579         else if (flags[other])
 580                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
 581         else
 582                 return BLEND(NOKEY, FIX, 0x00, 0x00);
 583 }
 584
 585 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
 586 {
 587         unsigned long infront_mask;
 588         int first;
 589
 590         infront_mask = ~(behind_mask | BIT(idx));
 591         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
 592         first = ffs(infront_mask) - 1;
 593
 594         if (!infront_mask)
 595                 return blend_topwin(flags[idx]);
 596         else if (behind_mask && first != -1 && flags[first])
 597                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
 598         else
 599                 return BLEND(NOKEY, FIX, 0x0, 0x0);
 600 }
 601
 602 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
 603 {
 604         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
 605
 606         while (mask) {
 607                 int idx = get_topmost_window(blend->z, &mask);
 608
 609                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
 610                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 611                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
 612                                 DC_WIN_BLEND_NOKEY);
 613                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
 614                                 DC_WIN_BLEND_1WIN);
 615                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
 616                                 DC_WIN_BLEND_2WIN_X);
 617                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
 618                                 DC_WIN_BLEND_2WIN_Y);
 619                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
 620                                 DC_WIN_BLEND_3WIN_XY);
 621         }
 622 }
 623
 624 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
 625 {
 626         csc->yof   = 0x00f0;
 627         csc->kyrgb = 0x012a;
 628         csc->kur   = 0x0000;
 629         csc->kvr   = 0x0198;
 630         csc->kug   = 0x039b;
 631         csc->kvg   = 0x032f;
 632         csc->kub   = 0x0204;
 633         csc->kvb   = 0x0000;
 634 }
 635
 636 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
 637 {
 638         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
 639         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
 640         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
 641         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
 642         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
 643         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
 644         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
 645         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
 646 }
 647
 648 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
 649 {
 650         mutex_lock(&dc->lock);
 651
 652         if (!dc->enabled) {
 653                 mutex_unlock(&dc->lock);
 654                 return -EFAULT;
 655         }
 656
 657         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
 658                         DC_CMD_DISPLAY_WINDOW_HEADER);
 659
 660         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
 661
 662         mutex_unlock(&dc->lock);
 663
 664         return 0;
 665 }
 666 EXPORT_SYMBOL(tegra_dc_update_csc);
 667
 668 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
 669 {
 670         int i;
 671         for (i = 0; i < 256; i++)
 672                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
 673 }
 674
 675 static int tegra_dc_lut_is_defaults(struct tegra_dc_lut *lut)
 676 {
 677         unsigned int i;
 678         for (i = 0; i < 256; i++)
 679                 if ((lut->r[i] != i) || (lut->g[i] != i) || (lut->b[i] != i))
 680                         return 0;
 681         return 1;
 682 }
 683
 684 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
 685 {
 686         unsigned int i;
 687         unsigned long val;
 688         struct tegra_dc_lut *lut = &win->lut;
 689
 690         for (i = 0; i < 256; i++) {
 691                 u32 rgb = ((u32)lut->r[i]) |
 692                           ((u32)lut->g[i]<<8) |
 693                           ((u32)lut->b[i]<<16);
 694                 tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
 695         }
 696
 697         val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 698
 699         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
 700                 val |= CP_ENABLE;
 701         else
 702                 val &= ~CP_ENABLE;
 703
 704         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
 705 }
 706
 707 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
 708 {
 709         struct tegra_dc_win *win = &dc->windows[win_idx];
 710
 711         mutex_lock(&dc->lock);
 712
 713         if (!dc->enabled) {
 714                 mutex_unlock(&dc->lock);
 715                 return -EFAULT;
 716         }
 717
 718         if (!tegra_dc_lut_is_defaults(&win->lut))
 719                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
 720         else
 721                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
 722
 723         if (fboveride)
 724                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
 725         else
 726                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
 727
 728         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
 729                         DC_CMD_DISPLAY_WINDOW_HEADER);
 730
 731         tegra_dc_set_lut(dc, win);
 732
 733         mutex_unlock(&dc->lock);
 734
 735         return 0;
 736 }
 737 EXPORT_SYMBOL(tegra_dc_update_lut);
 738
 739 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
 740 {
 741         unsigned i;
 742         unsigned v0 = 128;
 743         unsigned v1 = 0;
 744         /* linear horizontal and vertical filters */
 745         for (i = 0; i < 16; i++) {
 746                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
 747                                 DC_WIN_H_FILTER_P(i));
 748
 749                 tegra_dc_writel(dc, v0,
 750                                 DC_WIN_V_FILTER_P(i));
 751                 v0 -= 8;
 752                 v1 += 8;
 753         }
 754 }
 755
 756 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
 757         struct tegra_dc_win *w)
 758 {
 759         /* windows A, B, C for first and second display */
 760         static const enum tegra_la_id la_id_tab[2][3] = {
 761                 /* first display */
 762                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
 763                         TEGRA_LA_DISPLAY_0C },
 764                 /* second display */
 765                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
 766                         TEGRA_LA_DISPLAY_0CB },
 767         };
 768         /* window B V-filter tap for first and second display. */
 769         static const enum tegra_la_id vfilter_tab[2] = {
 770                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
 771         };
 772         unsigned long bw;
 773
 774         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
 775         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
 776         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
 777
 778         bw = w->new_bandwidth;
 779
 780         /* tegra_dc_get_bandwidth() treats V filter windows as double
 781          * bandwidth, but LA has a seperate client for V filter */
 782         if (w->idx == 1 && win_use_v_filter(w))
 783                 bw /= 2;
 784
 785         /* our bandwidth is in bytes/sec, but LA takes MBps.
 786          * round up bandwidth to 1MBps */
 787         bw = bw / 1000000 + 1;
 788
 789 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
 790         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
 791         /* if window B, also set the 1B client for the 2-tap V filter. */
 792         if (w->idx == 1)
 793                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
 794 #endif
 795
 796         w->bandwidth = w->new_bandwidth;
 797 }
 798
 799 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
 800                                                    struct tegra_dc_win *b)
 801 {
 802         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
 803                 return 0;
 804
 805         /* because memory access to load the fifo can overlap, only care
 806          * if windows overlap vertically */
 807         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
 808                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
 809 }
 810
 811 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
 812                                                  int n)
 813 {
 814         unsigned i;
 815         unsigned j;
 816         unsigned overlap_count;
 817         unsigned max_bw = 0;
 818
 819         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
 820                          "inaccurate.\n");
 821
 822         /* If we had a large number of windows, we would compute adjacency
 823          * graph representing 2 window overlaps, find all cliques in the graph,
 824          * assign bandwidth to each clique, and then select the clique with
 825          * maximum bandwidth. But because we have at most 3 windows,
 826          * implementing proper Bron-Kerbosh algorithm would be an overkill,
 827          * brute force will suffice.
 828          *
 829          * Thus: find maximum bandwidth for either single or a pair of windows
 830          * and count number of window pair overlaps. If there are three
 831          * pairs, all 3 window overlap.
 832          */
 833
 834         overlap_count = 0;
 835         for (i = 0; i < n; i++) {
 836                 unsigned int bw1;
 837
 838                 if (wins[i] == NULL)
 839                         continue;
 840                 bw1 = wins[i]->new_bandwidth;
 841                 if (bw1 > max_bw)
 842                         /* Single window */
 843                         max_bw = bw1;
 844
 845                 for (j = i + 1; j < n; j++) {
 846                         if (wins[j] == NULL)
 847                                 continue;
 848                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
 849                                 unsigned int bw2 = wins[j]->new_bandwidth;
 850                                 if (bw1 + bw2 > max_bw)
 851                                         /* Window pair overlaps */
 852                                         max_bw = bw1 + bw2;
 853                                 overlap_count++;
 854                         }
 855                 }
 856         }
 857
 858         if (overlap_count == 3)
 859                 /* All three windows overlap */
 860                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
 861                          wins[2]->new_bandwidth;
 862
 863         return max_bw;
 864 }
 865
 866 /*
 867  * Calculate peak EMC bandwidth for each enabled window =
 868  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
 869  * (windows_tiling ? 2 : 1)
 870  *
 871  *
 872  * note:
 873  * (*) We use 2 tap V filter, so need double BW if use V filter
 874  * (*) Tiling mode on T30 and DDR3 requires double BW
 875  */
 876 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
 877         struct tegra_dc_win *w)
 878 {
 879         unsigned long ret;
 880         int tiled_windows_bw_multiplier;
 881         unsigned long bpp;
 882
 883         if (!WIN_IS_ENABLED(w))
 884                 return 0;
 885
 886         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
 887             w->out_w == 0 || w->out_h == 0)
 888                 return 0;
 889
 890         tiled_windows_bw_multiplier =
 891                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
 892
 893         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
 894          * but the size reported by tegra_dc_fmt_bpp for the planar version
 895          * is of the luma plane's size only. */
 896         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
 897                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
 898         /* perform calculations with most significant bits of pixel clock
 899          * to prevent overflow of long. */
 900         ret = (unsigned long)(dc->pixel_clk >> 16) *
 901                 bpp / 8 *
 902                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
 903                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
 904
 905 /*
 906  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
 907  * will request 147MBps from EMC.
 908  */
 909         ret = ret * 2 + ret / 10;
 910
 911         /* if overflowed */
 912         if (ret > (1UL << 31))
 913                 return ULONG_MAX;
 914
 915         return ret << 16; /* restore the scaling we did above */
 916 }
 917
 918 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
 919 {
 920         int i;
 921
 922         BUG_ON(n > DC_N_WINDOWS);
 923
 924         /* emc rate and latency allowance both need to know per window
 925          * bandwidths */
 926         for (i = 0; i < n; i++) {
 927                 struct tegra_dc_win *w = windows[i];
 928                 if (w)
 929                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
 930         }
 931
 932         return tegra_dc_find_max_bandwidth(windows, n);
 933 }
 934
 935 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
 936 {
 937         unsigned i;
 938
 939         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
 940                 dc->emc_clk_rate = dc->new_emc_clk_rate;
 941                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
 942         }
 943
 944         for (i = 0; i < DC_N_WINDOWS; i++) {
 945                 struct tegra_dc_win *w = &dc->windows[i];
 946                 if (w->bandwidth != w->new_bandwidth)
 947                         tegra_dc_set_latency_allowance(dc, w);
 948         }
 949 }
 950
 951 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
 952 {
 953         unsigned long new_rate;
 954         struct tegra_dc *dc;
 955
 956         if (!use_dynamic_emc)
 957                 return 0;
 958
 959         dc = windows[0]->dc;
 960
 961         /* calculate the new rate based on this POST */
 962         new_rate = tegra_dc_get_bandwidth(windows, n);
 963         new_rate = EMC_BW_TO_FREQ(new_rate);
 964
 965         if (tegra_dc_has_multiple_dc())
 966                 new_rate = ULONG_MAX;
 967
 968         dc->new_emc_clk_rate = new_rate;
 969
 970         return 0;
 971 }
 972
 973 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
 974                                   bool v, unsigned Bpp)
 975 {
 976         /*
 977          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
 978          *           (post_scaled_size_in_pixels - 1)), MAX)
 979          * Where the value of MAX is as follows:
 980          * For V_DDA_INCREMENT: 15.0 (0xF000)
 981          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
 982          *                       8.0 (0x8000) for 2 Bytes/pix formats.
 983          */
 984
 985         fixed20_12 out = dfixed_init(out_int);
 986         u32 dda_inc;
 987         int max;
 988
 989         if (v) {
 990                 max = 15;
 991         } else {
 992                 switch (Bpp) {
 993                 default:
 994                         WARN_ON_ONCE(1);
 995                         /* fallthrough */
 996                 case 4:
 997                         max = 4;
 998                         break;
 999                 case 2:
1000                         max = 8;
1001                         break;
1002                 }
1003         }
1004
1005         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1006         in.full -= dfixed_const(1);
1007
1008         dda_inc = dfixed_div(in, out);
1009
1010         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1011
1012         return dda_inc;
1013 }
1014
1015 static inline u32 compute_initial_dda(fixed20_12 in)
1016 {
1017         return dfixed_frac(in);
1018 }
1019
1020 /* does not support updating windows on multiple dcs in one call */
1021 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1022 {
1023         struct tegra_dc *dc;
1024         unsigned long update_mask = GENERAL_ACT_REQ;
1025         unsigned long val;
1026         bool update_blend = false;
1027         int i;
1028
1029         dc = windows[0]->dc;
1030
1031         mutex_lock(&dc->lock);
1032
1033         if (!dc->enabled) {
1034                 mutex_unlock(&dc->lock);
1035                 return -EFAULT;
1036         }
1037
1038         if (no_vsync)
1039                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1040         else
1041                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1042
1043         for (i = 0; i < n; i++) {
1044                 struct tegra_dc_win *win = windows[i];
1045                 unsigned h_dda;
1046                 unsigned v_dda;
1047                 fixed20_12 h_offset, v_offset;
1048                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1049                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1050                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1051                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1052                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1053                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1054                 const bool filter_h = win_use_h_filter(win);
1055                 const bool filter_v = win_use_v_filter(win);
1056
1057                 if (win->z != dc->blend.z[win->idx]) {
1058                         dc->blend.z[win->idx] = win->z;
1059                         update_blend = true;
1060                 }
1061                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1062                         dc->blend.flags[win->idx]) {
1063                         dc->blend.flags[win->idx] =
1064                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1065                         update_blend = true;
1066                 }
1067
1068                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1069                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1070
1071                 if (!no_vsync)
1072                         update_mask |= WIN_A_ACT_REQ << win->idx;
1073
1074                 if (!WIN_IS_ENABLED(win)) {
1075                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1076                         continue;
1077                 }
1078
1079                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1080                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1081
1082                 tegra_dc_writel(dc,
1083                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1084                                 DC_WIN_POSITION);
1085                 tegra_dc_writel(dc,
1086                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1087                                 DC_WIN_SIZE);
1088                 tegra_dc_writel(dc,
1089                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1090                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1091                                 DC_WIN_PRESCALED_SIZE);
1092
1093                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1094                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1095                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1096                                 DC_WIN_DDA_INCREMENT);
1097                 h_dda = compute_initial_dda(win->x);
1098                 v_dda = compute_initial_dda(win->y);
1099                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1100                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1101
1102                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1103                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1104                 tegra_dc_writel(dc,
1105                                 (unsigned long)win->phys_addr,
1106                                 DC_WINBUF_START_ADDR);
1107
1108                 if (!yuvp) {
1109                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1110                 } else {
1111                         tegra_dc_writel(dc,
1112                                         (unsigned long)win->phys_addr_u,
1113                                         DC_WINBUF_START_ADDR_U);
1114                         tegra_dc_writel(dc,
1115                                         (unsigned long)win->phys_addr_v,
1116                                         DC_WINBUF_START_ADDR_V);
1117                         tegra_dc_writel(dc,
1118                                         LINE_STRIDE(win->stride) |
1119                                         UV_LINE_STRIDE(win->stride_uv),
1120                                         DC_WIN_LINE_STRIDE);
1121                 }
1122
1123                 h_offset = win->x;
1124                 if (invert_h) {
1125                         h_offset.full += win->w.full - dfixed_const(1);
1126                 }
1127
1128                 v_offset = win->y;
1129                 if (invert_v) {
1130                         v_offset.full += win->h.full - dfixed_const(1);
1131                 }
1132
1133                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1134                                 DC_WINBUF_ADDR_H_OFFSET);
1135                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1136                                 DC_WINBUF_ADDR_V_OFFSET);
1137
1138                 if (WIN_IS_TILED(win))
1139                         tegra_dc_writel(dc,
1140                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1141                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1142                                         DC_WIN_BUFFER_ADDR_MODE);
1143                 else
1144                         tegra_dc_writel(dc,
1145                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1146                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1147                                         DC_WIN_BUFFER_ADDR_MODE);
1148
1149                 val = WIN_ENABLE;
1150                 if (yuvp)
1151                         val |= CSC_ENABLE;
1152                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1153                         val |= COLOR_EXPAND;
1154
1155                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1156                         val |= CP_ENABLE;
1157
1158                 if (filter_h)
1159                         val |= H_FILTER_ENABLE;
1160                 if (filter_v)
1161                         val |= V_FILTER_ENABLE;
1162
1163                 if (invert_h)
1164                         val |= H_DIRECTION_DECREMENT;
1165                 if (invert_v)
1166                         val |= V_DIRECTION_DECREMENT;
1167
1168                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1169
1170                 win->dirty = no_vsync ? 0 : 1;
1171
1172                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1173                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1174                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1175                         __func__, win->idx, win->z,
1176                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1177                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1178                         win->out_x, win->out_y, win->out_w, win->out_h,
1179                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1180         }
1181
1182         if (update_blend) {
1183                 tegra_dc_set_blending(dc, &dc->blend);
1184                 for (i = 0; i < DC_N_WINDOWS; i++) {
1185                         if (!no_vsync)
1186                                 dc->windows[i].dirty = 1;
1187                         update_mask |= WIN_A_ACT_REQ << i;
1188                 }
1189         }
1190
1191         tegra_dc_set_dynamic_emc(windows, n);
1192
1193         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1194
1195         if (!no_vsync) {
1196                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1197                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1198                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1199         } else {
1200                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1201                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1202
1203                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1204         }
1205
1206         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1207
1208         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1209                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1210
1211         mutex_unlock(&dc->lock);
1212
1213         return 0;
1214 }
1215 EXPORT_SYMBOL(tegra_dc_update_windows);
1216
1217 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1218 {
1219         return dc->syncpt[i].id;
1220 }
1221 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1222
1223 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1224 {
1225         u32 max;
1226
1227         mutex_lock(&dc->lock);
1228         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1229                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1230         dc->syncpt[i].max = max;
1231         mutex_unlock(&dc->lock);
1232
1233         return max;
1234 }
1235
1236 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1237 {
1238         mutex_lock(&dc->lock);
1239         if ( dc->enabled )
1240                 while (dc->syncpt[i].min < val) {
1241                         dc->syncpt[i].min++;
1242                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1243                                         dc->syncpt[i].id);
1244                 }
1245         mutex_unlock(&dc->lock);
1246 }
1247
1248 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1249                                              int n)
1250 {
1251         int i;
1252
1253         for (i = 0; i < n; i++) {
1254                 if (windows[i]->dirty)
1255                         return false;
1256         }
1257
1258         return true;
1259 }
1260
1261 /* does not support syncing windows on multiple dcs in one call */
1262 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1263 {
1264         if (n < 1 || n > DC_N_WINDOWS)
1265                 return -EINVAL;
1266
1267         if (!windows[0]->dc->enabled)
1268                 return -EFAULT;
1269
1270 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1271         /* Don't want to timeout on simulator */
1272         return wait_event_interruptible(windows[0]->dc->wq,
1273                 tegra_dc_windows_are_clean(windows, n));
1274 #else
1275         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1276                                          tegra_dc_windows_are_clean(windows, n),
1277                                          HZ);
1278 #endif
1279 }
1280 EXPORT_SYMBOL(tegra_dc_sync_windows);
1281
1282 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1283 {
1284 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1285         return clk_get_rate(dc->clk);
1286 #else
1287         return 27000000;
1288 #endif
1289 }
1290
1291 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1292 {
1293         unsigned long rate;
1294         unsigned long div;
1295
1296         rate = tegra_dc_clk_get_rate(dc);
1297
1298         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1299
1300         if (div < 2)
1301                 return 0;
1302
1303         return rate * 2 / div;
1304 }
1305
1306 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1307 {
1308         int pclk;
1309
1310         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1311                 struct clk *parent_clk =
1312                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1313
1314                 if (clk_get_parent(clk) != parent_clk)
1315                         clk_set_parent(clk, parent_clk);
1316         }
1317
1318         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1319                 unsigned long rate;
1320                 struct clk *parent_clk =
1321                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1322                 struct clk *base_clk = clk_get_parent(parent_clk);
1323
1324                 /* needs to match tegra_dc_hdmi_supported_modes[]
1325                 and tegra_pll_d_freq_table[] */
1326                 if (dc->mode.pclk > 70000000)
1327                         rate = 594000000;
1328                 else if (dc->mode.pclk > 25200000)
1329                         rate = 216000000;
1330                 else
1331                         rate = 504000000;
1332
1333                 if (rate != clk_get_rate(base_clk))
1334                         clk_set_rate(base_clk, rate);
1335
1336                 if (clk_get_parent(clk) != parent_clk)
1337                         clk_set_parent(clk, parent_clk);
1338         }
1339
1340         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1341                 unsigned long rate;
1342                 struct clk *parent_clk;
1343                 struct clk *base_clk;
1344
1345                 if (clk == dc->clk) {
1346                         parent_clk = clk_get_sys(NULL,
1347                                         dc->out->parent_clk ? : "pll_d_out0");
1348                         base_clk = clk_get_parent(parent_clk);
1349                         tegra_clk_cfg_ex(base_clk,
1350                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1351                 } else {
1352                         if (dc->pdata->default_out->dsi->dsi_instance) {
1353                                 parent_clk = clk_get_sys(NULL,
1354                                         dc->out->parent_clk ? : "pll_d2_out0");
1355                                 base_clk = clk_get_parent(parent_clk);
1356                                 tegra_clk_cfg_ex(base_clk,
1357                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1358                         } else {
1359                                 parent_clk = clk_get_sys(NULL,
1360                                         dc->out->parent_clk ? : "pll_d_out0");
1361                                 base_clk = clk_get_parent(parent_clk);
1362                                 tegra_clk_cfg_ex(base_clk,
1363                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1364                         }
1365                 }
1366
1367                 rate = dc->mode.pclk;
1368                 if (rate != clk_get_rate(base_clk))
1369                         clk_set_rate(base_clk, rate);
1370
1371                 if (clk_get_parent(clk) != parent_clk)
1372                         clk_set_parent(clk, parent_clk);
1373         }
1374
1375         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1376         tegra_dvfs_set_rate(clk, pclk);
1377 }
1378
1379 /* return non-zero if constraint is violated */
1380 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1381 {
1382         long a, b;
1383
1384         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1385         a = 0;
1386
1387         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1388         b = mode->h_front_porch - 1;
1389
1390         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1391         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1392                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1393         /* check Constraint 1 and 6 */
1394         if (a > b)
1395                 return 1;
1396
1397         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1398         if (mode->h_sync_width < 1)
1399                 return 4;
1400
1401         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1402         if (mode->h_active < 16)
1403                 return 7;
1404
1405         if (href) {
1406                 if (b > a && a % 2)
1407                         *href = a + 1; /* use smallest even value */
1408                 else
1409                         *href = a; /* even or only possible value */
1410         }
1411
1412         return 0;
1413 }
1414
1415 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1416 {
1417         long a;
1418         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1419
1420         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1421         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1422                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1423
1424         /* Constraint 6 */
1425         if (mode->v_front_porch < a + 1)
1426                 a = mode->v_front_porch - 1;
1427
1428         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1429         if (mode->v_sync_width < 1)
1430                 return 4;
1431
1432         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1433         if (mode->v_active < 16)
1434                 return 7;
1435
1436         if (vref)
1437                 *vref = a;
1438         return 0;
1439 }
1440
1441 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1442 {
1443         int ret;
1444         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1445         if (ret)
1446                 return ret;
1447         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1448         if (ret)
1449                 return ret;
1450
1451         return 0;
1452 }
1453
1454 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1455 {
1456         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1457         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1458                 return false;
1459
1460         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1461         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1462                 return false;
1463
1464         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1465          * (vertical blank). */
1466         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1467                 return false;
1468
1469         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1470         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1471                 return false;
1472
1473         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1474         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1475                 return false;
1476
1477         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1478          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1479         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1480                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1481                 return false;
1482
1483         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1484         if (mode->h_active < 16 || mode->v_active < 16)
1485                 return false;
1486
1487         return true;
1488 }
1489
1490 #ifdef DEBUG
1491 /* return in 1000ths of a Hertz */
1492 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1493 {
1494         long h_total, v_total, refresh;
1495         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1496                 m->h_sync_width;
1497         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1498                 m->v_sync_width;
1499         refresh = dc->pixel_clk / h_total;
1500         refresh *= 1000;
1501         refresh /= v_total;
1502         return refresh;
1503 }
1504
1505 static void print_mode(struct tegra_dc *dc,
1506                         const struct tegra_dc_mode *mode, const char *note)
1507 {
1508         if (mode) {
1509                 int refresh = calc_refresh(dc, mode);
1510                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1511                         note ? note : "",
1512                         mode->h_active, mode->v_active,
1513                         refresh / 1000, refresh % 1000,
1514                         mode->pclk);
1515         }
1516 }
1517 #else /* !DEBUG */
1518 static inline void print_mode(struct tegra_dc *dc,
1519                         const struct tegra_dc_mode *mode, const char *note) { }
1520 #endif /* DEBUG */
1521
1522 static inline void enable_dc_irq(unsigned int irq)
1523 {
1524 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1525         enable_irq(irq);
1526 #else
1527         /* Always disable DC interrupts on FPGA. */
1528         disable_irq(irq);
1529 #endif
1530 }
1531
1532 static inline void disable_dc_irq(unsigned int irq)
1533 {
1534         disable_irq(irq);
1535 }
1536
1537 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1538 {
1539         unsigned long val;
1540         unsigned long rate;
1541         unsigned long div;
1542         unsigned long pclk;
1543
1544         print_mode(dc, mode, __func__);
1545
1546         /* use default EMC rate when switching modes */
1547         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1548         tegra_dc_program_bandwidth(dc);
1549
1550         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1551         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1552                         DC_DISP_REF_TO_SYNC);
1553         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1554                         DC_DISP_SYNC_WIDTH);
1555         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1556                         DC_DISP_BACK_PORCH);
1557         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1558                         DC_DISP_DISP_ACTIVE);
1559         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1560                         DC_DISP_FRONT_PORCH);
1561
1562         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1563                         DC_DISP_DATA_ENABLE_OPTIONS);
1564
1565         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1566         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1567                 val |= PIN1_LVS_OUTPUT;
1568         else
1569                 val &= ~PIN1_LVS_OUTPUT;
1570
1571         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1572                 val |= PIN1_LHS_OUTPUT;
1573         else
1574                 val &= ~PIN1_LHS_OUTPUT;
1575         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1576
1577         /* TODO: MIPI/CRT/HDMI clock cals */
1578
1579         val = DISP_DATA_FORMAT_DF1P1C;
1580
1581         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1582                 val |= DISP_DATA_ALIGNMENT_MSB;
1583         else
1584                 val |= DISP_DATA_ALIGNMENT_LSB;
1585
1586         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1587                 val |= DISP_DATA_ORDER_RED_BLUE;
1588         else
1589                 val |= DISP_DATA_ORDER_BLUE_RED;
1590
1591         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1592
1593         rate = tegra_dc_clk_get_rate(dc);
1594
1595         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1596         if (pclk < (mode->pclk / 100 * 99) ||
1597             pclk > (mode->pclk / 100 * 109)) {
1598                 dev_err(&dc->ndev->dev,
1599                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1600                         rate, mode->pclk,
1601                         pclk, (mode->pclk / 100 * 99),
1602                         (mode->pclk / 100 * 109));
1603                 return -EINVAL;
1604         }
1605
1606         div = (rate * 2 / pclk) - 2;
1607
1608         tegra_dc_writel(dc, 0x00010001,
1609                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1610         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1611                         DC_DISP_DISP_CLOCK_CONTROL);
1612
1613         dc->pixel_clk = dc->mode.pclk;
1614
1615         return 0;
1616 }
1617
1618
1619 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1620 {
1621         memcpy(&dc->mode, mode, sizeof(dc->mode));
1622
1623         print_mode(dc, mode, __func__);
1624
1625         return 0;
1626 }
1627 EXPORT_SYMBOL(tegra_dc_set_mode);
1628
1629 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1630                 const struct fb_videomode *fbmode, bool stereo_mode)
1631 {
1632         struct tegra_dc_mode mode;
1633
1634         if (!fbmode->pixclock)
1635                 return -EINVAL;
1636
1637         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1638         mode.h_sync_width = fbmode->hsync_len;
1639         mode.v_sync_width = fbmode->vsync_len;
1640         mode.h_back_porch = fbmode->left_margin;
1641         mode.v_back_porch = fbmode->upper_margin;
1642         mode.h_active = fbmode->xres;
1643         mode.v_active = fbmode->yres;
1644         mode.h_front_porch = fbmode->right_margin;
1645         mode.v_front_porch = fbmode->lower_margin;
1646         mode.stereo_mode = stereo_mode;
1647         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1648                 /* HDMI controller requires h_ref=1, v_ref=1 */
1649                 mode.h_ref_to_sync = 1;
1650                 mode.v_ref_to_sync = 1;
1651         } else {
1652                 calc_ref_to_sync(&mode);
1653         }
1654         if (!check_ref_to_sync(&mode)) {
1655                 dev_err(&dc->ndev->dev,
1656                                 "Display timing doesn't meet restrictions.\n");
1657                 return -EINVAL;
1658         }
1659         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1660                 mode.h_active, mode.v_active, mode.pclk,
1661                 mode.h_ref_to_sync, mode.v_ref_to_sync
1662         );
1663
1664         if (mode.stereo_mode) {
1665                 mode.pclk *= 2;
1666                 /* total v_active = yres*2 + activespace */
1667                 mode.v_active = fbmode->yres*2 +
1668                                 fbmode->vsync_len +
1669                                 fbmode->upper_margin +
1670                                 fbmode->lower_margin;
1671         }
1672
1673         mode.flags = 0;
1674
1675         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1676                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1677
1678         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1679                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1680
1681         return tegra_dc_set_mode(dc, &mode);
1682 }
1683 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1684
1685 void
1686 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1687 {
1688         unsigned int ctrl;
1689         unsigned long out_sel;
1690         unsigned long cmd_state;
1691
1692         mutex_lock(&dc->lock);
1693         if (!dc->enabled) {
1694                 mutex_unlock(&dc->lock);
1695                 return;
1696         }
1697
1698         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1699                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1700                 cfg->clk_select);
1701
1702         /* The new value should be effected immediately */
1703         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1704         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1705
1706         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1707                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1708         else
1709                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1710
1711         switch (cfg->which_pwm) {
1712         case TEGRA_PWM_PM0:
1713                 /* Select the LM0 on PM0 */
1714                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1715                 out_sel &= ~(7 << 0);
1716                 out_sel |= (3 << 0);
1717                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1718                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1719                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1720                 break;
1721         case TEGRA_PWM_PM1:
1722                 /* Select the LM1 on PM1 */
1723                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1724                 out_sel &= ~(7 << 4);
1725                 out_sel |= (3 << 4);
1726                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1727                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1728                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1729                 break;
1730         default:
1731                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1732                 break;
1733         }
1734         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1735         mutex_unlock(&dc->lock);
1736 }
1737 EXPORT_SYMBOL(tegra_dc_config_pwm);
1738
1739 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1740                                 const struct tegra_dc_out_pin *pins,
1741                                 const unsigned int n_pins)
1742 {
1743         unsigned int i;
1744
1745         int name;
1746         int pol;
1747
1748         u32 pol1, pol3;
1749
1750         u32 set1, unset1;
1751         u32 set3, unset3;
1752
1753         set1 = set3 = unset1 = unset3 = 0;
1754
1755         for (i = 0; i < n_pins; i++) {
1756                 name = (pins + i)->name;
1757                 pol  = (pins + i)->pol;
1758
1759                 /* set polarity by name */
1760                 switch (name) {
1761                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1762                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1763                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1764                         else
1765                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1766                         break;
1767                 case TEGRA_DC_OUT_PIN_H_SYNC:
1768                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1769                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1770                         else
1771                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1772                         break;
1773                 case TEGRA_DC_OUT_PIN_V_SYNC:
1774                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1775                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1776                         else
1777                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1778                         break;
1779                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1780                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1781                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1782                         else
1783                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1784                         break;
1785                 default:
1786                         printk("Invalid argument in function %s\n",
1787                                __FUNCTION__);
1788                         break;
1789                 }
1790         }
1791
1792         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1793         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1794
1795         pol1 |= set1;
1796         pol1 &= ~unset1;
1797
1798         pol3 |= set3;
1799         pol3 &= ~unset3;
1800
1801         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1802         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1803 }
1804
1805 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1806 {
1807         dc->out = out;
1808
1809         if (out->n_modes > 0)
1810                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1811
1812         switch (out->type) {
1813         case TEGRA_DC_OUT_RGB:
1814                 dc->out_ops = &tegra_dc_rgb_ops;
1815                 break;
1816
1817         case TEGRA_DC_OUT_HDMI:
1818                 dc->out_ops = &tegra_dc_hdmi_ops;
1819                 break;
1820
1821         case TEGRA_DC_OUT_DSI:
1822                 dc->out_ops = &tegra_dc_dsi_ops;
1823                 break;
1824
1825         default:
1826                 dc->out_ops = NULL;
1827                 break;
1828         }
1829
1830         if (dc->out_ops && dc->out_ops->init)
1831                 dc->out_ops->init(dc);
1832
1833 }
1834
1835 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1836 {
1837         if (dc->out)
1838                 return dc->out->height;
1839         else
1840                 return 0;
1841 }
1842 EXPORT_SYMBOL(tegra_dc_get_out_height);
1843
1844 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1845 {
1846         if (dc->out)
1847                 return dc->out->width;
1848         else
1849                 return 0;
1850 }
1851 EXPORT_SYMBOL(tegra_dc_get_out_width);
1852
1853 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1854 {
1855         if (dc->out && dc->out->max_pixclock)
1856                 return dc->out->max_pixclock;
1857         else
1858                 return 0;
1859 }
1860 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1861
1862 void tegra_dc_enable_crc(struct tegra_dc *dc)
1863 {
1864         u32 val;
1865         tegra_dc_io_start(dc);
1866
1867         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1868                 CRC_ENABLE_ENABLE;
1869         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1870         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1871         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1872 }
1873
1874 void tegra_dc_disable_crc(struct tegra_dc *dc)
1875 {
1876         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1877         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1878         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1879
1880         tegra_dc_io_end(dc);
1881 }
1882
1883 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1884 {
1885         int crc = 0;
1886
1887         if(!dc) {
1888                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1889                 goto crc_error;
1890         }
1891
1892         /* TODO: Replace mdelay with code to sync VBlANK, since
1893          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1894         mdelay(TEGRA_CRC_LATCHED_DELAY);
1895
1896         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1897 crc_error:
1898         return crc;
1899 }
1900
1901 static void tegra_dc_vblank(struct work_struct *work)
1902 {
1903         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1904         bool nvsd_updated = false;
1905
1906         mutex_lock(&dc->lock);
1907
1908         /* update EMC clock if calculated bandwidth has changed */
1909         tegra_dc_program_bandwidth(dc);
1910
1911         /* Update the SD brightness */
1912         if (dc->enabled && dc->out->sd_settings)
1913                 nvsd_updated = nvsd_update_brightness(dc);
1914
1915         mutex_unlock(&dc->lock);
1916
1917         /* Do the actual brightness update outside of the mutex */
1918         if (nvsd_updated && dc->out->sd_settings &&
1919             dc->out->sd_settings->bl_device) {
1920
1921                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1922                 struct backlight_device *bl = platform_get_drvdata(pdev);
1923                 if (bl)
1924                         backlight_update_status(bl);
1925         }
1926 }
1927
1928 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1929 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1930 {
1931         u32 val, i;
1932
1933         /* Check for any underflow reset conditions */
1934         for (i = 0; i < DC_N_WINDOWS; i++) {
1935                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1936                         dc->windows[i].underflows++;
1937
1938 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1939                         if (dc->windows[i].underflows > 4)
1940                                 schedule_work(&dc->reset_work);
1941 #endif
1942                 } else {
1943                         dc->windows[i].underflows = 0;
1944                 }
1945         }
1946
1947         if (!dc->underflow_mask) {
1948                 /* If we have no underflow to check, go ahead
1949                    and disable the interrupt */
1950                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1951                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1952                         val &= ~FRAME_END_INT;
1953                 else
1954                         val &= ~V_BLANK_INT;
1955                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1956         }
1957
1958         /* Clear the underflow mask now that we've checked it. */
1959         dc->underflow_mask = 0;
1960 }
1961
1962 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
1963 {
1964         u32 val, i;
1965         u32 completed = 0;
1966         u32 dirty = 0;
1967
1968         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1969         for (i = 0; i < DC_N_WINDOWS; i++) {
1970 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1971                 /* FIXME: this is not needed when the simulator
1972                    clears WIN_x_UPDATE bits as in HW */
1973                 dc->windows[i].dirty = 0;
1974                 completed = 1;
1975 #else
1976                 if (!(val & (WIN_A_UPDATE << i))) {
1977                         dc->windows[i].dirty = 0;
1978                         completed = 1;
1979                 } else {
1980                         dirty = 1;
1981                 }
1982 #endif
1983         }
1984
1985         if (!dirty) {
1986                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1987                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1988                         val &= ~V_BLANK_INT;
1989                 else
1990                         val &= ~FRAME_END_INT;
1991                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1992         }
1993
1994         if (completed) {
1995                 if (!dirty) {
1996                         /* With the last completed window, go ahead
1997                            and enable the vblank interrupt for nvsd. */
1998                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1999                         val |= V_BLANK_INT;
2000                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2001
2002                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2003                         val |= V_BLANK_INT;
2004                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2005                 }
2006
2007                 wake_up(&dc->wq);
2008         }
2009 }
2010
2011 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2012 {
2013         if (status & V_BLANK_INT) {
2014                 /* Sync up windows. */
2015                 tegra_dc_trigger_windows(dc);
2016
2017                 /* Schedule any additional bottom-half vblank actvities. */
2018                 schedule_work(&dc->vblank_work);
2019
2020                 /* Mark the vblank as complete. */
2021                 complete(&dc->vblank_complete);
2022
2023         }
2024
2025         /* Check underflow at frame end */
2026         if (status & FRAME_END_INT)
2027                 tegra_dc_underflow_handler(dc);
2028 }
2029
2030 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2031 {
2032         if (status & V_BLANK_INT) {
2033                 /* Check underflow */
2034                 tegra_dc_underflow_handler(dc);
2035
2036                 /* Schedule any additional bottom-half vblank actvities. */
2037                 schedule_work(&dc->vblank_work);
2038
2039                 /* Mark the vblank as complete. */
2040                 complete(&dc->vblank_complete);
2041         }
2042
2043         if (status & FRAME_END_INT)
2044                 tegra_dc_trigger_windows(dc);
2045 }
2046 #endif
2047
2048 /* return an arbitrarily large number if count overflow occurs.
2049  * make it a nice base-10 number to show up in stats output */
2050 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2051 {
2052         unsigned count = tegra_dc_readl(dc, reg);
2053         tegra_dc_writel(dc, 0, reg);
2054         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2055 }
2056
2057 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2058 {
2059 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2060         struct tegra_dc *dc = ptr;
2061         unsigned long status;
2062         unsigned long val;
2063         unsigned long underflow_mask;
2064
2065         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2066         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2067
2068         /*
2069          * Overlays can get thier internal state corrupted during and underflow
2070          * condition.  The only way to fix this state is to reset the DC.
2071          * if we get 4 consecutive frames with underflows, assume we're
2072          * hosed and reset.
2073          */
2074         underflow_mask = status & ALL_UF_INT;
2075
2076         if (underflow_mask) {
2077                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2078                 val |= V_BLANK_INT;
2079                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2080                 dc->underflow_mask |= underflow_mask;
2081                 dc->stats.underflows++;
2082                 if (status & WIN_A_UF_INT)
2083                         dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2084                                 DC_WINBUF_AD_UFLOW_STATUS);
2085                 if (status & WIN_B_UF_INT)
2086                         dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2087                                 DC_WINBUF_BD_UFLOW_STATUS);
2088                 if (status & WIN_C_UF_INT)
2089                         dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2090                                 DC_WINBUF_CD_UFLOW_STATUS);
2091         }
2092
2093         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2094                 tegra_dc_one_shot_irq(dc, status);
2095         else
2096                 tegra_dc_continuous_irq(dc, status);
2097
2098         return IRQ_HANDLED;
2099 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2100         return IRQ_NONE;
2101 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2102 }
2103
2104 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2105 {
2106         u32 color_control;
2107
2108         switch (dc->out->depth) {
2109         case 3:
2110                 color_control = BASE_COLOR_SIZE111;
2111                 break;
2112
2113         case 6:
2114                 color_control = BASE_COLOR_SIZE222;
2115                 break;
2116
2117         case 8:
2118                 color_control = BASE_COLOR_SIZE332;
2119                 break;
2120
2121         case 9:
2122                 color_control = BASE_COLOR_SIZE333;
2123                 break;
2124
2125         case 12:
2126                 color_control = BASE_COLOR_SIZE444;
2127                 break;
2128
2129         case 15:
2130                 color_control = BASE_COLOR_SIZE555;
2131                 break;
2132
2133         case 16:
2134                 color_control = BASE_COLOR_SIZE565;
2135                 break;
2136
2137         case 18:
2138                 color_control = BASE_COLOR_SIZE666;
2139                 break;
2140
2141         default:
2142                 color_control = BASE_COLOR_SIZE888;
2143                 break;
2144         }
2145
2146         switch (dc->out->dither) {
2147         case TEGRA_DC_DISABLE_DITHER:
2148                 color_control |= DITHER_CONTROL_DISABLE;
2149                 break;
2150         case TEGRA_DC_ORDERED_DITHER:
2151                 color_control |= DITHER_CONTROL_ORDERED;
2152                 break;
2153         case TEGRA_DC_ERRDIFF_DITHER:
2154                 /* The line buffer for error-diffusion dither is limited
2155                  * to 1280 pixels per line. This limits the maximum
2156                  * horizontal active area size to 1280 pixels when error
2157                  * diffusion is enabled.
2158                  */
2159                 BUG_ON(dc->mode.h_active > 1280);
2160                 color_control |= DITHER_CONTROL_ERRDIFF;
2161                 break;
2162         }
2163
2164         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2165 }
2166
2167 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2168 {
2169         u32 syncpt_id;
2170
2171         switch (dc->ndev->id) {
2172         case 0:
2173                 switch (idx) {
2174                 case 0:
2175                         syncpt_id = NVSYNCPT_DISP0_A;
2176                         break;
2177                 case 1:
2178                         syncpt_id = NVSYNCPT_DISP0_B;
2179                         break;
2180                 case 2:
2181                         syncpt_id = NVSYNCPT_DISP0_C;
2182                         break;
2183                 default:
2184                         BUG();
2185                         break;
2186                 }
2187                 break;
2188         case 1:
2189                 switch (idx) {
2190                 case 0:
2191                         syncpt_id = NVSYNCPT_DISP1_A;
2192                         break;
2193                 case 1:
2194                         syncpt_id = NVSYNCPT_DISP1_B;
2195                         break;
2196                 case 2:
2197                         syncpt_id = NVSYNCPT_DISP1_C;
2198                         break;
2199                 default:
2200                         BUG();
2201                         break;
2202                 }
2203                 break;
2204         default:
2205                 BUG();
2206                 break;
2207         }
2208
2209         return syncpt_id;
2210 }
2211
2212 static void tegra_dc_init(struct tegra_dc *dc)
2213 {
2214         int i;
2215
2216         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2217         if (dc->ndev->id == 0) {
2218                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2219                                       TEGRA_MC_PRIO_MED);
2220                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2221                                       TEGRA_MC_PRIO_MED);
2222                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2223                                       TEGRA_MC_PRIO_MED);
2224                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2225                                       TEGRA_MC_PRIO_MED);
2226                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2227                                       TEGRA_MC_PRIO_HIGH);
2228         } else if (dc->ndev->id == 1) {
2229                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2230                                       TEGRA_MC_PRIO_MED);
2231                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2232                                       TEGRA_MC_PRIO_MED);
2233                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2234                                       TEGRA_MC_PRIO_MED);
2235                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2236                                       TEGRA_MC_PRIO_MED);
2237                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2238                                       TEGRA_MC_PRIO_HIGH);
2239         }
2240         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2241                         DC_CMD_CONT_SYNCPT_VSYNC);
2242         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2243         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2244         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2245         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2246
2247         tegra_dc_writel(dc, (FRAME_END_INT |
2248                              V_BLANK_INT |
2249                              ALL_UF_INT), DC_CMD_INT_MASK);
2250         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_ENABLE);
2251
2252         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2253
2254         tegra_dc_set_color_control(dc);
2255         for (i = 0; i < DC_N_WINDOWS; i++) {
2256                 struct tegra_dc_win *win = &dc->windows[i];
2257                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2258                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2259                 tegra_dc_set_csc(dc, &win->csc);
2260                 tegra_dc_set_lut(dc, win);
2261                 tegra_dc_set_scaling_filter(dc);
2262         }
2263
2264
2265         for (i = 0; i < dc->n_windows; i++) {
2266                 u32 syncpt = get_syncpt(dc, i);
2267
2268                 dc->syncpt[i].id = syncpt;
2269
2270                 dc->syncpt[i].min = dc->syncpt[i].max =
2271                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2272         }
2273
2274         print_mode(dc, &dc->mode, __func__);
2275
2276         if (dc->mode.pclk)
2277                 tegra_dc_program_mode(dc, &dc->mode);
2278
2279         /* Initialize SD AFTER the modeset.
2280            nvsd_init handles the sd_settings = NULL case. */
2281         nvsd_init(dc, dc->out->sd_settings);
2282 }
2283
2284 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2285 {
2286         if (dc->out->enable)
2287                 dc->out->enable();
2288
2289         tegra_dc_setup_clk(dc, dc->clk);
2290         tegra_periph_reset_assert(dc->clk);
2291         clk_enable(dc->clk);
2292         clk_enable(dc->emc_clk);
2293
2294         /* do not accept interrupts during initialization */
2295         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2296         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2297
2298         enable_dc_irq(dc->irq);
2299
2300         tegra_dc_init(dc);
2301
2302         if (dc->out_ops && dc->out_ops->enable)
2303                 dc->out_ops->enable(dc);
2304
2305         if (dc->out->out_pins)
2306                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2307                                             dc->out->n_out_pins);
2308
2309         if (dc->out->postpoweron)
2310                 dc->out->postpoweron();
2311
2312         /* force a full blending update */
2313         dc->blend.z[0] = -1;
2314
2315         tegra_dc_ext_enable(dc->ext);
2316
2317         return true;
2318 }
2319
2320 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2321 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2322 {
2323         if (dc->out->enable)
2324                 dc->out->enable();
2325
2326         tegra_dc_setup_clk(dc, dc->clk);
2327         clk_enable(dc->clk);
2328         clk_enable(dc->emc_clk);
2329
2330         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2331                 mutex_lock(&tegra_dcs[1]->lock);
2332                 disable_irq(tegra_dcs[1]->irq);
2333         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2334                 mutex_lock(&tegra_dcs[0]->lock);
2335                 disable_irq(tegra_dcs[0]->irq);
2336         }
2337
2338         msleep(5);
2339         tegra_periph_reset_assert(dc->clk);
2340         msleep(2);
2341 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2342         tegra_periph_reset_deassert(dc->clk);
2343         msleep(1);
2344 #endif
2345
2346         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2347                 enable_dc_irq(tegra_dcs[1]->irq);
2348                 mutex_unlock(&tegra_dcs[1]->lock);
2349         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2350                 enable_dc_irq(tegra_dcs[0]->irq);
2351                 mutex_unlock(&tegra_dcs[0]->lock);
2352         }
2353
2354         enable_dc_irq(dc->irq);
2355
2356         tegra_dc_init(dc);
2357
2358         if (dc->out_ops && dc->out_ops->enable)
2359                 dc->out_ops->enable(dc);
2360
2361         if (dc->out->out_pins)
2362                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2363                                             dc->out->n_out_pins);
2364
2365         if (dc->out->postpoweron)
2366                 dc->out->postpoweron();
2367
2368         /* force a full blending update */
2369         dc->blend.z[0] = -1;
2370
2371         return true;
2372 }
2373 #endif
2374
2375 static bool _tegra_dc_enable(struct tegra_dc *dc)
2376 {
2377         if (dc->mode.pclk == 0)
2378                 return false;
2379
2380         if (!dc->out)
2381                 return false;
2382
2383         tegra_dc_io_start(dc);
2384
2385         return _tegra_dc_controller_enable(dc);
2386 }
2387
2388 void tegra_dc_enable(struct tegra_dc *dc)
2389 {
2390         mutex_lock(&dc->lock);
2391
2392         if (!dc->enabled)
2393                 dc->enabled = _tegra_dc_enable(dc);
2394
2395         mutex_unlock(&dc->lock);
2396 }
2397
2398 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2399 {
2400         unsigned i;
2401
2402         disable_irq(dc->irq);
2403
2404         if (dc->out_ops && dc->out_ops->disable)
2405                 dc->out_ops->disable(dc);
2406
2407         clk_disable(dc->emc_clk);
2408         clk_disable(dc->clk);
2409         tegra_dvfs_set_rate(dc->clk, 0);
2410
2411         if (dc->out && dc->out->disable)
2412                 dc->out->disable();
2413
2414         for (i = 0; i < dc->n_windows; i++) {
2415                 struct tegra_dc_win *w = &dc->windows[i];
2416
2417                 /* reset window bandwidth */
2418                 w->bandwidth = 0;
2419                 w->new_bandwidth = 0;
2420
2421                 /* disable windows */
2422                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2423
2424                 /* flush any pending syncpt waits */
2425                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2426                         dc->syncpt[i].min++;
2427                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2428                                 dc->syncpt[i].id);
2429                 }
2430         }
2431 }
2432
2433 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2434 {
2435 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2436         u32 val;
2437         if (dc->enabled)  {
2438                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2439                 if (enable)
2440                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2441                 else
2442                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2443                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2444         }
2445 #endif
2446 }
2447
2448 bool tegra_dc_stats_get(struct tegra_dc *dc)
2449 {
2450 #if 0 /* right now it is always enabled */
2451         u32 val;
2452         bool res;
2453
2454         if (dc->enabled)  {
2455                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2456                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2457         } else {
2458                 res = false;
2459         }
2460
2461         return res;
2462 #endif
2463         return true;
2464 }
2465
2466 /* make the screen blank by disabling all windows */
2467 void tegra_dc_blank(struct tegra_dc *dc)
2468 {
2469         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2470         unsigned i;
2471
2472         for (i = 0; i < DC_N_WINDOWS; i++) {
2473                 dcwins[i] = tegra_dc_get_window(dc, i);
2474                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2475         }
2476
2477         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2478         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2479 }
2480
2481 static void _tegra_dc_disable(struct tegra_dc *dc)
2482 {
2483         _tegra_dc_controller_disable(dc);
2484         tegra_dc_io_end(dc);
2485 }
2486
2487 void tegra_dc_disable(struct tegra_dc *dc)
2488 {
2489         if (dc->overlay)
2490                 tegra_overlay_disable(dc->overlay);
2491
2492         tegra_dc_ext_disable(dc->ext);
2493
2494         mutex_lock(&dc->lock);
2495
2496         if (dc->enabled) {
2497                 dc->enabled = false;
2498
2499                 if (!dc->suspended)
2500                         _tegra_dc_disable(dc);
2501         }
2502
2503         mutex_unlock(&dc->lock);
2504 }
2505
2506 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2507 static void tegra_dc_reset_worker(struct work_struct *work)
2508 {
2509         struct tegra_dc *dc =
2510                 container_of(work, struct tegra_dc, reset_work);
2511
2512         unsigned long val = 0;
2513
2514         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2515
2516         tegra_dc_ext_disable(dc->ext);
2517
2518         mutex_lock(&shared_lock);
2519         mutex_lock(&dc->lock);
2520
2521         if (dc->enabled == false)
2522                 goto unlock;
2523
2524         dc->enabled = false;
2525
2526         /*
2527          * off host read bus
2528          */
2529         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2530         val &= ~(0x00000100);
2531         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2532
2533         /*
2534          * set DC to STOP mode
2535          */
2536         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2537
2538         msleep(10);
2539
2540         _tegra_dc_controller_disable(dc);
2541
2542         /* _tegra_dc_controller_reset_enable deasserts reset */
2543         _tegra_dc_controller_reset_enable(dc);
2544
2545         dc->enabled = true;
2546 unlock:
2547         mutex_unlock(&dc->lock);
2548         mutex_unlock(&shared_lock);
2549 }
2550 #endif
2551
2552
2553 static int tegra_dc_probe(struct nvhost_device *ndev)
2554 {
2555         struct tegra_dc *dc;
2556         struct clk *clk;
2557         struct clk *emc_clk;
2558         struct resource *res;
2559         struct resource *base_res;
2560         struct resource *fb_mem = NULL;
2561         int ret = 0;
2562         void __iomem *base;
2563         int irq;
2564         int i;
2565
2566         if (!ndev->dev.platform_data) {
2567                 dev_err(&ndev->dev, "no platform data\n");
2568                 return -ENOENT;
2569         }
2570
2571         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2572         if (!dc) {
2573                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2574                 return -ENOMEM;
2575         }
2576
2577         irq = nvhost_get_irq_byname(ndev, "irq");
2578         if (irq <= 0) {
2579                 dev_err(&ndev->dev, "no irq\n");
2580                 ret = -ENOENT;
2581                 goto err_free;
2582         }
2583
2584         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2585         if (!res) {
2586                 dev_err(&ndev->dev, "no mem resource\n");
2587                 ret = -ENOENT;
2588                 goto err_free;
2589         }
2590
2591         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2592         if (!base_res) {
2593                 dev_err(&ndev->dev, "request_mem_region failed\n");
2594                 ret = -EBUSY;
2595                 goto err_free;
2596         }
2597
2598         base = ioremap(res->start, resource_size(res));
2599         if (!base) {
2600                 dev_err(&ndev->dev, "registers can't be mapped\n");
2601                 ret = -EBUSY;
2602                 goto err_release_resource_reg;
2603         }
2604
2605         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2606
2607         clk = clk_get(&ndev->dev, NULL);
2608         if (IS_ERR_OR_NULL(clk)) {
2609                 dev_err(&ndev->dev, "can't get clock\n");
2610                 ret = -ENOENT;
2611                 goto err_iounmap_reg;
2612         }
2613
2614         emc_clk = clk_get(&ndev->dev, "emc");
2615         if (IS_ERR_OR_NULL(emc_clk)) {
2616                 dev_err(&ndev->dev, "can't get emc clock\n");
2617                 ret = -ENOENT;
2618                 goto err_put_clk;
2619         }
2620
2621         dc->clk = clk;
2622         dc->emc_clk = emc_clk;
2623
2624         dc->base_res = base_res;
2625         dc->base = base;
2626         dc->irq = irq;
2627         dc->ndev = ndev;
2628         dc->pdata = ndev->dev.platform_data;
2629
2630         /*
2631          * The emc is a shared clock, it will be set based on
2632          * the requirements for each user on the bus.
2633          */
2634         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2635         clk_set_rate(emc_clk, dc->emc_clk_rate);
2636
2637         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2638                 dc->enabled = true;
2639
2640         mutex_init(&dc->lock);
2641         init_completion(&dc->vblank_complete);
2642         init_waitqueue_head(&dc->wq);
2643 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2644         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2645 #endif
2646         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2647
2648         dc->n_windows = DC_N_WINDOWS;
2649         for (i = 0; i < dc->n_windows; i++) {
2650                 struct tegra_dc_win *win = &dc->windows[i];
2651                 win->idx = i;
2652                 win->dc = dc;
2653                 tegra_dc_init_csc_defaults(&win->csc);
2654                 tegra_dc_init_lut_defaults(&win->lut);
2655         }
2656
2657         ret = tegra_dc_set(dc, ndev->id);
2658         if (ret < 0) {
2659                 dev_err(&ndev->dev, "can't add dc\n");
2660                 goto err_free_irq;
2661         }
2662
2663         nvhost_set_drvdata(ndev, dc);
2664
2665         if (dc->pdata->default_out)
2666                 tegra_dc_set_out(dc, dc->pdata->default_out);
2667         else
2668                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2669
2670         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2671                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2672
2673         dc->ext = tegra_dc_ext_register(ndev, dc);
2674         if (IS_ERR_OR_NULL(dc->ext)) {
2675                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2676                 dc->ext = NULL;
2677         }
2678
2679         /* interrupt handler must be registered before tegra_fb_register() */
2680         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2681                         dev_name(&ndev->dev), dc)) {
2682                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2683                 ret = -EBUSY;
2684                 goto err_put_emc_clk;
2685         }
2686
2687         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2688         disable_dc_irq(dc->irq);
2689
2690         mutex_lock(&dc->lock);
2691         if (dc->enabled)
2692                 _tegra_dc_enable(dc);
2693         mutex_unlock(&dc->lock);
2694
2695         tegra_dc_create_debugfs(dc);
2696
2697         dev_info(&ndev->dev, "probed\n");
2698
2699         if (dc->pdata->fb) {
2700                 if (dc->pdata->fb->bits_per_pixel == -1) {
2701                         unsigned long fmt;
2702                         tegra_dc_writel(dc,
2703                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2704                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2705
2706                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2707                         dc->pdata->fb->bits_per_pixel =
2708                                 tegra_dc_fmt_bpp(fmt);
2709                 }
2710
2711                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2712                 if (IS_ERR_OR_NULL(dc->fb))
2713                         dc->fb = NULL;
2714         }
2715
2716         if (dc->fb) {
2717                 dc->overlay = tegra_overlay_register(ndev, dc);
2718                 if (IS_ERR_OR_NULL(dc->overlay))
2719                         dc->overlay = NULL;
2720         }
2721
2722         if (dc->out && dc->out->hotplug_init)
2723                 dc->out->hotplug_init();
2724
2725         if (dc->out_ops && dc->out_ops->detect)
2726                 dc->out_ops->detect(dc);
2727         else
2728                 dc->connected = true;
2729
2730         tegra_dc_create_sysfs(&dc->ndev->dev);
2731
2732         return 0;
2733
2734 err_free_irq:
2735         free_irq(irq, dc);
2736 err_put_emc_clk:
2737         clk_put(emc_clk);
2738 err_put_clk:
2739         clk_put(clk);
2740 err_iounmap_reg:
2741         iounmap(base);
2742         if (fb_mem)
2743                 release_resource(fb_mem);
2744 err_release_resource_reg:
2745         release_resource(base_res);
2746 err_free:
2747         kfree(dc);
2748
2749         return ret;
2750 }
2751
2752 static int tegra_dc_remove(struct nvhost_device *ndev)
2753 {
2754         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2755
2756         tegra_dc_remove_sysfs(&dc->ndev->dev);
2757         tegra_dc_remove_debugfs(dc);
2758
2759         if (dc->overlay) {
2760                 tegra_overlay_unregister(dc->overlay);
2761         }
2762
2763         if (dc->fb) {
2764                 tegra_fb_unregister(dc->fb);
2765                 if (dc->fb_mem)
2766                         release_resource(dc->fb_mem);
2767         }
2768
2769         tegra_dc_ext_disable(dc->ext);
2770
2771         if (dc->ext)
2772                 tegra_dc_ext_unregister(dc->ext);
2773
2774         if (dc->enabled)
2775                 _tegra_dc_disable(dc);
2776
2777         free_irq(dc->irq, dc);
2778         clk_put(dc->emc_clk);
2779         clk_put(dc->clk);
2780         iounmap(dc->base);
2781         if (dc->fb_mem)
2782                 release_resource(dc->base_res);
2783         kfree(dc);
2784         tegra_dc_set(NULL, ndev->id);
2785         return 0;
2786 }
2787
2788 #ifdef CONFIG_PM
2789 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2790 {
2791         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2792
2793         dev_info(&ndev->dev, "suspend\n");
2794
2795         if (dc->overlay)
2796                 tegra_overlay_disable(dc->overlay);
2797
2798         tegra_dc_ext_disable(dc->ext);
2799
2800         mutex_lock(&dc->lock);
2801
2802         if (dc->out_ops && dc->out_ops->suspend)
2803                 dc->out_ops->suspend(dc);
2804
2805         if (dc->enabled) {
2806                 _tegra_dc_disable(dc);
2807
2808                 dc->suspended = true;
2809         }
2810
2811         if (dc->out && dc->out->postsuspend) {
2812                 dc->out->postsuspend();
2813                 msleep(100); /* avoid resume event due to voltage falling */
2814         }
2815
2816         mutex_unlock(&dc->lock);
2817
2818         return 0;
2819 }
2820
2821 static int tegra_dc_resume(struct nvhost_device *ndev)
2822 {
2823         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2824
2825         dev_info(&ndev->dev, "resume\n");
2826
2827         mutex_lock(&dc->lock);
2828         dc->suspended = false;
2829
2830         if (dc->enabled)
2831                 _tegra_dc_enable(dc);
2832
2833         if (dc->out && dc->out->hotplug_init)
2834                 dc->out->hotplug_init();
2835
2836         if (dc->out_ops && dc->out_ops->resume)
2837                 dc->out_ops->resume(dc);
2838         mutex_unlock(&dc->lock);
2839
2840         return 0;
2841 }
2842
2843 #endif /* CONFIG_PM */
2844
2845 extern int suspend_set(const char *val, struct kernel_param *kp)
2846 {
2847         if (!strcmp(val, "dump"))
2848                 dump_regs(tegra_dcs[0]);
2849 #ifdef CONFIG_PM
2850         else if (!strcmp(val, "suspend"))
2851                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2852         else if (!strcmp(val, "resume"))
2853                 tegra_dc_resume(tegra_dcs[0]->ndev);
2854 #endif
2855
2856         return 0;
2857 }
2858
2859 extern int suspend_get(char *buffer, struct kernel_param *kp)
2860 {
2861         return 0;
2862 }
2863
2864 int suspend;
2865
2866 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2867
2868 struct nvhost_driver tegra_dc_driver = {
2869         .driver = {
2870                 .name = "tegradc",
2871                 .owner = THIS_MODULE,
2872         },
2873         .probe = tegra_dc_probe,
2874         .remove = tegra_dc_remove,
2875 #ifdef CONFIG_PM
2876         .suspend = tegra_dc_suspend,
2877         .resume = tegra_dc_resume,
2878 #endif
2879 };
2880
2881 static int __init tegra_dc_module_init(void)
2882 {
2883         int ret = tegra_dc_ext_module_init();
2884         if (ret)
2885                 return ret;
2886         return nvhost_driver_register(&tegra_dc_driver);
2887 }
2888
2889 static void __exit tegra_dc_module_exit(void)
2890 {
2891         nvhost_driver_unregister(&tegra_dc_driver);
2892         tegra_dc_ext_module_exit();
2893 }
2894
2895 module_exit(tegra_dc_module_exit);
2896 module_init(tegra_dc_module_init);