834637db0f3a35afbb10e1b0f108ab475fe6735e
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39 #ifdef CONFIG_SWITCH
40 #include <linux/switch.h>
41 #endif
42
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "host1x/host1x.h"
55 #include "host1x/host1x_syncpt.h"
56 #include "nvsd.h"
57
58 #define TEGRA_CRC_LATCHED_DELAY         34
59
60 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
61 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
62
63 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
64 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
65 #else
66 /* ignore underflows when on simulation and fpga platform */
67 #define ALL_UF_INT (0)
68 #endif
69
70 static int no_vsync;
71 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
72         .refresh = 60,
73         .xres = 640,
74         .yres = 480,
75         .pixclock = KHZ2PICOS(25200),
76         .hsync_len = 96,        /* h_sync_width */
77         .vsync_len = 2,         /* v_sync_width */
78         .left_margin = 48,      /* h_back_porch */
79         .upper_margin = 33,     /* v_back_porch */
80         .right_margin = 16,     /* h_front_porch */
81         .lower_margin = 10,     /* v_front_porch */
82         .vmode = 0,
83         .sync = 0,
84 };
85
86 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
87
88 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
89
90 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
91
92 DEFINE_MUTEX(tegra_dc_lock);
93 DEFINE_MUTEX(shared_lock);
94
95 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
96 {
97         if (!tegra_is_clk_enabled(dc->clk)) {
98                 clk_enable(dc->clk);
99                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
100         }
101 }
102
103 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
104 {
105         if (tegra_is_clk_enabled(dc->clk)) {
106                 clk_disable(dc->clk);
107                 tegra_dvfs_set_rate(dc->clk, 0);
108         }
109 }
110
111 #define DUMP_REG(a) do {                        \
112         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
113                  #a, a, tegra_dc_readl(dc, a));               \
114         print(data, buff);                                    \
115         } while (0)
116
117 #define print_mode_info(dc, mode) do {                        \
118         trace_printk("%s:Mode settings: "                              \
119                         "ref_to_sync: H = %d V = %d, "                  \
120                         "sync_width: H = %d V = %d, "                   \
121                         "back_porch: H = %d V = %d, "                   \
122                         "active: H = %d V = %d, "                       \
123                         "front_porch: H = %d V = %d, "                  \
124                         "pclk = %d, stereo mode = %d\n",                \
125                         dc->ndev->name,                                 \
126                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
127                         mode.h_sync_width, mode.v_sync_width,           \
128                         mode.h_back_porch, mode.v_back_porch,           \
129                         mode.h_active, mode.v_active,                   \
130                         mode.h_front_porch, mode.v_front_porch,         \
131                         mode.pclk, mode.stereo_mode);                   \
132         } while (0)
133
134 #define print_underflow_info(dc) do {                 \
135         trace_printk("%s:Underflow stats: underflows : %llu, "      \
136                         "undeflows_a : %llu, "                          \
137                         "underflows_b : %llu, "                         \
138                         "underflows_c : %llu\n",                        \
139                         dc->ndev->name,                                 \
140                         dc->stats.underflows,                           \
141                         dc->stats.underflows_a, dc->stats.underflows_b, \
142                         dc->stats.underflows_c);                        \
143         } while (0)
144
145 static void _dump_regs(struct tegra_dc *dc, void *data,
146                        void (* print)(void *data, const char *str))
147 {
148         int i;
149         char buff[256];
150
151         tegra_dc_io_start(dc);
152         tegra_dc_clk_enable(dc);
153
154         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
155         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
156         DUMP_REG(DC_CMD_SIGNAL_RAISE);
157         DUMP_REG(DC_CMD_INT_STATUS);
158         DUMP_REG(DC_CMD_INT_MASK);
159         DUMP_REG(DC_CMD_INT_ENABLE);
160         DUMP_REG(DC_CMD_INT_TYPE);
161         DUMP_REG(DC_CMD_INT_POLARITY);
162         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
163         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
164         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
165         DUMP_REG(DC_CMD_STATE_ACCESS);
166         DUMP_REG(DC_CMD_STATE_CONTROL);
167         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
168         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
169
170         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
171         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
172         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
173         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
174         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
175         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
176         DUMP_REG(DC_DISP_REF_TO_SYNC);
177         DUMP_REG(DC_DISP_SYNC_WIDTH);
178         DUMP_REG(DC_DISP_BACK_PORCH);
179         DUMP_REG(DC_DISP_DISP_ACTIVE);
180         DUMP_REG(DC_DISP_FRONT_PORCH);
181         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
182         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
183         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
184         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
185         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
186         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
187         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
188         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
189         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
190         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
191         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
192         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
193         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
194         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
195         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
196         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
197         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
198         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
199         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
200         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
201         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
202         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
203         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
204         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
205         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
206         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
207         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
208         DUMP_REG(DC_DISP_M0_CONTROL);
209         DUMP_REG(DC_DISP_M1_CONTROL);
210         DUMP_REG(DC_DISP_DI_CONTROL);
211         DUMP_REG(DC_DISP_PP_CONTROL);
212         DUMP_REG(DC_DISP_PP_SELECT_A);
213         DUMP_REG(DC_DISP_PP_SELECT_B);
214         DUMP_REG(DC_DISP_PP_SELECT_C);
215         DUMP_REG(DC_DISP_PP_SELECT_D);
216         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
217         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
218         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
219         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
220         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
221         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
222         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
223         DUMP_REG(DC_DISP_BORDER_COLOR);
224         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
225         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
226         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
227         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
228         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
229         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
230         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
231         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
232         DUMP_REG(DC_DISP_CURSOR_POSITION);
233         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
234         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
235         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
236         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
237         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
238         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
239         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
240         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
241         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
242         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
243         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
244         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
245         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
246
247
248         for (i = 0; i < 3; i++) {
249                 print(data, "\n");
250                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
251                 print(data, buff);
252
253                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
254                                 DC_CMD_DISPLAY_WINDOW_HEADER);
255                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
256                 DUMP_REG(DC_WIN_WIN_OPTIONS);
257                 DUMP_REG(DC_WIN_BYTE_SWAP);
258                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
259                 DUMP_REG(DC_WIN_COLOR_DEPTH);
260                 DUMP_REG(DC_WIN_POSITION);
261                 DUMP_REG(DC_WIN_SIZE);
262                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
263                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
264                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
265                 DUMP_REG(DC_WIN_DDA_INCREMENT);
266                 DUMP_REG(DC_WIN_LINE_STRIDE);
267                 DUMP_REG(DC_WIN_BUF_STRIDE);
268                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
269                 DUMP_REG(DC_WIN_BLEND_NOKEY);
270                 DUMP_REG(DC_WIN_BLEND_1WIN);
271                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
272                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
273                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
274                 DUMP_REG(DC_WINBUF_START_ADDR);
275                 DUMP_REG(DC_WINBUF_START_ADDR_U);
276                 DUMP_REG(DC_WINBUF_START_ADDR_V);
277                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
278                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
279                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
280                 DUMP_REG(DC_WIN_CSC_YOF);
281                 DUMP_REG(DC_WIN_CSC_KYRGB);
282                 DUMP_REG(DC_WIN_CSC_KUR);
283                 DUMP_REG(DC_WIN_CSC_KVR);
284                 DUMP_REG(DC_WIN_CSC_KUG);
285                 DUMP_REG(DC_WIN_CSC_KVG);
286                 DUMP_REG(DC_WIN_CSC_KUB);
287                 DUMP_REG(DC_WIN_CSC_KVB);
288         }
289
290         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
291         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
292         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
293         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
294         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
295         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
296         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
297         DUMP_REG(DC_DISP_M1_CONTROL);
298         DUMP_REG(DC_COM_PM1_CONTROL);
299         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
300         DUMP_REG(DC_DISP_SD_CONTROL);
301
302         tegra_dc_clk_disable(dc->clk);
303         tegra_dc_io_end(dc);
304 }
305
306 #undef DUMP_REG
307
308 #ifdef DEBUG
309 static void dump_regs_print(void *data, const char *str)
310 {
311         struct tegra_dc *dc = data;
312         dev_dbg(&dc->ndev->dev, "%s", str);
313 }
314
315 static void dump_regs(struct tegra_dc *dc)
316 {
317         _dump_regs(dc, dc, dump_regs_print);
318 }
319 #else /* !DEBUG */
320
321 static void dump_regs(struct tegra_dc *dc) {}
322
323 #endif /* DEBUG */
324
325 #ifdef CONFIG_DEBUG_FS
326
327 static void dbg_regs_print(void *data, const char *str)
328 {
329         struct seq_file *s = data;
330
331         seq_printf(s, "%s", str);
332 }
333
334 #undef DUMP_REG
335
336 static int dbg_dc_show(struct seq_file *s, void *unused)
337 {
338         struct tegra_dc *dc = s->private;
339
340         _dump_regs(dc, s, dbg_regs_print);
341
342         return 0;
343 }
344
345
346 static int dbg_dc_open(struct inode *inode, struct file *file)
347 {
348         return single_open(file, dbg_dc_show, inode->i_private);
349 }
350
351 static const struct file_operations regs_fops = {
352         .open           = dbg_dc_open,
353         .read           = seq_read,
354         .llseek         = seq_lseek,
355         .release        = single_release,
356 };
357
358 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
359 {
360         struct tegra_dc *dc = s->private;
361         struct tegra_dc_mode *m;
362
363         mutex_lock(&dc->lock);
364         m = &dc->mode;
365         seq_printf(s,
366                 "pclk: %d\n"
367                 "h_ref_to_sync: %d\n"
368                 "v_ref_to_sync: %d\n"
369                 "h_sync_width: %d\n"
370                 "v_sync_width: %d\n"
371                 "h_back_porch: %d\n"
372                 "v_back_porch: %d\n"
373                 "h_active: %d\n"
374                 "v_active: %d\n"
375                 "h_front_porch: %d\n"
376                 "v_front_porch: %d\n"
377                 "stereo_mode: %d\n",
378                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
379                 m->h_sync_width, m->v_sync_width,
380                 m->h_back_porch, m->v_back_porch,
381                 m->h_active, m->v_active,
382                 m->h_front_porch, m->v_front_porch,
383                 m->stereo_mode);
384         mutex_unlock(&dc->lock);
385         return 0;
386 }
387
388 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
389 {
390         return single_open(file, dbg_dc_mode_show, inode->i_private);
391 }
392
393 static const struct file_operations mode_fops = {
394         .open           = dbg_dc_mode_open,
395         .read           = seq_read,
396         .llseek         = seq_lseek,
397         .release        = single_release,
398 };
399
400 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
401 {
402         struct tegra_dc *dc = s->private;
403
404         mutex_lock(&dc->lock);
405         seq_printf(s,
406                 "underflows: %llu\n"
407                 "underflows_a: %llu\n"
408                 "underflows_b: %llu\n"
409                 "underflows_c: %llu\n",
410                 dc->stats.underflows,
411                 dc->stats.underflows_a,
412                 dc->stats.underflows_b,
413                 dc->stats.underflows_c);
414         mutex_unlock(&dc->lock);
415
416         return 0;
417 }
418
419 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
420 {
421         return single_open(file, dbg_dc_stats_show, inode->i_private);
422 }
423
424 static const struct file_operations stats_fops = {
425         .open           = dbg_dc_stats_open,
426         .read           = seq_read,
427         .llseek         = seq_lseek,
428         .release        = single_release,
429 };
430
431 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
432 {
433         if (dc->debugdir)
434                 debugfs_remove_recursive(dc->debugdir);
435         dc->debugdir = NULL;
436 }
437
438 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
439 {
440         struct dentry *retval;
441
442         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
443         if (!dc->debugdir)
444                 goto remove_out;
445
446         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
447                 &regs_fops);
448         if (!retval)
449                 goto remove_out;
450
451         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
452                 &mode_fops);
453         if (!retval)
454                 goto remove_out;
455
456         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
457                 &stats_fops);
458         if (!retval)
459                 goto remove_out;
460
461         return;
462 remove_out:
463         dev_err(&dc->ndev->dev, "could not create debugfs\n");
464         tegra_dc_remove_debugfs(dc);
465 }
466
467 #else /* !CONFIG_DEBUGFS */
468 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
469 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
470 #endif /* CONFIG_DEBUGFS */
471
472 static int tegra_dc_set(struct tegra_dc *dc, int index)
473 {
474         int ret = 0;
475
476         mutex_lock(&tegra_dc_lock);
477         if (index >= TEGRA_MAX_DC) {
478                 ret = -EINVAL;
479                 goto out;
480         }
481
482         if (dc != NULL && tegra_dcs[index] != NULL) {
483                 ret = -EBUSY;
484                 goto out;
485         }
486
487         tegra_dcs[index] = dc;
488
489 out:
490         mutex_unlock(&tegra_dc_lock);
491
492         return ret;
493 }
494
495 unsigned int tegra_dc_has_multiple_dc(void)
496 {
497         unsigned int idx;
498         unsigned int cnt = 0;
499         struct tegra_dc *dc;
500
501         mutex_lock(&tegra_dc_lock);
502         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
503                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
504         mutex_unlock(&tegra_dc_lock);
505
506         return (cnt > 1);
507 }
508
509 /* get the stride size of a window.
510  * return: stride size in bytes for window win. or 0 if unavailble. */
511 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
512 {
513         u32 stride;
514
515         if (!dc->enabled)
516                 return 0;
517         BUG_ON(win > DC_N_WINDOWS);
518         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
519                 DC_CMD_DISPLAY_WINDOW_HEADER);
520         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
521         return GET_LINE_STRIDE(stride);
522 }
523 EXPORT_SYMBOL(tegra_dc_get_stride);
524
525 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
526 {
527         if (idx < TEGRA_MAX_DC)
528                 return tegra_dcs[idx];
529         else
530                 return NULL;
531 }
532 EXPORT_SYMBOL(tegra_dc_get_dc);
533
534 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
535 {
536         if (win >= dc->n_windows)
537                 return NULL;
538
539         return &dc->windows[win];
540 }
541 EXPORT_SYMBOL(tegra_dc_get_window);
542
543 static int get_topmost_window(u32 *depths, unsigned long *wins)
544 {
545         int idx, best = -1;
546
547         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
548                 if (best == -1 || depths[idx] < depths[best])
549                         best = idx;
550         }
551         clear_bit(best, wins);
552         return best;
553 }
554
555 bool tegra_dc_get_connected(struct tegra_dc *dc)
556 {
557         return dc->connected;
558 }
559 EXPORT_SYMBOL(tegra_dc_get_connected);
560
561 bool tegra_dc_hpd(struct tegra_dc *dc)
562 {
563         int sense;
564         int level;
565
566         level = gpio_get_value(dc->out->hotplug_gpio);
567
568         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
569
570         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
571                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
572 }
573 EXPORT_SYMBOL(tegra_dc_hpd);
574
575 static u32 blend_topwin(u32 flags)
576 {
577         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
578                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
579         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
580                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
581         else
582                 return BLEND(NOKEY, FIX, 0xff, 0xff);
583 }
584
585 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
586 {
587         int other;
588
589         for (other = 0; other < DC_N_WINDOWS; other++) {
590                 if (other != idx && (xy-- == 0))
591                         break;
592         }
593         if (BIT(other) & behind_mask)
594                 return blend_topwin(flags[idx]);
595         else if (flags[other])
596                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
597         else
598                 return BLEND(NOKEY, FIX, 0x00, 0x00);
599 }
600
601 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
602 {
603         unsigned long infront_mask;
604         int first;
605
606         infront_mask = ~(behind_mask | BIT(idx));
607         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
608         first = ffs(infront_mask) - 1;
609
610         if (!infront_mask)
611                 return blend_topwin(flags[idx]);
612         else if (behind_mask && first != -1 && flags[first])
613                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
614         else
615                 return BLEND(NOKEY, FIX, 0x0, 0x0);
616 }
617
618 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
619 {
620         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
621
622         while (mask) {
623                 int idx = get_topmost_window(blend->z, &mask);
624
625                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
626                                 DC_CMD_DISPLAY_WINDOW_HEADER);
627                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
628                                 DC_WIN_BLEND_NOKEY);
629                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
630                                 DC_WIN_BLEND_1WIN);
631                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
632                                 DC_WIN_BLEND_2WIN_X);
633                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
634                                 DC_WIN_BLEND_2WIN_Y);
635                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
636                                 DC_WIN_BLEND_3WIN_XY);
637         }
638 }
639
640 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
641 {
642         csc->yof   = 0x00f0;
643         csc->kyrgb = 0x012a;
644         csc->kur   = 0x0000;
645         csc->kvr   = 0x0198;
646         csc->kug   = 0x039b;
647         csc->kvg   = 0x032f;
648         csc->kub   = 0x0204;
649         csc->kvb   = 0x0000;
650 }
651
652 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
653 {
654         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
655         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
656         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
657         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
658         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
659         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
660         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
661         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
662 }
663
664 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
665 {
666         mutex_lock(&dc->lock);
667
668         if (!dc->enabled) {
669                 mutex_unlock(&dc->lock);
670                 return -EFAULT;
671         }
672
673         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
674                         DC_CMD_DISPLAY_WINDOW_HEADER);
675
676         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
677
678         mutex_unlock(&dc->lock);
679
680         return 0;
681 }
682 EXPORT_SYMBOL(tegra_dc_update_csc);
683
684 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
685 {
686         int i;
687         for (i = 0; i < 256; i++)
688                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
689 }
690
691 static int tegra_dc_loop_lut(struct tegra_dc *dc,
692                              struct tegra_dc_win *win,
693                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
694 {
695         struct tegra_dc_lut *lut = &win->lut;
696         struct tegra_dc_lut *global_lut = &dc->fb_lut;
697         int i;
698         for (i = 0; i < 256; i++) {
699
700                 u32 r = (u32)lut->r[i];
701                 u32 g = (u32)lut->g[i];
702                 u32 b = (u32)lut->b[i];
703
704                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
705                         r = (u32)global_lut->r[r];
706                         g = (u32)global_lut->g[g];
707                         b = (u32)global_lut->b[b];
708                 }
709
710                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
711                         return 0;
712         }
713         return 1;
714 }
715
716 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
717 {
718         if (rgb != (i | (i<<8) | (i<<16)))
719                 return 0;
720         return 1;
721 }
722
723 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
724 {
725         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
726         return 1;
727 }
728
729 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
730 {
731         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
732
733         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
734
735         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
736                 val |= CP_ENABLE;
737         else
738                 val &= ~CP_ENABLE;
739
740         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
741 }
742
743 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
744 {
745         struct tegra_dc_win *win = &dc->windows[win_idx];
746
747         mutex_lock(&dc->lock);
748
749         if (!dc->enabled) {
750                 mutex_unlock(&dc->lock);
751                 return -EFAULT;
752         }
753
754         if (fbovr > 0)
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
756         else if (fbovr == 0)
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
758
759         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
760                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
761         else
762                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
763
764         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
765                         DC_CMD_DISPLAY_WINDOW_HEADER);
766
767         tegra_dc_set_lut(dc, win);
768
769         mutex_unlock(&dc->lock);
770
771         tegra_dc_update_windows(&win, 1);
772
773         return 0;
774 }
775
776 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
777 {
778         if (win_idx > -1)
779                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
780
781         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
782                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
783                 if (err)
784                         return err;
785         }
786
787         return 0;
788 }
789 EXPORT_SYMBOL(tegra_dc_update_lut);
790
791 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
792 {
793         unsigned i;
794         unsigned v0 = 128;
795         unsigned v1 = 0;
796         /* linear horizontal and vertical filters */
797         for (i = 0; i < 16; i++) {
798                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
799                                 DC_WIN_H_FILTER_P(i));
800
801                 tegra_dc_writel(dc, v0,
802                                 DC_WIN_V_FILTER_P(i));
803                 v0 -= 8;
804                 v1 += 8;
805         }
806 }
807
808 void tegra_dc_host_suspend(struct tegra_dc *dc)
809 {
810         tegra_dsi_host_suspend(dc);
811         tegra_dc_clk_disable(dc);
812 }
813
814 void tegra_dc_host_resume(struct tegra_dc *dc) {
815         tegra_dc_clk_enable(dc);
816         tegra_dsi_host_resume(dc);
817 }
818
819 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
820                                   bool v, unsigned Bpp)
821 {
822         /*
823          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
824          *           (post_scaled_size_in_pixels - 1)), MAX)
825          * Where the value of MAX is as follows:
826          * For V_DDA_INCREMENT: 15.0 (0xF000)
827          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
828          *                       8.0 (0x8000) for 2 Bytes/pix formats.
829          */
830
831         fixed20_12 out = dfixed_init(out_int);
832         u32 dda_inc;
833         int max;
834
835         if (v) {
836                 max = 15;
837         } else {
838                 switch (Bpp) {
839                 default:
840                         WARN_ON_ONCE(1);
841                         /* fallthrough */
842                 case 4:
843                         max = 4;
844                         break;
845                 case 2:
846                         max = 8;
847                         break;
848                 }
849         }
850
851         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
852         in.full -= dfixed_const(1);
853
854         dda_inc = dfixed_div(in, out);
855
856         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
857
858         return dda_inc;
859 }
860
861 static inline u32 compute_initial_dda(fixed20_12 in)
862 {
863         return dfixed_frac(in);
864 }
865
866 /* does not support updating windows on multiple dcs in one call */
867 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
868 {
869         struct tegra_dc *dc;
870         unsigned long update_mask = GENERAL_ACT_REQ;
871         unsigned long val;
872         bool update_blend = false;
873         int i;
874
875         dc = windows[0]->dc;
876
877         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
878                 /* Acquire one_shot_lock to avoid race condition between
879                  * cancellation of old delayed work and schedule of new
880                  * delayed work. */
881                 mutex_lock(&dc->one_shot_lock);
882                 cancel_delayed_work_sync(&dc->one_shot_work);
883         }
884         mutex_lock(&dc->lock);
885
886         if (!dc->enabled) {
887                 mutex_unlock(&dc->lock);
888                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
889                         mutex_unlock(&dc->one_shot_lock);
890                 return -EFAULT;
891         }
892
893         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
894                 tegra_dc_host_resume(dc);
895
896         if (no_vsync)
897                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
898         else
899                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
900
901         for (i = 0; i < n; i++) {
902                 struct tegra_dc_win *win = windows[i];
903                 unsigned h_dda;
904                 unsigned v_dda;
905                 fixed20_12 h_offset, v_offset;
906                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
907                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
908                 bool yuv = tegra_dc_is_yuv(win->fmt);
909                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
910                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
911                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
912                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
913                 const bool filter_h = win_use_h_filter(dc, win);
914                 const bool filter_v = win_use_v_filter(dc, win);
915
916                 if (win->z != dc->blend.z[win->idx]) {
917                         dc->blend.z[win->idx] = win->z;
918                         update_blend = true;
919                 }
920                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
921                         dc->blend.flags[win->idx]) {
922                         dc->blend.flags[win->idx] =
923                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
924                         update_blend = true;
925                 }
926
927                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
928                                 DC_CMD_DISPLAY_WINDOW_HEADER);
929
930                 if (!no_vsync)
931                         update_mask |= WIN_A_ACT_REQ << win->idx;
932
933                 if (!WIN_IS_ENABLED(win)) {
934                         dc->windows[i].dirty = 1;
935                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
936                         continue;
937                 }
938
939                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
940                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
941
942                 tegra_dc_writel(dc,
943                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
944                                 DC_WIN_POSITION);
945                 tegra_dc_writel(dc,
946                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
947                                 DC_WIN_SIZE);
948
949                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
950                         tegra_dc_writel(dc,
951                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
952                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
953                                         DC_WIN_PRESCALED_SIZE);
954
955                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
956                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
957                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
958                                         DC_WIN_DDA_INCREMENT);
959                         h_dda = compute_initial_dda(win->x);
960                         v_dda = compute_initial_dda(win->y);
961                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
962                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
963                 }
964
965                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
966                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
967                 tegra_dc_writel(dc,
968                                 (unsigned long)win->phys_addr,
969                                 DC_WINBUF_START_ADDR);
970
971                 if (!yuvp) {
972                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
973                 } else {
974                         tegra_dc_writel(dc,
975                                         (unsigned long)win->phys_addr_u,
976                                         DC_WINBUF_START_ADDR_U);
977                         tegra_dc_writel(dc,
978                                         (unsigned long)win->phys_addr_v,
979                                         DC_WINBUF_START_ADDR_V);
980                         tegra_dc_writel(dc,
981                                         LINE_STRIDE(win->stride) |
982                                         UV_LINE_STRIDE(win->stride_uv),
983                                         DC_WIN_LINE_STRIDE);
984                 }
985
986                 h_offset = win->x;
987                 if (invert_h) {
988                         h_offset.full += win->w.full - dfixed_const(1);
989                 }
990
991                 v_offset = win->y;
992                 if (invert_v) {
993                         v_offset.full += win->h.full - dfixed_const(1);
994                 }
995
996                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
997                                 DC_WINBUF_ADDR_H_OFFSET);
998                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
999                                 DC_WINBUF_ADDR_V_OFFSET);
1000
1001                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
1002                         if (WIN_IS_TILED(win))
1003                                 tegra_dc_writel(dc,
1004                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1005                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1006                                                 DC_WIN_BUFFER_ADDR_MODE);
1007                         else
1008                                 tegra_dc_writel(dc,
1009                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1010                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1011                                                 DC_WIN_BUFFER_ADDR_MODE);
1012                 }
1013
1014                 val = WIN_ENABLE;
1015                 if (yuv)
1016                         val |= CSC_ENABLE;
1017                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1018                         val |= COLOR_EXPAND;
1019
1020                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1021                         val |= CP_ENABLE;
1022
1023                 if (filter_h)
1024                         val |= H_FILTER_ENABLE;
1025                 if (filter_v)
1026                         val |= V_FILTER_ENABLE;
1027
1028                 if (invert_h)
1029                         val |= H_DIRECTION_DECREMENT;
1030                 if (invert_v)
1031                         val |= V_DIRECTION_DECREMENT;
1032
1033                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1034
1035 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1036                 if (win->global_alpha == 255)
1037                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1038                 else
1039                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1040                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1041 #endif
1042
1043                 win->dirty = no_vsync ? 0 : 1;
1044
1045                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1046                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1047                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1048                         __func__, win->idx, win->z,
1049                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1050                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1051                         win->out_x, win->out_y, win->out_w, win->out_h,
1052                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1053                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1054                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1055                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1056         }
1057
1058         if (update_blend) {
1059                 tegra_dc_set_blending(dc, &dc->blend);
1060                 for (i = 0; i < DC_N_WINDOWS; i++) {
1061                         if (!no_vsync)
1062                                 dc->windows[i].dirty = 1;
1063                         update_mask |= WIN_A_ACT_REQ << i;
1064                 }
1065         }
1066
1067         tegra_dc_set_dynamic_emc(windows, n);
1068
1069         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1070
1071         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1072         if (!no_vsync) {
1073                 set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1074                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1075         } else {
1076                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1077                 tegra_dc_mask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1078         }
1079
1080         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1081                 schedule_delayed_work(&dc->one_shot_work,
1082                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1083
1084         /* update EMC clock if calculated bandwidth has changed */
1085         tegra_dc_program_bandwidth(dc, false);
1086
1087         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1088                 update_mask |= NC_HOST_TRIG;
1089
1090         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1091         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1092
1093         mutex_unlock(&dc->lock);
1094         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1095                 mutex_unlock(&dc->one_shot_lock);
1096
1097         return 0;
1098 }
1099 EXPORT_SYMBOL(tegra_dc_update_windows);
1100
1101 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1102 {
1103         return dc->syncpt[i].id;
1104 }
1105 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1106
1107 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1108 {
1109         u32 max;
1110
1111         mutex_lock(&dc->lock);
1112         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1113                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1114         dc->syncpt[i].max = max;
1115         mutex_unlock(&dc->lock);
1116
1117         return max;
1118 }
1119
1120 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1121 {
1122         mutex_lock(&dc->lock);
1123         if ( dc->enabled )
1124                 while (dc->syncpt[i].min < val) {
1125                         dc->syncpt[i].min++;
1126                         nvhost_syncpt_cpu_incr(
1127                                         &nvhost_get_host(dc->ndev)->syncpt,
1128                                         dc->syncpt[i].id);
1129                 }
1130         mutex_unlock(&dc->lock);
1131 }
1132
1133 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1134                                              int n)
1135 {
1136         int i;
1137
1138         for (i = 0; i < n; i++) {
1139                 if (windows[i]->dirty)
1140                         return false;
1141         }
1142
1143         return true;
1144 }
1145
1146 /* does not support syncing windows on multiple dcs in one call */
1147 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1148 {
1149         int ret;
1150         if (n < 1 || n > DC_N_WINDOWS)
1151                 return -EINVAL;
1152
1153         if (!windows[0]->dc->enabled)
1154                 return -EFAULT;
1155
1156 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1157         /* Don't want to timeout on simulator */
1158         ret = wait_event_interruptible(windows[0]->dc->wq,
1159                 tegra_dc_windows_are_clean(windows, n));
1160 #else
1161         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1162                         windows[0]->dc->ndev->name);
1163         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1164                                          tegra_dc_windows_are_clean(windows, n),
1165                                          HZ);
1166         trace_printk("%s:After wait_event_interruptible_timeout\n",
1167                         windows[0]->dc->ndev->name);
1168 #endif
1169         return ret;
1170 }
1171 EXPORT_SYMBOL(tegra_dc_sync_windows);
1172
1173 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1174 {
1175 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1176         return clk_get_rate(dc->clk);
1177 #else
1178         return 27000000;
1179 #endif
1180 }
1181
1182 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1183 {
1184         unsigned long rate;
1185         unsigned long div;
1186
1187         rate = tegra_dc_clk_get_rate(dc);
1188
1189         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1190
1191         if (div < 2)
1192                 return 0;
1193
1194         return rate * 2 / div;
1195 }
1196
1197 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1198 {
1199         unsigned long rate;
1200         unsigned long div;
1201
1202         rate = clk_get_rate(parent);
1203
1204         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1205
1206         if (div < 2)
1207                 return 0;
1208
1209         return rate * 2 / div;
1210 }
1211
1212 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1213 {
1214         int pclk;
1215
1216         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1217                 unsigned long rate;
1218                 struct clk *parent_clk =
1219                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1220
1221                 if (dc->out->parent_clk_backup &&
1222                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1223                         rate = tegra_dc_pclk_predict_rate(
1224                                 parent_clk, dc->mode.pclk);
1225                         /* use pll_d as last resort */
1226                         if (rate < (dc->mode.pclk / 100 * 99) ||
1227                             rate > (dc->mode.pclk / 100 * 109))
1228                                 parent_clk = clk_get_sys(
1229                                         NULL, dc->out->parent_clk_backup);
1230                 }
1231
1232                 if (clk_get_parent(clk) != parent_clk)
1233                         clk_set_parent(clk, parent_clk);
1234
1235                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1236                         struct clk *base_clk = clk_get_parent(parent_clk);
1237
1238                         /* Assuming either pll_d or pll_d2 is used */
1239                         rate = dc->mode.pclk * 2;
1240
1241                         if (rate != clk_get_rate(base_clk))
1242                                 clk_set_rate(base_clk, rate);
1243                 }
1244         }
1245
1246         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1247                 unsigned long rate;
1248                 struct clk *parent_clk =
1249                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1250                 struct clk *base_clk = clk_get_parent(parent_clk);
1251
1252                 /*
1253                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1254                  * The required rate needs to be setup at 4x multiplier,
1255                  * as out0 is 1/2 of the actual PLL output.
1256                  */
1257
1258                 rate = dc->mode.pclk * 4;
1259                 if (rate != clk_get_rate(base_clk))
1260                         clk_set_rate(base_clk, rate);
1261
1262                 if (clk_get_parent(clk) != parent_clk)
1263                         clk_set_parent(clk, parent_clk);
1264         }
1265
1266         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1267                 unsigned long rate;
1268                 struct clk *parent_clk;
1269                 struct clk *base_clk;
1270
1271                 if (clk == dc->clk) {
1272                         parent_clk = clk_get_sys(NULL,
1273                                         dc->out->parent_clk ? : "pll_d_out0");
1274                         base_clk = clk_get_parent(parent_clk);
1275                         tegra_clk_cfg_ex(base_clk,
1276                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1277                 } else {
1278                         if (dc->pdata->default_out->dsi->dsi_instance) {
1279                                 parent_clk = clk_get_sys(NULL,
1280                                         dc->out->parent_clk ? : "pll_d2_out0");
1281                                 base_clk = clk_get_parent(parent_clk);
1282                                 tegra_clk_cfg_ex(base_clk,
1283                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1284                         } else {
1285                                 parent_clk = clk_get_sys(NULL,
1286                                         dc->out->parent_clk ? : "pll_d_out0");
1287                                 base_clk = clk_get_parent(parent_clk);
1288                                 tegra_clk_cfg_ex(base_clk,
1289                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1290                         }
1291                 }
1292
1293                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1294                 if (rate != clk_get_rate(base_clk))
1295                         clk_set_rate(base_clk, rate);
1296
1297                 if (clk_get_parent(clk) != parent_clk)
1298                         clk_set_parent(clk, parent_clk);
1299         }
1300
1301         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1302         tegra_dvfs_set_rate(clk, pclk);
1303 }
1304
1305 /* return non-zero if constraint is violated */
1306 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1307 {
1308         long a, b;
1309
1310         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1311         a = 0;
1312
1313         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1314         b = mode->h_front_porch - 1;
1315
1316         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1317         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1318                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1319         /* check Constraint 1 and 6 */
1320         if (a > b)
1321                 return 1;
1322
1323         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1324         if (mode->h_sync_width < 1)
1325                 return 4;
1326
1327         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1328         if (mode->h_active < 16)
1329                 return 7;
1330
1331         if (href) {
1332                 if (b > a && a % 2)
1333                         *href = a + 1; /* use smallest even value */
1334                 else
1335                         *href = a; /* even or only possible value */
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1342 {
1343         long a;
1344         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1345
1346         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1347         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1348                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1349
1350         /* Constraint 6 */
1351         if (mode->v_front_porch < a + 1)
1352                 a = mode->v_front_porch - 1;
1353
1354         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1355         if (mode->v_sync_width < 1)
1356                 return 4;
1357
1358         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1359         if (mode->v_active < 16)
1360                 return 7;
1361
1362         if (vref)
1363                 *vref = a;
1364         return 0;
1365 }
1366
1367 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1368 {
1369         int ret;
1370         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1371         if (ret)
1372                 return ret;
1373         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1374         if (ret)
1375                 return ret;
1376
1377         return 0;
1378 }
1379
1380 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1381 {
1382         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1383         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1384                 return false;
1385
1386         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1387         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1388                 return false;
1389
1390         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1391          * (vertical blank). */
1392         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1393                 return false;
1394
1395         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1396         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1397                 return false;
1398
1399         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1400         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1401                 return false;
1402
1403         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1404          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1405         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1406                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1407                 return false;
1408
1409         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1410         if (mode->h_active < 16 || mode->v_active < 16)
1411                 return false;
1412
1413         return true;
1414 }
1415
1416 #ifdef DEBUG
1417 /* return in 1000ths of a Hertz */
1418 static int calc_refresh(const struct tegra_dc_mode *m)
1419 {
1420         long h_total, v_total, refresh;
1421         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1422                 m->h_sync_width;
1423         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1424                 m->v_sync_width;
1425         refresh = m->pclk / h_total;
1426         refresh *= 1000;
1427         refresh /= v_total;
1428         return refresh;
1429 }
1430
1431 static void print_mode(struct tegra_dc *dc,
1432                         const struct tegra_dc_mode *mode, const char *note)
1433 {
1434         if (mode) {
1435                 int refresh = calc_refresh(dc, mode);
1436                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1437                         note ? note : "",
1438                         mode->h_active, mode->v_active,
1439                         refresh / 1000, refresh % 1000,
1440                         mode->pclk);
1441         }
1442 }
1443 #else /* !DEBUG */
1444 static inline void print_mode(struct tegra_dc *dc,
1445                         const struct tegra_dc_mode *mode, const char *note) { }
1446 #endif /* DEBUG */
1447
1448 static inline void enable_dc_irq(unsigned int irq)
1449 {
1450 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1451         enable_irq(irq);
1452 #else
1453         /* Always disable DC interrupts on FPGA. */
1454         disable_irq(irq);
1455 #endif
1456 }
1457
1458 static inline void disable_dc_irq(unsigned int irq)
1459 {
1460         disable_irq(irq);
1461 }
1462
1463 static inline void tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
1464 {
1465         u32 val;
1466
1467         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1468         val |= int_val;
1469         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1470 }
1471
1472 static inline void tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
1473 {
1474         u32 val;
1475
1476         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1477         val &= ~int_val;
1478         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1479 }
1480
1481 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1482 {
1483         unsigned long val;
1484         unsigned long rate;
1485         unsigned long div;
1486         unsigned long pclk;
1487
1488         print_mode(dc, mode, __func__);
1489
1490         /* use default EMC rate when switching modes */
1491         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1492         tegra_dc_program_bandwidth(dc, true);
1493
1494         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1495         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1496                         DC_DISP_REF_TO_SYNC);
1497         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1498                         DC_DISP_SYNC_WIDTH);
1499         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1500                         DC_DISP_BACK_PORCH);
1501         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1502                         DC_DISP_DISP_ACTIVE);
1503         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1504                         DC_DISP_FRONT_PORCH);
1505
1506         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1507                         DC_DISP_DATA_ENABLE_OPTIONS);
1508
1509         /* TODO: MIPI/CRT/HDMI clock cals */
1510
1511         val = DISP_DATA_FORMAT_DF1P1C;
1512
1513         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1514                 val |= DISP_DATA_ALIGNMENT_MSB;
1515         else
1516                 val |= DISP_DATA_ALIGNMENT_LSB;
1517
1518         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1519                 val |= DISP_DATA_ORDER_RED_BLUE;
1520         else
1521                 val |= DISP_DATA_ORDER_BLUE_RED;
1522
1523         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1524
1525         rate = tegra_dc_clk_get_rate(dc);
1526
1527         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1528         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1529         if (pclk < (mode->pclk / 100 * 99) ||
1530             pclk > (mode->pclk / 100 * 109)) {
1531                 dev_err(&dc->ndev->dev,
1532                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1533                         rate, mode->pclk,
1534                         pclk, (mode->pclk / 100 * 99),
1535                         (mode->pclk / 100 * 109));
1536                 return -EINVAL;
1537         }
1538
1539         div = (rate * 2 / pclk) - 2;
1540         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1541
1542         tegra_dc_writel(dc, 0x00010001,
1543                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1544         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1545                         DC_DISP_DISP_CLOCK_CONTROL);
1546
1547 #ifdef CONFIG_SWITCH
1548         switch_set_state(&dc->modeset_switch,
1549                          (mode->h_active << 16) | mode->v_active);
1550 #endif
1551
1552         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1553         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1554
1555         print_mode_info(dc, dc->mode);
1556         return 0;
1557 }
1558
1559
1560 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1561 {
1562         memcpy(&dc->mode, mode, sizeof(dc->mode));
1563
1564         print_mode(dc, mode, __func__);
1565
1566         return 0;
1567 }
1568 EXPORT_SYMBOL(tegra_dc_set_mode);
1569
1570 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1571                 const struct fb_videomode *fbmode, bool stereo_mode)
1572 {
1573         struct tegra_dc_mode mode;
1574
1575         if (!fbmode->pixclock)
1576                 return -EINVAL;
1577
1578         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1579         mode.h_sync_width = fbmode->hsync_len;
1580         mode.v_sync_width = fbmode->vsync_len;
1581         mode.h_back_porch = fbmode->left_margin;
1582         mode.v_back_porch = fbmode->upper_margin;
1583         mode.h_active = fbmode->xres;
1584         mode.v_active = fbmode->yres;
1585         mode.h_front_porch = fbmode->right_margin;
1586         mode.v_front_porch = fbmode->lower_margin;
1587         mode.stereo_mode = stereo_mode;
1588         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1589                 /* HDMI controller requires h_ref=1, v_ref=1 */
1590                 mode.h_ref_to_sync = 1;
1591                 mode.v_ref_to_sync = 1;
1592         } else {
1593                 calc_ref_to_sync(&mode);
1594         }
1595         if (!check_ref_to_sync(&mode)) {
1596                 dev_err(&dc->ndev->dev,
1597                                 "Display timing doesn't meet restrictions.\n");
1598                 return -EINVAL;
1599         }
1600         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1601                 mode.h_active, mode.v_active, mode.pclk,
1602                 mode.h_ref_to_sync, mode.v_ref_to_sync
1603         );
1604
1605 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1606         /* Double the pixel clock and update v_active only for frame packed mode */
1607         if (mode.stereo_mode) {
1608                 mode.pclk *= 2;
1609                 /* total v_active = yres*2 + activespace */
1610                 mode.v_active = fbmode->yres*2 +
1611                                 fbmode->vsync_len +
1612                                 fbmode->upper_margin +
1613                                 fbmode->lower_margin;
1614         }
1615 #endif
1616
1617         mode.flags = 0;
1618
1619         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1620                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1621
1622         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1623                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1624
1625         return tegra_dc_set_mode(dc, &mode);
1626 }
1627 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1628
1629 void
1630 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1631 {
1632         unsigned int ctrl;
1633         unsigned long out_sel;
1634         unsigned long cmd_state;
1635
1636         mutex_lock(&dc->lock);
1637         if (!dc->enabled) {
1638                 mutex_unlock(&dc->lock);
1639                 return;
1640         }
1641
1642         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1643                 tegra_dc_host_resume(dc);
1644
1645         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1646                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1647                 cfg->clk_select);
1648
1649         /* The new value should be effected immediately */
1650         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1651         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1652
1653         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1654                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1655         else
1656                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1657
1658         switch (cfg->which_pwm) {
1659         case TEGRA_PWM_PM0:
1660                 /* Select the LM0 on PM0 */
1661                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1662                 out_sel &= ~(7 << 0);
1663                 out_sel |= (3 << 0);
1664                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1665                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1666                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1667                 break;
1668         case TEGRA_PWM_PM1:
1669                 /* Select the LM1 on PM1 */
1670                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1671                 out_sel &= ~(7 << 4);
1672                 out_sel |= (3 << 4);
1673                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1674                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1675                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1676                 break;
1677         default:
1678                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1679                 break;
1680         }
1681         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1682         mutex_unlock(&dc->lock);
1683 }
1684 EXPORT_SYMBOL(tegra_dc_config_pwm);
1685
1686 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1687                                 const struct tegra_dc_out_pin *pins,
1688                                 const unsigned int n_pins)
1689 {
1690         unsigned int i;
1691
1692         int name;
1693         int pol;
1694
1695         u32 pol1, pol3;
1696
1697         u32 set1, unset1;
1698         u32 set3, unset3;
1699
1700         set1 = set3 = unset1 = unset3 = 0;
1701
1702         for (i = 0; i < n_pins; i++) {
1703                 name = (pins + i)->name;
1704                 pol  = (pins + i)->pol;
1705
1706                 /* set polarity by name */
1707                 switch (name) {
1708                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1709                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1710                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1711                         else
1712                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1713                         break;
1714                 case TEGRA_DC_OUT_PIN_H_SYNC:
1715                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1716                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1717                         else
1718                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1719                         break;
1720                 case TEGRA_DC_OUT_PIN_V_SYNC:
1721                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1722                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1723                         else
1724                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1725                         break;
1726                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1727                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1728                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1729                         else
1730                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1731                         break;
1732                 default:
1733                         printk("Invalid argument in function %s\n",
1734                                __FUNCTION__);
1735                         break;
1736                 }
1737         }
1738
1739         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1740         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1741
1742         pol1 |= set1;
1743         pol1 &= ~unset1;
1744
1745         pol3 |= set3;
1746         pol3 &= ~unset3;
1747
1748         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1749         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1750 }
1751
1752 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1753 {
1754         dc->out = out;
1755
1756         if (out->n_modes > 0)
1757                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1758
1759         switch (out->type) {
1760         case TEGRA_DC_OUT_RGB:
1761                 dc->out_ops = &tegra_dc_rgb_ops;
1762                 break;
1763
1764         case TEGRA_DC_OUT_HDMI:
1765                 dc->out_ops = &tegra_dc_hdmi_ops;
1766                 break;
1767
1768         case TEGRA_DC_OUT_DSI:
1769                 dc->out_ops = &tegra_dc_dsi_ops;
1770                 break;
1771
1772         default:
1773                 dc->out_ops = NULL;
1774                 break;
1775         }
1776
1777         if (dc->out_ops && dc->out_ops->init)
1778                 dc->out_ops->init(dc);
1779
1780 }
1781
1782 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1783 {
1784         if (dc->out)
1785                 return dc->out->height;
1786         else
1787                 return 0;
1788 }
1789 EXPORT_SYMBOL(tegra_dc_get_out_height);
1790
1791 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1792 {
1793         if (dc->out)
1794                 return dc->out->width;
1795         else
1796                 return 0;
1797 }
1798 EXPORT_SYMBOL(tegra_dc_get_out_width);
1799
1800 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1801 {
1802         if (dc->out && dc->out->max_pixclock)
1803                 return dc->out->max_pixclock;
1804         else
1805                 return 0;
1806 }
1807 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1808
1809 void tegra_dc_enable_crc(struct tegra_dc *dc)
1810 {
1811         u32 val;
1812         tegra_dc_io_start(dc);
1813
1814         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1815                 CRC_ENABLE_ENABLE;
1816         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1817         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1818         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1819 }
1820
1821 void tegra_dc_disable_crc(struct tegra_dc *dc)
1822 {
1823         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1824         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1825         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1826
1827         tegra_dc_io_end(dc);
1828 }
1829
1830 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1831 {
1832         int crc = 0;
1833
1834         if (!dc) {
1835                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1836                 goto crc_error;
1837         }
1838
1839         /* TODO: Replace mdelay with code to sync VBlANK, since
1840          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1841         mdelay(TEGRA_CRC_LATCHED_DELAY);
1842
1843         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1844 crc_error:
1845         return crc;
1846 }
1847
1848 static void tegra_dc_vblank(struct work_struct *work)
1849 {
1850         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1851         bool nvsd_updated = false;
1852
1853         mutex_lock(&dc->lock);
1854
1855         if (!dc->enabled) {
1856                 mutex_unlock(&dc->lock);
1857                 return;
1858         }
1859
1860         /* use the new frame's bandwidth setting instead of max(current, new),
1861          * skip this if we're using tegra_dc_one_shot_worker() */
1862         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1863                 tegra_dc_program_bandwidth(dc, true);
1864
1865         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1866         if (!tegra_dc_windows_are_dirty(dc))
1867                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1868
1869         /* Update the SD brightness */
1870         if (dc->enabled && dc->out->sd_settings) {
1871                 nvsd_updated = nvsd_update_brightness(dc);
1872                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1873                  * V_BLANK_NVSD bit of vblank ref-count. */
1874                 if (nvsd_updated) {
1875                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1876                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1877                 } else {
1878                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1879                 }
1880         }
1881
1882         /* Mask vblank interrupt if ref-count is zero. */
1883         if (!dc->vblank_ref_count)
1884                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1885
1886         mutex_unlock(&dc->lock);
1887
1888         /* Do the actual brightness update outside of the mutex */
1889         if (nvsd_updated && dc->out->sd_settings &&
1890             dc->out->sd_settings->bl_device) {
1891
1892                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1893                 struct backlight_device *bl = platform_get_drvdata(pdev);
1894                 if (bl)
1895                         backlight_update_status(bl);
1896         }
1897 }
1898
1899 static void tegra_dc_one_shot_worker(struct work_struct *work)
1900 {
1901         struct tegra_dc *dc = container_of(
1902                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1903         mutex_lock(&dc->lock);
1904
1905         /* memory client has gone idle */
1906         tegra_dc_clear_bandwidth(dc);
1907
1908         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1909                 tegra_dc_host_suspend(dc);
1910
1911         mutex_unlock(&dc->lock);
1912 }
1913
1914 /* return an arbitrarily large number if count overflow occurs.
1915  * make it a nice base-10 number to show up in stats output */
1916 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1917 {
1918         unsigned count = tegra_dc_readl(dc, reg);
1919         tegra_dc_writel(dc, 0, reg);
1920         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1921 }
1922
1923 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1924 {
1925         u32 val;
1926         int i;
1927
1928         dc->stats.underflows++;
1929         if (dc->underflow_mask & WIN_A_UF_INT) {
1930                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1931                         DC_WINBUF_AD_UFLOW_STATUS);
1932                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1933         }
1934         if (dc->underflow_mask & WIN_B_UF_INT) {
1935                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1936                         DC_WINBUF_BD_UFLOW_STATUS);
1937                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1938         }
1939         if (dc->underflow_mask & WIN_C_UF_INT) {
1940                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1941                         DC_WINBUF_CD_UFLOW_STATUS);
1942                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1943         }
1944
1945         /* Check for any underflow reset conditions */
1946         for (i = 0; i < DC_N_WINDOWS; i++) {
1947                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1948                         dc->windows[i].underflows++;
1949
1950 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1951                         if (dc->windows[i].underflows > 4) {
1952                                 schedule_work(&dc->reset_work);
1953                                 /* reset counter */
1954                                 dc->windows[i].underflows = 0;
1955                                 trace_printk("%s:Reset work scheduled for "
1956                                                 "window %c\n",
1957                                                 dc->ndev->name, (65 + i));
1958                         }
1959 #endif
1960 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1961                         if (dc->windows[i].underflows > 4) {
1962                                 printk("%s:dc in underflow state."
1963                                         " enable UF_LINE_FLUSH to clear up\n",
1964                                         __func__);
1965                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1966                                                 DC_DISP_DISP_MISC_CONTROL);
1967                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1968                                                 DC_CMD_STATE_CONTROL);
1969                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1970                                                 DC_CMD_STATE_CONTROL);
1971
1972                                 tegra_dc_writel(dc, 0,
1973                                                 DC_DISP_DISP_MISC_CONTROL);
1974                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1975                                                 DC_CMD_STATE_CONTROL);
1976                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1977                                                 DC_CMD_STATE_CONTROL);
1978                         }
1979 #endif
1980                 } else {
1981                         dc->windows[i].underflows = 0;
1982                 }
1983         }
1984
1985         /* Clear the underflow mask now that we've checked it. */
1986         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1987         dc->underflow_mask = 0;
1988         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1989         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1990         print_underflow_info(dc);
1991 }
1992
1993 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1994 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1995 {
1996 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1997         u32 val;
1998
1999         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2000         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2001             return true;
2002 #endif
2003         return false;
2004 }
2005
2006 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2007 {
2008         u32 val, i;
2009         u32 completed = 0;
2010         u32 dirty = 0;
2011
2012         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2013         for (i = 0; i < DC_N_WINDOWS; i++) {
2014 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2015                 /* FIXME: this is not needed when the simulator
2016                    clears WIN_x_UPDATE bits as in HW */
2017                 dc->windows[i].dirty = 0;
2018                 completed = 1;
2019 #else
2020                 if (!(val & (WIN_A_ACT_REQ << i))) {
2021                         dc->windows[i].dirty = 0;
2022                         completed = 1;
2023                 } else {
2024                         dirty = 1;
2025                 }
2026 #endif
2027         }
2028
2029         if (!dirty) {
2030                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2031                         tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2032         }
2033
2034         if (completed)
2035                 wake_up(&dc->wq);
2036 }
2037
2038 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2039 {
2040         if (status & V_BLANK_INT) {
2041                 /* Sync up windows. */
2042                 tegra_dc_trigger_windows(dc);
2043
2044                 /* Schedule any additional bottom-half vblank actvities. */
2045                 schedule_work(&dc->vblank_work);
2046         }
2047
2048         if (status & FRAME_END_INT) {
2049                 /* Mark the frame_end as complete. */
2050                 if (!completion_done(&dc->frame_end_complete))
2051                         complete(&dc->frame_end_complete);
2052         }
2053 }
2054
2055 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2056 {
2057         /* Schedule any additional bottom-half vblank actvities. */
2058         if (status & V_BLANK_INT)
2059                 schedule_work(&dc->vblank_work);
2060
2061         if (status & FRAME_END_INT) {
2062                 /* Mark the frame_end as complete. */
2063                 if (!completion_done(&dc->frame_end_complete))
2064                         complete(&dc->frame_end_complete);
2065
2066                 tegra_dc_trigger_windows(dc);
2067         }
2068 }
2069 #endif
2070
2071 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2072 {
2073 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2074         struct tegra_dc *dc = ptr;
2075         unsigned long status;
2076         unsigned long underflow_mask;
2077         u32 val;
2078
2079         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2080                 WARN(1, "IRQ when DC not powered!\n");
2081                 tegra_dc_io_start(dc);
2082                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2083                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2084                 tegra_dc_io_end(dc);
2085                 return IRQ_HANDLED;
2086         }
2087
2088         /* clear all status flags except underflow, save those for the worker */
2089         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2090         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2091         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2092         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2093
2094         /*
2095          * Overlays can get thier internal state corrupted during and underflow
2096          * condition.  The only way to fix this state is to reset the DC.
2097          * if we get 4 consecutive frames with underflows, assume we're
2098          * hosed and reset.
2099          */
2100         underflow_mask = status & ALL_UF_INT;
2101
2102         /* Check underflow */
2103         if (underflow_mask) {
2104                 dc->underflow_mask |= underflow_mask;
2105                 schedule_delayed_work(&dc->underflow_work,
2106                         msecs_to_jiffies(1));
2107         }
2108
2109         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2110                 tegra_dc_one_shot_irq(dc, status);
2111         else
2112                 tegra_dc_continuous_irq(dc, status);
2113
2114         return IRQ_HANDLED;
2115 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2116         return IRQ_NONE;
2117 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2118 }
2119
2120 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2121 {
2122         u32 color_control;
2123
2124         switch (dc->out->depth) {
2125         case 3:
2126                 color_control = BASE_COLOR_SIZE111;
2127                 break;
2128
2129         case 6:
2130                 color_control = BASE_COLOR_SIZE222;
2131                 break;
2132
2133         case 8:
2134                 color_control = BASE_COLOR_SIZE332;
2135                 break;
2136
2137         case 9:
2138                 color_control = BASE_COLOR_SIZE333;
2139                 break;
2140
2141         case 12:
2142                 color_control = BASE_COLOR_SIZE444;
2143                 break;
2144
2145         case 15:
2146                 color_control = BASE_COLOR_SIZE555;
2147                 break;
2148
2149         case 16:
2150                 color_control = BASE_COLOR_SIZE565;
2151                 break;
2152
2153         case 18:
2154                 color_control = BASE_COLOR_SIZE666;
2155                 break;
2156
2157         default:
2158                 color_control = BASE_COLOR_SIZE888;
2159                 break;
2160         }
2161
2162         switch (dc->out->dither) {
2163         case TEGRA_DC_DISABLE_DITHER:
2164                 color_control |= DITHER_CONTROL_DISABLE;
2165                 break;
2166         case TEGRA_DC_ORDERED_DITHER:
2167                 color_control |= DITHER_CONTROL_ORDERED;
2168                 break;
2169         case TEGRA_DC_ERRDIFF_DITHER:
2170                 /* The line buffer for error-diffusion dither is limited
2171                  * to 1280 pixels per line. This limits the maximum
2172                  * horizontal active area size to 1280 pixels when error
2173                  * diffusion is enabled.
2174                  */
2175                 BUG_ON(dc->mode.h_active > 1280);
2176                 color_control |= DITHER_CONTROL_ERRDIFF;
2177                 break;
2178         }
2179
2180         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2181 }
2182
2183 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2184 {
2185         u32 syncpt_id;
2186
2187         switch (dc->ndev->id) {
2188         case 0:
2189                 switch (idx) {
2190                 case 0:
2191                         syncpt_id = NVSYNCPT_DISP0_A;
2192                         break;
2193                 case 1:
2194                         syncpt_id = NVSYNCPT_DISP0_B;
2195                         break;
2196                 case 2:
2197                         syncpt_id = NVSYNCPT_DISP0_C;
2198                         break;
2199                 default:
2200                         BUG();
2201                         break;
2202                 }
2203                 break;
2204         case 1:
2205                 switch (idx) {
2206                 case 0:
2207                         syncpt_id = NVSYNCPT_DISP1_A;
2208                         break;
2209                 case 1:
2210                         syncpt_id = NVSYNCPT_DISP1_B;
2211                         break;
2212                 case 2:
2213                         syncpt_id = NVSYNCPT_DISP1_C;
2214                         break;
2215                 default:
2216                         BUG();
2217                         break;
2218                 }
2219                 break;
2220         default:
2221                 BUG();
2222                 break;
2223         }
2224
2225         return syncpt_id;
2226 }
2227
2228 static int tegra_dc_init(struct tegra_dc *dc)
2229 {
2230         int i;
2231
2232         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2233         if (dc->ndev->id == 0) {
2234                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2235                                       TEGRA_MC_PRIO_MED);
2236                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2237                                       TEGRA_MC_PRIO_MED);
2238                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2239                                       TEGRA_MC_PRIO_MED);
2240                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2241                                       TEGRA_MC_PRIO_MED);
2242                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2243                                       TEGRA_MC_PRIO_HIGH);
2244         } else if (dc->ndev->id == 1) {
2245                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2246                                       TEGRA_MC_PRIO_MED);
2247                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2248                                       TEGRA_MC_PRIO_MED);
2249                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2250                                       TEGRA_MC_PRIO_MED);
2251                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2252                                       TEGRA_MC_PRIO_MED);
2253                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2254                                       TEGRA_MC_PRIO_HIGH);
2255         }
2256         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2257                         DC_CMD_CONT_SYNCPT_VSYNC);
2258         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2259         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2260         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2261         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2262 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2263         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2264 #endif
2265         /* enable interrupts for vblank, frame_end and underflows */
2266         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2267                 DC_CMD_INT_ENABLE);
2268         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2269
2270         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2271
2272         tegra_dc_set_color_control(dc);
2273         for (i = 0; i < DC_N_WINDOWS; i++) {
2274                 struct tegra_dc_win *win = &dc->windows[i];
2275                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2276                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2277                 tegra_dc_set_csc(dc, &win->csc);
2278                 tegra_dc_set_lut(dc, win);
2279                 tegra_dc_set_scaling_filter(dc);
2280         }
2281
2282
2283         for (i = 0; i < dc->n_windows; i++) {
2284                 u32 syncpt = get_syncpt(dc, i);
2285
2286                 dc->syncpt[i].id = syncpt;
2287
2288                 dc->syncpt[i].min = dc->syncpt[i].max =
2289                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2290                                         syncpt);
2291         }
2292
2293         print_mode(dc, &dc->mode, __func__);
2294
2295         if (dc->mode.pclk)
2296                 if (tegra_dc_program_mode(dc, &dc->mode))
2297                         return -EINVAL;
2298
2299         /* Initialize SD AFTER the modeset.
2300            nvsd_init handles the sd_settings = NULL case. */
2301         nvsd_init(dc, dc->out->sd_settings);
2302
2303         return 0;
2304 }
2305
2306 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2307 {
2308         int failed_init = 0;
2309
2310         if (dc->out->enable)
2311                 dc->out->enable();
2312
2313         tegra_dc_setup_clk(dc, dc->clk);
2314         tegra_dc_clk_enable(dc);
2315
2316         /* do not accept interrupts during initialization */
2317         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2318         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2319
2320         enable_dc_irq(dc->irq);
2321
2322         failed_init = tegra_dc_init(dc);
2323         if (failed_init) {
2324                 _tegra_dc_controller_disable(dc);
2325                 return false;
2326         }
2327
2328         if (dc->out_ops && dc->out_ops->enable)
2329                 dc->out_ops->enable(dc);
2330
2331         if (dc->out->postpoweron)
2332                 dc->out->postpoweron();
2333
2334         /* force a full blending update */
2335         dc->blend.z[0] = -1;
2336
2337         tegra_dc_ext_enable(dc->ext);
2338
2339         trace_printk("%s:enable\n", dc->ndev->name);
2340         return true;
2341 }
2342
2343 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2344 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2345 {
2346         bool ret = true;
2347
2348         if (dc->out->enable)
2349                 dc->out->enable();
2350
2351         tegra_dc_setup_clk(dc, dc->clk);
2352         tegra_dc_clk_enable(dc);
2353
2354         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2355                 mutex_lock(&tegra_dcs[1]->lock);
2356                 disable_irq(tegra_dcs[1]->irq);
2357         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2358                 mutex_lock(&tegra_dcs[0]->lock);
2359                 disable_irq(tegra_dcs[0]->irq);
2360         }
2361
2362         msleep(5);
2363         tegra_periph_reset_assert(dc->clk);
2364         msleep(2);
2365 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2366         tegra_periph_reset_deassert(dc->clk);
2367         msleep(1);
2368 #endif
2369
2370         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2371                 enable_dc_irq(tegra_dcs[1]->irq);
2372                 mutex_unlock(&tegra_dcs[1]->lock);
2373         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2374                 enable_dc_irq(tegra_dcs[0]->irq);
2375                 mutex_unlock(&tegra_dcs[0]->lock);
2376         }
2377
2378         enable_dc_irq(dc->irq);
2379
2380         if (tegra_dc_init(dc)) {
2381                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2382                 ret = false;
2383         }
2384
2385         if (dc->out_ops && dc->out_ops->enable)
2386                 dc->out_ops->enable(dc);
2387
2388         if (dc->out->postpoweron)
2389                 dc->out->postpoweron();
2390
2391         /* force a full blending update */
2392         dc->blend.z[0] = -1;
2393
2394         tegra_dc_ext_enable(dc->ext);
2395
2396         if (!ret) {
2397                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2398                 _tegra_dc_controller_disable(dc);
2399         }
2400
2401         trace_printk("%s:reset enable\n", dc->ndev->name);
2402         return ret;
2403 }
2404 #endif
2405
2406 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2407 {
2408         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2409 }
2410
2411 static bool _tegra_dc_enable(struct tegra_dc *dc)
2412 {
2413         if (dc->mode.pclk == 0) {
2414                 switch (dc->out->type) {
2415                 case TEGRA_DC_OUT_HDMI:
2416                 /* DC enable called but no videomode is loaded.
2417                      Check if HDMI is connected, then set fallback mdoe */
2418                 if (tegra_dc_hpd(dc)) {
2419                         if (_tegra_dc_set_default_videomode(dc))
2420                                 return false;
2421                 } else
2422                         return false;
2423
2424                 break;
2425
2426                 /* Do nothing for other outputs for now */
2427                 case TEGRA_DC_OUT_RGB:
2428
2429                 case TEGRA_DC_OUT_DSI:
2430
2431                 default:
2432                         return false;
2433                 }
2434         }
2435
2436         if (!dc->out)
2437                 return false;
2438
2439         tegra_dc_io_start(dc);
2440
2441         return _tegra_dc_controller_enable(dc);
2442 }
2443
2444 void tegra_dc_enable(struct tegra_dc *dc)
2445 {
2446         mutex_lock(&dc->lock);
2447
2448         if (!dc->enabled)
2449                 dc->enabled = _tegra_dc_enable(dc);
2450
2451         mutex_unlock(&dc->lock);
2452         print_mode_info(dc, dc->mode);
2453 }
2454
2455 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2456 {
2457         unsigned i;
2458
2459         if (dc->out && dc->out->prepoweroff)
2460                 dc->out->prepoweroff();
2461
2462         if (dc->out_ops && dc->out_ops->disable)
2463                 dc->out_ops->disable(dc);
2464
2465         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2466         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2467         disable_irq(dc->irq);
2468
2469         tegra_dc_clear_bandwidth(dc);
2470         tegra_dc_clk_disable(dc);
2471
2472         if (dc->out && dc->out->disable)
2473                 dc->out->disable();
2474
2475         for (i = 0; i < dc->n_windows; i++) {
2476                 struct tegra_dc_win *w = &dc->windows[i];
2477
2478                 /* reset window bandwidth */
2479                 w->bandwidth = 0;
2480                 w->new_bandwidth = 0;
2481
2482                 /* disable windows */
2483                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2484
2485                 /* flush any pending syncpt waits */
2486                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2487                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2488                                 dc->syncpt[i].id);
2489                         dc->syncpt[i].min++;
2490                         nvhost_syncpt_cpu_incr(
2491                                 &nvhost_get_host(dc->ndev)->syncpt,
2492                                 dc->syncpt[i].id);
2493                 }
2494         }
2495         trace_printk("%s:disabled\n", dc->ndev->name);
2496 }
2497
2498 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2499 {
2500 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2501         u32 val;
2502         if (dc->enabled)  {
2503                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2504                 if (enable)
2505                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2506                 else
2507                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2508                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2509         }
2510 #endif
2511 }
2512
2513 bool tegra_dc_stats_get(struct tegra_dc *dc)
2514 {
2515 #if 0 /* right now it is always enabled */
2516         u32 val;
2517         bool res;
2518
2519         if (dc->enabled)  {
2520                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2521                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2522         } else {
2523                 res = false;
2524         }
2525
2526         return res;
2527 #endif
2528         return true;
2529 }
2530
2531 /* make the screen blank by disabling all windows */
2532 void tegra_dc_blank(struct tegra_dc *dc)
2533 {
2534         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2535         unsigned i;
2536
2537         for (i = 0; i < DC_N_WINDOWS; i++) {
2538                 dcwins[i] = tegra_dc_get_window(dc, i);
2539                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2540         }
2541
2542         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2543         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2544 }
2545
2546 static void _tegra_dc_disable(struct tegra_dc *dc)
2547 {
2548         _tegra_dc_controller_disable(dc);
2549         tegra_dc_io_end(dc);
2550 }
2551
2552 void tegra_dc_disable(struct tegra_dc *dc)
2553 {
2554         tegra_dc_ext_disable(dc->ext);
2555
2556         /* it's important that new underflow work isn't scheduled before the
2557          * lock is acquired. */
2558         cancel_delayed_work_sync(&dc->underflow_work);
2559         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2560                 mutex_lock(&dc->one_shot_lock);
2561                 cancel_delayed_work_sync(&dc->one_shot_work);
2562         }
2563
2564         mutex_lock(&dc->lock);
2565
2566         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2567                 tegra_dc_host_resume(dc);
2568
2569         if (dc->enabled) {
2570                 dc->enabled = false;
2571
2572                 if (!dc->suspended)
2573                         _tegra_dc_disable(dc);
2574         }
2575
2576 #ifdef CONFIG_SWITCH
2577         switch_set_state(&dc->modeset_switch, 0);
2578 #endif
2579
2580         mutex_unlock(&dc->lock);
2581         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2582                 mutex_unlock(&dc->one_shot_lock);
2583         print_mode_info(dc, dc->mode);
2584 }
2585
2586 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2587 static void tegra_dc_reset_worker(struct work_struct *work)
2588 {
2589         struct tegra_dc *dc =
2590                 container_of(work, struct tegra_dc, reset_work);
2591
2592         unsigned long val = 0;
2593
2594         mutex_lock(&shared_lock);
2595
2596         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2597
2598         tegra_dc_ext_disable(dc->ext);
2599
2600         mutex_lock(&dc->lock);
2601
2602         if (dc->enabled == false)
2603                 goto unlock;
2604
2605         dc->enabled = false;
2606
2607         /*
2608          * off host read bus
2609          */
2610         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2611         val &= ~(0x00000100);
2612         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2613
2614         /*
2615          * set DC to STOP mode
2616          */
2617         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2618
2619         msleep(10);
2620
2621         _tegra_dc_controller_disable(dc);
2622
2623         /* _tegra_dc_controller_reset_enable deasserts reset */
2624         _tegra_dc_controller_reset_enable(dc);
2625
2626         dc->enabled = true;
2627
2628         /* reopen host read bus */
2629         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2630         val &= ~(0x00000100);
2631         val |= 0x100;
2632         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2633
2634 unlock:
2635         mutex_unlock(&dc->lock);
2636         mutex_unlock(&shared_lock);
2637         trace_printk("%s:reset complete\n", dc->ndev->name);
2638 }
2639 #endif
2640
2641 static void tegra_dc_underflow_worker(struct work_struct *work)
2642 {
2643         struct tegra_dc *dc = container_of(
2644                 to_delayed_work(work), struct tegra_dc, underflow_work);
2645
2646         mutex_lock(&dc->lock);
2647         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2648                 tegra_dc_host_resume(dc);
2649
2650         if (dc->enabled) {
2651                 tegra_dc_underflow_handler(dc);
2652         }
2653         mutex_unlock(&dc->lock);
2654 }
2655
2656 #ifdef CONFIG_SWITCH
2657 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2658 {
2659         struct tegra_dc *dc =
2660                 container_of(sdev, struct tegra_dc, modeset_switch);
2661
2662         if (!sdev->state)
2663                 return sprintf(buf, "offline\n");
2664
2665         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2666 }
2667 #endif
2668
2669 static int tegra_dc_probe(struct nvhost_device *ndev,
2670         struct nvhost_device_id *id_table)
2671 {
2672         struct tegra_dc *dc;
2673         struct clk *clk;
2674         struct clk *emc_clk;
2675         struct resource *res;
2676         struct resource *base_res;
2677         struct resource *fb_mem = NULL;
2678         int ret = 0;
2679         void __iomem *base;
2680         int irq;
2681         int i;
2682
2683         if (!ndev->dev.platform_data) {
2684                 dev_err(&ndev->dev, "no platform data\n");
2685                 return -ENOENT;
2686         }
2687
2688         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2689         if (!dc) {
2690                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2691                 return -ENOMEM;
2692         }
2693
2694         irq = nvhost_get_irq_byname(ndev, "irq");
2695         if (irq <= 0) {
2696                 dev_err(&ndev->dev, "no irq\n");
2697                 ret = -ENOENT;
2698                 goto err_free;
2699         }
2700
2701         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2702         if (!res) {
2703                 dev_err(&ndev->dev, "no mem resource\n");
2704                 ret = -ENOENT;
2705                 goto err_free;
2706         }
2707
2708         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2709         if (!base_res) {
2710                 dev_err(&ndev->dev, "request_mem_region failed\n");
2711                 ret = -EBUSY;
2712                 goto err_free;
2713         }
2714
2715         base = ioremap(res->start, resource_size(res));
2716         if (!base) {
2717                 dev_err(&ndev->dev, "registers can't be mapped\n");
2718                 ret = -EBUSY;
2719                 goto err_release_resource_reg;
2720         }
2721
2722         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2723
2724         clk = clk_get(&ndev->dev, NULL);
2725         if (IS_ERR_OR_NULL(clk)) {
2726                 dev_err(&ndev->dev, "can't get clock\n");
2727                 ret = -ENOENT;
2728                 goto err_iounmap_reg;
2729         }
2730
2731         emc_clk = clk_get(&ndev->dev, "emc");
2732         if (IS_ERR_OR_NULL(emc_clk)) {
2733                 dev_err(&ndev->dev, "can't get emc clock\n");
2734                 ret = -ENOENT;
2735                 goto err_put_clk;
2736         }
2737
2738         dc->clk = clk;
2739         dc->emc_clk = emc_clk;
2740         dc->shift_clk_div = 1;
2741         /* Initialize one shot work delay, it will be assigned by dsi
2742          * according to refresh rate later. */
2743         dc->one_shot_delay_ms = 40;
2744
2745         dc->base_res = base_res;
2746         dc->base = base;
2747         dc->irq = irq;
2748         dc->ndev = ndev;
2749         dc->pdata = ndev->dev.platform_data;
2750
2751         /*
2752          * The emc is a shared clock, it will be set based on
2753          * the requirements for each user on the bus.
2754          */
2755         dc->emc_clk_rate = 0;
2756
2757         mutex_init(&dc->lock);
2758         mutex_init(&dc->one_shot_lock);
2759         init_completion(&dc->frame_end_complete);
2760         init_waitqueue_head(&dc->wq);
2761 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2762         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2763 #endif
2764         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2765         dc->vblank_ref_count = 0;
2766         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2767         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2768
2769         tegra_dc_init_lut_defaults(&dc->fb_lut);
2770
2771         dc->n_windows = DC_N_WINDOWS;
2772         for (i = 0; i < dc->n_windows; i++) {
2773                 struct tegra_dc_win *win = &dc->windows[i];
2774                 win->idx = i;
2775                 win->dc = dc;
2776                 tegra_dc_init_csc_defaults(&win->csc);
2777                 tegra_dc_init_lut_defaults(&win->lut);
2778         }
2779
2780         ret = tegra_dc_set(dc, ndev->id);
2781         if (ret < 0) {
2782                 dev_err(&ndev->dev, "can't add dc\n");
2783                 goto err_free_irq;
2784         }
2785
2786         nvhost_set_drvdata(ndev, dc);
2787
2788 #ifdef CONFIG_SWITCH
2789         dc->modeset_switch.name = dev_name(&ndev->dev);
2790         dc->modeset_switch.state = 0;
2791         dc->modeset_switch.print_state = switch_modeset_print_mode;
2792         switch_dev_register(&dc->modeset_switch);
2793 #endif
2794
2795         tegra_dc_feature_register(dc);
2796
2797         if (dc->pdata->default_out)
2798                 tegra_dc_set_out(dc, dc->pdata->default_out);
2799         else
2800                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2801
2802         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2803                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2804
2805         dc->ext = tegra_dc_ext_register(ndev, dc);
2806         if (IS_ERR_OR_NULL(dc->ext)) {
2807                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2808                 dc->ext = NULL;
2809         }
2810
2811         mutex_lock(&dc->lock);
2812         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2813                 dc->enabled = _tegra_dc_enable(dc);
2814         mutex_unlock(&dc->lock);
2815
2816         /* interrupt handler must be registered before tegra_fb_register() */
2817         if (request_irq(irq, tegra_dc_irq, 0,
2818                         dev_name(&ndev->dev), dc)) {
2819                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2820                 ret = -EBUSY;
2821                 goto err_put_emc_clk;
2822         }
2823
2824         tegra_dc_create_debugfs(dc);
2825
2826         dev_info(&ndev->dev, "probed\n");
2827
2828         if (dc->pdata->fb) {
2829                 if (dc->pdata->fb->bits_per_pixel == -1) {
2830                         unsigned long fmt;
2831                         tegra_dc_writel(dc,
2832                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2833                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2834
2835                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2836                         dc->pdata->fb->bits_per_pixel =
2837                                 tegra_dc_fmt_bpp(fmt);
2838                 }
2839
2840                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2841                 if (IS_ERR_OR_NULL(dc->fb))
2842                         dc->fb = NULL;
2843         }
2844
2845         if (dc->out && dc->out->hotplug_init)
2846                 dc->out->hotplug_init();
2847
2848         if (dc->out_ops && dc->out_ops->detect)
2849                 dc->out_ops->detect(dc);
2850         else
2851                 dc->connected = true;
2852
2853         tegra_dc_create_sysfs(&dc->ndev->dev);
2854
2855         return 0;
2856
2857 err_free_irq:
2858         free_irq(irq, dc);
2859 err_put_emc_clk:
2860         clk_put(emc_clk);
2861 err_put_clk:
2862         clk_put(clk);
2863 err_iounmap_reg:
2864         iounmap(base);
2865         if (fb_mem)
2866                 release_resource(fb_mem);
2867 err_release_resource_reg:
2868         release_resource(base_res);
2869 err_free:
2870         kfree(dc);
2871
2872         return ret;
2873 }
2874
2875 static int tegra_dc_remove(struct nvhost_device *ndev)
2876 {
2877         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2878
2879         tegra_dc_remove_sysfs(&dc->ndev->dev);
2880         tegra_dc_remove_debugfs(dc);
2881
2882         if (dc->fb) {
2883                 tegra_fb_unregister(dc->fb);
2884                 if (dc->fb_mem)
2885                         release_resource(dc->fb_mem);
2886         }
2887
2888         tegra_dc_ext_disable(dc->ext);
2889
2890         if (dc->ext)
2891                 tegra_dc_ext_unregister(dc->ext);
2892
2893         if (dc->enabled)
2894                 _tegra_dc_disable(dc);
2895
2896 #ifdef CONFIG_SWITCH
2897         switch_dev_unregister(&dc->modeset_switch);
2898 #endif
2899         free_irq(dc->irq, dc);
2900         clk_put(dc->emc_clk);
2901         clk_put(dc->clk);
2902         iounmap(dc->base);
2903         if (dc->fb_mem)
2904                 release_resource(dc->base_res);
2905         kfree(dc);
2906         tegra_dc_set(NULL, ndev->id);
2907         return 0;
2908 }
2909
2910 #ifdef CONFIG_PM
2911 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2912 {
2913         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2914
2915         trace_printk("%s:suspend\n", dc->ndev->name);
2916         dev_info(&ndev->dev, "suspend\n");
2917
2918         tegra_dc_ext_disable(dc->ext);
2919
2920         mutex_lock(&dc->lock);
2921
2922         if (dc->out_ops && dc->out_ops->suspend)
2923                 dc->out_ops->suspend(dc);
2924
2925         if (dc->enabled) {
2926                 _tegra_dc_disable(dc);
2927
2928                 dc->suspended = true;
2929         }
2930
2931         if (dc->out && dc->out->postsuspend) {
2932                 dc->out->postsuspend();
2933                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2934                         /*
2935                          * avoid resume event due to voltage falling
2936                          */
2937                         msleep(100);
2938         }
2939
2940         mutex_unlock(&dc->lock);
2941
2942         return 0;
2943 }
2944
2945 static int tegra_dc_resume(struct nvhost_device *ndev)
2946 {
2947         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2948
2949         trace_printk("%s:resume\n", dc->ndev->name);
2950         dev_info(&ndev->dev, "resume\n");
2951
2952         mutex_lock(&dc->lock);
2953         dc->suspended = false;
2954
2955         if (dc->enabled)
2956                 _tegra_dc_enable(dc);
2957
2958         if (dc->out && dc->out->hotplug_init)
2959                 dc->out->hotplug_init();
2960
2961         if (dc->out_ops && dc->out_ops->resume)
2962                 dc->out_ops->resume(dc);
2963         mutex_unlock(&dc->lock);
2964
2965         return 0;
2966 }
2967
2968 #endif /* CONFIG_PM */
2969
2970 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2971 {
2972         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2973
2974         if (!dc || !dc->enabled)
2975                 return;
2976
2977         tegra_dc_blank(dc);
2978         tegra_dc_disable(dc);
2979 }
2980
2981 extern int suspend_set(const char *val, struct kernel_param *kp)
2982 {
2983         if (!strcmp(val, "dump"))
2984                 dump_regs(tegra_dcs[0]);
2985 #ifdef CONFIG_PM
2986         else if (!strcmp(val, "suspend"))
2987                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2988         else if (!strcmp(val, "resume"))
2989                 tegra_dc_resume(tegra_dcs[0]->ndev);
2990 #endif
2991
2992         return 0;
2993 }
2994
2995 extern int suspend_get(char *buffer, struct kernel_param *kp)
2996 {
2997         return 0;
2998 }
2999
3000 int suspend;
3001
3002 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3003
3004 struct nvhost_driver tegra_dc_driver = {
3005         .driver = {
3006                 .name = "tegradc",
3007                 .owner = THIS_MODULE,
3008         },
3009         .probe = tegra_dc_probe,
3010         .remove = tegra_dc_remove,
3011 #ifdef CONFIG_PM
3012         .suspend = tegra_dc_suspend,
3013         .resume = tegra_dc_resume,
3014 #endif
3015         .shutdown = tegra_dc_shutdown,
3016 };
3017
3018 static int __init tegra_dc_module_init(void)
3019 {
3020         int ret = tegra_dc_ext_module_init();
3021         if (ret)
3022                 return ret;
3023         return nvhost_driver_register(&tegra_dc_driver);
3024 }
3025
3026 static void __exit tegra_dc_module_exit(void)
3027 {
3028         nvhost_driver_unregister(&tegra_dc_driver);
3029         tegra_dc_ext_module_exit();
3030 }
3031
3032 module_exit(tegra_dc_module_exit);
3033 module_init(tegra_dc_module_init);