7161d8bf16944734dfcb1c941ad3dd44fb4725bc
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "nvsd.h"
53
54 #define TEGRA_CRC_LATCHED_DELAY         34
55
56 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
57 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
58
59 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
60 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
61 #else
62 /* ignore underflows when on simulation and fpga platform */
63 #define ALL_UF_INT (0)
64 #endif
65
66 static int no_vsync;
67 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
68         .refresh = 60,
69         .xres = 640,
70         .yres = 480,
71         .pixclock = KHZ2PICOS(25200),
72         .hsync_len = 96,        /* h_sync_width */
73         .vsync_len = 2,         /* v_sync_width */
74         .left_margin = 48,      /* h_back_porch */
75         .upper_margin = 33,     /* v_back_porch */
76         .right_margin = 16,     /* h_front_porch */
77         .lower_margin = 10,     /* v_front_porch */
78         .vmode = 0,
79         .sync = 0,
80 };
81
82 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
83
84 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
85
86 static int use_dynamic_emc = 1;
87
88 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
89
90 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
91
92 DEFINE_MUTEX(tegra_dc_lock);
93 DEFINE_MUTEX(shared_lock);
94
95 static const struct {
96         bool h;
97         bool v;
98 } can_filter[] = {
99         /* Window A has no filtering */
100         { false, false },
101         /* Window B has both H and V filtering */
102         { true,  true  },
103         /* Window C has only H filtering */
104         { false, true  },
105 };
106 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
107 {
108         return can_filter[win->idx].v &&
109                 win->h.full != dfixed_const(win->out_h);
110 }
111 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
112 {
113         return can_filter[win->idx].h &&
114                 win->w.full != dfixed_const(win->out_w);
115 }
116
117 static inline int tegra_dc_fmt_bpp(int fmt)
118 {
119         switch (fmt) {
120         case TEGRA_WIN_FMT_P1:
121                 return 1;
122
123         case TEGRA_WIN_FMT_P2:
124                 return 2;
125
126         case TEGRA_WIN_FMT_P4:
127                 return 4;
128
129         case TEGRA_WIN_FMT_P8:
130                 return 8;
131
132         case TEGRA_WIN_FMT_B4G4R4A4:
133         case TEGRA_WIN_FMT_B5G5R5A:
134         case TEGRA_WIN_FMT_B5G6R5:
135         case TEGRA_WIN_FMT_AB5G5R5:
136                 return 16;
137
138         case TEGRA_WIN_FMT_B8G8R8A8:
139         case TEGRA_WIN_FMT_R8G8B8A8:
140         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
141         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
142                 return 32;
143
144         /* for planar formats, size of the Y plane, 8bit */
145         case TEGRA_WIN_FMT_YCbCr420P:
146         case TEGRA_WIN_FMT_YUV420P:
147         case TEGRA_WIN_FMT_YCbCr422P:
148         case TEGRA_WIN_FMT_YUV422P:
149         case TEGRA_WIN_FMT_YCbCr422R:
150         case TEGRA_WIN_FMT_YUV422R:
151         case TEGRA_WIN_FMT_YCbCr422RA:
152         case TEGRA_WIN_FMT_YUV422RA:
153                 return 8;
154
155         /* YUYV packed into 32-bits */
156         case TEGRA_WIN_FMT_YCbCr422:
157         case TEGRA_WIN_FMT_YUV422:
158                 return 16;
159         }
160         return 0;
161 }
162
163 static inline bool tegra_dc_is_yuv(int fmt)
164 {
165         switch (fmt) {
166         case TEGRA_WIN_FMT_YUV420P:
167         case TEGRA_WIN_FMT_YCbCr420P:
168         case TEGRA_WIN_FMT_YCbCr422P:
169         case TEGRA_WIN_FMT_YUV422P:
170         case TEGRA_WIN_FMT_YCbCr422:
171         case TEGRA_WIN_FMT_YUV422:
172         case TEGRA_WIN_FMT_YCbCr422R:
173         case TEGRA_WIN_FMT_YUV422R:
174         case TEGRA_WIN_FMT_YCbCr422RA:
175         case TEGRA_WIN_FMT_YUV422RA:
176                 return true;
177         }
178         return false;
179 }
180
181 static inline bool tegra_dc_is_yuv_planar(int fmt)
182 {
183         switch (fmt) {
184         case TEGRA_WIN_FMT_YUV420P:
185         case TEGRA_WIN_FMT_YCbCr420P:
186         case TEGRA_WIN_FMT_YCbCr422P:
187         case TEGRA_WIN_FMT_YUV422P:
188         case TEGRA_WIN_FMT_YCbCr422R:
189         case TEGRA_WIN_FMT_YUV422R:
190         case TEGRA_WIN_FMT_YCbCr422RA:
191         case TEGRA_WIN_FMT_YUV422RA:
192                 return true;
193         }
194         return false;
195 }
196
197 #define DUMP_REG(a) do {                        \
198         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
199                  #a, a, tegra_dc_readl(dc, a));               \
200         print(data, buff);                                    \
201         } while (0)
202
203 #define print_mode_info(dc, mode) do {                        \
204         trace_printk("%s:Mode settings: "                              \
205                         "ref_to_sync: H = %d V = %d, "                  \
206                         "sync_width: H = %d V = %d, "                   \
207                         "back_porch: H = %d V = %d, "                   \
208                         "active: H = %d V = %d, "                       \
209                         "front_porch: H = %d V = %d, "                  \
210                         "pclk = %d, stereo mode = %d\n",                \
211                         dc->ndev->name,                                 \
212                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
213                         mode.h_sync_width, mode.v_sync_width,           \
214                         mode.h_back_porch, mode.v_back_porch,           \
215                         mode.h_active, mode.v_active,                   \
216                         mode.h_front_porch, mode.v_front_porch,         \
217                         mode.pclk, mode.stereo_mode);                   \
218         } while (0)
219
220 #define print_underflow_info(dc) do {                 \
221         trace_printk("%s:Underflow stats: underflows : %llu, "      \
222                         "undeflows_a : %llu, "                          \
223                         "underflows_b : %llu, "                         \
224                         "underflows_c : %llu\n",                        \
225                         dc->ndev->name,                                 \
226                         dc->stats.underflows,                           \
227                         dc->stats.underflows_a, dc->stats.underflows_b, \
228                         dc->stats.underflows_c);                        \
229         } while (0)
230
231 static void _dump_regs(struct tegra_dc *dc, void *data,
232                        void (* print)(void *data, const char *str))
233 {
234         int i;
235         char buff[256];
236
237         tegra_dc_io_start(dc);
238         clk_enable(dc->clk);
239
240         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
241         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
242         DUMP_REG(DC_CMD_SIGNAL_RAISE);
243         DUMP_REG(DC_CMD_INT_STATUS);
244         DUMP_REG(DC_CMD_INT_MASK);
245         DUMP_REG(DC_CMD_INT_ENABLE);
246         DUMP_REG(DC_CMD_INT_TYPE);
247         DUMP_REG(DC_CMD_INT_POLARITY);
248         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
249         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
250         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
251         DUMP_REG(DC_CMD_STATE_ACCESS);
252         DUMP_REG(DC_CMD_STATE_CONTROL);
253         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
254         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
255
256         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
257         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
258         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
259         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
260         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
261         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
262         DUMP_REG(DC_DISP_REF_TO_SYNC);
263         DUMP_REG(DC_DISP_SYNC_WIDTH);
264         DUMP_REG(DC_DISP_BACK_PORCH);
265         DUMP_REG(DC_DISP_DISP_ACTIVE);
266         DUMP_REG(DC_DISP_FRONT_PORCH);
267         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
268         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
269         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
270         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
271         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
272         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
273         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
274         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
275         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
276         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
277         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
278         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
279         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
280         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
281         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
282         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
283         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
284         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
285         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
286         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
287         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
288         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
289         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
290         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
291         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
292         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
293         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
294         DUMP_REG(DC_DISP_M0_CONTROL);
295         DUMP_REG(DC_DISP_M1_CONTROL);
296         DUMP_REG(DC_DISP_DI_CONTROL);
297         DUMP_REG(DC_DISP_PP_CONTROL);
298         DUMP_REG(DC_DISP_PP_SELECT_A);
299         DUMP_REG(DC_DISP_PP_SELECT_B);
300         DUMP_REG(DC_DISP_PP_SELECT_C);
301         DUMP_REG(DC_DISP_PP_SELECT_D);
302         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
303         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
304         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
305         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
306         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
307         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
308         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
309         DUMP_REG(DC_DISP_BORDER_COLOR);
310         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
311         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
312         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
313         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
314         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
315         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
316         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
317         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
318         DUMP_REG(DC_DISP_CURSOR_POSITION);
319         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
320         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
321         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
322         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
323         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
324         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
325         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
326         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
327         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
328         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
329         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
330         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
331         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
332
333
334         for (i = 0; i < 3; i++) {
335                 print(data, "\n");
336                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
337                 print(data, buff);
338
339                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
340                                 DC_CMD_DISPLAY_WINDOW_HEADER);
341                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
342                 DUMP_REG(DC_WIN_WIN_OPTIONS);
343                 DUMP_REG(DC_WIN_BYTE_SWAP);
344                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
345                 DUMP_REG(DC_WIN_COLOR_DEPTH);
346                 DUMP_REG(DC_WIN_POSITION);
347                 DUMP_REG(DC_WIN_SIZE);
348                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
349                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
350                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
351                 DUMP_REG(DC_WIN_DDA_INCREMENT);
352                 DUMP_REG(DC_WIN_LINE_STRIDE);
353                 DUMP_REG(DC_WIN_BUF_STRIDE);
354                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
355                 DUMP_REG(DC_WIN_BLEND_NOKEY);
356                 DUMP_REG(DC_WIN_BLEND_1WIN);
357                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
358                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
359                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
360                 DUMP_REG(DC_WINBUF_START_ADDR);
361                 DUMP_REG(DC_WINBUF_START_ADDR_U);
362                 DUMP_REG(DC_WINBUF_START_ADDR_V);
363                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
364                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
365                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
366                 DUMP_REG(DC_WIN_CSC_YOF);
367                 DUMP_REG(DC_WIN_CSC_KYRGB);
368                 DUMP_REG(DC_WIN_CSC_KUR);
369                 DUMP_REG(DC_WIN_CSC_KVR);
370                 DUMP_REG(DC_WIN_CSC_KUG);
371                 DUMP_REG(DC_WIN_CSC_KVG);
372                 DUMP_REG(DC_WIN_CSC_KUB);
373                 DUMP_REG(DC_WIN_CSC_KVB);
374         }
375
376         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
377         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
378         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
379         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
380         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
381         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
382         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
383         DUMP_REG(DC_DISP_M1_CONTROL);
384         DUMP_REG(DC_COM_PM1_CONTROL);
385         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
386         DUMP_REG(DC_DISP_SD_CONTROL);
387
388         clk_disable(dc->clk);
389         tegra_dc_io_end(dc);
390 }
391
392 #undef DUMP_REG
393
394 #ifdef DEBUG
395 static void dump_regs_print(void *data, const char *str)
396 {
397         struct tegra_dc *dc = data;
398         dev_dbg(&dc->ndev->dev, "%s", str);
399 }
400
401 static void dump_regs(struct tegra_dc *dc)
402 {
403         _dump_regs(dc, dc, dump_regs_print);
404 }
405 #else /* !DEBUG */
406
407 static void dump_regs(struct tegra_dc *dc) {}
408
409 #endif /* DEBUG */
410
411 #ifdef CONFIG_DEBUG_FS
412
413 static void dbg_regs_print(void *data, const char *str)
414 {
415         struct seq_file *s = data;
416
417         seq_printf(s, "%s", str);
418 }
419
420 #undef DUMP_REG
421
422 static int dbg_dc_show(struct seq_file *s, void *unused)
423 {
424         struct tegra_dc *dc = s->private;
425
426         _dump_regs(dc, s, dbg_regs_print);
427
428         return 0;
429 }
430
431
432 static int dbg_dc_open(struct inode *inode, struct file *file)
433 {
434         return single_open(file, dbg_dc_show, inode->i_private);
435 }
436
437 static const struct file_operations regs_fops = {
438         .open           = dbg_dc_open,
439         .read           = seq_read,
440         .llseek         = seq_lseek,
441         .release        = single_release,
442 };
443
444 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
445 {
446         struct tegra_dc *dc = s->private;
447         struct tegra_dc_mode *m;
448
449         mutex_lock(&dc->lock);
450         m = &dc->mode;
451         seq_printf(s,
452                 "pclk: %d\n"
453                 "h_ref_to_sync: %d\n"
454                 "v_ref_to_sync: %d\n"
455                 "h_sync_width: %d\n"
456                 "v_sync_width: %d\n"
457                 "h_back_porch: %d\n"
458                 "v_back_porch: %d\n"
459                 "h_active: %d\n"
460                 "v_active: %d\n"
461                 "h_front_porch: %d\n"
462                 "v_front_porch: %d\n"
463                 "stereo_mode: %d\n",
464                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
465                 m->h_sync_width, m->v_sync_width,
466                 m->h_back_porch, m->v_back_porch,
467                 m->h_active, m->v_active,
468                 m->h_front_porch, m->v_front_porch,
469                 m->stereo_mode);
470         mutex_unlock(&dc->lock);
471         return 0;
472 }
473
474 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
475 {
476         return single_open(file, dbg_dc_mode_show, inode->i_private);
477 }
478
479 static const struct file_operations mode_fops = {
480         .open           = dbg_dc_mode_open,
481         .read           = seq_read,
482         .llseek         = seq_lseek,
483         .release        = single_release,
484 };
485
486 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
487 {
488         struct tegra_dc *dc = s->private;
489
490         mutex_lock(&dc->lock);
491         seq_printf(s,
492                 "underflows: %llu\n"
493                 "underflows_a: %llu\n"
494                 "underflows_b: %llu\n"
495                 "underflows_c: %llu\n",
496                 dc->stats.underflows,
497                 dc->stats.underflows_a,
498                 dc->stats.underflows_b,
499                 dc->stats.underflows_c);
500         mutex_unlock(&dc->lock);
501
502         return 0;
503 }
504
505 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
506 {
507         return single_open(file, dbg_dc_stats_show, inode->i_private);
508 }
509
510 static const struct file_operations stats_fops = {
511         .open           = dbg_dc_stats_open,
512         .read           = seq_read,
513         .llseek         = seq_lseek,
514         .release        = single_release,
515 };
516
517 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
518 {
519         if (dc->debugdir)
520                 debugfs_remove_recursive(dc->debugdir);
521         dc->debugdir = NULL;
522 }
523
524 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
525 {
526         struct dentry *retval;
527
528         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
529         if (!dc->debugdir)
530                 goto remove_out;
531
532         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
533                 &regs_fops);
534         if (!retval)
535                 goto remove_out;
536
537         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
538                 &mode_fops);
539         if (!retval)
540                 goto remove_out;
541
542         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
543                 &stats_fops);
544         if (!retval)
545                 goto remove_out;
546
547         return;
548 remove_out:
549         dev_err(&dc->ndev->dev, "could not create debugfs\n");
550         tegra_dc_remove_debugfs(dc);
551 }
552
553 #else /* !CONFIG_DEBUGFS */
554 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
555 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
556 #endif /* CONFIG_DEBUGFS */
557
558 static int tegra_dc_set(struct tegra_dc *dc, int index)
559 {
560         int ret = 0;
561
562         mutex_lock(&tegra_dc_lock);
563         if (index >= TEGRA_MAX_DC) {
564                 ret = -EINVAL;
565                 goto out;
566         }
567
568         if (dc != NULL && tegra_dcs[index] != NULL) {
569                 ret = -EBUSY;
570                 goto out;
571         }
572
573         tegra_dcs[index] = dc;
574
575 out:
576         mutex_unlock(&tegra_dc_lock);
577
578         return ret;
579 }
580
581 static unsigned int tegra_dc_has_multiple_dc(void)
582 {
583         unsigned int idx;
584         unsigned int cnt = 0;
585         struct tegra_dc *dc;
586
587         mutex_lock(&tegra_dc_lock);
588         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
589                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
590         mutex_unlock(&tegra_dc_lock);
591
592         return (cnt > 1);
593 }
594
595 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
596 {
597         if (idx < TEGRA_MAX_DC)
598                 return tegra_dcs[idx];
599         else
600                 return NULL;
601 }
602 EXPORT_SYMBOL(tegra_dc_get_dc);
603
604 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
605 {
606         if (win >= dc->n_windows)
607                 return NULL;
608
609         return &dc->windows[win];
610 }
611 EXPORT_SYMBOL(tegra_dc_get_window);
612
613 static int get_topmost_window(u32 *depths, unsigned long *wins)
614 {
615         int idx, best = -1;
616
617         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
618                 if (best == -1 || depths[idx] < depths[best])
619                         best = idx;
620         }
621         clear_bit(best, wins);
622         return best;
623 }
624
625 bool tegra_dc_get_connected(struct tegra_dc *dc)
626 {
627         return dc->connected;
628 }
629 EXPORT_SYMBOL(tegra_dc_get_connected);
630
631 static u32 blend_topwin(u32 flags)
632 {
633         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
634                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
635         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
636                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
637         else
638                 return BLEND(NOKEY, FIX, 0xff, 0xff);
639 }
640
641 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
642 {
643         int other;
644
645         for (other = 0; other < DC_N_WINDOWS; other++) {
646                 if (other != idx && (xy-- == 0))
647                         break;
648         }
649         if (BIT(other) & behind_mask)
650                 return blend_topwin(flags[idx]);
651         else if (flags[other])
652                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
653         else
654                 return BLEND(NOKEY, FIX, 0x00, 0x00);
655 }
656
657 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
658 {
659         unsigned long infront_mask;
660         int first;
661
662         infront_mask = ~(behind_mask | BIT(idx));
663         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
664         first = ffs(infront_mask) - 1;
665
666         if (!infront_mask)
667                 return blend_topwin(flags[idx]);
668         else if (behind_mask && first != -1 && flags[first])
669                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
670         else
671                 return BLEND(NOKEY, FIX, 0x0, 0x0);
672 }
673
674 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
675 {
676         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
677
678         while (mask) {
679                 int idx = get_topmost_window(blend->z, &mask);
680
681                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
682                                 DC_CMD_DISPLAY_WINDOW_HEADER);
683                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
684                                 DC_WIN_BLEND_NOKEY);
685                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
686                                 DC_WIN_BLEND_1WIN);
687                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
688                                 DC_WIN_BLEND_2WIN_X);
689                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
690                                 DC_WIN_BLEND_2WIN_Y);
691                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
692                                 DC_WIN_BLEND_3WIN_XY);
693         }
694 }
695
696 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
697 {
698         csc->yof   = 0x00f0;
699         csc->kyrgb = 0x012a;
700         csc->kur   = 0x0000;
701         csc->kvr   = 0x0198;
702         csc->kug   = 0x039b;
703         csc->kvg   = 0x032f;
704         csc->kub   = 0x0204;
705         csc->kvb   = 0x0000;
706 }
707
708 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
709 {
710         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
711         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
712         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
713         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
714         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
715         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
716         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
717         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
718 }
719
720 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
721 {
722         mutex_lock(&dc->lock);
723
724         if (!dc->enabled) {
725                 mutex_unlock(&dc->lock);
726                 return -EFAULT;
727         }
728
729         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
730                         DC_CMD_DISPLAY_WINDOW_HEADER);
731
732         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
733
734         mutex_unlock(&dc->lock);
735
736         return 0;
737 }
738 EXPORT_SYMBOL(tegra_dc_update_csc);
739
740 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
741 {
742         int i;
743         for (i = 0; i < 256; i++)
744                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
745 }
746
747 static int tegra_dc_loop_lut(struct tegra_dc *dc,
748                              struct tegra_dc_win *win,
749                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
750 {
751         struct tegra_dc_lut *lut = &win->lut;
752         struct tegra_dc_lut *global_lut = &dc->fb_lut;
753         int i;
754         for (i = 0; i < 256; i++) {
755
756                 u32 r = (u32)lut->r[i];
757                 u32 g = (u32)lut->g[i];
758                 u32 b = (u32)lut->b[i];
759
760                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
761                         r = (u32)global_lut->r[r];
762                         g = (u32)global_lut->g[g];
763                         b = (u32)global_lut->b[b];
764                 }
765
766                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
767                         return 0;
768         }
769         return 1;
770 }
771
772 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
773 {
774         if (rgb != (i | (i<<8) | (i<<16)))
775                 return 0;
776         return 1;
777 }
778
779 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
780 {
781         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
782         return 1;
783 }
784
785 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
786 {
787         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
788
789         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
790
791         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
792                 val |= CP_ENABLE;
793         else
794                 val &= ~CP_ENABLE;
795
796         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
797 }
798
799 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
800 {
801         struct tegra_dc_win *win = &dc->windows[win_idx];
802
803         mutex_lock(&dc->lock);
804
805         if (!dc->enabled) {
806                 mutex_unlock(&dc->lock);
807                 return -EFAULT;
808         }
809
810         if (fbovr > 0)
811                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
812         else if (fbovr == 0)
813                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
814
815         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
816                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
817         else
818                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
819
820         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
821                         DC_CMD_DISPLAY_WINDOW_HEADER);
822
823         tegra_dc_set_lut(dc, win);
824
825         mutex_unlock(&dc->lock);
826
827         tegra_dc_update_windows(&win, 1);
828
829         return 0;
830 }
831
832 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
833 {
834         if (win_idx > -1)
835                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
836
837         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
838                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
839                 if (err)
840                         return err;
841         }
842
843         return 0;
844 }
845 EXPORT_SYMBOL(tegra_dc_update_lut);
846
847 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
848 {
849         unsigned i;
850         unsigned v0 = 128;
851         unsigned v1 = 0;
852         /* linear horizontal and vertical filters */
853         for (i = 0; i < 16; i++) {
854                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
855                                 DC_WIN_H_FILTER_P(i));
856
857                 tegra_dc_writel(dc, v0,
858                                 DC_WIN_V_FILTER_P(i));
859                 v0 -= 8;
860                 v1 += 8;
861         }
862 }
863
864 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
865         struct tegra_dc_win *w)
866 {
867         /* windows A, B, C for first and second display */
868         static const enum tegra_la_id la_id_tab[2][3] = {
869                 /* first display */
870                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
871                         TEGRA_LA_DISPLAY_0C },
872                 /* second display */
873                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
874                         TEGRA_LA_DISPLAY_0CB },
875         };
876         /* window B V-filter tap for first and second display. */
877         static const enum tegra_la_id vfilter_tab[2] = {
878                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
879         };
880         unsigned long bw;
881
882         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
883         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
884         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
885
886         bw = w->new_bandwidth;
887
888         /* tegra_dc_get_bandwidth() treats V filter windows as double
889          * bandwidth, but LA has a seperate client for V filter */
890         if (w->idx == 1 && win_use_v_filter(w))
891                 bw /= 2;
892
893         /* our bandwidth is in kbytes/sec, but LA takes MBps.
894          * round up bandwidth to next 1MBps */
895         bw = bw / 1000 + 1;
896
897 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
898         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
899         /* if window B, also set the 1B client for the 2-tap V filter. */
900         if (w->idx == 1)
901                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
902 #endif
903
904         w->bandwidth = w->new_bandwidth;
905 }
906
907 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
908                                                    struct tegra_dc_win *b)
909 {
910         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
911                 return 0;
912
913         /* because memory access to load the fifo can overlap, only care
914          * if windows overlap vertically */
915         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
916                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
917 }
918
919 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
920                                                  int n)
921 {
922         unsigned i;
923         unsigned j;
924         unsigned overlap_count;
925         unsigned max_bw = 0;
926
927         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
928                          "inaccurate.\n");
929
930         /* If we had a large number of windows, we would compute adjacency
931          * graph representing 2 window overlaps, find all cliques in the graph,
932          * assign bandwidth to each clique, and then select the clique with
933          * maximum bandwidth. But because we have at most 3 windows,
934          * implementing proper Bron-Kerbosh algorithm would be an overkill,
935          * brute force will suffice.
936          *
937          * Thus: find maximum bandwidth for either single or a pair of windows
938          * and count number of window pair overlaps. If there are three
939          * pairs, all 3 window overlap.
940          */
941
942         overlap_count = 0;
943         for (i = 0; i < n; i++) {
944                 unsigned int bw1;
945
946                 if (wins[i] == NULL)
947                         continue;
948                 bw1 = wins[i]->new_bandwidth;
949                 if (bw1 > max_bw)
950                         /* Single window */
951                         max_bw = bw1;
952
953                 for (j = i + 1; j < n; j++) {
954                         if (wins[j] == NULL)
955                                 continue;
956                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
957                                 unsigned int bw2 = wins[j]->new_bandwidth;
958                                 if (bw1 + bw2 > max_bw)
959                                         /* Window pair overlaps */
960                                         max_bw = bw1 + bw2;
961                                 overlap_count++;
962                         }
963                 }
964         }
965
966         if (overlap_count == 3)
967                 /* All three windows overlap */
968                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
969                          wins[2]->new_bandwidth;
970
971         return max_bw;
972 }
973
974 /*
975  * Calculate peak EMC bandwidth for each enabled window =
976  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
977  * (windows_tiling ? 2 : 1)
978  *
979  * note:
980  * (*) We use 2 tap V filter, so need double BW if use V filter
981  * (*) Tiling mode on T30 and DDR3 requires double BW
982  *
983  * return:
984  * bandwidth in kBps
985  */
986 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
987         struct tegra_dc_win *w)
988 {
989         unsigned long ret;
990         int tiled_windows_bw_multiplier;
991         unsigned long bpp;
992
993         if (!WIN_IS_ENABLED(w))
994                 return 0;
995
996         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
997             w->out_w == 0 || w->out_h == 0)
998                 return 0;
999
1000         tiled_windows_bw_multiplier =
1001                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
1002
1003         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
1004          * but the size reported by tegra_dc_fmt_bpp for the planar version
1005          * is of the luma plane's size only. */
1006         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
1007                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
1008         ret = dc->mode.pclk / 1000UL * bpp / 8 * (win_use_v_filter(w) ? 2 : 1)
1009                 * dfixed_trunc(w->w) / w->out_w *
1010                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
1011         /*
1012          * Assuming ~35% efficiency: i.e. if we calculate we need 70MBps, we
1013          * will request 200MBps from EMC.
1014          */
1015         ret = ret * 29 / 10;
1016
1017         return ret;
1018 }
1019
1020 static unsigned long tegra_dc_get_bandwidth(
1021         struct tegra_dc_win *windows[], int n)
1022 {
1023         int i;
1024
1025         BUG_ON(n > DC_N_WINDOWS);
1026
1027         /* emc rate and latency allowance both need to know per window
1028          * bandwidths */
1029         for (i = 0; i < n; i++) {
1030                 struct tegra_dc_win *w = windows[i];
1031
1032                 if (w)
1033                         w->new_bandwidth =
1034                                 tegra_dc_calc_win_bandwidth(w->dc, w);
1035         }
1036
1037         return tegra_dc_find_max_bandwidth(windows, n);
1038 }
1039
1040 /* to save power, call when display memory clients would be idle */
1041 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
1042 {
1043         trace_printk("%s:%s rate=%d\n", dc->ndev->name, __func__,
1044                 dc->emc_clk_rate);
1045         if (tegra_is_clk_enabled(dc->emc_clk))
1046                 clk_disable(dc->emc_clk);
1047         dc->emc_clk_rate = 0;
1048 }
1049
1050 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
1051 {
1052         unsigned i;
1053
1054         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
1055                 /* going from 0 to non-zero */
1056                 if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk))
1057                         clk_enable(dc->emc_clk);
1058
1059                 dc->emc_clk_rate = dc->new_emc_clk_rate;
1060                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
1061
1062                 if (!dc->new_emc_clk_rate) /* going from non-zero to 0 */
1063                         clk_disable(dc->emc_clk);
1064         }
1065
1066         for (i = 0; i < DC_N_WINDOWS; i++) {
1067                 struct tegra_dc_win *w = &dc->windows[i];
1068
1069                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1070                         tegra_dc_set_latency_allowance(dc, w);
1071                 trace_printk("%s:win%u bandwidth=%d\n", dc->ndev->name, w->idx,
1072                         w->bandwidth);
1073         }
1074 }
1075
1076 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1077 {
1078         unsigned long new_rate;
1079         struct tegra_dc *dc;
1080
1081         if (!use_dynamic_emc)
1082                 return 0;
1083
1084         dc = windows[0]->dc;
1085
1086         /* calculate the new rate based on this POST */
1087         new_rate = tegra_dc_get_bandwidth(windows, n);
1088         if (WARN_ONCE(new_rate > (ULONG_MAX / 1000), "bandwidth maxed out\n"))
1089                 new_rate = ULONG_MAX;
1090         else
1091                 new_rate = EMC_BW_TO_FREQ(new_rate * 1000);
1092
1093         if (tegra_dc_has_multiple_dc())
1094                 new_rate = ULONG_MAX;
1095
1096         trace_printk("%s:new_emc_clk_rate=%ld\n", dc->ndev->name, new_rate);
1097         dc->new_emc_clk_rate = new_rate;
1098
1099         return 0;
1100 }
1101
1102 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1103                                   bool v, unsigned Bpp)
1104 {
1105         /*
1106          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1107          *           (post_scaled_size_in_pixels - 1)), MAX)
1108          * Where the value of MAX is as follows:
1109          * For V_DDA_INCREMENT: 15.0 (0xF000)
1110          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1111          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1112          */
1113
1114         fixed20_12 out = dfixed_init(out_int);
1115         u32 dda_inc;
1116         int max;
1117
1118         if (v) {
1119                 max = 15;
1120         } else {
1121                 switch (Bpp) {
1122                 default:
1123                         WARN_ON_ONCE(1);
1124                         /* fallthrough */
1125                 case 4:
1126                         max = 4;
1127                         break;
1128                 case 2:
1129                         max = 8;
1130                         break;
1131                 }
1132         }
1133
1134         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1135         in.full -= dfixed_const(1);
1136
1137         dda_inc = dfixed_div(in, out);
1138
1139         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1140
1141         return dda_inc;
1142 }
1143
1144 static inline u32 compute_initial_dda(fixed20_12 in)
1145 {
1146         return dfixed_frac(in);
1147 }
1148
1149 /* does not support updating windows on multiple dcs in one call */
1150 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1151 {
1152         struct tegra_dc *dc;
1153         unsigned long update_mask = GENERAL_ACT_REQ;
1154         unsigned long val;
1155         bool update_blend = false;
1156         int i;
1157
1158         dc = windows[0]->dc;
1159
1160         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1161                 /* Acquire one_shot_lock to avoid race condition between
1162                  * cancellation of old delayed work and schedule of new
1163                  * delayed work. */
1164                 mutex_lock(&dc->one_shot_lock);
1165                 cancel_delayed_work_sync(&dc->one_shot_work);
1166         }
1167         mutex_lock(&dc->lock);
1168
1169         if (!dc->enabled) {
1170                 mutex_unlock(&dc->lock);
1171                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1172                         mutex_unlock(&dc->one_shot_lock);
1173                 return -EFAULT;
1174         }
1175
1176         if (no_vsync)
1177                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1178         else
1179                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1180
1181         for (i = 0; i < n; i++) {
1182                 struct tegra_dc_win *win = windows[i];
1183                 unsigned h_dda;
1184                 unsigned v_dda;
1185                 fixed20_12 h_offset, v_offset;
1186                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1187                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1188                 bool yuv = tegra_dc_is_yuv(win->fmt);
1189                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1190                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1191                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1192                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1193                 const bool filter_h = win_use_h_filter(win);
1194                 const bool filter_v = win_use_v_filter(win);
1195
1196                 if (win->z != dc->blend.z[win->idx]) {
1197                         dc->blend.z[win->idx] = win->z;
1198                         update_blend = true;
1199                 }
1200                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1201                         dc->blend.flags[win->idx]) {
1202                         dc->blend.flags[win->idx] =
1203                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1204                         update_blend = true;
1205                 }
1206
1207                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1208                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1209
1210                 if (!no_vsync)
1211                         update_mask |= WIN_A_ACT_REQ << win->idx;
1212
1213                 if (!WIN_IS_ENABLED(win)) {
1214                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1215                         continue;
1216                 }
1217
1218                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
1219                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
1220
1221                 tegra_dc_writel(dc,
1222                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1223                                 DC_WIN_POSITION);
1224                 tegra_dc_writel(dc,
1225                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1226                                 DC_WIN_SIZE);
1227                 tegra_dc_writel(dc,
1228                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1229                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1230                                 DC_WIN_PRESCALED_SIZE);
1231
1232                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1233                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1234                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1235                                 DC_WIN_DDA_INCREMENT);
1236                 h_dda = compute_initial_dda(win->x);
1237                 v_dda = compute_initial_dda(win->y);
1238                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1239                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1240
1241                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1242                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1243                 tegra_dc_writel(dc,
1244                                 (unsigned long)win->phys_addr,
1245                                 DC_WINBUF_START_ADDR);
1246
1247                 if (!yuvp) {
1248                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1249                 } else {
1250                         tegra_dc_writel(dc,
1251                                         (unsigned long)win->phys_addr_u,
1252                                         DC_WINBUF_START_ADDR_U);
1253                         tegra_dc_writel(dc,
1254                                         (unsigned long)win->phys_addr_v,
1255                                         DC_WINBUF_START_ADDR_V);
1256                         tegra_dc_writel(dc,
1257                                         LINE_STRIDE(win->stride) |
1258                                         UV_LINE_STRIDE(win->stride_uv),
1259                                         DC_WIN_LINE_STRIDE);
1260                 }
1261
1262                 h_offset = win->x;
1263                 if (invert_h) {
1264                         h_offset.full += win->w.full - dfixed_const(1);
1265                 }
1266
1267                 v_offset = win->y;
1268                 if (invert_v) {
1269                         v_offset.full += win->h.full - dfixed_const(1);
1270                 }
1271
1272                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1273                                 DC_WINBUF_ADDR_H_OFFSET);
1274                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1275                                 DC_WINBUF_ADDR_V_OFFSET);
1276
1277                 if (WIN_IS_TILED(win))
1278                         tegra_dc_writel(dc,
1279                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1280                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1281                                         DC_WIN_BUFFER_ADDR_MODE);
1282                 else
1283                         tegra_dc_writel(dc,
1284                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1285                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1286                                         DC_WIN_BUFFER_ADDR_MODE);
1287
1288                 val = WIN_ENABLE;
1289                 if (yuv)
1290                         val |= CSC_ENABLE;
1291                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1292                         val |= COLOR_EXPAND;
1293
1294                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1295                         val |= CP_ENABLE;
1296
1297                 if (filter_h)
1298                         val |= H_FILTER_ENABLE;
1299                 if (filter_v)
1300                         val |= V_FILTER_ENABLE;
1301
1302                 if (invert_h)
1303                         val |= H_DIRECTION_DECREMENT;
1304                 if (invert_v)
1305                         val |= V_DIRECTION_DECREMENT;
1306
1307                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1308
1309                 win->dirty = no_vsync ? 0 : 1;
1310
1311                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1312                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1313                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1314                         __func__, win->idx, win->z,
1315                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1316                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1317                         win->out_x, win->out_y, win->out_w, win->out_h,
1318                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1319                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1320                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1321                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1322         }
1323
1324         if (update_blend) {
1325                 tegra_dc_set_blending(dc, &dc->blend);
1326                 for (i = 0; i < DC_N_WINDOWS; i++) {
1327                         if (!no_vsync)
1328                                 dc->windows[i].dirty = 1;
1329                         update_mask |= WIN_A_ACT_REQ << i;
1330                 }
1331         }
1332
1333         tegra_dc_set_dynamic_emc(windows, n);
1334
1335         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1336
1337         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1338         if (!no_vsync) {
1339                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1340                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1341                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1342         } else {
1343                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1344                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1345                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1346         }
1347
1348         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1349                 schedule_delayed_work(&dc->one_shot_work,
1350                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1351
1352         /* update EMC clock if calculated bandwidth has changed */
1353         tegra_dc_program_bandwidth(dc);
1354
1355         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1356                 update_mask |= NC_HOST_TRIG;
1357
1358         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1359         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1360
1361         mutex_unlock(&dc->lock);
1362         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1363                 mutex_unlock(&dc->one_shot_lock);
1364
1365         return 0;
1366 }
1367 EXPORT_SYMBOL(tegra_dc_update_windows);
1368
1369 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1370 {
1371         return dc->syncpt[i].id;
1372 }
1373 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1374
1375 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1376 {
1377         u32 max;
1378
1379         mutex_lock(&dc->lock);
1380         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1381                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1382         dc->syncpt[i].max = max;
1383         mutex_unlock(&dc->lock);
1384
1385         return max;
1386 }
1387
1388 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1389 {
1390         mutex_lock(&dc->lock);
1391         if ( dc->enabled )
1392                 while (dc->syncpt[i].min < val) {
1393                         dc->syncpt[i].min++;
1394                         nvhost_syncpt_cpu_incr(
1395                                         &nvhost_get_host(dc->ndev)->syncpt,
1396                                         dc->syncpt[i].id);
1397                 }
1398         mutex_unlock(&dc->lock);
1399 }
1400
1401 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1402                                              int n)
1403 {
1404         int i;
1405
1406         for (i = 0; i < n; i++) {
1407                 if (windows[i]->dirty)
1408                         return false;
1409         }
1410
1411         return true;
1412 }
1413
1414 /* does not support syncing windows on multiple dcs in one call */
1415 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1416 {
1417         int ret;
1418         if (n < 1 || n > DC_N_WINDOWS)
1419                 return -EINVAL;
1420
1421         if (!windows[0]->dc->enabled)
1422                 return -EFAULT;
1423
1424 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1425         /* Don't want to timeout on simulator */
1426         ret = wait_event_interruptible(windows[0]->dc->wq,
1427                 tegra_dc_windows_are_clean(windows, n));
1428 #else
1429         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1430                         windows[0]->dc->ndev->name);
1431         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1432                                          tegra_dc_windows_are_clean(windows, n),
1433                                          HZ);
1434         trace_printk("%s:After wait_event_interruptible_timeout\n",
1435                         windows[0]->dc->ndev->name);
1436 #endif
1437         return ret;
1438 }
1439 EXPORT_SYMBOL(tegra_dc_sync_windows);
1440
1441 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1442 {
1443 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1444         return clk_get_rate(dc->clk);
1445 #else
1446         return 27000000;
1447 #endif
1448 }
1449
1450 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1451 {
1452         unsigned long rate;
1453         unsigned long div;
1454
1455         rate = tegra_dc_clk_get_rate(dc);
1456
1457         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1458
1459         if (div < 2)
1460                 return 0;
1461
1462         return rate * 2 / div;
1463 }
1464
1465 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1466 {
1467         unsigned long rate;
1468         unsigned long div;
1469
1470         rate = clk_get_rate(parent);
1471
1472         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1473
1474         if (div < 2)
1475                 return 0;
1476
1477         return rate * 2 / div;
1478 }
1479
1480 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1481 {
1482         int pclk;
1483
1484         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1485                 unsigned long rate;
1486                 struct clk *parent_clk =
1487                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1488
1489                 if (dc->out->parent_clk_backup &&
1490                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1491                         rate = tegra_dc_pclk_predict_rate(
1492                                 parent_clk, dc->mode.pclk);
1493                         /* use pll_d as last resort */
1494                         if (rate < (dc->mode.pclk / 100 * 99) ||
1495                             rate > (dc->mode.pclk / 100 * 109))
1496                                 parent_clk = clk_get_sys(
1497                                         NULL, dc->out->parent_clk_backup);
1498                 }
1499
1500                 if (clk_get_parent(clk) != parent_clk)
1501                         clk_set_parent(clk, parent_clk);
1502
1503                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1504                         struct clk *base_clk = clk_get_parent(parent_clk);
1505
1506                         /* Assuming either pll_d or pll_d2 is used */
1507                         rate = dc->mode.pclk * 2;
1508
1509                         if (rate != clk_get_rate(base_clk))
1510                                 clk_set_rate(base_clk, rate);
1511                 }
1512         }
1513
1514         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1515                 unsigned long rate;
1516                 struct clk *parent_clk =
1517                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1518                 struct clk *base_clk = clk_get_parent(parent_clk);
1519
1520                 /*
1521                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1522                  * The required rate needs to be setup at 4x multiplier,
1523                  * as out0 is 1/2 of the actual PLL output.
1524                  */
1525
1526                 rate = dc->mode.pclk * 4;
1527                 if (rate != clk_get_rate(base_clk))
1528                         clk_set_rate(base_clk, rate);
1529
1530                 if (clk_get_parent(clk) != parent_clk)
1531                         clk_set_parent(clk, parent_clk);
1532         }
1533
1534         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1535                 unsigned long rate;
1536                 struct clk *parent_clk;
1537                 struct clk *base_clk;
1538
1539                 if (clk == dc->clk) {
1540                         parent_clk = clk_get_sys(NULL,
1541                                         dc->out->parent_clk ? : "pll_d_out0");
1542                         base_clk = clk_get_parent(parent_clk);
1543                         tegra_clk_cfg_ex(base_clk,
1544                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1545                 } else {
1546                         if (dc->pdata->default_out->dsi->dsi_instance) {
1547                                 parent_clk = clk_get_sys(NULL,
1548                                         dc->out->parent_clk ? : "pll_d2_out0");
1549                                 base_clk = clk_get_parent(parent_clk);
1550                                 tegra_clk_cfg_ex(base_clk,
1551                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1552                         } else {
1553                                 parent_clk = clk_get_sys(NULL,
1554                                         dc->out->parent_clk ? : "pll_d_out0");
1555                                 base_clk = clk_get_parent(parent_clk);
1556                                 tegra_clk_cfg_ex(base_clk,
1557                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1558                         }
1559                 }
1560
1561                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1562                 if (rate != clk_get_rate(base_clk))
1563                         clk_set_rate(base_clk, rate);
1564
1565                 if (clk_get_parent(clk) != parent_clk)
1566                         clk_set_parent(clk, parent_clk);
1567         }
1568
1569         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1570         tegra_dvfs_set_rate(clk, pclk);
1571 }
1572
1573 /* return non-zero if constraint is violated */
1574 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1575 {
1576         long a, b;
1577
1578         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1579         a = 0;
1580
1581         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1582         b = mode->h_front_porch - 1;
1583
1584         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1585         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1586                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1587         /* check Constraint 1 and 6 */
1588         if (a > b)
1589                 return 1;
1590
1591         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1592         if (mode->h_sync_width < 1)
1593                 return 4;
1594
1595         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1596         if (mode->h_active < 16)
1597                 return 7;
1598
1599         if (href) {
1600                 if (b > a && a % 2)
1601                         *href = a + 1; /* use smallest even value */
1602                 else
1603                         *href = a; /* even or only possible value */
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1610 {
1611         long a;
1612         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1613
1614         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1615         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1616                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1617
1618         /* Constraint 6 */
1619         if (mode->v_front_porch < a + 1)
1620                 a = mode->v_front_porch - 1;
1621
1622         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1623         if (mode->v_sync_width < 1)
1624                 return 4;
1625
1626         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1627         if (mode->v_active < 16)
1628                 return 7;
1629
1630         if (vref)
1631                 *vref = a;
1632         return 0;
1633 }
1634
1635 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1636 {
1637         int ret;
1638         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1639         if (ret)
1640                 return ret;
1641         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1642         if (ret)
1643                 return ret;
1644
1645         return 0;
1646 }
1647
1648 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1649 {
1650         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1651         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1652                 return false;
1653
1654         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1655         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1656                 return false;
1657
1658         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1659          * (vertical blank). */
1660         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1661                 return false;
1662
1663         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1664         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1665                 return false;
1666
1667         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1668         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1669                 return false;
1670
1671         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1672          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1673         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1674                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1675                 return false;
1676
1677         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1678         if (mode->h_active < 16 || mode->v_active < 16)
1679                 return false;
1680
1681         return true;
1682 }
1683
1684 #ifdef DEBUG
1685 /* return in 1000ths of a Hertz */
1686 static int calc_refresh(const struct tegra_dc_mode *m)
1687 {
1688         long h_total, v_total, refresh;
1689         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1690                 m->h_sync_width;
1691         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1692                 m->v_sync_width;
1693         refresh = m->pclk / h_total;
1694         refresh *= 1000;
1695         refresh /= v_total;
1696         return refresh;
1697 }
1698
1699 static void print_mode(struct tegra_dc *dc,
1700                         const struct tegra_dc_mode *mode, const char *note)
1701 {
1702         if (mode) {
1703                 int refresh = calc_refresh(dc, mode);
1704                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1705                         note ? note : "",
1706                         mode->h_active, mode->v_active,
1707                         refresh / 1000, refresh % 1000,
1708                         mode->pclk);
1709         }
1710 }
1711 #else /* !DEBUG */
1712 static inline void print_mode(struct tegra_dc *dc,
1713                         const struct tegra_dc_mode *mode, const char *note) { }
1714 #endif /* DEBUG */
1715
1716 static inline void enable_dc_irq(unsigned int irq)
1717 {
1718 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1719         enable_irq(irq);
1720 #else
1721         /* Always disable DC interrupts on FPGA. */
1722         disable_irq(irq);
1723 #endif
1724 }
1725
1726 static inline void disable_dc_irq(unsigned int irq)
1727 {
1728         disable_irq(irq);
1729 }
1730
1731 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1732 {
1733         unsigned long val;
1734         unsigned long rate;
1735         unsigned long div;
1736         unsigned long pclk;
1737
1738         print_mode(dc, mode, __func__);
1739
1740         /* use default EMC rate when switching modes */
1741         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1742         tegra_dc_program_bandwidth(dc);
1743
1744         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1745         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1746                         DC_DISP_REF_TO_SYNC);
1747         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1748                         DC_DISP_SYNC_WIDTH);
1749         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1750                         DC_DISP_BACK_PORCH);
1751         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1752                         DC_DISP_DISP_ACTIVE);
1753         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1754                         DC_DISP_FRONT_PORCH);
1755
1756         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1757                         DC_DISP_DATA_ENABLE_OPTIONS);
1758
1759         /* TODO: MIPI/CRT/HDMI clock cals */
1760
1761         val = DISP_DATA_FORMAT_DF1P1C;
1762
1763         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1764                 val |= DISP_DATA_ALIGNMENT_MSB;
1765         else
1766                 val |= DISP_DATA_ALIGNMENT_LSB;
1767
1768         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1769                 val |= DISP_DATA_ORDER_RED_BLUE;
1770         else
1771                 val |= DISP_DATA_ORDER_BLUE_RED;
1772
1773         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1774
1775         rate = tegra_dc_clk_get_rate(dc);
1776
1777         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1778         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1779         if (pclk < (mode->pclk / 100 * 99) ||
1780             pclk > (mode->pclk / 100 * 109)) {
1781                 dev_err(&dc->ndev->dev,
1782                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1783                         rate, mode->pclk,
1784                         pclk, (mode->pclk / 100 * 99),
1785                         (mode->pclk / 100 * 109));
1786                 return -EINVAL;
1787         }
1788
1789         div = (rate * 2 / pclk) - 2;
1790         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1791
1792         tegra_dc_writel(dc, 0x00010001,
1793                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1794         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1795                         DC_DISP_DISP_CLOCK_CONTROL);
1796
1797 #ifdef CONFIG_SWITCH
1798         switch_set_state(&dc->modeset_switch,
1799                          (mode->h_active << 16) | mode->v_active);
1800 #endif
1801
1802         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1803         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1804
1805         print_mode_info(dc, dc->mode);
1806         return 0;
1807 }
1808
1809
1810 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1811 {
1812         memcpy(&dc->mode, mode, sizeof(dc->mode));
1813
1814         print_mode(dc, mode, __func__);
1815
1816         return 0;
1817 }
1818 EXPORT_SYMBOL(tegra_dc_set_mode);
1819
1820 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1821                 const struct fb_videomode *fbmode, bool stereo_mode)
1822 {
1823         struct tegra_dc_mode mode;
1824
1825         if (!fbmode->pixclock)
1826                 return -EINVAL;
1827
1828         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1829         mode.h_sync_width = fbmode->hsync_len;
1830         mode.v_sync_width = fbmode->vsync_len;
1831         mode.h_back_porch = fbmode->left_margin;
1832         mode.v_back_porch = fbmode->upper_margin;
1833         mode.h_active = fbmode->xres;
1834         mode.v_active = fbmode->yres;
1835         mode.h_front_porch = fbmode->right_margin;
1836         mode.v_front_porch = fbmode->lower_margin;
1837         mode.stereo_mode = stereo_mode;
1838         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1839                 /* HDMI controller requires h_ref=1, v_ref=1 */
1840                 mode.h_ref_to_sync = 1;
1841                 mode.v_ref_to_sync = 1;
1842         } else {
1843                 calc_ref_to_sync(&mode);
1844         }
1845         if (!check_ref_to_sync(&mode)) {
1846                 dev_err(&dc->ndev->dev,
1847                                 "Display timing doesn't meet restrictions.\n");
1848                 return -EINVAL;
1849         }
1850         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1851                 mode.h_active, mode.v_active, mode.pclk,
1852                 mode.h_ref_to_sync, mode.v_ref_to_sync
1853         );
1854
1855 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1856         /* Double the pixel clock and update v_active only for frame packed mode */
1857         if (mode.stereo_mode) {
1858                 mode.pclk *= 2;
1859                 /* total v_active = yres*2 + activespace */
1860                 mode.v_active = fbmode->yres*2 +
1861                                 fbmode->vsync_len +
1862                                 fbmode->upper_margin +
1863                                 fbmode->lower_margin;
1864         }
1865 #endif
1866
1867         mode.flags = 0;
1868
1869         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1870                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1871
1872         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1873                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1874
1875         return tegra_dc_set_mode(dc, &mode);
1876 }
1877 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1878
1879 void
1880 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1881 {
1882         unsigned int ctrl;
1883         unsigned long out_sel;
1884         unsigned long cmd_state;
1885
1886         mutex_lock(&dc->lock);
1887         if (!dc->enabled) {
1888                 mutex_unlock(&dc->lock);
1889                 return;
1890         }
1891
1892         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1893                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1894                 cfg->clk_select);
1895
1896         /* The new value should be effected immediately */
1897         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1898         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1899
1900         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1901                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1902         else
1903                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1904
1905         switch (cfg->which_pwm) {
1906         case TEGRA_PWM_PM0:
1907                 /* Select the LM0 on PM0 */
1908                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1909                 out_sel &= ~(7 << 0);
1910                 out_sel |= (3 << 0);
1911                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1912                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1913                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1914                 break;
1915         case TEGRA_PWM_PM1:
1916                 /* Select the LM1 on PM1 */
1917                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1918                 out_sel &= ~(7 << 4);
1919                 out_sel |= (3 << 4);
1920                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1921                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1922                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1923                 break;
1924         default:
1925                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1926                 break;
1927         }
1928         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1929         mutex_unlock(&dc->lock);
1930 }
1931 EXPORT_SYMBOL(tegra_dc_config_pwm);
1932
1933 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1934                                 const struct tegra_dc_out_pin *pins,
1935                                 const unsigned int n_pins)
1936 {
1937         unsigned int i;
1938
1939         int name;
1940         int pol;
1941
1942         u32 pol1, pol3;
1943
1944         u32 set1, unset1;
1945         u32 set3, unset3;
1946
1947         set1 = set3 = unset1 = unset3 = 0;
1948
1949         for (i = 0; i < n_pins; i++) {
1950                 name = (pins + i)->name;
1951                 pol  = (pins + i)->pol;
1952
1953                 /* set polarity by name */
1954                 switch (name) {
1955                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1956                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1957                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1958                         else
1959                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1960                         break;
1961                 case TEGRA_DC_OUT_PIN_H_SYNC:
1962                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1963                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1964                         else
1965                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1966                         break;
1967                 case TEGRA_DC_OUT_PIN_V_SYNC:
1968                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1969                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1970                         else
1971                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1972                         break;
1973                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1974                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1975                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1976                         else
1977                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1978                         break;
1979                 default:
1980                         printk("Invalid argument in function %s\n",
1981                                __FUNCTION__);
1982                         break;
1983                 }
1984         }
1985
1986         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1987         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1988
1989         pol1 |= set1;
1990         pol1 &= ~unset1;
1991
1992         pol3 |= set3;
1993         pol3 &= ~unset3;
1994
1995         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1996         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1997 }
1998
1999 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2000 {
2001         dc->out = out;
2002
2003         if (out->n_modes > 0)
2004                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
2005
2006         switch (out->type) {
2007         case TEGRA_DC_OUT_RGB:
2008                 dc->out_ops = &tegra_dc_rgb_ops;
2009                 break;
2010
2011         case TEGRA_DC_OUT_HDMI:
2012                 dc->out_ops = &tegra_dc_hdmi_ops;
2013                 break;
2014
2015         case TEGRA_DC_OUT_DSI:
2016                 dc->out_ops = &tegra_dc_dsi_ops;
2017                 break;
2018
2019         default:
2020                 dc->out_ops = NULL;
2021                 break;
2022         }
2023
2024         if (dc->out_ops && dc->out_ops->init)
2025                 dc->out_ops->init(dc);
2026
2027 }
2028
2029 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2030 {
2031         if (dc->out)
2032                 return dc->out->height;
2033         else
2034                 return 0;
2035 }
2036 EXPORT_SYMBOL(tegra_dc_get_out_height);
2037
2038 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2039 {
2040         if (dc->out)
2041                 return dc->out->width;
2042         else
2043                 return 0;
2044 }
2045 EXPORT_SYMBOL(tegra_dc_get_out_width);
2046
2047 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2048 {
2049         if (dc->out && dc->out->max_pixclock)
2050                 return dc->out->max_pixclock;
2051         else
2052                 return 0;
2053 }
2054 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2055
2056 void tegra_dc_enable_crc(struct tegra_dc *dc)
2057 {
2058         u32 val;
2059         tegra_dc_io_start(dc);
2060
2061         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2062                 CRC_ENABLE_ENABLE;
2063         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2064         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2065         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2066 }
2067
2068 void tegra_dc_disable_crc(struct tegra_dc *dc)
2069 {
2070         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2071         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2072         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2073
2074         tegra_dc_io_end(dc);
2075 }
2076
2077 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2078 {
2079         int crc = 0;
2080
2081         if(!dc) {
2082                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2083                 goto crc_error;
2084         }
2085
2086         /* TODO: Replace mdelay with code to sync VBlANK, since
2087          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2088         mdelay(TEGRA_CRC_LATCHED_DELAY);
2089
2090         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2091 crc_error:
2092         return crc;
2093 }
2094
2095 static void tegra_dc_vblank(struct work_struct *work)
2096 {
2097         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2098         bool nvsd_updated = false;
2099
2100         mutex_lock(&dc->lock);
2101
2102         /* Update the SD brightness */
2103         if (dc->enabled && dc->out->sd_settings)
2104                 nvsd_updated = nvsd_update_brightness(dc);
2105
2106         mutex_unlock(&dc->lock);
2107
2108         /* Do the actual brightness update outside of the mutex */
2109         if (nvsd_updated && dc->out->sd_settings &&
2110             dc->out->sd_settings->bl_device) {
2111
2112                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2113                 struct backlight_device *bl = platform_get_drvdata(pdev);
2114                 if (bl)
2115                         backlight_update_status(bl);
2116         }
2117 }
2118
2119 /* Must acquire dc lock and dc one-shot lock before invoking this function.
2120  * Acquire dc one-shot lock first and then dc lock. */
2121 void tegra_dc_host_trigger(struct tegra_dc *dc)
2122 {
2123         /* We release the lock here to prevent deadlock between
2124          * cancel_delayed_work_sync and one-shot work. */
2125         mutex_unlock(&dc->lock);
2126
2127         cancel_delayed_work_sync(&dc->one_shot_work);
2128         mutex_lock(&dc->lock);
2129
2130         schedule_delayed_work(&dc->one_shot_work,
2131                                 msecs_to_jiffies(dc->one_shot_delay_ms));
2132         tegra_dc_program_bandwidth(dc);
2133         tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
2134 }
2135
2136 static void tegra_dc_one_shot_worker(struct work_struct *work)
2137 {
2138         struct tegra_dc *dc = container_of(
2139                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2140         mutex_lock(&dc->lock);
2141         /* memory client has gone idle */
2142         tegra_dc_clear_bandwidth(dc);
2143         mutex_unlock(&dc->lock);
2144 }
2145
2146 /* return an arbitrarily large number if count overflow occurs.
2147  * make it a nice base-10 number to show up in stats output */
2148 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2149 {
2150         unsigned count = tegra_dc_readl(dc, reg);
2151         tegra_dc_writel(dc, 0, reg);
2152         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2153 }
2154
2155 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2156 {
2157         u32 val;
2158         int i;
2159
2160         dc->stats.underflows++;
2161         if (dc->underflow_mask & WIN_A_UF_INT) {
2162                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2163                         DC_WINBUF_AD_UFLOW_STATUS);
2164                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
2165         }
2166         if (dc->underflow_mask & WIN_B_UF_INT) {
2167                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2168                         DC_WINBUF_BD_UFLOW_STATUS);
2169                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
2170         }
2171         if (dc->underflow_mask & WIN_C_UF_INT) {
2172                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2173                         DC_WINBUF_CD_UFLOW_STATUS);
2174                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
2175         }
2176
2177         /* Check for any underflow reset conditions */
2178         for (i = 0; i < DC_N_WINDOWS; i++) {
2179                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2180                         dc->windows[i].underflows++;
2181
2182 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2183                         if (dc->windows[i].underflows > 4) {
2184                                 schedule_work(&dc->reset_work);
2185                                 /* reset counter */
2186                                 dc->windows[i].underflows = 0;
2187                                 trace_printk("%s:Reset work scheduled for "
2188                                                 "window %c\n",
2189                                                 dc->ndev->name, (65 + i));
2190                         }
2191 #endif
2192                 } else {
2193                         dc->windows[i].underflows = 0;
2194                 }
2195         }
2196
2197         /* Clear the underflow mask now that we've checked it. */
2198         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2199         dc->underflow_mask = 0;
2200         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2201         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2202         print_underflow_info(dc);
2203 }
2204
2205 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2206 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2207 {
2208 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2209         u32 val;
2210
2211         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2212         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2213             return true;
2214 #endif
2215         return false;
2216 }
2217
2218 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2219 {
2220         u32 val, i;
2221         u32 completed = 0;
2222         u32 dirty = 0;
2223
2224         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2225         for (i = 0; i < DC_N_WINDOWS; i++) {
2226 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2227                 /* FIXME: this is not needed when the simulator
2228                    clears WIN_x_UPDATE bits as in HW */
2229                 dc->windows[i].dirty = 0;
2230                 completed = 1;
2231 #else
2232                 if (!(val & (WIN_A_UPDATE << i))) {
2233                         dc->windows[i].dirty = 0;
2234                         completed = 1;
2235                 } else {
2236                         dirty = 1;
2237                 }
2238 #endif
2239         }
2240
2241         if (!dirty) {
2242                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2243                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2244                         val &= ~V_BLANK_INT;
2245                 else
2246                         val &= ~FRAME_END_INT;
2247                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2248         }
2249
2250         if (completed) {
2251                 if (!dirty) {
2252                         /* With the last completed window, go ahead
2253                            and enable the vblank interrupt for nvsd. */
2254                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2255                         val |= V_BLANK_INT;
2256                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2257                 }
2258
2259                 wake_up(&dc->wq);
2260         }
2261 }
2262
2263 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2264 {
2265         if (status & V_BLANK_INT) {
2266                 /* Sync up windows. */
2267                 tegra_dc_trigger_windows(dc);
2268
2269                 /* Schedule any additional bottom-half vblank actvities. */
2270                 schedule_work(&dc->vblank_work);
2271         }
2272
2273         if (status & FRAME_END_INT) {
2274                 /* Mark the frame_end as complete. */
2275                 if (!completion_done(&dc->frame_end_complete))
2276                         complete(&dc->frame_end_complete);
2277         }
2278 }
2279
2280 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2281 {
2282         if (status & V_BLANK_INT) {
2283                 /* Schedule any additional bottom-half vblank actvities. */
2284                 schedule_work(&dc->vblank_work);
2285
2286                 /* All windows updated. Mask subsequent V_BLANK interrupts */
2287                 if (!tegra_dc_windows_are_dirty(dc)) {
2288                         u32 val;
2289
2290                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2291                         val &= ~V_BLANK_INT;
2292                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2293                 }
2294         }
2295
2296         if (status & FRAME_END_INT) {
2297                 /* Mark the frame_end as complete. */
2298                 if (!completion_done(&dc->frame_end_complete))
2299                         complete(&dc->frame_end_complete);
2300
2301                 tegra_dc_trigger_windows(dc);
2302         }
2303 }
2304 #endif
2305
2306 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2307 {
2308 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2309         struct tegra_dc *dc = ptr;
2310         unsigned long status;
2311         unsigned long underflow_mask;
2312         u32 val;
2313
2314         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2315                 WARN(1, "IRQ when DC not powered!\n");
2316                 tegra_dc_io_start(dc);
2317                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2318                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2319                 tegra_dc_io_end(dc);
2320                 return IRQ_HANDLED;
2321         }
2322
2323         /* clear all status flags except underflow, save those for the worker */
2324         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2325         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2326         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2327         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2328
2329         /*
2330          * Overlays can get thier internal state corrupted during and underflow
2331          * condition.  The only way to fix this state is to reset the DC.
2332          * if we get 4 consecutive frames with underflows, assume we're
2333          * hosed and reset.
2334          */
2335         underflow_mask = status & ALL_UF_INT;
2336
2337         /* Check underflow */
2338         if (underflow_mask) {
2339                 dc->underflow_mask |= underflow_mask;
2340                 schedule_delayed_work(&dc->underflow_work,
2341                         msecs_to_jiffies(1));
2342         }
2343
2344         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2345                 tegra_dc_one_shot_irq(dc, status);
2346         else
2347                 tegra_dc_continuous_irq(dc, status);
2348
2349         return IRQ_HANDLED;
2350 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2351         return IRQ_NONE;
2352 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2353 }
2354
2355 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2356 {
2357         u32 color_control;
2358
2359         switch (dc->out->depth) {
2360         case 3:
2361                 color_control = BASE_COLOR_SIZE111;
2362                 break;
2363
2364         case 6:
2365                 color_control = BASE_COLOR_SIZE222;
2366                 break;
2367
2368         case 8:
2369                 color_control = BASE_COLOR_SIZE332;
2370                 break;
2371
2372         case 9:
2373                 color_control = BASE_COLOR_SIZE333;
2374                 break;
2375
2376         case 12:
2377                 color_control = BASE_COLOR_SIZE444;
2378                 break;
2379
2380         case 15:
2381                 color_control = BASE_COLOR_SIZE555;
2382                 break;
2383
2384         case 16:
2385                 color_control = BASE_COLOR_SIZE565;
2386                 break;
2387
2388         case 18:
2389                 color_control = BASE_COLOR_SIZE666;
2390                 break;
2391
2392         default:
2393                 color_control = BASE_COLOR_SIZE888;
2394                 break;
2395         }
2396
2397         switch (dc->out->dither) {
2398         case TEGRA_DC_DISABLE_DITHER:
2399                 color_control |= DITHER_CONTROL_DISABLE;
2400                 break;
2401         case TEGRA_DC_ORDERED_DITHER:
2402                 color_control |= DITHER_CONTROL_ORDERED;
2403                 break;
2404         case TEGRA_DC_ERRDIFF_DITHER:
2405                 /* The line buffer for error-diffusion dither is limited
2406                  * to 1280 pixels per line. This limits the maximum
2407                  * horizontal active area size to 1280 pixels when error
2408                  * diffusion is enabled.
2409                  */
2410                 BUG_ON(dc->mode.h_active > 1280);
2411                 color_control |= DITHER_CONTROL_ERRDIFF;
2412                 break;
2413         }
2414
2415         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2416 }
2417
2418 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2419 {
2420         u32 syncpt_id;
2421
2422         switch (dc->ndev->id) {
2423         case 0:
2424                 switch (idx) {
2425                 case 0:
2426                         syncpt_id = NVSYNCPT_DISP0_A;
2427                         break;
2428                 case 1:
2429                         syncpt_id = NVSYNCPT_DISP0_B;
2430                         break;
2431                 case 2:
2432                         syncpt_id = NVSYNCPT_DISP0_C;
2433                         break;
2434                 default:
2435                         BUG();
2436                         break;
2437                 }
2438                 break;
2439         case 1:
2440                 switch (idx) {
2441                 case 0:
2442                         syncpt_id = NVSYNCPT_DISP1_A;
2443                         break;
2444                 case 1:
2445                         syncpt_id = NVSYNCPT_DISP1_B;
2446                         break;
2447                 case 2:
2448                         syncpt_id = NVSYNCPT_DISP1_C;
2449                         break;
2450                 default:
2451                         BUG();
2452                         break;
2453                 }
2454                 break;
2455         default:
2456                 BUG();
2457                 break;
2458         }
2459
2460         return syncpt_id;
2461 }
2462
2463 static int tegra_dc_init(struct tegra_dc *dc)
2464 {
2465         int i;
2466
2467         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2468         if (dc->ndev->id == 0) {
2469                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2470                                       TEGRA_MC_PRIO_MED);
2471                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2472                                       TEGRA_MC_PRIO_MED);
2473                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2474                                       TEGRA_MC_PRIO_MED);
2475                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2476                                       TEGRA_MC_PRIO_MED);
2477                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2478                                       TEGRA_MC_PRIO_HIGH);
2479         } else if (dc->ndev->id == 1) {
2480                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2481                                       TEGRA_MC_PRIO_MED);
2482                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2483                                       TEGRA_MC_PRIO_MED);
2484                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2485                                       TEGRA_MC_PRIO_MED);
2486                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2487                                       TEGRA_MC_PRIO_MED);
2488                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2489                                       TEGRA_MC_PRIO_HIGH);
2490         }
2491         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2492                         DC_CMD_CONT_SYNCPT_VSYNC);
2493         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2494         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2495         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2496         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2497
2498         /* enable interrupts for vblank, frame_end and underflows */
2499         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2500                 DC_CMD_INT_ENABLE);
2501         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2502
2503         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2504
2505         tegra_dc_set_color_control(dc);
2506         for (i = 0; i < DC_N_WINDOWS; i++) {
2507                 struct tegra_dc_win *win = &dc->windows[i];
2508                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2509                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2510                 tegra_dc_set_csc(dc, &win->csc);
2511                 tegra_dc_set_lut(dc, win);
2512                 tegra_dc_set_scaling_filter(dc);
2513         }
2514
2515
2516         for (i = 0; i < dc->n_windows; i++) {
2517                 u32 syncpt = get_syncpt(dc, i);
2518
2519                 dc->syncpt[i].id = syncpt;
2520
2521                 dc->syncpt[i].min = dc->syncpt[i].max =
2522                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2523                                         syncpt);
2524         }
2525
2526         print_mode(dc, &dc->mode, __func__);
2527
2528         if (dc->mode.pclk)
2529                 if (tegra_dc_program_mode(dc, &dc->mode))
2530                         return -EINVAL;
2531
2532         /* Initialize SD AFTER the modeset.
2533            nvsd_init handles the sd_settings = NULL case. */
2534         nvsd_init(dc, dc->out->sd_settings);
2535
2536         return 0;
2537 }
2538
2539 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2540 {
2541         int failed_init = 0;
2542
2543         if (dc->out->enable)
2544                 dc->out->enable();
2545
2546         tegra_dc_setup_clk(dc, dc->clk);
2547         clk_enable(dc->clk);
2548
2549         /* do not accept interrupts during initialization */
2550         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2551         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2552
2553         enable_dc_irq(dc->irq);
2554
2555         failed_init = tegra_dc_init(dc);
2556         if (failed_init) {
2557                 _tegra_dc_controller_disable(dc);
2558                 return false;
2559         }
2560
2561         if (dc->out_ops && dc->out_ops->enable)
2562                 dc->out_ops->enable(dc);
2563
2564         if (dc->out->postpoweron)
2565                 dc->out->postpoweron();
2566
2567         /* force a full blending update */
2568         dc->blend.z[0] = -1;
2569
2570         tegra_dc_ext_enable(dc->ext);
2571
2572         trace_printk("%s:enable\n", dc->ndev->name);
2573         return true;
2574 }
2575
2576 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2577 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2578 {
2579         bool ret = true;
2580
2581         if (dc->out->enable)
2582                 dc->out->enable();
2583
2584         tegra_dc_setup_clk(dc, dc->clk);
2585         clk_enable(dc->clk);
2586
2587         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2588                 mutex_lock(&tegra_dcs[1]->lock);
2589                 disable_irq(tegra_dcs[1]->irq);
2590         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2591                 mutex_lock(&tegra_dcs[0]->lock);
2592                 disable_irq(tegra_dcs[0]->irq);
2593         }
2594
2595         msleep(5);
2596         tegra_periph_reset_assert(dc->clk);
2597         msleep(2);
2598 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2599         tegra_periph_reset_deassert(dc->clk);
2600         msleep(1);
2601 #endif
2602
2603         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2604                 enable_dc_irq(tegra_dcs[1]->irq);
2605                 mutex_unlock(&tegra_dcs[1]->lock);
2606         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2607                 enable_dc_irq(tegra_dcs[0]->irq);
2608                 mutex_unlock(&tegra_dcs[0]->lock);
2609         }
2610
2611         enable_dc_irq(dc->irq);
2612
2613         if (tegra_dc_init(dc)) {
2614                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2615                 ret = false;
2616         }
2617
2618         if (dc->out_ops && dc->out_ops->enable)
2619                 dc->out_ops->enable(dc);
2620
2621         if (dc->out->postpoweron)
2622                 dc->out->postpoweron();
2623
2624         /* force a full blending update */
2625         dc->blend.z[0] = -1;
2626
2627         tegra_dc_ext_enable(dc->ext);
2628
2629         if (!ret) {
2630                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2631                 _tegra_dc_controller_disable(dc);
2632         }
2633
2634         trace_printk("%s:reset enable\n", dc->ndev->name);
2635         return ret;
2636 }
2637 #endif
2638
2639 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2640 {
2641         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2642 }
2643
2644 static bool _tegra_dc_enable(struct tegra_dc *dc)
2645 {
2646         if (dc->mode.pclk == 0) {
2647                 /*  DC enable called but no videomode is loaded.
2648                      Set fallback mode to enable driver with.*/
2649                 if (_tegra_dc_set_default_videomode(dc))
2650                         return false;
2651         }
2652
2653         if (!dc->out)
2654                 return false;
2655
2656         tegra_dc_io_start(dc);
2657
2658         return _tegra_dc_controller_enable(dc);
2659 }
2660
2661 void tegra_dc_enable(struct tegra_dc *dc)
2662 {
2663         mutex_lock(&dc->lock);
2664
2665         if (!dc->enabled)
2666                 dc->enabled = _tegra_dc_enable(dc);
2667
2668         mutex_unlock(&dc->lock);
2669         print_mode_info(dc, dc->mode);
2670 }
2671
2672 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2673 {
2674         unsigned i;
2675
2676         if (dc->out_ops && dc->out_ops->disable)
2677                 dc->out_ops->disable(dc);
2678
2679         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2680         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2681         disable_irq(dc->irq);
2682
2683         tegra_dc_clear_bandwidth(dc);
2684         clk_disable(dc->clk);
2685         tegra_dvfs_set_rate(dc->clk, 0);
2686
2687         if (dc->out && dc->out->disable)
2688                 dc->out->disable();
2689
2690         for (i = 0; i < dc->n_windows; i++) {
2691                 struct tegra_dc_win *w = &dc->windows[i];
2692
2693                 /* reset window bandwidth */
2694                 w->bandwidth = 0;
2695                 w->new_bandwidth = 0;
2696
2697                 /* disable windows */
2698                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2699
2700                 /* flush any pending syncpt waits */
2701                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2702                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2703                                 dc->syncpt[i].id);
2704                         dc->syncpt[i].min++;
2705                         nvhost_syncpt_cpu_incr(
2706                                 &nvhost_get_host(dc->ndev)->syncpt,
2707                                 dc->syncpt[i].id);
2708                 }
2709         }
2710         trace_printk("%s:disabled\n", dc->ndev->name);
2711 }
2712
2713 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2714 {
2715 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2716         u32 val;
2717         if (dc->enabled)  {
2718                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2719                 if (enable)
2720                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2721                 else
2722                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2723                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2724         }
2725 #endif
2726 }
2727
2728 bool tegra_dc_stats_get(struct tegra_dc *dc)
2729 {
2730 #if 0 /* right now it is always enabled */
2731         u32 val;
2732         bool res;
2733
2734         if (dc->enabled)  {
2735                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2736                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2737         } else {
2738                 res = false;
2739         }
2740
2741         return res;
2742 #endif
2743         return true;
2744 }
2745
2746 /* make the screen blank by disabling all windows */
2747 void tegra_dc_blank(struct tegra_dc *dc)
2748 {
2749         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2750         unsigned i;
2751
2752         for (i = 0; i < DC_N_WINDOWS; i++) {
2753                 dcwins[i] = tegra_dc_get_window(dc, i);
2754                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2755         }
2756
2757         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2758         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2759 }
2760
2761 static void _tegra_dc_disable(struct tegra_dc *dc)
2762 {
2763         _tegra_dc_controller_disable(dc);
2764         tegra_dc_io_end(dc);
2765 }
2766
2767 void tegra_dc_disable(struct tegra_dc *dc)
2768 {
2769         tegra_dc_ext_disable(dc->ext);
2770
2771         /* it's important that new underflow work isn't scheduled before the
2772          * lock is acquired. */
2773         cancel_delayed_work_sync(&dc->underflow_work);
2774         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2775                 mutex_lock(&dc->one_shot_lock);
2776                 cancel_delayed_work_sync(&dc->one_shot_work);
2777         }
2778
2779         mutex_lock(&dc->lock);
2780
2781         if (dc->enabled) {
2782                 dc->enabled = false;
2783
2784                 if (!dc->suspended)
2785                         _tegra_dc_disable(dc);
2786         }
2787
2788 #ifdef CONFIG_SWITCH
2789         switch_set_state(&dc->modeset_switch, 0);
2790 #endif
2791
2792         mutex_unlock(&dc->lock);
2793         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2794                 mutex_unlock(&dc->one_shot_lock);
2795         print_mode_info(dc, dc->mode);
2796 }
2797
2798 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2799 static void tegra_dc_reset_worker(struct work_struct *work)
2800 {
2801         struct tegra_dc *dc =
2802                 container_of(work, struct tegra_dc, reset_work);
2803
2804         unsigned long val = 0;
2805
2806         mutex_lock(&shared_lock);
2807
2808         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2809
2810         tegra_dc_ext_disable(dc->ext);
2811
2812         mutex_lock(&dc->lock);
2813
2814         if (dc->enabled == false)
2815                 goto unlock;
2816
2817         dc->enabled = false;
2818
2819         /*
2820          * off host read bus
2821          */
2822         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2823         val &= ~(0x00000100);
2824         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2825
2826         /*
2827          * set DC to STOP mode
2828          */
2829         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2830
2831         msleep(10);
2832
2833         _tegra_dc_controller_disable(dc);
2834
2835         /* _tegra_dc_controller_reset_enable deasserts reset */
2836         _tegra_dc_controller_reset_enable(dc);
2837
2838         dc->enabled = true;
2839
2840         /* reopen host read bus */
2841         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2842         val &= ~(0x00000100);
2843         val |= 0x100;
2844         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2845
2846 unlock:
2847         mutex_unlock(&dc->lock);
2848         mutex_unlock(&shared_lock);
2849         trace_printk("%s:reset complete\n", dc->ndev->name);
2850 }
2851 #endif
2852
2853 static void tegra_dc_underflow_worker(struct work_struct *work)
2854 {
2855         struct tegra_dc *dc = container_of(
2856                 to_delayed_work(work), struct tegra_dc, underflow_work);
2857
2858         mutex_lock(&dc->lock);
2859         if (dc->enabled) {
2860                 tegra_dc_underflow_handler(dc);
2861         }
2862         mutex_unlock(&dc->lock);
2863 }
2864
2865 #ifdef CONFIG_SWITCH
2866 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2867 {
2868         struct tegra_dc *dc =
2869                 container_of(sdev, struct tegra_dc, modeset_switch);
2870
2871         if (!sdev->state)
2872                 return sprintf(buf, "offline\n");
2873
2874         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2875 }
2876 #endif
2877
2878 static int tegra_dc_probe(struct nvhost_device *ndev)
2879 {
2880         struct tegra_dc *dc;
2881         struct clk *clk;
2882         struct clk *emc_clk;
2883         struct resource *res;
2884         struct resource *base_res;
2885         struct resource *fb_mem = NULL;
2886         int ret = 0;
2887         void __iomem *base;
2888         int irq;
2889         int i;
2890
2891         if (!ndev->dev.platform_data) {
2892                 dev_err(&ndev->dev, "no platform data\n");
2893                 return -ENOENT;
2894         }
2895
2896         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2897         if (!dc) {
2898                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2899                 return -ENOMEM;
2900         }
2901
2902         irq = nvhost_get_irq_byname(ndev, "irq");
2903         if (irq <= 0) {
2904                 dev_err(&ndev->dev, "no irq\n");
2905                 ret = -ENOENT;
2906                 goto err_free;
2907         }
2908
2909         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2910         if (!res) {
2911                 dev_err(&ndev->dev, "no mem resource\n");
2912                 ret = -ENOENT;
2913                 goto err_free;
2914         }
2915
2916         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2917         if (!base_res) {
2918                 dev_err(&ndev->dev, "request_mem_region failed\n");
2919                 ret = -EBUSY;
2920                 goto err_free;
2921         }
2922
2923         base = ioremap(res->start, resource_size(res));
2924         if (!base) {
2925                 dev_err(&ndev->dev, "registers can't be mapped\n");
2926                 ret = -EBUSY;
2927                 goto err_release_resource_reg;
2928         }
2929
2930         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2931
2932         clk = clk_get(&ndev->dev, NULL);
2933         if (IS_ERR_OR_NULL(clk)) {
2934                 dev_err(&ndev->dev, "can't get clock\n");
2935                 ret = -ENOENT;
2936                 goto err_iounmap_reg;
2937         }
2938
2939         emc_clk = clk_get(&ndev->dev, "emc");
2940         if (IS_ERR_OR_NULL(emc_clk)) {
2941                 dev_err(&ndev->dev, "can't get emc clock\n");
2942                 ret = -ENOENT;
2943                 goto err_put_clk;
2944         }
2945
2946         dc->clk = clk;
2947         dc->emc_clk = emc_clk;
2948         dc->shift_clk_div = 1;
2949         /* Initialize one shot work delay, it will be assigned by dsi
2950          * according to refresh rate later. */
2951         dc->one_shot_delay_ms = 40;
2952
2953         dc->base_res = base_res;
2954         dc->base = base;
2955         dc->irq = irq;
2956         dc->ndev = ndev;
2957         dc->pdata = ndev->dev.platform_data;
2958
2959         /*
2960          * The emc is a shared clock, it will be set based on
2961          * the requirements for each user on the bus.
2962          */
2963         dc->emc_clk_rate = 0;
2964
2965         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2966                 dc->enabled = true;
2967
2968         mutex_init(&dc->lock);
2969         mutex_init(&dc->one_shot_lock);
2970         init_completion(&dc->frame_end_complete);
2971         init_waitqueue_head(&dc->wq);
2972 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2973         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2974 #endif
2975         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2976         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2977         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2978
2979         tegra_dc_init_lut_defaults(&dc->fb_lut);
2980
2981         dc->n_windows = DC_N_WINDOWS;
2982         for (i = 0; i < dc->n_windows; i++) {
2983                 struct tegra_dc_win *win = &dc->windows[i];
2984                 win->idx = i;
2985                 win->dc = dc;
2986                 tegra_dc_init_csc_defaults(&win->csc);
2987                 tegra_dc_init_lut_defaults(&win->lut);
2988         }
2989
2990         ret = tegra_dc_set(dc, ndev->id);
2991         if (ret < 0) {
2992                 dev_err(&ndev->dev, "can't add dc\n");
2993                 goto err_free_irq;
2994         }
2995
2996         nvhost_set_drvdata(ndev, dc);
2997
2998 #ifdef CONFIG_SWITCH
2999         dc->modeset_switch.name = dev_name(&ndev->dev);
3000         dc->modeset_switch.state = 0;
3001         dc->modeset_switch.print_state = switch_modeset_print_mode;
3002         switch_dev_register(&dc->modeset_switch);
3003 #endif
3004
3005         if (dc->pdata->default_out)
3006                 tegra_dc_set_out(dc, dc->pdata->default_out);
3007         else
3008                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
3009
3010         dc->vblank_syncpt = (dc->ndev->id == 0) ?
3011                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
3012
3013         dc->ext = tegra_dc_ext_register(ndev, dc);
3014         if (IS_ERR_OR_NULL(dc->ext)) {
3015                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3016                 dc->ext = NULL;
3017         }
3018
3019         /* interrupt handler must be registered before tegra_fb_register() */
3020         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
3021                         dev_name(&ndev->dev), dc)) {
3022                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3023                 ret = -EBUSY;
3024                 goto err_put_emc_clk;
3025         }
3026
3027         /* hack to balance enable_irq calls in _tegra_dc_enable() */
3028         disable_dc_irq(dc->irq);
3029
3030         mutex_lock(&dc->lock);
3031         if (dc->enabled)
3032                 _tegra_dc_enable(dc);
3033         mutex_unlock(&dc->lock);
3034
3035         tegra_dc_create_debugfs(dc);
3036
3037         dev_info(&ndev->dev, "probed\n");
3038
3039         if (dc->pdata->fb) {
3040                 if (dc->pdata->fb->bits_per_pixel == -1) {
3041                         unsigned long fmt;
3042                         tegra_dc_writel(dc,
3043                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3044                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3045
3046                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3047                         dc->pdata->fb->bits_per_pixel =
3048                                 tegra_dc_fmt_bpp(fmt);
3049                 }
3050
3051                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3052                 if (IS_ERR_OR_NULL(dc->fb))
3053                         dc->fb = NULL;
3054         }
3055
3056         if (dc->out && dc->out->hotplug_init)
3057                 dc->out->hotplug_init();
3058
3059         if (dc->out_ops && dc->out_ops->detect)
3060                 dc->out_ops->detect(dc);
3061         else
3062                 dc->connected = true;
3063
3064         tegra_dc_create_sysfs(&dc->ndev->dev);
3065
3066         return 0;
3067
3068 err_free_irq:
3069         free_irq(irq, dc);
3070 err_put_emc_clk:
3071         clk_put(emc_clk);
3072 err_put_clk:
3073         clk_put(clk);
3074 err_iounmap_reg:
3075         iounmap(base);
3076         if (fb_mem)
3077                 release_resource(fb_mem);
3078 err_release_resource_reg:
3079         release_resource(base_res);
3080 err_free:
3081         kfree(dc);
3082
3083         return ret;
3084 }
3085
3086 static int tegra_dc_remove(struct nvhost_device *ndev)
3087 {
3088         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3089
3090         tegra_dc_remove_sysfs(&dc->ndev->dev);
3091         tegra_dc_remove_debugfs(dc);
3092
3093         if (dc->fb) {
3094                 tegra_fb_unregister(dc->fb);
3095                 if (dc->fb_mem)
3096                         release_resource(dc->fb_mem);
3097         }
3098
3099         tegra_dc_ext_disable(dc->ext);
3100
3101         if (dc->ext)
3102                 tegra_dc_ext_unregister(dc->ext);
3103
3104         if (dc->enabled)
3105                 _tegra_dc_disable(dc);
3106
3107 #ifdef CONFIG_SWITCH
3108         switch_dev_unregister(&dc->modeset_switch);
3109 #endif
3110         free_irq(dc->irq, dc);
3111         clk_put(dc->emc_clk);
3112         clk_put(dc->clk);
3113         iounmap(dc->base);
3114         if (dc->fb_mem)
3115                 release_resource(dc->base_res);
3116         kfree(dc);
3117         tegra_dc_set(NULL, ndev->id);
3118         return 0;
3119 }
3120
3121 #ifdef CONFIG_PM
3122 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3123 {
3124         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3125
3126         trace_printk("%s:suspend\n", dc->ndev->name);
3127         dev_info(&ndev->dev, "suspend\n");
3128
3129         tegra_dc_ext_disable(dc->ext);
3130
3131         mutex_lock(&dc->lock);
3132
3133         if (dc->out_ops && dc->out_ops->suspend)
3134                 dc->out_ops->suspend(dc);
3135
3136         if (dc->enabled) {
3137                 _tegra_dc_disable(dc);
3138
3139                 dc->suspended = true;
3140         }
3141
3142         if (dc->out && dc->out->postsuspend) {
3143                 dc->out->postsuspend();
3144                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3145                         /*
3146                          * avoid resume event due to voltage falling
3147                          */
3148                         msleep(100);
3149         }
3150
3151         mutex_unlock(&dc->lock);
3152
3153         return 0;
3154 }
3155
3156 static int tegra_dc_resume(struct nvhost_device *ndev)
3157 {
3158         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3159
3160         trace_printk("%s:resume\n", dc->ndev->name);
3161         dev_info(&ndev->dev, "resume\n");
3162
3163         mutex_lock(&dc->lock);
3164         dc->suspended = false;
3165
3166         if (dc->enabled)
3167                 _tegra_dc_enable(dc);
3168
3169         if (dc->out && dc->out->hotplug_init)
3170                 dc->out->hotplug_init();
3171
3172         if (dc->out_ops && dc->out_ops->resume)
3173                 dc->out_ops->resume(dc);
3174         mutex_unlock(&dc->lock);
3175
3176         return 0;
3177 }
3178
3179 #endif /* CONFIG_PM */
3180
3181 extern int suspend_set(const char *val, struct kernel_param *kp)
3182 {
3183         if (!strcmp(val, "dump"))
3184                 dump_regs(tegra_dcs[0]);
3185 #ifdef CONFIG_PM
3186         else if (!strcmp(val, "suspend"))
3187                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3188         else if (!strcmp(val, "resume"))
3189                 tegra_dc_resume(tegra_dcs[0]->ndev);
3190 #endif
3191
3192         return 0;
3193 }
3194
3195 extern int suspend_get(char *buffer, struct kernel_param *kp)
3196 {
3197         return 0;
3198 }
3199
3200 int suspend;
3201
3202 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3203
3204 struct nvhost_driver tegra_dc_driver = {
3205         .driver = {
3206                 .name = "tegradc",
3207                 .owner = THIS_MODULE,
3208         },
3209         .probe = tegra_dc_probe,
3210         .remove = tegra_dc_remove,
3211 #ifdef CONFIG_PM
3212         .suspend = tegra_dc_suspend,
3213         .resume = tegra_dc_resume,
3214 #endif
3215 };
3216
3217 static int __init tegra_dc_module_init(void)
3218 {
3219         int ret = tegra_dc_ext_module_init();
3220         if (ret)
3221                 return ret;
3222         return nvhost_driver_register(&tegra_dc_driver);
3223 }
3224
3225 static void __exit tegra_dc_module_exit(void)
3226 {
3227         nvhost_driver_unregister(&tegra_dc_driver);
3228         tegra_dc_ext_module_exit();
3229 }
3230
3231 module_exit(tegra_dc_module_exit);
3232 module_init(tegra_dc_module_init);