video: tegra: dc: remove emc clock worker
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37
38 #include <mach/clk.h>
39 #include <mach/dc.h>
40 #include <mach/fb.h>
41 #include <mach/mc.h>
42 #include <mach/nvhost.h>
43
44 #include "dc_reg.h"
45 #include "dc_priv.h"
46 #include "overlay.h"
47 #include "nvsd.h"
48
49 #define TEGRA_CRC_LATCHED_DELAY         34
50
51 static int no_vsync;
52
53 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
54
55 static int use_dynamic_emc = 1;
56
57 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
58
59 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
60
61 DEFINE_MUTEX(tegra_dc_lock);
62 DEFINE_MUTEX(shared_lock);
63
64 static inline int tegra_dc_fmt_bpp(int fmt)
65 {
66         switch (fmt) {
67         case TEGRA_WIN_FMT_P1:
68                 return 1;
69
70         case TEGRA_WIN_FMT_P2:
71                 return 2;
72
73         case TEGRA_WIN_FMT_P4:
74                 return 4;
75
76         case TEGRA_WIN_FMT_P8:
77                 return 8;
78
79         case TEGRA_WIN_FMT_B4G4R4A4:
80         case TEGRA_WIN_FMT_B5G5R5A:
81         case TEGRA_WIN_FMT_B5G6R5:
82         case TEGRA_WIN_FMT_AB5G5R5:
83                 return 16;
84
85         case TEGRA_WIN_FMT_B8G8R8A8:
86         case TEGRA_WIN_FMT_R8G8B8A8:
87         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
88         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
89                 return 32;
90
91         /* for planar formats, size of the Y plane, 8bit */
92         case TEGRA_WIN_FMT_YCbCr420P:
93         case TEGRA_WIN_FMT_YUV420P:
94         case TEGRA_WIN_FMT_YCbCr422P:
95         case TEGRA_WIN_FMT_YUV422P:
96                 return 8;
97
98         case TEGRA_WIN_FMT_YCbCr422:
99         case TEGRA_WIN_FMT_YUV422:
100         case TEGRA_WIN_FMT_YCbCr422R:
101         case TEGRA_WIN_FMT_YUV422R:
102         case TEGRA_WIN_FMT_YCbCr422RA:
103         case TEGRA_WIN_FMT_YUV422RA:
104                 /* FIXME: need to know the bpp of these formats */
105                 return 0;
106         }
107         return 0;
108 }
109
110 static inline bool tegra_dc_is_yuv_planar(int fmt)
111 {
112         switch (fmt) {
113         case TEGRA_WIN_FMT_YUV420P:
114         case TEGRA_WIN_FMT_YCbCr420P:
115         case TEGRA_WIN_FMT_YCbCr422P:
116         case TEGRA_WIN_FMT_YUV422P:
117                 return true;
118         }
119         return false;
120 }
121
122 #define DUMP_REG(a) do {                        \
123         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
124                  #a, a, tegra_dc_readl(dc, a));               \
125         print(data, buff);                                    \
126         } while (0)
127
128 static void _dump_regs(struct tegra_dc *dc, void *data,
129                        void (* print)(void *data, const char *str))
130 {
131         int i;
132         char buff[256];
133
134         tegra_dc_io_start(dc);
135         clk_enable(dc->clk);
136
137         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
138         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
139         DUMP_REG(DC_CMD_SIGNAL_RAISE);
140         DUMP_REG(DC_CMD_INT_STATUS);
141         DUMP_REG(DC_CMD_INT_MASK);
142         DUMP_REG(DC_CMD_INT_ENABLE);
143         DUMP_REG(DC_CMD_INT_TYPE);
144         DUMP_REG(DC_CMD_INT_POLARITY);
145         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
146         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
147         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
148         DUMP_REG(DC_CMD_STATE_ACCESS);
149         DUMP_REG(DC_CMD_STATE_CONTROL);
150         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
151         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
152
153         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
154         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
155         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
156         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
157         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
158         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
159         DUMP_REG(DC_DISP_REF_TO_SYNC);
160         DUMP_REG(DC_DISP_SYNC_WIDTH);
161         DUMP_REG(DC_DISP_BACK_PORCH);
162         DUMP_REG(DC_DISP_DISP_ACTIVE);
163         DUMP_REG(DC_DISP_FRONT_PORCH);
164         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
165         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
166         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
167         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
168         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
169         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
170         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
171         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
172         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
173         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
174         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
175         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
176         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
177         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
178         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
179         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
180         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
181         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
182         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
183         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
184         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
185         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
186         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
187         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
188         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
189         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
190         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
191         DUMP_REG(DC_DISP_M0_CONTROL);
192         DUMP_REG(DC_DISP_M1_CONTROL);
193         DUMP_REG(DC_DISP_DI_CONTROL);
194         DUMP_REG(DC_DISP_PP_CONTROL);
195         DUMP_REG(DC_DISP_PP_SELECT_A);
196         DUMP_REG(DC_DISP_PP_SELECT_B);
197         DUMP_REG(DC_DISP_PP_SELECT_C);
198         DUMP_REG(DC_DISP_PP_SELECT_D);
199         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
200         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
201         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
202         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
203         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
204         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
205         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
206         DUMP_REG(DC_DISP_BORDER_COLOR);
207         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
208         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
209         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
210         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
211         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
212         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
213         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
214         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
215         DUMP_REG(DC_DISP_CURSOR_POSITION);
216         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
217         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
218         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
219         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
220         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
221         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
222         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
223         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
224         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
225         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
226         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
227         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
228         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
229
230
231         for (i = 0; i < 3; i++) {
232                 print(data, "\n");
233                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
234                 print(data, buff);
235
236                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
237                                 DC_CMD_DISPLAY_WINDOW_HEADER);
238                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
239                 DUMP_REG(DC_WIN_WIN_OPTIONS);
240                 DUMP_REG(DC_WIN_BYTE_SWAP);
241                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
242                 DUMP_REG(DC_WIN_COLOR_DEPTH);
243                 DUMP_REG(DC_WIN_POSITION);
244                 DUMP_REG(DC_WIN_SIZE);
245                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
246                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
247                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
248                 DUMP_REG(DC_WIN_DDA_INCREMENT);
249                 DUMP_REG(DC_WIN_LINE_STRIDE);
250                 DUMP_REG(DC_WIN_BUF_STRIDE);
251                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
252                 DUMP_REG(DC_WIN_BLEND_NOKEY);
253                 DUMP_REG(DC_WIN_BLEND_1WIN);
254                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
255                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
256                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
257                 DUMP_REG(DC_WINBUF_START_ADDR);
258                 DUMP_REG(DC_WINBUF_START_ADDR_U);
259                 DUMP_REG(DC_WINBUF_START_ADDR_V);
260                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
261                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
262                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
263                 DUMP_REG(DC_WIN_CSC_YOF);
264                 DUMP_REG(DC_WIN_CSC_KYRGB);
265                 DUMP_REG(DC_WIN_CSC_KUR);
266                 DUMP_REG(DC_WIN_CSC_KVR);
267                 DUMP_REG(DC_WIN_CSC_KUG);
268                 DUMP_REG(DC_WIN_CSC_KVG);
269                 DUMP_REG(DC_WIN_CSC_KUB);
270                 DUMP_REG(DC_WIN_CSC_KVB);
271         }
272
273         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
274         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
275         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
276         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
277         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
278         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
279         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
280         DUMP_REG(DC_DISP_M1_CONTROL);
281         DUMP_REG(DC_COM_PM1_CONTROL);
282         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
283         DUMP_REG(DC_DISP_SD_CONTROL);
284
285         clk_disable(dc->clk);
286         tegra_dc_io_end(dc);
287 }
288
289 #undef DUMP_REG
290
291 #ifdef DEBUG
292 static void dump_regs_print(void *data, const char *str)
293 {
294         struct tegra_dc *dc = data;
295         dev_dbg(&dc->ndev->dev, "%s", str);
296 }
297
298 static void dump_regs(struct tegra_dc *dc)
299 {
300         _dump_regs(dc, dc, dump_regs_print);
301 }
302 #else /* !DEBUG */
303
304 static void dump_regs(struct tegra_dc *dc) {}
305
306 #endif /* DEBUG */
307
308 #ifdef CONFIG_DEBUG_FS
309
310 static void dbg_regs_print(void *data, const char *str)
311 {
312         struct seq_file *s = data;
313
314         seq_printf(s, "%s", str);
315 }
316
317 #undef DUMP_REG
318
319 static int dbg_dc_show(struct seq_file *s, void *unused)
320 {
321         struct tegra_dc *dc = s->private;
322
323         _dump_regs(dc, s, dbg_regs_print);
324
325         return 0;
326 }
327
328
329 static int dbg_dc_open(struct inode *inode, struct file *file)
330 {
331         return single_open(file, dbg_dc_show, inode->i_private);
332 }
333
334 static const struct file_operations regs_fops = {
335         .open           = dbg_dc_open,
336         .read           = seq_read,
337         .llseek         = seq_lseek,
338         .release        = single_release,
339 };
340
341 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
342 {
343         struct tegra_dc *dc = s->private;
344         struct tegra_dc_mode *m;
345
346         mutex_lock(&dc->lock);
347         m = &dc->mode;
348         seq_printf(s,
349                 "pclk: %d\n"
350                 "h_ref_to_sync: %d\n"
351                 "v_ref_to_sync: %d\n"
352                 "h_sync_width: %d\n"
353                 "v_sync_width: %d\n"
354                 "h_back_porch: %d\n"
355                 "v_back_porch: %d\n"
356                 "h_active: %d\n"
357                 "v_active: %d\n"
358                 "h_front_porch: %d\n"
359                 "v_front_porch: %d\n"
360                 "stereo_mode: %d\n",
361                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
362                 m->h_sync_width, m->v_sync_width,
363                 m->h_back_porch, m->v_back_porch,
364                 m->h_active, m->v_active,
365                 m->h_front_porch, m->v_front_porch,
366                 m->stereo_mode);
367         mutex_unlock(&dc->lock);
368         return 0;
369 }
370
371 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_mode_show, inode->i_private);
374 }
375
376 static const struct file_operations mode_fops = {
377         .open           = dbg_dc_mode_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386
387         mutex_lock(&dc->lock);
388         seq_printf(s,
389                 "underflows: %u\n"
390                 "underflows_a: %u\n"
391                 "underflows_b: %u\n"
392                 "underflows_c: %u\n",
393                 dc->stats.underflows,
394                 dc->stats.underflows_a,
395                 dc->stats.underflows_b,
396                 dc->stats.underflows_c);
397         mutex_unlock(&dc->lock);
398
399         return 0;
400 }
401
402 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
403 {
404         return single_open(file, dbg_dc_stats_show, inode->i_private);
405 }
406
407 static const struct file_operations stats_fops = {
408         .open           = dbg_dc_stats_open,
409         .read           = seq_read,
410         .llseek         = seq_lseek,
411         .release        = single_release,
412 };
413
414 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
415 {
416         if (dc->debugdir)
417                 debugfs_remove_recursive(dc->debugdir);
418         dc->debugdir = NULL;
419 }
420
421 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
422 {
423         struct dentry *retval;
424
425         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
426         if (!dc->debugdir)
427                 goto remove_out;
428
429         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
430                 &regs_fops);
431         if (!retval)
432                 goto remove_out;
433
434         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
435                 &mode_fops);
436         if (!retval)
437                 goto remove_out;
438
439         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
440                 &stats_fops);
441         if (!retval)
442                 goto remove_out;
443
444         return;
445 remove_out:
446         dev_err(&dc->ndev->dev, "could not create debugfs\n");
447         tegra_dc_remove_debugfs(dc);
448 }
449
450 #else /* !CONFIG_DEBUGFS */
451 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
452 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
453 #endif /* CONFIG_DEBUGFS */
454
455 static int tegra_dc_set(struct tegra_dc *dc, int index)
456 {
457         int ret = 0;
458
459         mutex_lock(&tegra_dc_lock);
460         if (index >= TEGRA_MAX_DC) {
461                 ret = -EINVAL;
462                 goto out;
463         }
464
465         if (dc != NULL && tegra_dcs[index] != NULL) {
466                 ret = -EBUSY;
467                 goto out;
468         }
469
470         tegra_dcs[index] = dc;
471
472 out:
473         mutex_unlock(&tegra_dc_lock);
474
475         return ret;
476 }
477
478 static unsigned int tegra_dc_has_multiple_dc(void)
479 {
480         unsigned int idx;
481         unsigned int cnt = 0;
482         struct tegra_dc *dc;
483
484         mutex_lock(&tegra_dc_lock);
485         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
486                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
487         mutex_unlock(&tegra_dc_lock);
488
489         return (cnt > 1);
490 }
491
492 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
493 {
494         if (idx < TEGRA_MAX_DC)
495                 return tegra_dcs[idx];
496         else
497                 return NULL;
498 }
499 EXPORT_SYMBOL(tegra_dc_get_dc);
500
501 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
502 {
503         if (win >= dc->n_windows)
504                 return NULL;
505
506         return &dc->windows[win];
507 }
508 EXPORT_SYMBOL(tegra_dc_get_window);
509
510 static int get_topmost_window(u32 *depths, unsigned long *wins)
511 {
512         int idx, best = -1;
513
514         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
515                 if (best == -1 || depths[idx] < depths[best])
516                         best = idx;
517         }
518         clear_bit(best, wins);
519         return best;
520 }
521
522 static u32 blend_topwin(u32 flags)
523 {
524         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
525                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
526         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
527                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
528         else
529                 return BLEND(NOKEY, FIX, 0xff, 0xff);
530 }
531
532 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
533 {
534         int other;
535
536         for (other = 0; other < DC_N_WINDOWS; other++) {
537                 if (other != idx && (xy-- == 0))
538                         break;
539         }
540         if (BIT(other) & behind_mask)
541                 return blend_topwin(flags[idx]);
542         else if (flags[other])
543                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
544         else
545                 return BLEND(NOKEY, FIX, 0x00, 0x00);
546 }
547
548 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
549 {
550         unsigned long infront_mask;
551         int first;
552
553         infront_mask = ~(behind_mask | BIT(idx));
554         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
555         first = ffs(infront_mask) - 1;
556
557         if (!infront_mask)
558                 return blend_topwin(flags[idx]);
559         else if (behind_mask && first != -1 && flags[first])
560                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
561         else
562                 return BLEND(NOKEY, FIX, 0x0, 0x0);
563 }
564
565 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
566 {
567         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
568
569         while (mask) {
570                 int idx = get_topmost_window(blend->z, &mask);
571
572                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
573                                 DC_CMD_DISPLAY_WINDOW_HEADER);
574                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
575                                 DC_WIN_BLEND_NOKEY);
576                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
577                                 DC_WIN_BLEND_1WIN);
578                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
579                                 DC_WIN_BLEND_2WIN_X);
580                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
581                                 DC_WIN_BLEND_2WIN_Y);
582                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
583                                 DC_WIN_BLEND_3WIN_XY);
584         }
585 }
586
587 static void tegra_dc_set_csc(struct tegra_dc *dc)
588 {
589         tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
590         tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
591         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
592         tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
593         tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
594         tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
595         tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
596         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
597 }
598
599 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
600 {
601         unsigned i;
602         unsigned v0 = 128;
603         unsigned v1 = 0;
604         /* linear horizontal and vertical filters */
605         for (i = 0; i < 16; i++) {
606                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
607                                 DC_WIN_H_FILTER_P(i));
608
609                 tegra_dc_writel(dc, v0,
610                                 DC_WIN_V_FILTER_P(i));
611                 v0 -= 8;
612                 v1 += 8;
613         }
614 }
615
616 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
617                                                    struct tegra_dc_win *b)
618 {
619         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
620                 return 0;
621         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
622                ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
623 }
624
625 static unsigned int tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
626                                                 unsigned int bw[], int n)
627 {
628         /* We have n windows and knows their geometries and bandwidthes. If any
629          * of them overlapped vertically, the overlapped area bandwidth get
630          * combined.
631          *
632          * This function will find the maximum bandwidth of overlapped area.
633          * If there is no windows overlapped, then return the maximum
634          * bandwidth of windows.
635          */
636
637         /* We know win_2 is always overlapped with win_0 and win_1. */
638         if (tegra_dc_windows_is_overlapped(wins[0], wins[1]))
639                 return bw[0] + bw[1] + bw[2];
640         else
641                 return max(bw[0], bw[1]) + bw[2];
642
643 }
644
645 /* 8 bits per byte (1 << 3) */
646 #define BIT_TO_BYTE_SHIFT 3
647 /*
648  * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we
649  * will request 140MBps from EMC.
650  */
651 #define MEM_EFFICIENCY_SHIFT 1
652 static unsigned long tegra_dc_get_emc_rate(struct tegra_dc_win *wins[], int n)
653 {
654         int i;
655         unsigned int bw[DC_N_WINDOWS];
656         struct tegra_dc_win *w;
657         struct tegra_dc *dc;
658         unsigned int max;
659         unsigned int ret;
660
661         dc = wins[0]->dc;
662
663         if (tegra_dc_has_multiple_dc())
664                 return tegra_dc_get_default_emc_clk_rate(dc);
665
666         BUG_ON(n > ARRAY_SIZE(bw));
667         /*
668          * Calculate peak EMC bandwidth for each enabled window =
669          * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
670          * (windows_tiling ? 2 : 1)
671          *
672          *
673          * note:
674          * (*) We use 2 tap V filter, so need double BW if use V filter
675          * (*) Tiling mode on T30 and DDR3 requires double BW
676          */
677         for (i = 0; w = wins[i], bw[i] = 0, i < n; i++) {
678                 if (!WIN_IS_ENABLED(w))
679                         continue;
680                 bw[i] = dc->pixel_clk *
681                         (tegra_dc_fmt_bpp(w->fmt) >> BIT_TO_BYTE_SHIFT) *
682                         (WIN_USE_V_FILTER(w) ? 2 : 1) /
683                         w->out_w * w->w *
684                         (WIN_IS_TILED(w) ? TILED_WINDOWS_BW_MULTIPLIER : 1);
685         }
686
687         max = tegra_dc_find_max_bandwidth(wins, bw, n) << MEM_EFFICIENCY_SHIFT;
688
689         ret = EMC_BW_TO_FREQ(max);
690
691         /*
692          * If the calculated peak BW is bigger than board specified BW, then
693          * either the above calculation is wrong, or board specified BW is
694          * wrong.
695          */
696         WARN_ONCE(ret > tegra_dc_get_default_emc_clk_rate(dc),
697                   "Calculated EMC bandwidth is %luHz, "
698                   "maximum allowed EMC bandwidth is %luHz\n",
699                   ret, tegra_dc_get_default_emc_clk_rate(dc));
700
701         return ret;
702 }
703 #undef BIT_TO_BYTE_SHIFT
704 #undef MEM_EFFICIENCY_SHIFT
705
706 static void tegra_dc_change_emc(struct tegra_dc *dc)
707 {
708         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
709                 dc->emc_clk_rate = dc->new_emc_clk_rate;
710                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
711         }
712 }
713
714 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
715 {
716         unsigned long new_rate;
717         struct tegra_dc *dc;
718
719         if (!use_dynamic_emc)
720                 return 0;
721
722         dc = windows[0]->dc;
723
724         /* calculate the new rate based on this POST */
725         new_rate = tegra_dc_get_emc_rate(windows, n);
726
727         dc->new_emc_clk_rate = new_rate;
728
729         return 0;
730 }
731
732 /* does not support updating windows on multiple dcs in one call */
733 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
734 {
735         struct tegra_dc *dc;
736         unsigned long update_mask = GENERAL_ACT_REQ;
737         unsigned long val;
738         bool update_blend = false;
739         int i;
740
741         dc = windows[0]->dc;
742
743         mutex_lock(&dc->lock);
744
745         if (!dc->enabled) {
746                 mutex_unlock(&dc->lock);
747                 return -EFAULT;
748         }
749
750         if (no_vsync)
751                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
752         else
753                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
754
755         for (i = 0; i < n; i++) {
756                 struct tegra_dc_win *win = windows[i];
757                 unsigned h_dda;
758                 unsigned v_dda;
759                 unsigned h_offset;
760                 unsigned v_offset;
761                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
762                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
763                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
764
765                 if (win->z != dc->blend.z[win->idx]) {
766                         dc->blend.z[win->idx] = win->z;
767                         update_blend = true;
768                 }
769                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
770                         dc->blend.flags[win->idx]) {
771                         dc->blend.flags[win->idx] =
772                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
773                         update_blend = true;
774                 }
775
776                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
777                                 DC_CMD_DISPLAY_WINDOW_HEADER);
778
779                 if (!no_vsync)
780                         update_mask |= WIN_A_ACT_REQ << win->idx;
781
782                 if (!WIN_IS_ENABLED(win)) {
783                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
784                         continue;
785                 }
786
787                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
788                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
789
790                 tegra_dc_writel(dc,
791                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
792                                 DC_WIN_POSITION);
793                 tegra_dc_writel(dc,
794                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
795                                 DC_WIN_SIZE);
796                 tegra_dc_writel(dc,
797                                 V_PRESCALED_SIZE(win->h) |
798                                 H_PRESCALED_SIZE(win->w * tegra_dc_fmt_bpp(win->fmt) / 8),
799                                 DC_WIN_PRESCALED_SIZE);
800
801                 h_dda = ((win->w - 1) * 0x1000) / max_t(int, win->out_w - 1, 1);
802                 v_dda = ((win->h - 1) * 0x1000) / max_t(int, win->out_h - 1, 1);
803                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
804                                 DC_WIN_DDA_INCREMENT);
805                 tegra_dc_writel(dc, 0, DC_WIN_H_INITIAL_DDA);
806                 tegra_dc_writel(dc, 0, DC_WIN_V_INITIAL_DDA);
807
808                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
809                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
810                 tegra_dc_writel(dc,
811                                 (unsigned long)win->phys_addr +
812                                 (unsigned long)win->offset,
813                                 DC_WINBUF_START_ADDR);
814
815                 if (!yuvp) {
816                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
817                 } else {
818                         tegra_dc_writel(dc,
819                                         (unsigned long)win->phys_addr +
820                                         (unsigned long)win->offset_u,
821                                         DC_WINBUF_START_ADDR_U);
822                         tegra_dc_writel(dc,
823                                         (unsigned long)win->phys_addr +
824                                         (unsigned long)win->offset_v,
825                                         DC_WINBUF_START_ADDR_V);
826                         tegra_dc_writel(dc,
827                                         LINE_STRIDE(win->stride) |
828                                         UV_LINE_STRIDE(win->stride_uv),
829                                         DC_WIN_LINE_STRIDE);
830                 }
831
832                 h_offset = win->x;
833                 if (invert_h) {
834                         h_offset += win->w - 1;
835                 }
836                 h_offset *= tegra_dc_fmt_bpp(win->fmt) / 8;
837
838                 v_offset = win->y;
839                 if (invert_v) {
840                         v_offset += win->h - 1;
841                 }
842
843                 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
844                 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
845
846                 if (WIN_IS_TILED(win))
847                         tegra_dc_writel(dc,
848                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
849                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
850                                         DC_WIN_BUFFER_ADDR_MODE);
851                 else
852                         tegra_dc_writel(dc,
853                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
854                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
855                                         DC_WIN_BUFFER_ADDR_MODE);
856
857                 val = WIN_ENABLE;
858                 if (yuvp)
859                         val |= CSC_ENABLE;
860                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
861                         val |= COLOR_EXPAND;
862
863                 /* only B and C have H filer, force it on if scaling */
864                 if (win->idx != 0 && win->w != win->out_w)
865                         win->flags |= TEGRA_WIN_FLAG_H_FILTER;
866                 /* only B has V filter, set it if scaling */
867                 if (win->idx == 1 && win->h != win->out_h)
868                         win->flags |= TEGRA_WIN_FLAG_V_FILTER;
869
870                 if (WIN_USE_H_FILTER(win))
871                         val |= H_FILTER_ENABLE;
872                 if (WIN_USE_V_FILTER(win))
873                         val |= V_FILTER_ENABLE;
874
875                 if (invert_h)
876                         val |= H_DIRECTION_DECREMENT;
877                 if (invert_v)
878                         val |= V_DIRECTION_DECREMENT;
879
880                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
881
882                 win->dirty = no_vsync ? 0 : 1;
883         }
884
885         if (update_blend) {
886                 tegra_dc_set_blending(dc, &dc->blend);
887                 for (i = 0; i < DC_N_WINDOWS; i++) {
888                         if (!no_vsync)
889                                 dc->windows[i].dirty = 1;
890                         update_mask |= WIN_A_ACT_REQ << i;
891                 }
892         }
893
894         tegra_dc_set_dynamic_emc(windows, n);
895
896         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
897
898         if (!no_vsync) {
899                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
900                 val |= FRAME_END_INT;
901                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
902
903                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
904                 val |= FRAME_END_INT;
905                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
906         }
907
908         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
909
910         mutex_unlock(&dc->lock);
911
912         return 0;
913 }
914 EXPORT_SYMBOL(tegra_dc_update_windows);
915
916 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc)
917 {
918         return dc->syncpt_id;
919 }
920 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
921
922 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc)
923 {
924         u32 max;
925
926         mutex_lock(&dc->lock);
927         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt, dc->syncpt_id,
928                                         ((dc->enabled) ? 1 : 0) );
929         dc->syncpt_max = max;
930         mutex_unlock(&dc->lock);
931
932         return max;
933 }
934
935 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val)
936 {
937         mutex_lock(&dc->lock);
938         if ( dc->enabled )
939                 while (dc->syncpt_min < val) {
940                         dc->syncpt_min++;
941                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
942                                 dc->syncpt_id);
943                 }
944         mutex_unlock(&dc->lock);
945 }
946
947 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
948                                              int n)
949 {
950         int i;
951
952         for (i = 0; i < n; i++) {
953                 if (windows[i]->dirty)
954                         return false;
955         }
956
957         return true;
958 }
959
960 /* does not support syncing windows on multiple dcs in one call */
961 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
962 {
963         if (n < 1 || n > DC_N_WINDOWS)
964                 return -EINVAL;
965
966         if (!windows[0]->dc->enabled)
967                 return -EFAULT;
968
969         return wait_event_interruptible_timeout(windows[0]->dc->wq,
970                                          tegra_dc_windows_are_clean(windows, n),
971                                          HZ);
972 }
973 EXPORT_SYMBOL(tegra_dc_sync_windows);
974
975 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
976 {
977 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
978         return clk_get_rate(dc->clk);
979 #else
980         return 27000000;
981 #endif
982 }
983
984 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
985 {
986         unsigned long rate;
987         unsigned long div;
988
989         rate = tegra_dc_clk_get_rate(dc);
990
991         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
992
993         if (div < 2)
994                 return 0;
995
996         return rate * 2 / div;
997 }
998
999 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1000 {
1001         int pclk;
1002
1003         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1004                 struct clk *parent_clk =
1005                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1006
1007                 if (clk_get_parent(clk) != parent_clk)
1008                         clk_set_parent(clk, parent_clk);
1009         }
1010
1011         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1012                 unsigned long rate;
1013                 struct clk *parent_clk =
1014                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1015                 struct clk *base_clk = clk_get_parent(parent_clk);
1016
1017                 if (dc->mode.pclk > 70000000)
1018                         rate = 594000000;
1019                 else
1020                         rate = 216000000;
1021
1022                 if (rate != clk_get_rate(base_clk))
1023                         clk_set_rate(base_clk, rate);
1024
1025                 if (clk_get_parent(clk) != parent_clk)
1026                         clk_set_parent(clk, parent_clk);
1027         }
1028
1029         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1030                 unsigned long rate;
1031                 struct clk *parent_clk;
1032                 struct clk *base_clk;
1033
1034                 if (clk == dc->clk) {
1035                         parent_clk = clk_get_sys(NULL,
1036                                         dc->out->parent_clk ? : "pll_d_out0");
1037                         base_clk = clk_get_parent(parent_clk);
1038                 } else {
1039                         if (dc->pdata->default_out->dsi->dsi_instance) {
1040                                 parent_clk = clk_get_sys(NULL,
1041                                         dc->out->parent_clk ? : "pll_d2_out0");
1042                                 base_clk = clk_get_parent(parent_clk);
1043                                 tegra_clk_cfg_ex(base_clk,
1044                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1045                         } else {
1046                                 parent_clk = clk_get_sys(NULL,
1047                                         dc->out->parent_clk ? : "pll_d_out0");
1048                                 base_clk = clk_get_parent(parent_clk);
1049                         }
1050                 }
1051
1052                 rate = dc->mode.pclk;
1053                 if (rate != clk_get_rate(base_clk))
1054                         clk_set_rate(base_clk, rate);
1055
1056                 if (clk_get_parent(clk) != parent_clk)
1057                         clk_set_parent(clk, parent_clk);
1058         }
1059
1060         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1061         tegra_dvfs_set_rate(clk, pclk);
1062 }
1063
1064 /* return non-zero if constraint is violated */
1065 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1066 {
1067         long a, b;
1068
1069         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1070         a = 0;
1071
1072         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1073         b = mode->h_front_porch - 1;
1074
1075         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1076         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1077                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1078         /* check Constraint 1 and 6 */
1079         if (a > b)
1080                 return 1;
1081
1082         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1083         if (mode->h_sync_width < 1)
1084                 return 4;
1085
1086         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1087         if (mode->h_active < 16)
1088                 return 7;
1089
1090         if (href) {
1091                 if (b > a && a % 2)
1092                         *href = a + 1; /* use smallest even value */
1093                 else
1094                         *href = a; /* even or only possible value */
1095         }
1096
1097         return 0;
1098 }
1099
1100 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1101 {
1102         long a;
1103         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1104
1105         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1106         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1107                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1108
1109         /* Constraint 6 */
1110         if (mode->v_front_porch < a + 1)
1111                 a = mode->v_front_porch - 1;
1112
1113         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1114         if (mode->v_sync_width < 1)
1115                 return 4;
1116
1117         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1118         if (mode->v_active < 16)
1119                 return 7;
1120
1121         if (vref)
1122                 *vref = a;
1123         return 0;
1124 }
1125
1126 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1127 {
1128         int ret;
1129         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1130         if (ret)
1131                 return ret;
1132         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1133         if (ret)
1134                 return ret;
1135
1136         return 0;
1137 }
1138
1139 #ifdef DEBUG
1140 /* return in 1000ths of a Hertz */
1141 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1142 {
1143         long h_total, v_total, refresh;
1144         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1145                 m->h_sync_width;
1146         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1147                 m->v_sync_width;
1148         refresh = dc->pixel_clk / h_total;
1149         refresh *= 1000;
1150         refresh /= v_total;
1151         return refresh;
1152 }
1153
1154 static void print_mode(struct tegra_dc *dc,
1155                         const struct tegra_dc_mode *mode, const char *note)
1156 {
1157         if (mode) {
1158                 int refresh = calc_refresh(mode);
1159                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1160                         note ? note : "",
1161                         mode->h_active, mode->v_active,
1162                         refresh / 1000, refresh % 1000,
1163                         mode->pclk);
1164         }
1165 }
1166 #else /* !DEBUG */
1167 static inline void print_mode(struct tegra_dc *dc,
1168                         const struct tegra_dc_mode *mode, const char *note) { }
1169 #endif /* DEBUG */
1170
1171 static inline void enable_dc_irq(unsigned int irq)
1172 {
1173 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1174         enable_irq(irq);
1175 #else
1176         /* Always disable DC interrupts on FPGA. */
1177         disable_irq(irq);
1178 #endif
1179 }
1180
1181 static inline void disable_dc_irq(unsigned int irq)
1182 {
1183         disable_irq(irq);
1184 }
1185
1186 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1187 {
1188         unsigned long val;
1189         unsigned long rate;
1190         unsigned long div;
1191         unsigned long pclk;
1192
1193         print_mode(dc, mode, __func__);
1194
1195         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1196         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1197                         DC_DISP_REF_TO_SYNC);
1198         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1199                         DC_DISP_SYNC_WIDTH);
1200         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1201                         DC_DISP_BACK_PORCH);
1202         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1203                         DC_DISP_DISP_ACTIVE);
1204         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1205                         DC_DISP_FRONT_PORCH);
1206
1207         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1208                         DC_DISP_DATA_ENABLE_OPTIONS);
1209
1210         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1211         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1212                 val |= PIN1_LVS_OUTPUT;
1213         else
1214                 val &= ~PIN1_LVS_OUTPUT;
1215
1216         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1217                 val |= PIN1_LHS_OUTPUT;
1218         else
1219                 val &= ~PIN1_LHS_OUTPUT;
1220         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1221
1222         /* TODO: MIPI/CRT/HDMI clock cals */
1223
1224         val = DISP_DATA_FORMAT_DF1P1C;
1225
1226         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1227                 val |= DISP_DATA_ALIGNMENT_MSB;
1228         else
1229                 val |= DISP_DATA_ALIGNMENT_LSB;
1230
1231         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1232                 val |= DISP_DATA_ORDER_RED_BLUE;
1233         else
1234                 val |= DISP_DATA_ORDER_BLUE_RED;
1235
1236         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1237
1238         rate = tegra_dc_clk_get_rate(dc);
1239
1240         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1241         if (pclk < (mode->pclk / 100 * 99) ||
1242             pclk > (mode->pclk / 100 * 109)) {
1243                 dev_err(&dc->ndev->dev,
1244                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1245                         rate, mode->pclk,
1246                         pclk, (mode->pclk / 100 * 99),
1247                         (mode->pclk / 100 * 109));
1248                 return -EINVAL;
1249         }
1250
1251         div = (rate * 2 / pclk) - 2;
1252
1253         tegra_dc_writel(dc, 0x00010001,
1254                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1255         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1256                         DC_DISP_DISP_CLOCK_CONTROL);
1257
1258         dc->pixel_clk = dc->mode.pclk;
1259
1260         return 0;
1261 }
1262
1263
1264 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1265 {
1266         memcpy(&dc->mode, mode, sizeof(dc->mode));
1267
1268         print_mode(dc, mode, __func__);
1269
1270         return 0;
1271 }
1272 EXPORT_SYMBOL(tegra_dc_set_mode);
1273
1274 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1275                 const struct fb_videomode *fbmode, bool stereo_mode)
1276 {
1277         struct tegra_dc_mode mode;
1278
1279         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1280         mode.h_sync_width = fbmode->hsync_len;
1281         mode.v_sync_width = fbmode->vsync_len;
1282         mode.h_back_porch = fbmode->left_margin;
1283         mode.v_back_porch = fbmode->upper_margin;
1284         mode.h_active = fbmode->xres;
1285         mode.v_active = fbmode->yres;
1286         mode.h_front_porch = fbmode->right_margin;
1287         mode.v_front_porch = fbmode->lower_margin;
1288         mode.stereo_mode = stereo_mode;
1289         if (calc_ref_to_sync(&mode)) {
1290                 dev_err(&dc->ndev->dev, "bad href/vref values, overriding.\n");
1291                 mode.h_ref_to_sync = 11;
1292                 mode.v_ref_to_sync = 1;
1293         }
1294         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1295                 mode.h_active, mode.v_active, mode.pclk,
1296                 mode.h_ref_to_sync, mode.v_ref_to_sync
1297         );
1298
1299         if (mode.stereo_mode) {
1300                 mode.pclk *= 2;
1301                 /* total v_active = yres*2 + activespace */
1302                 mode.v_active = fbmode->yres*2 +
1303                                 fbmode->vsync_len +
1304                                 fbmode->upper_margin +
1305                                 fbmode->lower_margin;
1306         }
1307
1308         mode.flags = 0;
1309
1310         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1311                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1312
1313         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1314                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1315
1316         return tegra_dc_set_mode(dc, &mode);
1317 }
1318 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1319
1320 void
1321 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1322 {
1323         unsigned int ctrl;
1324         unsigned long out_sel;
1325         unsigned long cmd_state;
1326
1327         mutex_lock(&dc->lock);
1328         if (!dc->enabled) {
1329                 mutex_unlock(&dc->lock);
1330                 return;
1331         }
1332
1333         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1334                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1335                 cfg->clk_select);
1336
1337         /* The new value should be effected immediately */
1338         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1339         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1340
1341         switch (cfg->which_pwm) {
1342         case TEGRA_PWM_PM0:
1343                 /* Select the LM0 on PM0 */
1344                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1345                 out_sel &= ~(7 << 0);
1346                 out_sel |= (3 << 0);
1347                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1348                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1349                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1350                 break;
1351         case TEGRA_PWM_PM1:
1352                 /* Select the LM1 on PM1 */
1353                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1354                 out_sel &= ~(7 << 4);
1355                 out_sel |= (3 << 4);
1356                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1357                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1358                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1359                 break;
1360         default:
1361                 dev_err(&dc->ndev->dev, "Error\n");
1362                 break;
1363         }
1364         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1365         mutex_unlock(&dc->lock);
1366 }
1367 EXPORT_SYMBOL(tegra_dc_config_pwm);
1368
1369 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1370                                 const struct tegra_dc_out_pin *pins,
1371                                 const unsigned int n_pins)
1372 {
1373         unsigned int i;
1374
1375         int name;
1376         int pol;
1377
1378         u32 pol1, pol3;
1379
1380         u32 set1, unset1;
1381         u32 set3, unset3;
1382
1383         set1 = set3 = unset1 = unset3 = 0;
1384
1385         for (i = 0; i < n_pins; i++) {
1386                 name = (pins + i)->name;
1387                 pol  = (pins + i)->pol;
1388
1389                 /* set polarity by name */
1390                 switch (name) {
1391                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1392                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1393                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1394                         else
1395                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1396                         break;
1397                 case TEGRA_DC_OUT_PIN_H_SYNC:
1398                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1399                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1400                         else
1401                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1402                         break;
1403                 case TEGRA_DC_OUT_PIN_V_SYNC:
1404                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1405                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1406                         else
1407                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1408                         break;
1409                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1410                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1411                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1412                         else
1413                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1414                         break;
1415                 default:
1416                         printk("Invalid argument in function %s\n",
1417                                __FUNCTION__);
1418                         break;
1419                 }
1420         }
1421
1422         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1423         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1424
1425         pol1 |= set1;
1426         pol1 &= ~unset1;
1427
1428         pol3 |= set3;
1429         pol3 &= ~unset3;
1430
1431         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1432         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1433 }
1434
1435 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1436 {
1437         dc->out = out;
1438
1439         if (out->n_modes > 0)
1440                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1441
1442         switch (out->type) {
1443         case TEGRA_DC_OUT_RGB:
1444                 dc->out_ops = &tegra_dc_rgb_ops;
1445                 break;
1446
1447         case TEGRA_DC_OUT_HDMI:
1448                 dc->out_ops = &tegra_dc_hdmi_ops;
1449                 break;
1450
1451         case TEGRA_DC_OUT_DSI:
1452                 dc->out_ops = &tegra_dc_dsi_ops;
1453                 break;
1454
1455         default:
1456                 dc->out_ops = NULL;
1457                 break;
1458         }
1459
1460         if (dc->out_ops && dc->out_ops->init)
1461                 dc->out_ops->init(dc);
1462
1463 }
1464
1465 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1466 {
1467         if (dc->out)
1468                 return dc->out->height;
1469         else
1470                 return 0;
1471 }
1472 EXPORT_SYMBOL(tegra_dc_get_out_height);
1473
1474 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1475 {
1476         if (dc->out)
1477                 return dc->out->width;
1478         else
1479                 return 0;
1480 }
1481 EXPORT_SYMBOL(tegra_dc_get_out_width);
1482
1483 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1484 {
1485         if (dc->out && dc->out->max_pixclock)
1486                 return dc->out->max_pixclock;
1487         else
1488                 return 0;
1489 }
1490 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1491
1492 void tegra_dc_enable_crc(struct tegra_dc *dc)
1493 {
1494         u32 val;
1495         tegra_dc_io_start(dc);
1496
1497         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1498                 CRC_ENABLE_ENABLE;
1499         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1500         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1501         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1502 }
1503
1504 void tegra_dc_disable_crc(struct tegra_dc *dc)
1505 {
1506         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1507         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1508         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1509
1510         tegra_dc_io_end(dc);
1511 }
1512
1513 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1514 {
1515         int crc = 0;
1516         u32 val = 0;
1517
1518         if(!dc) {
1519                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1520                 goto crc_error;
1521         }
1522
1523         /* TODO: Replace mdelay with code to sync VBlANK, since
1524          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1525         mdelay(TEGRA_CRC_LATCHED_DELAY);
1526
1527         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1528 crc_error:
1529         return crc;
1530 }
1531
1532 static void tegra_dc_vblank(struct work_struct *work)
1533 {
1534         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1535         bool nvsd_updated = false;
1536
1537         mutex_lock(&dc->lock);
1538
1539         /* update EMC clock if calculated bandwidth has changed */
1540         tegra_dc_change_emc(dc);
1541
1542         /* Update the SD brightness */
1543         nvsd_updated = nvsd_update_brightness(dc);
1544
1545         mutex_unlock(&dc->lock);
1546
1547         /* Do the actual brightness update outside of the mutex */
1548         if (nvsd_updated && dc->out->sd_settings &&
1549             dc->out->sd_settings->bl_device) {
1550
1551                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1552                 struct backlight_device *bl = platform_get_drvdata(pdev);
1553                 if (bl)
1554                         backlight_update_status(bl);
1555         }
1556 }
1557
1558 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1559 {
1560 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1561         struct tegra_dc *dc = ptr;
1562         unsigned long status;
1563         unsigned long val;
1564         unsigned long underflow_mask;
1565         int i;
1566
1567         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1568         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1569
1570         /*
1571          * Overlays can get thier internal state corrupted during and underflow
1572          * condition.  The only way to fix this state is to reset the DC.
1573          * if we get 4 consecutive frames with underflows, assume we're
1574          * hosed and reset.
1575          */
1576         underflow_mask = status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1577
1578         if (underflow_mask) {
1579                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1580                 val |= V_BLANK_INT;
1581                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1582                 dc->underflow_mask |= underflow_mask;
1583                 dc->stats.underflows++;
1584                 if (status & WIN_A_UF_INT)
1585                         dc->stats.underflows_a++;
1586                 if (status & WIN_B_UF_INT)
1587                         dc->stats.underflows_b++;
1588                 if (status & WIN_C_UF_INT)
1589                         dc->stats.underflows_c++;
1590         }
1591
1592         if (status & V_BLANK_INT) {
1593                 int i;
1594
1595                 /* Check for any underflow reset conditions */
1596                 for (i = 0; i< DC_N_WINDOWS; i++) {
1597                         if (dc->underflow_mask & (WIN_A_UF_INT <<i)) {
1598                                 dc->windows[i].underflows++;
1599
1600 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1601                                 if (dc->windows[i].underflows > 4)
1602                                         schedule_work(&dc->reset_work);
1603 #endif
1604                         } else {
1605                                 dc->windows[i].underflows = 0;
1606                         }
1607                 }
1608
1609                 if (!dc->underflow_mask) {
1610                         /* If we have no underflow to check, go ahead
1611                            and disable the interrupt */
1612                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1613                         val &= ~V_BLANK_INT;
1614                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1615                 }
1616
1617                 /* Clear the underflow mask now that we've checked it. */
1618                 dc->underflow_mask = 0;
1619
1620                 /* Schedule any additional bottom-half vblank actvities. */
1621                 schedule_work(&dc->vblank_work);
1622
1623                 /* Mark the vblank as complete. */
1624                 complete(&dc->vblank_complete);
1625         }
1626
1627         if (status & FRAME_END_INT) {
1628                 int completed = 0;
1629                 int dirty = 0;
1630
1631                 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1632                 for (i = 0; i < DC_N_WINDOWS; i++) {
1633                         if (!(val & (WIN_A_UPDATE << i))) {
1634                                 dc->windows[i].dirty = 0;
1635                                 completed = 1;
1636                         } else {
1637                                 dirty = 1;
1638                         }
1639                 }
1640
1641                 if (!dirty) {
1642                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1643                         val &= ~FRAME_END_INT;
1644                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1645                 }
1646
1647                 if (completed) {
1648                         if (!dirty) {
1649                                 /* With the last completed window, go ahead
1650                                    and enable the vblank interrupt for nvsd. */
1651                                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1652                                 val |= V_BLANK_INT;
1653                                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1654
1655                                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1656                                 val |= V_BLANK_INT;
1657                                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1658                         }
1659
1660                         /* Wake up the workqueue regardless. */
1661                         wake_up(&dc->wq);
1662                 }
1663         }
1664
1665         return IRQ_HANDLED;
1666 #else /* CONFIG_TEGRA_SILICON_PLATFORM */
1667         return IRQ_NONE;
1668 #endif /* !CONFIG_TEGRA_SILICON_PLATFORM */
1669 }
1670
1671 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1672 {
1673         u32 color_control;
1674
1675         switch (dc->out->depth) {
1676         case 3:
1677                 color_control = BASE_COLOR_SIZE111;
1678                 break;
1679
1680         case 6:
1681                 color_control = BASE_COLOR_SIZE222;
1682                 break;
1683
1684         case 8:
1685                 color_control = BASE_COLOR_SIZE332;
1686                 break;
1687
1688         case 9:
1689                 color_control = BASE_COLOR_SIZE333;
1690                 break;
1691
1692         case 12:
1693                 color_control = BASE_COLOR_SIZE444;
1694                 break;
1695
1696         case 15:
1697                 color_control = BASE_COLOR_SIZE555;
1698                 break;
1699
1700         case 16:
1701                 color_control = BASE_COLOR_SIZE565;
1702                 break;
1703
1704         case 18:
1705                 color_control = BASE_COLOR_SIZE666;
1706                 break;
1707
1708         default:
1709                 color_control = BASE_COLOR_SIZE888;
1710                 break;
1711         }
1712
1713         switch (dc->out->dither) {
1714         case TEGRA_DC_DISABLE_DITHER:
1715                 color_control |= DITHER_CONTROL_DISABLE;
1716                 break;
1717         case TEGRA_DC_ORDERED_DITHER:
1718                 color_control |= DITHER_CONTROL_ORDERED;
1719                 break;
1720         case TEGRA_DC_ERRDIFF_DITHER:
1721                 /* The line buffer for error-diffusion dither is limited
1722                  * to 640 pixels per line. This limits the maximum
1723                  * horizontal active area size to 640 pixels when error
1724                  * diffusion is enabled.
1725                  */
1726                 BUG_ON(dc->mode.h_active > 640);
1727                 color_control |= DITHER_CONTROL_ERRDIFF;
1728                 break;
1729         }
1730
1731         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1732 }
1733
1734 static void tegra_dc_init(struct tegra_dc *dc)
1735 {
1736         u32 disp_syncpt = 0;
1737         u32 vblank_syncpt = 0;
1738         int i;
1739
1740         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1741         if (dc->ndev->id == 0) {
1742                 disp_syncpt = NVSYNCPT_DISP0;
1743                 vblank_syncpt = NVSYNCPT_VBLANK0;
1744
1745                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1746                                       TEGRA_MC_PRIO_MED);
1747                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1748                                       TEGRA_MC_PRIO_MED);
1749                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1750                                       TEGRA_MC_PRIO_MED);
1751                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1752                                       TEGRA_MC_PRIO_MED);
1753                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1754                                       TEGRA_MC_PRIO_HIGH);
1755         } else if (dc->ndev->id == 1) {
1756                 disp_syncpt = NVSYNCPT_DISP1;
1757                 vblank_syncpt = NVSYNCPT_VBLANK1;
1758
1759                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1760                                       TEGRA_MC_PRIO_MED);
1761                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1762                                       TEGRA_MC_PRIO_MED);
1763                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1764                                       TEGRA_MC_PRIO_MED);
1765                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1766                                       TEGRA_MC_PRIO_MED);
1767                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1768                                       TEGRA_MC_PRIO_HIGH);
1769         }
1770         tegra_dc_writel(dc, 0x00000100 | vblank_syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1771         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1772         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1773         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1774         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1775
1776         tegra_dc_writel(dc, (FRAME_END_INT |
1777                              V_BLANK_INT |
1778                              WIN_A_UF_INT |
1779                              WIN_B_UF_INT |
1780                              WIN_C_UF_INT), DC_CMD_INT_MASK);
1781         tegra_dc_writel(dc, (WIN_A_UF_INT |
1782                              WIN_B_UF_INT |
1783                              WIN_C_UF_INT), DC_CMD_INT_ENABLE);
1784
1785         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1786
1787         tegra_dc_set_color_control(dc);
1788         for (i = 0; i < DC_N_WINDOWS; i++) {
1789                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1790                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1791                 tegra_dc_set_csc(dc);
1792                 tegra_dc_set_scaling_filter(dc);
1793         }
1794
1795
1796         dc->syncpt_id = disp_syncpt;
1797
1798         dc->syncpt_min = dc->syncpt_max =
1799                 nvhost_syncpt_read(&dc->ndev->host->syncpt, disp_syncpt);
1800
1801         print_mode(dc, &dc->mode, __func__);
1802
1803         if (dc->mode.pclk)
1804                 tegra_dc_program_mode(dc, &dc->mode);
1805
1806         /* Initialize SD AFTER the modeset.
1807            nvsd_init handles the sd_settings = NULL case. */
1808         nvsd_init(dc, dc->out->sd_settings);
1809 }
1810
1811 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1812 {
1813         if (dc->out->enable)
1814                 dc->out->enable();
1815
1816         tegra_dc_setup_clk(dc, dc->clk);
1817         tegra_periph_reset_assert(dc->clk);
1818         clk_enable(dc->clk);
1819         clk_enable(dc->emc_clk);
1820         enable_dc_irq(dc->irq);
1821
1822         tegra_dc_init(dc);
1823
1824         if (dc->out_ops && dc->out_ops->enable)
1825                 dc->out_ops->enable(dc);
1826
1827         if (dc->out->out_pins)
1828                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1829                                             dc->out->n_out_pins);
1830
1831         if (dc->out->postpoweron)
1832                 dc->out->postpoweron();
1833
1834         /* force a full blending update */
1835         dc->blend.z[0] = -1;
1836
1837         return true;
1838 }
1839
1840 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1841 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1842 {
1843         if (dc->out->enable)
1844                 dc->out->enable();
1845
1846         tegra_dc_setup_clk(dc, dc->clk);
1847         clk_enable(dc->clk);
1848         clk_enable(dc->emc_clk);
1849
1850         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1851                 mutex_lock(&tegra_dcs[1]->lock);
1852                 disable_irq(tegra_dcs[1]->irq);
1853         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1854                 mutex_lock(&tegra_dcs[0]->lock);
1855                 disable_irq(tegra_dcs[0]->irq);
1856         }
1857
1858         msleep(5);
1859         tegra_periph_reset_assert(dc->clk);
1860         msleep(2);
1861 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1862         tegra_periph_reset_deassert(dc->clk);
1863         msleep(1);
1864 #endif
1865
1866         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1867                 enable_dc_irq(tegra_dcs[1]->irq);
1868                 mutex_unlock(&tegra_dcs[1]->lock);
1869         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1870                 enable_dc_irq(tegra_dcs[0]->irq);
1871                 mutex_unlock(&tegra_dcs[0]->lock);
1872         }
1873
1874         enable_dc_irq(dc->irq);
1875
1876         tegra_dc_init(dc);
1877
1878         if (dc->out_ops && dc->out_ops->enable)
1879                 dc->out_ops->enable(dc);
1880
1881         if (dc->out->out_pins)
1882                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1883                                             dc->out->n_out_pins);
1884
1885         if (dc->out->postpoweron)
1886                 dc->out->postpoweron();
1887
1888         /* force a full blending update */
1889         dc->blend.z[0] = -1;
1890
1891         return true;
1892 }
1893 #endif
1894
1895 static bool _tegra_dc_enable(struct tegra_dc *dc)
1896 {
1897         if (dc->mode.pclk == 0)
1898                 return false;
1899
1900         if (!dc->out)
1901                 return false;
1902
1903         tegra_dc_io_start(dc);
1904
1905         return _tegra_dc_controller_enable(dc);
1906 }
1907
1908 void tegra_dc_enable(struct tegra_dc *dc)
1909 {
1910         mutex_lock(&dc->lock);
1911
1912         if (!dc->enabled)
1913                 dc->enabled = _tegra_dc_enable(dc);
1914
1915         mutex_unlock(&dc->lock);
1916 }
1917
1918 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1919 {
1920         disable_irq(dc->irq);
1921
1922         if (dc->out_ops && dc->out_ops->disable)
1923                 dc->out_ops->disable(dc);
1924
1925         clk_disable(dc->emc_clk);
1926         clk_disable(dc->clk);
1927         tegra_dvfs_set_rate(dc->clk, 0);
1928
1929         if (dc->out && dc->out->disable)
1930                 dc->out->disable();
1931
1932         /* flush any pending syncpt waits */
1933         while (dc->syncpt_min < dc->syncpt_max) {
1934                 dc->syncpt_min++;
1935                 nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt, dc->syncpt_id);
1936         }
1937 }
1938
1939 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1940 {
1941 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1942         u32 val;
1943         if (dc->enabled)  {
1944                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1945                 if (enable)
1946                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1947                 else
1948                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1949                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1950         }
1951 #endif
1952 }
1953
1954 bool tegra_dc_stats_get(struct tegra_dc *dc)
1955 {
1956 #if 0 /* right now it is always enabled */
1957         u32 val;
1958         bool res;
1959
1960         if (dc->enabled)  {
1961                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1962                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1963         } else {
1964                 res = false;
1965         }
1966
1967         return res;
1968 #endif
1969         return true;
1970 }
1971
1972 static void _tegra_dc_disable(struct tegra_dc *dc)
1973 {
1974         _tegra_dc_controller_disable(dc);
1975         tegra_dc_io_end(dc);
1976 }
1977
1978 void tegra_dc_disable(struct tegra_dc *dc)
1979 {
1980         if (dc->overlay)
1981                 tegra_overlay_disable(dc->overlay);
1982
1983         mutex_lock(&dc->lock);
1984
1985         if (dc->enabled) {
1986                 dc->enabled = false;
1987
1988                 if (!dc->suspended)
1989                         _tegra_dc_disable(dc);
1990         }
1991
1992         mutex_unlock(&dc->lock);
1993 }
1994
1995 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1996 static void tegra_dc_reset_worker(struct work_struct *work)
1997 {
1998         struct tegra_dc *dc =
1999                 container_of(work, struct tegra_dc, reset_work);
2000
2001         unsigned long val = 0;
2002
2003         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2004
2005         mutex_lock(&shared_lock);
2006         mutex_lock(&dc->lock);
2007
2008         if (dc->enabled == false)
2009                 goto unlock;
2010
2011         dc->enabled = false;
2012
2013         /*
2014          * off host read bus
2015          */
2016         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2017         val &= ~(0x00000100);
2018         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2019
2020         /*
2021          * set DC to STOP mode
2022          */
2023         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2024
2025         msleep(10);
2026
2027         _tegra_dc_controller_disable(dc);
2028
2029         /* _tegra_dc_controller_reset_enable deasserts reset */
2030         _tegra_dc_controller_reset_enable(dc);
2031
2032         dc->enabled = true;
2033 unlock:
2034         mutex_unlock(&dc->lock);
2035         mutex_unlock(&shared_lock);
2036 }
2037 #endif
2038
2039
2040 static int tegra_dc_probe(struct nvhost_device *ndev)
2041 {
2042         struct tegra_dc *dc;
2043         struct clk *clk;
2044         struct clk *emc_clk;
2045         struct resource *res;
2046         struct resource *base_res;
2047         struct resource *fb_mem = NULL;
2048         int ret = 0;
2049         void __iomem *base;
2050         int irq;
2051         int i;
2052
2053         if (!ndev->dev.platform_data) {
2054                 dev_err(&ndev->dev, "no platform data\n");
2055                 return -ENOENT;
2056         }
2057
2058         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2059         if (!dc) {
2060                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2061                 return -ENOMEM;
2062         }
2063
2064         irq = nvhost_get_irq_byname(ndev, "irq");
2065         if (irq <= 0) {
2066                 dev_err(&ndev->dev, "no irq\n");
2067                 ret = -ENOENT;
2068                 goto err_free;
2069         }
2070
2071         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2072         if (!res) {
2073                 dev_err(&ndev->dev, "no mem resource\n");
2074                 ret = -ENOENT;
2075                 goto err_free;
2076         }
2077
2078         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2079         if (!base_res) {
2080                 dev_err(&ndev->dev, "request_mem_region failed\n");
2081                 ret = -EBUSY;
2082                 goto err_free;
2083         }
2084
2085         base = ioremap(res->start, resource_size(res));
2086         if (!base) {
2087                 dev_err(&ndev->dev, "registers can't be mapped\n");
2088                 ret = -EBUSY;
2089                 goto err_release_resource_reg;
2090         }
2091
2092         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2093
2094         clk = clk_get(&ndev->dev, NULL);
2095         if (IS_ERR_OR_NULL(clk)) {
2096                 dev_err(&ndev->dev, "can't get clock\n");
2097                 ret = -ENOENT;
2098                 goto err_iounmap_reg;
2099         }
2100
2101         emc_clk = clk_get(&ndev->dev, "emc");
2102         if (IS_ERR_OR_NULL(emc_clk)) {
2103                 dev_err(&ndev->dev, "can't get emc clock\n");
2104                 ret = -ENOENT;
2105                 goto err_put_clk;
2106         }
2107
2108         dc->clk = clk;
2109         dc->emc_clk = emc_clk;
2110
2111         dc->base_res = base_res;
2112         dc->base = base;
2113         dc->irq = irq;
2114         dc->ndev = ndev;
2115         dc->pdata = ndev->dev.platform_data;
2116
2117         /*
2118          * The emc is a shared clock, it will be set based on
2119          * the requirements for each user on the bus.
2120          */
2121         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2122         clk_set_rate(emc_clk, dc->emc_clk_rate);
2123
2124         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2125                 dc->enabled = true;
2126
2127         mutex_init(&dc->lock);
2128         init_completion(&dc->vblank_complete);
2129         init_waitqueue_head(&dc->wq);
2130 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2131         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2132 #endif
2133         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2134
2135         dc->n_windows = DC_N_WINDOWS;
2136         for (i = 0; i < dc->n_windows; i++) {
2137                 dc->windows[i].idx = i;
2138                 dc->windows[i].dc = dc;
2139         }
2140
2141         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2142                         dev_name(&ndev->dev), dc)) {
2143                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2144                 ret = -EBUSY;
2145                 goto err_put_emc_clk;
2146         }
2147
2148         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2149         disable_dc_irq(dc->irq);
2150
2151         ret = tegra_dc_set(dc, ndev->id);
2152         if (ret < 0) {
2153                 dev_err(&ndev->dev, "can't add dc\n");
2154                 goto err_free_irq;
2155         }
2156
2157         nvhost_set_drvdata(ndev, dc);
2158
2159         if (dc->pdata->default_out)
2160                 tegra_dc_set_out(dc, dc->pdata->default_out);
2161         else
2162                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2163
2164         mutex_lock(&dc->lock);
2165         if (dc->enabled)
2166                 _tegra_dc_enable(dc);
2167         mutex_unlock(&dc->lock);
2168
2169         tegra_dc_create_debugfs(dc);
2170
2171         dev_info(&ndev->dev, "probed\n");
2172
2173         if (dc->pdata->fb) {
2174                 if (dc->pdata->fb->bits_per_pixel == -1) {
2175                         unsigned long fmt;
2176                         tegra_dc_writel(dc,
2177                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2178                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2179
2180                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2181                         dc->pdata->fb->bits_per_pixel =
2182                                 tegra_dc_fmt_bpp(fmt);
2183                 }
2184
2185                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2186                 if (IS_ERR_OR_NULL(dc->fb))
2187                         dc->fb = NULL;
2188         }
2189
2190         if (dc->fb) {
2191                 dc->overlay = tegra_overlay_register(ndev, dc);
2192                 if (IS_ERR_OR_NULL(dc->overlay))
2193                         dc->overlay = NULL;
2194         }
2195
2196         if (dc->out && dc->out->hotplug_init)
2197                 dc->out->hotplug_init();
2198
2199         if (dc->out_ops && dc->out_ops->detect)
2200                 dc->out_ops->detect(dc);
2201
2202         tegra_dc_create_sysfs(&dc->ndev->dev);
2203
2204         return 0;
2205
2206 err_free_irq:
2207         free_irq(irq, dc);
2208 err_put_emc_clk:
2209         clk_put(emc_clk);
2210 err_put_clk:
2211         clk_put(clk);
2212 err_iounmap_reg:
2213         iounmap(base);
2214         if (fb_mem)
2215                 release_resource(fb_mem);
2216 err_release_resource_reg:
2217         release_resource(base_res);
2218 err_free:
2219         kfree(dc);
2220
2221         return ret;
2222 }
2223
2224 static int tegra_dc_remove(struct nvhost_device *ndev)
2225 {
2226         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2227
2228         tegra_dc_remove_sysfs(&dc->ndev->dev);
2229         tegra_dc_remove_debugfs(dc);
2230
2231         if (dc->overlay) {
2232                 tegra_overlay_unregister(dc->overlay);
2233         }
2234
2235         if (dc->fb) {
2236                 tegra_fb_unregister(dc->fb);
2237                 if (dc->fb_mem)
2238                         release_resource(dc->fb_mem);
2239         }
2240
2241
2242         if (dc->enabled)
2243                 _tegra_dc_disable(dc);
2244
2245         free_irq(dc->irq, dc);
2246         clk_put(dc->emc_clk);
2247         clk_put(dc->clk);
2248         iounmap(dc->base);
2249         if (dc->fb_mem)
2250                 release_resource(dc->base_res);
2251         kfree(dc);
2252         tegra_dc_set(NULL, ndev->id);
2253         return 0;
2254 }
2255
2256 #ifdef CONFIG_PM
2257 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2258 {
2259         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2260
2261         dev_info(&ndev->dev, "suspend\n");
2262
2263         if (dc->overlay)
2264                 tegra_overlay_disable(dc->overlay);
2265
2266         mutex_lock(&dc->lock);
2267
2268         if (dc->out_ops && dc->out_ops->suspend)
2269                 dc->out_ops->suspend(dc);
2270
2271         if (dc->enabled) {
2272                 tegra_fb_suspend(dc->fb);
2273                 _tegra_dc_disable(dc);
2274
2275                 dc->suspended = true;
2276         }
2277
2278         if (dc->out && dc->out->postsuspend) {
2279                 dc->out->postsuspend();
2280                 msleep(100); /* avoid resume event due to voltage falling */
2281         }
2282
2283         mutex_unlock(&dc->lock);
2284
2285         return 0;
2286 }
2287
2288 static int tegra_dc_resume(struct nvhost_device *ndev)
2289 {
2290         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2291
2292         dev_info(&ndev->dev, "resume\n");
2293
2294         mutex_lock(&dc->lock);
2295         dc->suspended = false;
2296
2297         if (dc->enabled)
2298                 _tegra_dc_enable(dc);
2299
2300         if (dc->out && dc->out->hotplug_init)
2301                 dc->out->hotplug_init();
2302
2303         if (dc->out_ops && dc->out_ops->resume)
2304                 dc->out_ops->resume(dc);
2305         mutex_unlock(&dc->lock);
2306
2307         return 0;
2308 }
2309
2310 #endif /* CONFIG_PM */
2311
2312 extern int suspend_set(const char *val, struct kernel_param *kp)
2313 {
2314         if (!strcmp(val, "dump"))
2315                 dump_regs(tegra_dcs[0]);
2316 #ifdef CONFIG_PM
2317         else if (!strcmp(val, "suspend"))
2318                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2319         else if (!strcmp(val, "resume"))
2320                 tegra_dc_resume(tegra_dcs[0]->ndev);
2321 #endif
2322
2323         return 0;
2324 }
2325
2326 extern int suspend_get(char *buffer, struct kernel_param *kp)
2327 {
2328         return 0;
2329 }
2330
2331 int suspend;
2332
2333 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2334
2335 struct nvhost_driver tegra_dc_driver = {
2336         .driver = {
2337                 .name = "tegradc",
2338                 .owner = THIS_MODULE,
2339         },
2340         .probe = tegra_dc_probe,
2341         .remove = tegra_dc_remove,
2342 #ifdef CONFIG_PM
2343         .suspend = tegra_dc_suspend,
2344         .resume = tegra_dc_resume,
2345 #endif
2346 };
2347
2348 static int __init tegra_dc_module_init(void)
2349 {
2350         return nvhost_driver_register(&tegra_dc_driver);
2351 }
2352
2353 static void __exit tegra_dc_module_exit(void)
2354 {
2355         nvhost_driver_unregister(&tegra_dc_driver);
2356 }
2357
2358 module_exit(tegra_dc_module_exit);
2359 module_init(tegra_dc_module_init);