video: tegra: dc: log suspend enter time
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2013, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
67         .refresh = 60,
68         .xres = 640,
69         .yres = 480,
70         .pixclock = KHZ2PICOS(25200),
71         .hsync_len = 96,        /* h_sync_width */
72         .vsync_len = 2,         /* v_sync_width */
73         .left_margin = 48,      /* h_back_porch */
74         .upper_margin = 33,     /* v_back_porch */
75         .right_margin = 16,     /* h_front_porch */
76         .lower_margin = 10,     /* v_front_porch */
77         .vmode = 0,
78         .sync = 0,
79 };
80
81 static struct tegra_dc_mode override_disp_mode[3];
82
83 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
84
85 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
86
87 DEFINE_MUTEX(tegra_dc_lock);
88 DEFINE_MUTEX(shared_lock);
89
90 static const struct {
91         bool h;
92         bool v;
93 } can_filter[] = {
94         /* Window A has no filtering */
95         { false, false },
96         /* Window B has both H and V filtering */
97         { true,  true  },
98         /* Window C has only H filtering */
99         { false, true  },
100 };
101
102 #ifdef CONFIG_TEGRA_DC_CMU
103 static struct tegra_dc_cmu default_cmu = {
104         /* lut1 maps sRGB to linear space. */
105         {
106                 0,    1,    2,    4,    5,    6,    7,    9,
107                 10,   11,   12,   14,   15,   16,   18,   20,
108                 21,   23,   25,   27,   29,   31,   33,   35,
109                 37,   40,   42,   45,   48,   50,   53,   56,
110                 59,   62,   66,   69,   72,   76,   79,   83,
111                 87,   91,   95,   99,   103,  107,  112,  116,
112                 121,  126,  131,  136,  141,  146,  151,  156,
113                 162,  168,  173,  179,  185,  191,  197,  204,
114                 210,  216,  223,  230,  237,  244,  251,  258,
115                 265,  273,  280,  288,  296,  304,  312,  320,
116                 329,  337,  346,  354,  363,  372,  381,  390,
117                 400,  409,  419,  428,  438,  448,  458,  469,
118                 479,  490,  500,  511,  522,  533,  544,  555,
119                 567,  578,  590,  602,  614,  626,  639,  651,
120                 664,  676,  689,  702,  715,  728,  742,  755,
121                 769,  783,  797,  811,  825,  840,  854,  869,
122                 884,  899,  914,  929,  945,  960,  976,  992,
123                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
124                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
125                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
126                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
127                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
128                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
129                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
130                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
131                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
132                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
133                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
134                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
135                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
136                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
137                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
138         },
139         /* csc */
140         {
141                 0x100, 0x0,   0x0,
142                 0x0,   0x100, 0x0,
143                 0x0,   0x0,   0x100,
144         },
145         /* lut2 maps linear space to sRGB*/
146         {
147                 0,    1,    2,    2,    3,    4,    5,    6,
148                 6,    7,    8,    9,    10,   10,   11,   12,
149                 13,   13,   14,   15,   15,   16,   16,   17,
150                 18,   18,   19,   19,   20,   20,   21,   21,
151                 22,   22,   23,   23,   23,   24,   24,   25,
152                 25,   25,   26,   26,   27,   27,   27,   28,
153                 28,   29,   29,   29,   30,   30,   30,   31,
154                 31,   31,   32,   32,   32,   33,   33,   33,
155                 34,   34,   34,   34,   35,   35,   35,   36,
156                 36,   36,   37,   37,   37,   37,   38,   38,
157                 38,   38,   39,   39,   39,   40,   40,   40,
158                 40,   41,   41,   41,   41,   42,   42,   42,
159                 42,   43,   43,   43,   43,   43,   44,   44,
160                 44,   44,   45,   45,   45,   45,   46,   46,
161                 46,   46,   46,   47,   47,   47,   47,   48,
162                 48,   48,   48,   48,   49,   49,   49,   49,
163                 49,   50,   50,   50,   50,   50,   51,   51,
164                 51,   51,   51,   52,   52,   52,   52,   52,
165                 53,   53,   53,   53,   53,   54,   54,   54,
166                 54,   54,   55,   55,   55,   55,   55,   55,
167                 56,   56,   56,   56,   56,   57,   57,   57,
168                 57,   57,   57,   58,   58,   58,   58,   58,
169                 58,   59,   59,   59,   59,   59,   59,   60,
170                 60,   60,   60,   60,   60,   61,   61,   61,
171                 61,   61,   61,   62,   62,   62,   62,   62,
172                 62,   63,   63,   63,   63,   63,   63,   64,
173                 64,   64,   64,   64,   64,   64,   65,   65,
174                 65,   65,   65,   65,   66,   66,   66,   66,
175                 66,   66,   66,   67,   67,   67,   67,   67,
176                 67,   67,   68,   68,   68,   68,   68,   68,
177                 68,   69,   69,   69,   69,   69,   69,   69,
178                 70,   70,   70,   70,   70,   70,   70,   71,
179                 71,   71,   71,   71,   71,   71,   72,   72,
180                 72,   72,   72,   72,   72,   72,   73,   73,
181                 73,   73,   73,   73,   73,   74,   74,   74,
182                 74,   74,   74,   74,   74,   75,   75,   75,
183                 75,   75,   75,   75,   75,   76,   76,   76,
184                 76,   76,   76,   76,   77,   77,   77,   77,
185                 77,   77,   77,   77,   78,   78,   78,   78,
186                 78,   78,   78,   78,   78,   79,   79,   79,
187                 79,   79,   79,   79,   79,   80,   80,   80,
188                 80,   80,   80,   80,   80,   81,   81,   81,
189                 81,   81,   81,   81,   81,   81,   82,   82,
190                 82,   82,   82,   82,   82,   82,   83,   83,
191                 83,   83,   83,   83,   83,   83,   83,   84,
192                 84,   84,   84,   84,   84,   84,   84,   84,
193                 85,   85,   85,   85,   85,   85,   85,   85,
194                 85,   86,   86,   86,   86,   86,   86,   86,
195                 86,   86,   87,   87,   87,   87,   87,   87,
196                 87,   87,   87,   88,   88,   88,   88,   88,
197                 88,   88,   88,   88,   88,   89,   89,   89,
198                 89,   89,   89,   89,   89,   89,   90,   90,
199                 90,   90,   90,   90,   90,   90,   90,   90,
200                 91,   91,   91,   91,   91,   91,   91,   91,
201                 91,   91,   92,   92,   92,   92,   92,   92,
202                 92,   92,   92,   92,   93,   93,   93,   93,
203                 93,   93,   93,   93,   93,   93,   94,   94,
204                 94,   94,   94,   94,   94,   94,   94,   94,
205                 95,   95,   95,   95,   95,   95,   95,   95,
206                 95,   95,   96,   96,   96,   96,   96,   96,
207                 96,   96,   96,   96,   96,   97,   97,   97,
208                 97,   97,   97,   97,   97,   97,   97,   98,
209                 98,   98,   98,   98,   98,   98,   98,   98,
210                 98,   98,   99,   99,   99,   99,   99,   99,
211                 99,   100,  101,  101,  102,  103,  103,  104,
212                 105,  105,  106,  107,  107,  108,  109,  109,
213                 110,  111,  111,  112,  113,  113,  114,  115,
214                 115,  116,  116,  117,  118,  118,  119,  119,
215                 120,  120,  121,  122,  122,  123,  123,  124,
216                 124,  125,  126,  126,  127,  127,  128,  128,
217                 129,  129,  130,  130,  131,  131,  132,  132,
218                 133,  133,  134,  134,  135,  135,  136,  136,
219                 137,  137,  138,  138,  139,  139,  140,  140,
220                 141,  141,  142,  142,  143,  143,  144,  144,
221                 145,  145,  145,  146,  146,  147,  147,  148,
222                 148,  149,  149,  150,  150,  150,  151,  151,
223                 152,  152,  153,  153,  153,  154,  154,  155,
224                 155,  156,  156,  156,  157,  157,  158,  158,
225                 158,  159,  159,  160,  160,  160,  161,  161,
226                 162,  162,  162,  163,  163,  164,  164,  164,
227                 165,  165,  166,  166,  166,  167,  167,  167,
228                 168,  168,  169,  169,  169,  170,  170,  170,
229                 171,  171,  172,  172,  172,  173,  173,  173,
230                 174,  174,  174,  175,  175,  176,  176,  176,
231                 177,  177,  177,  178,  178,  178,  179,  179,
232                 179,  180,  180,  180,  181,  181,  182,  182,
233                 182,  183,  183,  183,  184,  184,  184,  185,
234                 185,  185,  186,  186,  186,  187,  187,  187,
235                 188,  188,  188,  189,  189,  189,  189,  190,
236                 190,  190,  191,  191,  191,  192,  192,  192,
237                 193,  193,  193,  194,  194,  194,  195,  195,
238                 195,  196,  196,  196,  196,  197,  197,  197,
239                 198,  198,  198,  199,  199,  199,  200,  200,
240                 200,  200,  201,  201,  201,  202,  202,  202,
241                 202,  203,  203,  203,  204,  204,  204,  205,
242                 205,  205,  205,  206,  206,  206,  207,  207,
243                 207,  207,  208,  208,  208,  209,  209,  209,
244                 209,  210,  210,  210,  211,  211,  211,  211,
245                 212,  212,  212,  213,  213,  213,  213,  214,
246                 214,  214,  214,  215,  215,  215,  216,  216,
247                 216,  216,  217,  217,  217,  217,  218,  218,
248                 218,  219,  219,  219,  219,  220,  220,  220,
249                 220,  221,  221,  221,  221,  222,  222,  222,
250                 223,  223,  223,  223,  224,  224,  224,  224,
251                 225,  225,  225,  225,  226,  226,  226,  226,
252                 227,  227,  227,  227,  228,  228,  228,  228,
253                 229,  229,  229,  229,  230,  230,  230,  230,
254                 231,  231,  231,  231,  232,  232,  232,  232,
255                 233,  233,  233,  233,  234,  234,  234,  234,
256                 235,  235,  235,  235,  236,  236,  236,  236,
257                 237,  237,  237,  237,  238,  238,  238,  238,
258                 239,  239,  239,  239,  240,  240,  240,  240,
259                 240,  241,  241,  241,  241,  242,  242,  242,
260                 242,  243,  243,  243,  243,  244,  244,  244,
261                 244,  244,  245,  245,  245,  245,  246,  246,
262                 246,  246,  247,  247,  247,  247,  247,  248,
263                 248,  248,  248,  249,  249,  249,  249,  249,
264                 250,  250,  250,  250,  251,  251,  251,  251,
265                 251,  252,  252,  252,  252,  253,  253,  253,
266                 253,  253,  254,  254,  254,  254,  255,  255,
267         },
268 };
269 #endif
270
271 void tegra_dc_clk_enable(struct tegra_dc *dc)
272 {
273         if (!tegra_is_clk_enabled(dc->clk)) {
274                 clk_prepare_enable(dc->clk);
275                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
276         }
277 }
278
279 void tegra_dc_clk_disable(struct tegra_dc *dc)
280 {
281         if (tegra_is_clk_enabled(dc->clk)) {
282                 clk_disable_unprepare(dc->clk);
283                 tegra_dvfs_set_rate(dc->clk, 0);
284         }
285 }
286
287 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
288 {
289         /* extra reference to dc clk */
290         clk_prepare_enable(dc->clk);
291
292         if (dc->out_ops->hold)
293                 dc->out_ops->hold(dc);
294 }
295
296 void tegra_dc_release_dc_out(struct tegra_dc *dc)
297 {
298         if (dc->out_ops->release)
299                 dc->out_ops->release(dc);
300
301         /* balance extra dc clk reference */
302         clk_disable_unprepare(dc->clk);
303 }
304
305 #define DUMP_REG(a) do {                        \
306         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
307                  #a, a, tegra_dc_readl(dc, a));               \
308         print(data, buff);                                    \
309         } while (0)
310
311 static void _dump_regs(struct tegra_dc *dc, void *data,
312                        void (* print)(void *data, const char *str))
313 {
314         int i;
315         char buff[256];
316
317         mutex_lock(&dc->lock);
318         tegra_dc_io_start(dc);
319         tegra_dc_hold_dc_out(dc);
320
321         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
322         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE);
324         DUMP_REG(DC_CMD_INT_STATUS);
325         DUMP_REG(DC_CMD_INT_MASK);
326         DUMP_REG(DC_CMD_INT_ENABLE);
327         DUMP_REG(DC_CMD_INT_TYPE);
328         DUMP_REG(DC_CMD_INT_POLARITY);
329         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
330         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
331         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
332         DUMP_REG(DC_CMD_STATE_ACCESS);
333         DUMP_REG(DC_CMD_STATE_CONTROL);
334         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
335         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
336
337         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
338         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
339         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
340         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
341         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
342         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
343         DUMP_REG(DC_DISP_REF_TO_SYNC);
344         DUMP_REG(DC_DISP_SYNC_WIDTH);
345         DUMP_REG(DC_DISP_BACK_PORCH);
346         DUMP_REG(DC_DISP_DISP_ACTIVE);
347         DUMP_REG(DC_DISP_FRONT_PORCH);
348         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
349         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
350         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
351         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
352         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
353         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
354         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
355         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
356         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
357         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
358         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
359         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
360         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
361         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
362         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
363         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
364         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
365         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
366         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
367         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
369         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
370         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
371         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
372         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
373         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
374         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
375         DUMP_REG(DC_DISP_M0_CONTROL);
376         DUMP_REG(DC_DISP_M1_CONTROL);
377         DUMP_REG(DC_DISP_DI_CONTROL);
378         DUMP_REG(DC_DISP_PP_CONTROL);
379         DUMP_REG(DC_DISP_PP_SELECT_A);
380         DUMP_REG(DC_DISP_PP_SELECT_B);
381         DUMP_REG(DC_DISP_PP_SELECT_C);
382         DUMP_REG(DC_DISP_PP_SELECT_D);
383         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
384         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
385         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
386         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
387         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
388         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
389         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
390         DUMP_REG(DC_DISP_BORDER_COLOR);
391         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
392         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
393         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
394         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
395         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
396         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
397         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
398         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
399         DUMP_REG(DC_DISP_CURSOR_POSITION);
400         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
401         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
402         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
403         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
404         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
405         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
406         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
407         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
408         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
409         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
410 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
411         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
412 #endif
413         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
414         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
415
416
417         for (i = 0; i < 3; i++) {
418                 print(data, "\n");
419                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
420                 print(data, buff);
421
422                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
423                                 DC_CMD_DISPLAY_WINDOW_HEADER);
424                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
425                 DUMP_REG(DC_WIN_WIN_OPTIONS);
426                 DUMP_REG(DC_WIN_BYTE_SWAP);
427                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
428                 DUMP_REG(DC_WIN_COLOR_DEPTH);
429                 DUMP_REG(DC_WIN_POSITION);
430                 DUMP_REG(DC_WIN_SIZE);
431                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
432                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
433                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
434                 DUMP_REG(DC_WIN_DDA_INCREMENT);
435                 DUMP_REG(DC_WIN_LINE_STRIDE);
436 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
437                 DUMP_REG(DC_WIN_BUF_STRIDE);
438                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
439 #endif
440                 DUMP_REG(DC_WIN_BLEND_NOKEY);
441                 DUMP_REG(DC_WIN_BLEND_1WIN);
442                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
443                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
444                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
445                 DUMP_REG(DC_WINBUF_START_ADDR);
446                 DUMP_REG(DC_WINBUF_START_ADDR_U);
447                 DUMP_REG(DC_WINBUF_START_ADDR_V);
448                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
449                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
450                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
451                 DUMP_REG(DC_WIN_CSC_YOF);
452                 DUMP_REG(DC_WIN_CSC_KYRGB);
453                 DUMP_REG(DC_WIN_CSC_KUR);
454                 DUMP_REG(DC_WIN_CSC_KVR);
455                 DUMP_REG(DC_WIN_CSC_KUG);
456                 DUMP_REG(DC_WIN_CSC_KVG);
457                 DUMP_REG(DC_WIN_CSC_KUB);
458                 DUMP_REG(DC_WIN_CSC_KVB);
459         }
460
461         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
462         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
463         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
464         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
465         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
466         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
467         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
468         DUMP_REG(DC_DISP_M1_CONTROL);
469         DUMP_REG(DC_COM_PM1_CONTROL);
470         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
471         DUMP_REG(DC_DISP_SD_CONTROL);
472 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
473         DUMP_REG(DC_COM_CMU_CSC_KRR);
474         DUMP_REG(DC_COM_CMU_CSC_KGR);
475         DUMP_REG(DC_COM_CMU_CSC_KBR);
476         DUMP_REG(DC_COM_CMU_CSC_KRG);
477         DUMP_REG(DC_COM_CMU_CSC_KGG);
478         DUMP_REG(DC_COM_CMU_CSC_KBR);
479         DUMP_REG(DC_COM_CMU_CSC_KRB);
480         DUMP_REG(DC_COM_CMU_CSC_KGB);
481         DUMP_REG(DC_COM_CMU_CSC_KBB);
482 #endif
483
484         tegra_dc_release_dc_out(dc);
485         tegra_dc_io_end(dc);
486         mutex_unlock(&dc->lock);
487 }
488
489 #undef DUMP_REG
490
491 #ifdef DEBUG
492 static void dump_regs_print(void *data, const char *str)
493 {
494         struct tegra_dc *dc = data;
495         dev_dbg(&dc->ndev->dev, "%s", str);
496 }
497
498 static void dump_regs(struct tegra_dc *dc)
499 {
500         _dump_regs(dc, dc, dump_regs_print);
501 }
502 #else /* !DEBUG */
503
504 static void dump_regs(struct tegra_dc *dc) {}
505
506 #endif /* DEBUG */
507
508 #ifdef CONFIG_DEBUG_FS
509
510 static void dbg_regs_print(void *data, const char *str)
511 {
512         struct seq_file *s = data;
513
514         seq_printf(s, "%s", str);
515 }
516
517 #undef DUMP_REG
518
519 static int dbg_dc_show(struct seq_file *s, void *unused)
520 {
521         struct tegra_dc *dc = s->private;
522
523         _dump_regs(dc, s, dbg_regs_print);
524
525         return 0;
526 }
527
528
529 static int dbg_dc_open(struct inode *inode, struct file *file)
530 {
531         return single_open(file, dbg_dc_show, inode->i_private);
532 }
533
534 static const struct file_operations regs_fops = {
535         .open           = dbg_dc_open,
536         .read           = seq_read,
537         .llseek         = seq_lseek,
538         .release        = single_release,
539 };
540
541 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
542 {
543         struct tegra_dc *dc = s->private;
544         struct tegra_dc_mode *m;
545
546         mutex_lock(&dc->lock);
547         m = &dc->mode;
548         seq_printf(s,
549                 "pclk: %d\n"
550                 "h_ref_to_sync: %d\n"
551                 "v_ref_to_sync: %d\n"
552                 "h_sync_width: %d\n"
553                 "v_sync_width: %d\n"
554                 "h_back_porch: %d\n"
555                 "v_back_porch: %d\n"
556                 "h_active: %d\n"
557                 "v_active: %d\n"
558                 "h_front_porch: %d\n"
559                 "v_front_porch: %d\n"
560                 "stereo_mode: %d\n",
561                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
562                 m->h_sync_width, m->v_sync_width,
563                 m->h_back_porch, m->v_back_porch,
564                 m->h_active, m->v_active,
565                 m->h_front_porch, m->v_front_porch,
566                 m->stereo_mode);
567         mutex_unlock(&dc->lock);
568         return 0;
569 }
570
571 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
572 {
573         return single_open(file, dbg_dc_mode_show, inode->i_private);
574 }
575
576 static const struct file_operations mode_fops = {
577         .open           = dbg_dc_mode_open,
578         .read           = seq_read,
579         .llseek         = seq_lseek,
580         .release        = single_release,
581 };
582
583 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
584 {
585         struct tegra_dc *dc = s->private;
586
587         mutex_lock(&dc->lock);
588         seq_printf(s,
589                 "underflows: %llu\n"
590                 "underflows_a: %llu\n"
591                 "underflows_b: %llu\n"
592                 "underflows_c: %llu\n",
593                 dc->stats.underflows,
594                 dc->stats.underflows_a,
595                 dc->stats.underflows_b,
596                 dc->stats.underflows_c);
597         mutex_unlock(&dc->lock);
598
599         return 0;
600 }
601
602 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
603 {
604         return single_open(file, dbg_dc_stats_show, inode->i_private);
605 }
606
607 static const struct file_operations stats_fops = {
608         .open           = dbg_dc_stats_open,
609         .read           = seq_read,
610         .llseek         = seq_lseek,
611         .release        = single_release,
612 };
613
614 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
615 {
616         if (dc->debugdir)
617                 debugfs_remove_recursive(dc->debugdir);
618         dc->debugdir = NULL;
619 }
620
621 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
622 {
623         struct dentry *retval;
624
625         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
626         if (!dc->debugdir)
627                 goto remove_out;
628
629         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
630                 &regs_fops);
631         if (!retval)
632                 goto remove_out;
633
634         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
635                 &mode_fops);
636         if (!retval)
637                 goto remove_out;
638
639         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
640                 &stats_fops);
641         if (!retval)
642                 goto remove_out;
643
644         return;
645 remove_out:
646         dev_err(&dc->ndev->dev, "could not create debugfs\n");
647         tegra_dc_remove_debugfs(dc);
648 }
649
650 #else /* !CONFIG_DEBUGFS */
651 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
652 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
653 #endif /* CONFIG_DEBUGFS */
654
655 static int tegra_dc_set(struct tegra_dc *dc, int index)
656 {
657         int ret = 0;
658
659         mutex_lock(&tegra_dc_lock);
660         if (index >= TEGRA_MAX_DC) {
661                 ret = -EINVAL;
662                 goto out;
663         }
664
665         if (dc != NULL && tegra_dcs[index] != NULL) {
666                 ret = -EBUSY;
667                 goto out;
668         }
669
670         tegra_dcs[index] = dc;
671
672 out:
673         mutex_unlock(&tegra_dc_lock);
674
675         return ret;
676 }
677
678 unsigned int tegra_dc_has_multiple_dc(void)
679 {
680         unsigned int idx;
681         unsigned int cnt = 0;
682         struct tegra_dc *dc;
683
684         mutex_lock(&tegra_dc_lock);
685         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
686                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
687         mutex_unlock(&tegra_dc_lock);
688
689         return (cnt > 1);
690 }
691
692 /* get the stride size of a window.
693  * return: stride size in bytes for window win. or 0 if unavailble. */
694 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
695 {
696         u32 stride;
697
698         if (!dc->enabled)
699                 return 0;
700         BUG_ON(win > DC_N_WINDOWS);
701         mutex_lock(&dc->lock);
702         tegra_dc_io_start(dc);
703         tegra_dc_hold_dc_out(dc);
704         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
705                 DC_CMD_DISPLAY_WINDOW_HEADER);
706         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
707         tegra_dc_release_dc_out(dc);
708         tegra_dc_io_end(dc);
709         mutex_unlock(&dc->lock);
710         return GET_LINE_STRIDE(stride);
711 }
712 EXPORT_SYMBOL(tegra_dc_get_stride);
713
714 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
715 {
716         if (idx < TEGRA_MAX_DC)
717                 return tegra_dcs[idx];
718         else
719                 return NULL;
720 }
721 EXPORT_SYMBOL(tegra_dc_get_dc);
722
723 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
724 {
725         if (win >= dc->n_windows)
726                 return NULL;
727
728         return &dc->windows[win];
729 }
730 EXPORT_SYMBOL(tegra_dc_get_window);
731
732 bool tegra_dc_get_connected(struct tegra_dc *dc)
733 {
734         return dc->connected;
735 }
736 EXPORT_SYMBOL(tegra_dc_get_connected);
737
738 bool tegra_dc_hpd(struct tegra_dc *dc)
739 {
740         int sense;
741         int level;
742         int hpd;
743
744         if (WARN_ON(!dc || !dc->out))
745                 return false;
746
747         if (dc->out->hotplug_state != 0) {
748                 if (dc->out->hotplug_state == 1) /* force on */
749                         return true;
750                 if (dc->out->hotplug_state == -1) /* force off */
751                         return false;
752         }
753         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
754
755         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
756
757         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
758                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
759
760         if (dc->out->hotplug_report)
761                 dc->out->hotplug_report(hpd);
762
763         return hpd;
764 }
765 EXPORT_SYMBOL(tegra_dc_hpd);
766
767 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
768 {
769         unsigned i;
770         unsigned v0 = 128;
771         unsigned v1 = 0;
772
773         /* linear horizontal and vertical filters */
774         for (i = 0; i < 16; i++) {
775                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
776                                 DC_WIN_H_FILTER_P(i));
777
778                 tegra_dc_writel(dc, v0,
779                                 DC_WIN_V_FILTER_P(i));
780                 v0 -= 8;
781                 v1 += 8;
782         }
783 }
784
785 #ifdef CONFIG_TEGRA_DC_CMU
786 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
787                                         struct tegra_dc_cmu *src_cmu)
788 {
789         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
790 }
791
792 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
793 {
794         u32 val;
795         u32 i;
796
797         for (i = 0; i < 256; i++) {
798                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
799                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
800         }
801
802         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
803         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
804         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
805         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
806         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
807         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
808         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
809         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
810         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
811
812         for (i = 0; i < 960; i++) {
813                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
814                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
815         }
816 }
817
818 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
819 {
820         u32 val;
821         u32 i;
822         bool flags;
823
824         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
825         if (val & CMU_ENABLE)
826                 flags = true;
827
828         val &= ~CMU_ENABLE;
829         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
830         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
831         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
832
833         /*TODO: Sync up with frame end */
834         mdelay(20);
835
836         for (i = 0; i < 256; i++) {
837                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
838                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
839                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
840                 cmu->lut1[i] = LUT1_READ_DATA(val);
841         }
842
843         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
844         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
845         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
846         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
847         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
848         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
849         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
850         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
851         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
852
853         for (i = 0; i < 960; i++) {
854                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
855                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
856                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
857                 cmu->lut2[i] = LUT2_READ_DATA(val);
858         }
859 }
860 EXPORT_SYMBOL(tegra_dc_get_cmu);
861
862 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
863 {
864         u32 val;
865
866         if (dc->pdata->cmu_enable) {
867                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
868         } else {
869                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
870                 return 0;
871         }
872
873         if (cmu != &dc->cmu) {
874                 tegra_dc_cache_cmu(&dc->cmu, cmu);
875
876                 /* Disable CMU */
877                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
878                 if (val & CMU_ENABLE) {
879                         val &= ~CMU_ENABLE;
880                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
881                         val = GENERAL_UPDATE;
882                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
883                         val = GENERAL_ACT_REQ;
884                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
885                         /*TODO: Sync up with vsync */
886                         mdelay(20);
887                 }
888
889                 tegra_dc_set_cmu(dc, &dc->cmu);
890         }
891
892         return 0;
893 }
894
895 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
896 {
897         int ret;
898
899         mutex_lock(&dc->lock);
900         if (!dc->enabled) {
901                 mutex_unlock(&dc->lock);
902                 return 0;
903         }
904         tegra_dc_io_start(dc);
905         tegra_dc_hold_dc_out(dc);
906
907         ret = _tegra_dc_update_cmu(dc, cmu);
908         tegra_dc_set_color_control(dc);
909
910         tegra_dc_release_dc_out(dc);
911         tegra_dc_io_end(dc);
912         mutex_unlock(&dc->lock);
913
914         return ret;
915 }
916 EXPORT_SYMBOL(tegra_dc_update_cmu);
917
918 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
919 {
920         dc->pdata->cmu_enable = cmu_enable;
921         if (dc->pdata->cmu)
922                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
923         else
924                 tegra_dc_update_cmu(dc, &default_cmu);
925 }
926 #else
927 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
928 #define tegra_dc_set_cmu(dc, cmu)
929 #define tegra_dc_update_cmu(dc, cmu)
930 #endif
931
932 /* disable_irq() blocks until handler completes, calling this function while
933  * holding dc->lock can deadlock. */
934 static inline void disable_dc_irq(const struct tegra_dc *dc)
935 {
936         disable_irq(dc->irq);
937 }
938
939 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
940 {
941         return dc->syncpt[i].id;
942 }
943 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
944
945 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
946 {
947         u32 max;
948
949         mutex_lock(&dc->lock);
950         tegra_dc_io_start(dc);
951         tegra_dc_hold_dc_out(dc);
952         max = nvhost_syncpt_incr_max_ext(dc->ndev,
953                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
954         dc->syncpt[i].max = max;
955         tegra_dc_release_dc_out(dc);
956         tegra_dc_io_end(dc);
957         mutex_unlock(&dc->lock);
958
959         return max;
960 }
961
962 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
963 {
964         mutex_lock(&dc->lock);
965         if (dc->enabled) {
966                 tegra_dc_io_start(dc);
967                 tegra_dc_hold_dc_out(dc);
968                 while (dc->syncpt[i].min < val) {
969                         dc->syncpt[i].min++;
970                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
971                 }
972                 tegra_dc_release_dc_out(dc);
973                 tegra_dc_io_end(dc);
974         }
975         mutex_unlock(&dc->lock);
976 }
977
978 void
979 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
980 {
981         unsigned int ctrl;
982         unsigned long out_sel;
983         unsigned long cmd_state;
984
985         mutex_lock(&dc->lock);
986         if (!dc->enabled) {
987                 mutex_unlock(&dc->lock);
988                 return;
989         }
990
991         tegra_dc_io_start(dc);
992         tegra_dc_hold_dc_out(dc);
993
994         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
995                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
996                 cfg->clk_select);
997
998         /* The new value should be effected immediately */
999         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1000         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1001
1002         switch (cfg->which_pwm) {
1003         case TEGRA_PWM_PM0:
1004                 /* Select the LM0 on PM0 */
1005                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1006                 out_sel &= ~(7 << 0);
1007                 out_sel |= (3 << 0);
1008                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1009                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1010                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1011                 break;
1012         case TEGRA_PWM_PM1:
1013                 /* Select the LM1 on PM1 */
1014                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1015                 out_sel &= ~(7 << 4);
1016                 out_sel |= (3 << 4);
1017                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1018                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1019                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1020                 break;
1021         default:
1022                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1023                 break;
1024         }
1025         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1026         tegra_dc_release_dc_out(dc);
1027         tegra_dc_io_end(dc);
1028         mutex_unlock(&dc->lock);
1029 }
1030 EXPORT_SYMBOL(tegra_dc_config_pwm);
1031
1032 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1033                                 const struct tegra_dc_out_pin *pins,
1034                                 const unsigned int n_pins)
1035 {
1036         unsigned int i;
1037
1038         int name;
1039         int pol;
1040
1041         u32 pol1, pol3;
1042
1043         u32 set1, unset1;
1044         u32 set3, unset3;
1045
1046         set1 = set3 = unset1 = unset3 = 0;
1047
1048         for (i = 0; i < n_pins; i++) {
1049                 name = (pins + i)->name;
1050                 pol  = (pins + i)->pol;
1051
1052                 /* set polarity by name */
1053                 switch (name) {
1054                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1055                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1056                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1057                         else
1058                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1059                         break;
1060                 case TEGRA_DC_OUT_PIN_H_SYNC:
1061                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1062                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1063                         else
1064                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1065                         break;
1066                 case TEGRA_DC_OUT_PIN_V_SYNC:
1067                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1068                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1069                         else
1070                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1071                         break;
1072                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1073                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1074                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1075                         else
1076                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1077                         break;
1078                 default:
1079                         printk("Invalid argument in function %s\n",
1080                                __FUNCTION__);
1081                         break;
1082                 }
1083         }
1084
1085         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1086         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1087
1088         pol1 |= set1;
1089         pol1 &= ~unset1;
1090
1091         pol3 |= set3;
1092         pol3 &= ~unset3;
1093
1094         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1095         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1096 }
1097
1098 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1099 {
1100         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1101                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1102                 dc->out->type == TEGRA_DC_OUT_DSI)
1103                 return override_disp_mode[dc->out->type].pclk ?
1104                         &override_disp_mode[dc->out->type] : NULL;
1105         else
1106                 return NULL;
1107 }
1108
1109 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1110 {
1111         struct tegra_dc_mode *mode;
1112
1113         dc->out = out;
1114         mode = tegra_dc_get_override_mode(dc);
1115
1116         if (mode)
1117                 tegra_dc_set_mode(dc, mode);
1118         else if (out->n_modes > 0)
1119                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1120
1121         switch (out->type) {
1122         case TEGRA_DC_OUT_RGB:
1123                 dc->out_ops = &tegra_dc_rgb_ops;
1124                 break;
1125
1126         case TEGRA_DC_OUT_HDMI:
1127                 dc->out_ops = &tegra_dc_hdmi_ops;
1128                 break;
1129
1130         case TEGRA_DC_OUT_DSI:
1131                 dc->out_ops = &tegra_dc_dsi_ops;
1132                 break;
1133
1134         default:
1135                 dc->out_ops = NULL;
1136                 break;
1137         }
1138
1139         if (dc->out_ops && dc->out_ops->init)
1140                 dc->out_ops->init(dc);
1141 }
1142
1143 /* returns on error: -EINVAL
1144  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1145 int tegra_dc_get_out(const struct tegra_dc *dc)
1146 {
1147         if (dc && dc->out)
1148                 return dc->out->type;
1149         return -EINVAL;
1150 }
1151
1152 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1153 {
1154         if (dc->out)
1155                 return dc->out->height;
1156         else
1157                 return 0;
1158 }
1159 EXPORT_SYMBOL(tegra_dc_get_out_height);
1160
1161 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1162 {
1163         if (dc->out)
1164                 return dc->out->width;
1165         else
1166                 return 0;
1167 }
1168 EXPORT_SYMBOL(tegra_dc_get_out_width);
1169
1170 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1171 {
1172         if (dc->out && dc->out->max_pixclock)
1173                 return dc->out->max_pixclock;
1174         else
1175                 return 0;
1176 }
1177 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1178
1179 void tegra_dc_enable_crc(struct tegra_dc *dc)
1180 {
1181         u32 val;
1182
1183         mutex_lock(&dc->lock);
1184         tegra_dc_io_start(dc);
1185         tegra_dc_hold_dc_out(dc);
1186
1187         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1188                 CRC_ENABLE_ENABLE;
1189         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1190         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1191         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1192         tegra_dc_release_dc_out(dc);
1193         tegra_dc_io_end(dc);
1194         mutex_unlock(&dc->lock);
1195 }
1196
1197 void tegra_dc_disable_crc(struct tegra_dc *dc)
1198 {
1199         mutex_lock(&dc->lock);
1200         tegra_dc_io_start(dc);
1201         tegra_dc_hold_dc_out(dc);
1202         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1203         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1204         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1205
1206         tegra_dc_release_dc_out(dc);
1207         tegra_dc_io_end(dc);
1208         mutex_unlock(&dc->lock);
1209 }
1210
1211 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1212 {
1213         int crc = 0;
1214
1215         if (!dc) {
1216                 pr_err("Failed to get dc: NULL parameter.\n");
1217                 goto crc_error;
1218         }
1219
1220 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1221         /* TODO: Replace mdelay with code to sync VBlANK, since
1222          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1223         mdelay(TEGRA_CRC_LATCHED_DELAY);
1224 #endif
1225
1226         mutex_lock(&dc->lock);
1227         tegra_dc_io_start(dc);
1228         tegra_dc_hold_dc_out(dc);
1229         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1230         tegra_dc_release_dc_out(dc);
1231         tegra_dc_io_end(dc);
1232         mutex_unlock(&dc->lock);
1233 crc_error:
1234         return crc;
1235 }
1236
1237 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1238 {
1239 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1240         u32 val;
1241
1242         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1243         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1244             return true;
1245 #endif
1246         return false;
1247 }
1248
1249 static inline void enable_dc_irq(const struct tegra_dc *dc)
1250 {
1251 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1252         enable_irq(dc->irq);
1253 #else
1254         /* Always disable DC interrupts on FPGA. */
1255         disable_irq(dc->irq);
1256 #endif
1257 }
1258
1259 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1260 {
1261         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1262                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1263 }
1264
1265 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1266 {
1267         int ret = -ENOTTY;
1268
1269         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1270                 return ret;
1271
1272         /*
1273          * Logic is as follows
1274          * a) Indicate we need a vblank.
1275          * b) Wait for completion to be signalled from isr.
1276          * c) Initialize completion for next iteration.
1277          */
1278
1279         tegra_dc_hold_dc_out(dc);
1280         dc->out->user_needs_vblank = true;
1281
1282         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1283         init_completion(&dc->out->user_vblank_comp);
1284         tegra_dc_release_dc_out(dc);
1285
1286         return ret;
1287 }
1288
1289 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1290 {
1291         /* Do the actual brightness update outside of the mutex dc->lock */
1292         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1293                 dc->out->sd_settings->bl_device_name) {
1294                 char *bl_device_name =
1295                         dc->out->sd_settings->bl_device_name;
1296                 dc->out->sd_settings->bl_device =
1297                         get_backlight_device_by_name(bl_device_name);
1298         }
1299
1300         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1301                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1302                 backlight_update_status(bl);
1303         }
1304 }
1305
1306 static void tegra_dc_vblank(struct work_struct *work)
1307 {
1308         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1309         bool nvsd_updated = false;
1310
1311         mutex_lock(&dc->lock);
1312
1313         if (!dc->enabled) {
1314                 mutex_unlock(&dc->lock);
1315                 return;
1316         }
1317
1318         tegra_dc_io_start(dc);
1319         tegra_dc_hold_dc_out(dc);
1320         /* use the new frame's bandwidth setting instead of max(current, new),
1321          * skip this if we're using tegra_dc_one_shot_worker() */
1322         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1323                 tegra_dc_program_bandwidth(dc, true);
1324
1325         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1326         if (!tegra_dc_windows_are_dirty(dc))
1327                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1328
1329         /* Update the SD brightness */
1330         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1331                 nvsd_updated = nvsd_update_brightness(dc);
1332                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1333                  * V_BLANK_NVSD bit of vblank ref-count. */
1334                 if (nvsd_updated) {
1335                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1336                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1337                 } else {
1338                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1339                 }
1340         }
1341
1342         /* Mask vblank interrupt if ref-count is zero. */
1343         if (!dc->vblank_ref_count)
1344                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1345
1346         tegra_dc_release_dc_out(dc);
1347         tegra_dc_io_end(dc);
1348         mutex_unlock(&dc->lock);
1349
1350         /* Do the actual brightness update outside of the mutex dc->lock */
1351         if (nvsd_updated)
1352                 tegra_dc_prism_update_backlight(dc);
1353 }
1354
1355 static void tegra_dc_one_shot_worker(struct work_struct *work)
1356 {
1357         struct tegra_dc *dc = container_of(
1358                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1359         mutex_lock(&dc->lock);
1360
1361         /* memory client has gone idle */
1362         tegra_dc_clear_bandwidth(dc);
1363
1364         if (dc->out_ops->idle) {
1365                 tegra_dc_io_start(dc);
1366                 dc->out_ops->idle(dc);
1367                 tegra_dc_io_end(dc);
1368         }
1369
1370         mutex_unlock(&dc->lock);
1371 }
1372
1373 /* return an arbitrarily large number if count overflow occurs.
1374  * make it a nice base-10 number to show up in stats output */
1375 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1376 {
1377         unsigned count = tegra_dc_readl(dc, reg);
1378
1379         tegra_dc_writel(dc, 0, reg);
1380         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1381 }
1382
1383 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1384 {
1385         int i;
1386
1387         dc->stats.underflows++;
1388         if (dc->underflow_mask & WIN_A_UF_INT)
1389                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1390                         DC_WINBUF_AD_UFLOW_STATUS);
1391         if (dc->underflow_mask & WIN_B_UF_INT)
1392                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1393                         DC_WINBUF_BD_UFLOW_STATUS);
1394         if (dc->underflow_mask & WIN_C_UF_INT)
1395                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1396                         DC_WINBUF_CD_UFLOW_STATUS);
1397
1398         /* Check for any underflow reset conditions */
1399         for (i = 0; i < DC_N_WINDOWS; i++) {
1400                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1401                         dc->windows[i].underflows++;
1402
1403 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1404                         if (dc->windows[i].underflows > 4) {
1405                                 schedule_work(&dc->reset_work);
1406                                 /* reset counter */
1407                                 dc->windows[i].underflows = 0;
1408                                 trace_display_reset(dc);
1409                         }
1410 #endif
1411 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1412                         if (dc->windows[i].underflows > 4) {
1413                                 trace_display_reset(dc);
1414                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1415                                                 DC_DISP_DISP_MISC_CONTROL);
1416                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1417                                                 DC_CMD_STATE_CONTROL);
1418                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1419                                                 DC_CMD_STATE_CONTROL);
1420
1421                                 tegra_dc_writel(dc, 0,
1422                                                 DC_DISP_DISP_MISC_CONTROL);
1423                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1424                                                 DC_CMD_STATE_CONTROL);
1425                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1426                                                 DC_CMD_STATE_CONTROL);
1427                         }
1428 #endif
1429                 } else {
1430                         dc->windows[i].underflows = 0;
1431                 }
1432         }
1433
1434         /* Clear the underflow mask now that we've checked it. */
1435         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1436         dc->underflow_mask = 0;
1437         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1438         trace_underflow(dc);
1439 }
1440
1441 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1442 static void tegra_dc_vpulse2(struct work_struct *work)
1443 {
1444         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1445         bool nvsd_updated = false;
1446
1447         mutex_lock(&dc->lock);
1448
1449         if (!dc->enabled) {
1450                 mutex_unlock(&dc->lock);
1451                 return;
1452         }
1453
1454         tegra_dc_io_start(dc);
1455         tegra_dc_hold_dc_out(dc);
1456
1457         /* Clear the V_PULSE2_FLIP if no update */
1458         if (!tegra_dc_windows_are_dirty(dc))
1459                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1460
1461         /* Update the SD brightness */
1462         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1463                 nvsd_updated = nvsd_update_brightness(dc);
1464                 if (nvsd_updated) {
1465                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1466                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1467                 } else {
1468                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1469                 }
1470         }
1471
1472         /* Mask vpulse2 interrupt if ref-count is zero. */
1473         if (!dc->vpulse2_ref_count)
1474                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1475
1476         tegra_dc_release_dc_out(dc);
1477         tegra_dc_io_end(dc);
1478         mutex_unlock(&dc->lock);
1479
1480         /* Do the actual brightness update outside of the mutex dc->lock */
1481         if (nvsd_updated)
1482                 tegra_dc_prism_update_backlight(dc);
1483 }
1484 #endif
1485
1486 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1487 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1488 {
1489         /* pending user vblank, so wakeup */
1490         if ((status & (V_BLANK_INT | MSF_INT)) &&
1491             (dc->out->user_needs_vblank)) {
1492                 dc->out->user_needs_vblank = false;
1493                 complete(&dc->out->user_vblank_comp);
1494         }
1495
1496         if (status & V_BLANK_INT) {
1497                 /* Sync up windows. */
1498                 tegra_dc_trigger_windows(dc);
1499
1500                 /* Schedule any additional bottom-half vblank actvities. */
1501                 queue_work(system_freezable_wq, &dc->vblank_work);
1502         }
1503
1504         if (status & FRAME_END_INT) {
1505                 /* Mark the frame_end as complete. */
1506                 if (!completion_done(&dc->frame_end_complete))
1507                         complete(&dc->frame_end_complete);
1508         }
1509
1510 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1511         if (status & V_PULSE2_INT)
1512                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1513 #endif
1514 }
1515
1516 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1517 {
1518         /* Schedule any additional bottom-half vblank actvities. */
1519         if (status & V_BLANK_INT)
1520                 queue_work(system_freezable_wq, &dc->vblank_work);
1521
1522         if (status & FRAME_END_INT) {
1523                 struct timespec tm = CURRENT_TIME;
1524                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1525                 wake_up(&dc->timestamp_wq);
1526
1527                 /* Mark the frame_end as complete. */
1528                 if (!completion_done(&dc->frame_end_complete))
1529                         complete(&dc->frame_end_complete);
1530
1531                 tegra_dc_trigger_windows(dc);
1532         }
1533
1534 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1535         if (status & V_PULSE2_INT)
1536                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1537 #endif
1538 }
1539
1540 /* XXX: Not sure if we limit look ahead to 1 frame */
1541 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1542 {
1543         BUG_ON(!dc->frametime_ns);
1544         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1545 }
1546
1547 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1548 {
1549         BUG_ON(!dc->frametime_ns);
1550         return (((new_ts - old_ts) > dc->frametime_ns)
1551                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1552                         != div_s64((old_ts - dc->frame_end_timestamp),
1553                                 dc->frametime_ns)));
1554 }
1555 #endif
1556
1557 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1558 {
1559 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1560         struct tegra_dc *dc = ptr;
1561         unsigned long status;
1562         unsigned long underflow_mask;
1563         u32 val;
1564         int need_disable = 0;
1565
1566         mutex_lock(&dc->lock);
1567         if (!dc->enabled || !tegra_dc_is_powered(dc)) {
1568                 mutex_unlock(&dc->lock);
1569                 return IRQ_HANDLED;
1570         }
1571
1572         clk_prepare_enable(dc->clk);
1573         tegra_dc_io_start(dc);
1574         tegra_dc_hold_dc_out(dc);
1575
1576         if (!nvhost_module_powered_ext(dc->ndev)) {
1577                 WARN(1, "IRQ when DC not powered!\n");
1578                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1579                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1580                 tegra_dc_release_dc_out(dc);
1581                 tegra_dc_io_end(dc);
1582                 clk_disable_unprepare(dc->clk);
1583                 mutex_unlock(&dc->lock);
1584                 return IRQ_HANDLED;
1585         }
1586
1587         /* clear all status flags except underflow, save those for the worker */
1588         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1589         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1590         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1591         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1592
1593         /*
1594          * Overlays can get thier internal state corrupted during and underflow
1595          * condition.  The only way to fix this state is to reset the DC.
1596          * if we get 4 consecutive frames with underflows, assume we're
1597          * hosed and reset.
1598          */
1599         underflow_mask = status & ALL_UF_INT;
1600
1601         /* Check underflow */
1602         if (underflow_mask) {
1603                 dc->underflow_mask |= underflow_mask;
1604                 schedule_delayed_work(&dc->underflow_work,
1605                         msecs_to_jiffies(1));
1606         }
1607
1608         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1609                 tegra_dc_one_shot_irq(dc, status);
1610         else
1611                 tegra_dc_continuous_irq(dc, status);
1612
1613         /* update video mode if it has changed since the last frame */
1614         if (status & (FRAME_END_INT | V_BLANK_INT))
1615                 if (tegra_dc_update_mode(dc))
1616                         need_disable = 1; /* force display off on error */
1617
1618         tegra_dc_release_dc_out(dc);
1619         tegra_dc_io_end(dc);
1620         clk_disable_unprepare(dc->clk);
1621         mutex_unlock(&dc->lock);
1622
1623         if (need_disable)
1624                 tegra_dc_disable(dc);
1625         return IRQ_HANDLED;
1626 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1627         return IRQ_NONE;
1628 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1629 }
1630
1631 void tegra_dc_set_color_control(struct tegra_dc *dc)
1632 {
1633         u32 color_control;
1634
1635         switch (dc->out->depth) {
1636         case 3:
1637                 color_control = BASE_COLOR_SIZE111;
1638                 break;
1639
1640         case 6:
1641                 color_control = BASE_COLOR_SIZE222;
1642                 break;
1643
1644         case 8:
1645                 color_control = BASE_COLOR_SIZE332;
1646                 break;
1647
1648         case 9:
1649                 color_control = BASE_COLOR_SIZE333;
1650                 break;
1651
1652         case 12:
1653                 color_control = BASE_COLOR_SIZE444;
1654                 break;
1655
1656         case 15:
1657                 color_control = BASE_COLOR_SIZE555;
1658                 break;
1659
1660         case 16:
1661                 color_control = BASE_COLOR_SIZE565;
1662                 break;
1663
1664         case 18:
1665                 color_control = BASE_COLOR_SIZE666;
1666                 break;
1667
1668         default:
1669                 color_control = BASE_COLOR_SIZE888;
1670                 break;
1671         }
1672
1673         switch (dc->out->dither) {
1674         case TEGRA_DC_DISABLE_DITHER:
1675                 color_control |= DITHER_CONTROL_DISABLE;
1676                 break;
1677         case TEGRA_DC_ORDERED_DITHER:
1678                 color_control |= DITHER_CONTROL_ORDERED;
1679                 break;
1680         case TEGRA_DC_ERRDIFF_DITHER:
1681                 /* The line buffer for error-diffusion dither is limited
1682                  * to 1280 pixels per line. This limits the maximum
1683                  * horizontal active area size to 1280 pixels when error
1684                  * diffusion is enabled.
1685                  */
1686                 BUG_ON(dc->mode.h_active > 1280);
1687                 color_control |= DITHER_CONTROL_ERRDIFF;
1688                 break;
1689         }
1690
1691 #ifdef CONFIG_TEGRA_DC_CMU
1692         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1693                 color_control |= CMU_ENABLE;
1694 #endif
1695
1696         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1697 }
1698
1699 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1700 {
1701         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1702                 return dc->win_syncpt[idx];
1703         BUG();
1704 }
1705
1706 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1707 {
1708 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1709         u32 start, end;
1710         unsigned long val;
1711
1712         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1713         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1714
1715         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1716                 dc->mode.v_back_porch + dc->mode.v_active;
1717         end = start + 1;
1718         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1719         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1720
1721         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1722         val |= V_PULSE2_INT;
1723         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1724
1725         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1726         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1727 #endif
1728 }
1729
1730 static int tegra_dc_init(struct tegra_dc *dc)
1731 {
1732         int i;
1733         int int_enable;
1734
1735         tegra_dc_io_start(dc);
1736         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1737         if (dc->ndev->id == 0) {
1738                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1739                                       TEGRA_MC_PRIO_MED);
1740                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1741                                       TEGRA_MC_PRIO_MED);
1742                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1743                                       TEGRA_MC_PRIO_MED);
1744 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1745                 /* only present on Tegra2 and 3 */
1746                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1747                                       TEGRA_MC_PRIO_MED);
1748 #endif
1749                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1750                                       TEGRA_MC_PRIO_HIGH);
1751         } else if (dc->ndev->id == 1) {
1752                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1753                                       TEGRA_MC_PRIO_MED);
1754                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1755                                       TEGRA_MC_PRIO_MED);
1756                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1757                                       TEGRA_MC_PRIO_MED);
1758 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1759                 /* only present on Tegra2 and 3 */
1760                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1761                                       TEGRA_MC_PRIO_MED);
1762 #endif
1763                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1764                                       TEGRA_MC_PRIO_HIGH);
1765         }
1766         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1767                         DC_CMD_CONT_SYNCPT_VSYNC);
1768
1769         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1770         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1771         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1772         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1773 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1774         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1775 #endif
1776         /* enable interrupts for vblank, frame_end and underflows */
1777         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1778         /* for panels with one-shot mode enable tearing effect interrupt */
1779         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1780                 int_enable |= MSF_INT;
1781
1782         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1783         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1784         tegra_dc_init_vpulse2_int(dc);
1785
1786         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1787
1788 #ifdef CONFIG_TEGRA_DC_CMU
1789         if (dc->pdata->cmu)
1790                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1791         else
1792                 _tegra_dc_update_cmu(dc, &default_cmu);
1793 #endif
1794         tegra_dc_set_color_control(dc);
1795         for (i = 0; i < DC_N_WINDOWS; i++) {
1796                 struct tegra_dc_win *win = &dc->windows[i];
1797                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1798                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1799                 tegra_dc_set_csc(dc, &win->csc);
1800                 tegra_dc_set_lut(dc, win);
1801                 tegra_dc_set_scaling_filter(dc);
1802         }
1803
1804         for (i = 0; i < dc->n_windows; i++) {
1805                 u32 syncpt = get_syncpt(dc, i);
1806
1807                 dc->syncpt[i].id = syncpt;
1808
1809                 dc->syncpt[i].min = dc->syncpt[i].max =
1810                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1811         }
1812
1813         trace_display_mode(dc, &dc->mode);
1814
1815         if (dc->mode.pclk) {
1816                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1817                         tegra_dc_io_end(dc);
1818                         return -EINVAL;
1819                 }
1820         }
1821
1822         /* Initialize SD AFTER the modeset.
1823            nvsd_init handles the sd_settings = NULL case. */
1824         nvsd_init(dc, dc->out->sd_settings);
1825
1826         tegra_dc_io_end(dc);
1827
1828         return 0;
1829 }
1830
1831 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1832 {
1833         int failed_init = 0;
1834
1835         tegra_dc_unpowergate_locked(dc);
1836
1837         if (dc->out->enable)
1838                 dc->out->enable(&dc->ndev->dev);
1839
1840         tegra_dc_setup_clk(dc, dc->clk);
1841         tegra_dc_clk_enable(dc);
1842         tegra_dc_io_start(dc);
1843
1844         tegra_dc_power_on(dc);
1845
1846         /* do not accept interrupts during initialization */
1847         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1848
1849         enable_dc_irq(dc);
1850
1851         failed_init = tegra_dc_init(dc);
1852         if (failed_init) {
1853                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1854                 disable_irq_nosync(dc->irq);
1855                 tegra_dc_clear_bandwidth(dc);
1856                 tegra_dc_clk_disable(dc);
1857                 if (dc->out && dc->out->disable)
1858                         dc->out->disable();
1859                 tegra_dc_io_end(dc);
1860                 return false;
1861         }
1862
1863         if (dc->out_ops && dc->out_ops->enable)
1864                 dc->out_ops->enable(dc);
1865
1866         /* force a full blending update */
1867         dc->blend.z[0] = -1;
1868
1869         tegra_dc_ext_enable(dc->ext);
1870
1871         trace_display_enable(dc);
1872
1873         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1874         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1875
1876         if (dc->out->postpoweron)
1877                 dc->out->postpoweron();
1878
1879         tegra_log_resume_time();
1880
1881         tegra_dc_io_end(dc);
1882         return true;
1883 }
1884
1885 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1886 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1887 {
1888         bool ret = true;
1889
1890         if (dc->out->enable)
1891                 dc->out->enable(&dc->ndev->dev);
1892
1893         tegra_dc_setup_clk(dc, dc->clk);
1894         tegra_dc_clk_enable(dc);
1895
1896         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1897                 mutex_lock(&tegra_dcs[1]->lock);
1898                 disable_irq_nosync(tegra_dcs[1]->irq);
1899         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1900                 mutex_lock(&tegra_dcs[0]->lock);
1901                 disable_irq_nosync(tegra_dcs[0]->irq);
1902         }
1903
1904         msleep(5);
1905         tegra_periph_reset_assert(dc->clk);
1906         msleep(2);
1907 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1908         tegra_periph_reset_deassert(dc->clk);
1909         msleep(1);
1910 #endif
1911
1912         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1913                 enable_dc_irq(tegra_dcs[1]);
1914                 mutex_unlock(&tegra_dcs[1]->lock);
1915         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1916                 enable_dc_irq(tegra_dcs[0]);
1917                 mutex_unlock(&tegra_dcs[0]->lock);
1918         }
1919
1920         enable_dc_irq(dc);
1921
1922         if (tegra_dc_init(dc)) {
1923                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1924                 ret = false;
1925         }
1926
1927         if (dc->out_ops && dc->out_ops->enable)
1928                 dc->out_ops->enable(dc);
1929
1930         if (dc->out->postpoweron)
1931                 dc->out->postpoweron();
1932
1933         /* force a full blending update */
1934         dc->blend.z[0] = -1;
1935
1936         tegra_dc_ext_enable(dc->ext);
1937
1938         if (!ret) {
1939                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1940                 _tegra_dc_controller_disable(dc);
1941         }
1942
1943         trace_display_reset(dc);
1944         return ret;
1945 }
1946 #endif
1947
1948 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1949 {
1950         if (dc->mode.pclk == 0) {
1951                 switch (dc->out->type) {
1952                 case TEGRA_DC_OUT_HDMI:
1953                 /* DC enable called but no videomode is loaded.
1954                      Check if HDMI is connected, then set fallback mdoe */
1955                 if (tegra_dc_hpd(dc)) {
1956                         return tegra_dc_set_fb_mode(dc,
1957                                         &tegra_dc_hdmi_fallback_mode, 0);
1958                 } else
1959                         return false;
1960
1961                 break;
1962
1963                 /* Do nothing for other outputs for now */
1964                 case TEGRA_DC_OUT_RGB:
1965
1966                 case TEGRA_DC_OUT_DSI:
1967
1968                 default:
1969                         return false;
1970                 }
1971         }
1972
1973         return false;
1974 }
1975
1976 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1977 {
1978         return _tegra_dc_set_default_videomode(dc);
1979 }
1980
1981 static bool _tegra_dc_enable(struct tegra_dc *dc)
1982 {
1983         if (dc->mode.pclk == 0)
1984                 return false;
1985
1986         if (!dc->out)
1987                 return false;
1988
1989         if (dc->enabled)
1990                 return true;
1991
1992         if (!_tegra_dc_controller_enable(dc))
1993                 return false;
1994
1995         return true;
1996 }
1997
1998 void tegra_dc_enable(struct tegra_dc *dc)
1999 {
2000         mutex_lock(&dc->lock);
2001
2002         if (!dc->enabled)
2003                 dc->enabled = _tegra_dc_enable(dc);
2004
2005         mutex_unlock(&dc->lock);
2006         trace_display_mode(dc, &dc->mode);
2007 }
2008
2009 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2010 {
2011         unsigned i;
2012
2013         tegra_dc_hold_dc_out(dc);
2014
2015         if (dc->out && dc->out->prepoweroff)
2016                 dc->out->prepoweroff();
2017
2018         if (dc->out_ops && dc->out_ops->disable)
2019                 dc->out_ops->disable(dc);
2020
2021         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2022
2023         disable_irq_nosync(dc->irq);
2024
2025         tegra_dc_clear_bandwidth(dc);
2026
2027         if (dc->out && dc->out->disable)
2028                 dc->out->disable();
2029
2030         for (i = 0; i < dc->n_windows; i++) {
2031                 struct tegra_dc_win *w = &dc->windows[i];
2032
2033                 /* reset window bandwidth */
2034                 w->bandwidth = 0;
2035                 w->new_bandwidth = 0;
2036
2037                 /* disable windows */
2038                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2039
2040                 /* flush any pending syncpt waits */
2041                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2042                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2043                                 dc->syncpt[i].min, dc->syncpt[i].max);
2044                         dc->syncpt[i].min++;
2045                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2046                 }
2047         }
2048         trace_display_disable(dc);
2049
2050         tegra_dc_clk_disable(dc);
2051         tegra_dc_release_dc_out(dc);
2052 }
2053
2054 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2055 {
2056 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2057         u32 val;
2058         if (dc->enabled)  {
2059                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2060                 if (enable)
2061                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2062                 else
2063                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2064                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2065         }
2066 #endif
2067 }
2068
2069 bool tegra_dc_stats_get(struct tegra_dc *dc)
2070 {
2071 #if 0 /* right now it is always enabled */
2072         u32 val;
2073         bool res;
2074
2075         if (dc->enabled)  {
2076                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2077                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2078         } else {
2079                 res = false;
2080         }
2081
2082         return res;
2083 #endif
2084         return true;
2085 }
2086
2087 /* make the screen blank by disabling all windows */
2088 void tegra_dc_blank(struct tegra_dc *dc)
2089 {
2090         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2091         unsigned i;
2092
2093         for (i = 0; i < DC_N_WINDOWS; i++) {
2094                 dcwins[i] = tegra_dc_get_window(dc, i);
2095                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2096         }
2097
2098         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2099         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2100 }
2101
2102 static void _tegra_dc_disable(struct tegra_dc *dc)
2103 {
2104         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2105                 mutex_lock(&dc->one_shot_lock);
2106                 cancel_delayed_work_sync(&dc->one_shot_work);
2107         }
2108
2109         tegra_dc_io_start(dc);
2110         _tegra_dc_controller_disable(dc);
2111         tegra_dc_io_end(dc);
2112
2113         tegra_dc_powergate_locked(dc);
2114
2115         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2116                 mutex_unlock(&dc->one_shot_lock);
2117
2118         /*
2119          * We will need to reinitialize the display the next time panel
2120          * is enabled.
2121          */
2122         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2123
2124         tegra_log_suspend_time();
2125 }
2126
2127 void tegra_dc_disable(struct tegra_dc *dc)
2128 {
2129         tegra_dc_ext_disable(dc->ext);
2130
2131         /* it's important that new underflow work isn't scheduled before the
2132          * lock is acquired. */
2133         cancel_delayed_work_sync(&dc->underflow_work);
2134
2135         mutex_lock(&dc->lock);
2136
2137         if (dc->enabled) {
2138                 dc->enabled = false;
2139
2140                 if (!dc->suspended)
2141                         _tegra_dc_disable(dc);
2142         }
2143
2144 #ifdef CONFIG_SWITCH
2145         switch_set_state(&dc->modeset_switch, 0);
2146 #endif
2147
2148         mutex_unlock(&dc->lock);
2149         synchronize_irq(dc->irq);
2150         trace_display_mode(dc, &dc->mode);
2151 }
2152
2153 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2154 static void tegra_dc_reset_worker(struct work_struct *work)
2155 {
2156         struct tegra_dc *dc =
2157                 container_of(work, struct tegra_dc, reset_work);
2158
2159         unsigned long val = 0;
2160
2161         mutex_lock(&shared_lock);
2162
2163         dev_warn(&dc->ndev->dev,
2164                 "overlay stuck in underflow state.  resetting.\n");
2165
2166         tegra_dc_ext_disable(dc->ext);
2167
2168         mutex_lock(&dc->lock);
2169
2170         if (dc->enabled == false)
2171                 goto unlock;
2172
2173         dc->enabled = false;
2174
2175         /*
2176          * off host read bus
2177          */
2178         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2179         val &= ~(0x00000100);
2180         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2181
2182         /*
2183          * set DC to STOP mode
2184          */
2185         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2186
2187         msleep(10);
2188
2189         _tegra_dc_controller_disable(dc);
2190
2191         /* _tegra_dc_controller_reset_enable deasserts reset */
2192         _tegra_dc_controller_reset_enable(dc);
2193
2194         dc->enabled = true;
2195
2196         /* reopen host read bus */
2197         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2198         val &= ~(0x00000100);
2199         val |= 0x100;
2200         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2201
2202 unlock:
2203         mutex_unlock(&dc->lock);
2204         mutex_unlock(&shared_lock);
2205         trace_display_reset(dc);
2206 }
2207 #endif
2208
2209 static void tegra_dc_underflow_worker(struct work_struct *work)
2210 {
2211         struct tegra_dc *dc = container_of(
2212                 to_delayed_work(work), struct tegra_dc, underflow_work);
2213
2214         mutex_lock(&dc->lock);
2215         tegra_dc_io_start(dc);
2216         tegra_dc_hold_dc_out(dc);
2217
2218         if (dc->enabled) {
2219                 tegra_dc_underflow_handler(dc);
2220         }
2221         tegra_dc_release_dc_out(dc);
2222         tegra_dc_io_end(dc);
2223         mutex_unlock(&dc->lock);
2224 }
2225
2226 #ifdef CONFIG_SWITCH
2227 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2228 {
2229         struct tegra_dc *dc =
2230                 container_of(sdev, struct tegra_dc, modeset_switch);
2231
2232         if (!sdev->state)
2233                 return sprintf(buf, "offline\n");
2234
2235         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2236 }
2237 #endif
2238
2239 static void tegra_dc_add_modes(struct tegra_dc *dc)
2240 {
2241         struct fb_monspecs specs;
2242         int i;
2243
2244         memset(&specs, 0, sizeof(specs));
2245         specs.max_x = dc->mode.h_active * 1000;
2246         specs.max_y = dc->mode.v_active * 1000;
2247         specs.modedb_len = dc->out->n_modes;
2248         specs.modedb = kzalloc(specs.modedb_len *
2249                 sizeof(struct fb_videomode), GFP_KERNEL);
2250         for (i = 0; i < dc->out->n_modes; i++)
2251                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2252                         &dc->out->modes[i]);
2253         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2254         kfree(specs.modedb);
2255 }
2256
2257 static int tegra_dc_probe(struct platform_device *ndev)
2258 {
2259         struct tegra_dc *dc;
2260         struct tegra_dc_mode *mode;
2261         struct clk *clk;
2262         struct clk *emc_clk;
2263         struct resource *res;
2264         struct resource *base_res;
2265         struct resource *fb_mem = NULL;
2266         int ret = 0;
2267         void __iomem *base;
2268         int irq;
2269         int i;
2270
2271         if (!ndev->dev.platform_data) {
2272                 dev_err(&ndev->dev, "no platform data\n");
2273                 return -ENOENT;
2274         }
2275
2276         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2277         if (!dc) {
2278                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2279                 return -ENOMEM;
2280         }
2281
2282         irq = platform_get_irq_byname(ndev, "irq");
2283         if (irq <= 0) {
2284                 dev_err(&ndev->dev, "no irq\n");
2285                 ret = -ENOENT;
2286                 goto err_free;
2287         }
2288
2289         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2290         if (!res) {
2291                 dev_err(&ndev->dev, "no mem resource\n");
2292                 ret = -ENOENT;
2293                 goto err_free;
2294         }
2295
2296         base_res = request_mem_region(res->start, resource_size(res),
2297                 ndev->name);
2298         if (!base_res) {
2299                 dev_err(&ndev->dev, "request_mem_region failed\n");
2300                 ret = -EBUSY;
2301                 goto err_free;
2302         }
2303
2304         base = ioremap(res->start, resource_size(res));
2305         if (!base) {
2306                 dev_err(&ndev->dev, "registers can't be mapped\n");
2307                 ret = -EBUSY;
2308                 goto err_release_resource_reg;
2309         }
2310         if (TEGRA_DISPLAY_BASE == res->start) {
2311                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2312                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2313                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2314                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2315                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2316         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2317                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2318                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2319                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2320                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2321                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2322         } else {
2323                 dev_err(&ndev->dev,
2324                         "Unknown base address %#08x: unable to assign syncpt\n",
2325                         res->start);
2326         }
2327
2328
2329         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2330
2331         clk = clk_get(&ndev->dev, NULL);
2332         if (IS_ERR_OR_NULL(clk)) {
2333                 dev_err(&ndev->dev, "can't get clock\n");
2334                 ret = -ENOENT;
2335                 goto err_iounmap_reg;
2336         }
2337
2338         emc_clk = clk_get(&ndev->dev, "emc");
2339         if (IS_ERR_OR_NULL(emc_clk)) {
2340                 dev_err(&ndev->dev, "can't get emc clock\n");
2341                 ret = -ENOENT;
2342                 goto err_put_clk;
2343         }
2344
2345         dc->clk = clk;
2346         dc->emc_clk = emc_clk;
2347         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2348         /* Initialize one shot work delay, it will be assigned by dsi
2349          * according to refresh rate later. */
2350         dc->one_shot_delay_ms = 40;
2351
2352         dc->base_res = base_res;
2353         dc->base = base;
2354         dc->irq = irq;
2355         dc->ndev = ndev;
2356         dc->pdata = ndev->dev.platform_data;
2357
2358         /*
2359          * The emc is a shared clock, it will be set based on
2360          * the requirements for each user on the bus.
2361          */
2362         dc->emc_clk_rate = 0;
2363
2364         mutex_init(&dc->lock);
2365         mutex_init(&dc->one_shot_lock);
2366         init_completion(&dc->frame_end_complete);
2367         init_waitqueue_head(&dc->wq);
2368         init_waitqueue_head(&dc->timestamp_wq);
2369 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2370         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2371 #endif
2372         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2373         dc->vblank_ref_count = 0;
2374 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2375         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2376 #endif
2377         dc->vpulse2_ref_count = 0;
2378         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2379         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2380
2381         tegra_dc_init_lut_defaults(&dc->fb_lut);
2382
2383         dc->n_windows = DC_N_WINDOWS;
2384         for (i = 0; i < dc->n_windows; i++) {
2385                 struct tegra_dc_win *win = &dc->windows[i];
2386                 win->idx = i;
2387                 win->dc = dc;
2388                 tegra_dc_init_csc_defaults(&win->csc);
2389                 tegra_dc_init_lut_defaults(&win->lut);
2390         }
2391
2392         ret = tegra_dc_set(dc, ndev->id);
2393         if (ret < 0) {
2394                 dev_err(&ndev->dev, "can't add dc\n");
2395                 goto err_put_emc_clk;
2396         }
2397
2398         platform_set_drvdata(ndev, dc);
2399
2400 #ifdef CONFIG_SWITCH
2401         dc->modeset_switch.name = dev_name(&ndev->dev);
2402         dc->modeset_switch.state = 0;
2403         dc->modeset_switch.print_state = switch_modeset_print_mode;
2404         ret = switch_dev_register(&dc->modeset_switch);
2405         if (ret < 0)
2406                 dev_err(&ndev->dev, "failed to register switch driver\n");
2407 #endif
2408
2409         tegra_dc_feature_register(dc);
2410
2411         if (dc->pdata->default_out)
2412                 tegra_dc_set_out(dc, dc->pdata->default_out);
2413         else
2414                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2415         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2416
2417         dc->ext = tegra_dc_ext_register(ndev, dc);
2418         if (IS_ERR_OR_NULL(dc->ext)) {
2419                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2420                 dc->ext = NULL;
2421         }
2422
2423         /* interrupt handler must be registered before tegra_fb_register() */
2424         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2425                         dev_name(&ndev->dev), dc)) {
2426                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2427                 ret = -EBUSY;
2428                 goto err_disable_dc;
2429         }
2430         disable_dc_irq(dc);
2431
2432         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2433                 _tegra_dc_set_default_videomode(dc);
2434                 dc->enabled = _tegra_dc_enable(dc);
2435         }
2436
2437         tegra_dc_create_debugfs(dc);
2438
2439         dev_info(&ndev->dev, "probed\n");
2440
2441         if (dc->pdata->fb) {
2442                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2443                         unsigned long fmt;
2444                         tegra_dc_writel(dc,
2445                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2446                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2447
2448                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2449                         dc->pdata->fb->bits_per_pixel =
2450                                 tegra_dc_fmt_bpp(fmt);
2451                 }
2452
2453                 mode = tegra_dc_get_override_mode(dc);
2454                 if (mode) {
2455                         dc->pdata->fb->xres = mode->h_active;
2456                         dc->pdata->fb->yres = mode->v_active;
2457                 }
2458
2459                 tegra_dc_io_start(dc);
2460                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2461                 tegra_dc_io_end(dc);
2462                 if (IS_ERR_OR_NULL(dc->fb)) {
2463                         dc->fb = NULL;
2464                         dev_err(&ndev->dev, "failed to register fb\n");
2465                         goto err_remove_debugfs;
2466                 }
2467         }
2468
2469         if (dc->out && dc->out->n_modes)
2470                 tegra_dc_add_modes(dc);
2471
2472         if (dc->out && dc->out->hotplug_init)
2473                 dc->out->hotplug_init(&ndev->dev);
2474
2475         if (dc->out_ops && dc->out_ops->detect)
2476                 dc->out_ops->detect(dc);
2477         else
2478                 dc->connected = true;
2479
2480         /* Powergate display module when it's unconnected. */
2481         if (!tegra_dc_get_connected(dc))
2482                 tegra_dc_powergate_locked(dc);
2483
2484         tegra_dc_create_sysfs(&dc->ndev->dev);
2485
2486         return 0;
2487
2488 err_remove_debugfs:
2489         tegra_dc_remove_debugfs(dc);
2490         free_irq(irq, dc);
2491 err_disable_dc:
2492         if (dc->ext) {
2493                 tegra_dc_ext_disable(dc->ext);
2494                 tegra_dc_ext_unregister(dc->ext);
2495         }
2496         mutex_lock(&dc->lock);
2497         if (dc->enabled)
2498                 _tegra_dc_disable(dc);
2499         dc->enabled = false;
2500         mutex_unlock(&dc->lock);
2501 #ifdef CONFIG_SWITCH
2502         switch_dev_unregister(&dc->modeset_switch);
2503 #endif
2504 err_put_emc_clk:
2505         clk_put(emc_clk);
2506 err_put_clk:
2507         clk_put(clk);
2508 err_iounmap_reg:
2509         iounmap(base);
2510         if (fb_mem)
2511                 release_resource(fb_mem);
2512 err_release_resource_reg:
2513         release_resource(base_res);
2514 err_free:
2515         kfree(dc);
2516
2517         return ret;
2518 }
2519
2520 static int __devexit tegra_dc_remove(struct platform_device *ndev)
2521 {
2522         struct tegra_dc *dc = platform_get_drvdata(ndev);
2523
2524         tegra_dc_remove_sysfs(&dc->ndev->dev);
2525         tegra_dc_remove_debugfs(dc);
2526
2527         if (dc->fb) {
2528                 tegra_fb_unregister(dc->fb);
2529                 if (dc->fb_mem)
2530                         release_resource(dc->fb_mem);
2531         }
2532
2533         tegra_dc_ext_disable(dc->ext);
2534
2535         if (dc->ext)
2536                 tegra_dc_ext_unregister(dc->ext);
2537
2538         mutex_lock(&dc->lock);
2539         if (dc->enabled)
2540                 _tegra_dc_disable(dc);
2541         dc->enabled = false;
2542         mutex_unlock(&dc->lock);
2543         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2544
2545 #ifdef CONFIG_SWITCH
2546         switch_dev_unregister(&dc->modeset_switch);
2547 #endif
2548         free_irq(dc->irq, dc);
2549         clk_put(dc->emc_clk);
2550         clk_put(dc->clk);
2551         iounmap(dc->base);
2552         if (dc->fb_mem)
2553                 release_resource(dc->base_res);
2554         kfree(dc);
2555         tegra_dc_set(NULL, ndev->id);
2556
2557         return 0;
2558 }
2559
2560 #ifdef CONFIG_PM
2561 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2562 {
2563         struct tegra_dc *dc = platform_get_drvdata(ndev);
2564
2565         trace_display_suspend(dc);
2566         dev_info(&ndev->dev, "suspend\n");
2567
2568         tegra_dc_ext_disable(dc->ext);
2569
2570         mutex_lock(&dc->lock);
2571         tegra_dc_io_start(dc);
2572
2573         if (dc->out_ops && dc->out_ops->suspend)
2574                 dc->out_ops->suspend(dc);
2575
2576         if (dc->enabled) {
2577                 _tegra_dc_disable(dc);
2578
2579                 dc->suspended = true;
2580         }
2581
2582         if (dc->out && dc->out->postsuspend) {
2583                 dc->out->postsuspend();
2584                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2585                         /*
2586                          * avoid resume event due to voltage falling
2587                          */
2588                         msleep(100);
2589         }
2590
2591         tegra_dc_io_end(dc);
2592         mutex_unlock(&dc->lock);
2593         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2594
2595         return 0;
2596 }
2597
2598 static int tegra_dc_resume(struct platform_device *ndev)
2599 {
2600         struct tegra_dc *dc = platform_get_drvdata(ndev);
2601
2602         trace_display_resume(dc);
2603         dev_info(&ndev->dev, "resume\n");
2604
2605         mutex_lock(&dc->lock);
2606         dc->suspended = false;
2607
2608         /* To pan the fb on resume */
2609         tegra_fb_pan_display_reset(dc->fb);
2610
2611         if (dc->enabled) {
2612                 dc->enabled = false;
2613                 _tegra_dc_set_default_videomode(dc);
2614                 dc->enabled = _tegra_dc_enable(dc);
2615         }
2616
2617         if (dc->out && dc->out->hotplug_init)
2618                 dc->out->hotplug_init(&ndev->dev);
2619
2620         if (dc->out_ops && dc->out_ops->resume)
2621                 dc->out_ops->resume(dc);
2622         mutex_unlock(&dc->lock);
2623
2624         return 0;
2625 }
2626
2627 #endif /* CONFIG_PM */
2628
2629 static void tegra_dc_shutdown(struct platform_device *ndev)
2630 {
2631         struct tegra_dc *dc = platform_get_drvdata(ndev);
2632
2633         if (!dc || !dc->enabled)
2634                 return;
2635
2636         tegra_dc_blank(dc);
2637         tegra_dc_disable(dc);
2638 }
2639
2640 extern int suspend_set(const char *val, struct kernel_param *kp)
2641 {
2642         if (!strcmp(val, "dump"))
2643                 dump_regs(tegra_dcs[0]);
2644 #ifdef CONFIG_PM
2645         else if (!strcmp(val, "suspend"))
2646                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2647         else if (!strcmp(val, "resume"))
2648                 tegra_dc_resume(tegra_dcs[0]->ndev);
2649 #endif
2650
2651         return 0;
2652 }
2653
2654 extern int suspend_get(char *buffer, struct kernel_param *kp)
2655 {
2656         return 0;
2657 }
2658
2659 int suspend;
2660
2661 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2662
2663 struct platform_driver tegra_dc_driver = {
2664         .driver = {
2665                 .name = "tegradc",
2666                 .owner = THIS_MODULE,
2667         },
2668         .probe = tegra_dc_probe,
2669         .remove = tegra_dc_remove,
2670 #ifdef CONFIG_PM
2671         .suspend = tegra_dc_suspend,
2672         .resume = tegra_dc_resume,
2673 #endif
2674         .shutdown = tegra_dc_shutdown,
2675 };
2676
2677 #ifndef MODULE
2678 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2679 {
2680         int i, params[11];
2681         char *p;
2682
2683         for (i = 0; i < ARRAY_SIZE(params); i++) {
2684                 if ((p = strsep(&options, ",")) != NULL) {
2685                         if (*p)
2686                                 params[i] = simple_strtoul(p, &p, 10);
2687                 } else
2688                         return -EINVAL;
2689         }
2690
2691         if ((mode->pclk = params[0]) == 0)
2692                 return -EINVAL;
2693
2694         mode->h_active      = params[1];
2695         mode->v_active      = params[2];
2696         mode->h_ref_to_sync = params[3];
2697         mode->v_ref_to_sync = params[4];
2698         mode->h_sync_width  = params[5];
2699         mode->v_sync_width  = params[6];
2700         mode->h_back_porch  = params[7];
2701         mode->v_back_porch  = params[8];
2702         mode->h_front_porch = params[9];
2703         mode->v_front_porch = params[10];
2704
2705         return 0;
2706 }
2707
2708 static int __init tegra_dc_mode_override(char *str)
2709 {
2710         char *p = str, *options;
2711
2712         if (!p || !*p)
2713                 return -EINVAL;
2714
2715         p = strstr(str, "hdmi:");
2716         if (p) {
2717                 p += 5;
2718                 options = strsep(&p, ";");
2719                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2720                         return -EINVAL;
2721         }
2722
2723         p = strstr(str, "rgb:");
2724         if (p) {
2725                 p += 4;
2726                 options = strsep(&p, ";");
2727                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2728                         return -EINVAL;
2729         }
2730
2731         p = strstr(str, "dsi:");
2732         if (p) {
2733                 p += 4;
2734                 options = strsep(&p, ";");
2735                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2736                         return -EINVAL;
2737         }
2738
2739         return 0;
2740 }
2741
2742 __setup("disp_params=", tegra_dc_mode_override);
2743 #endif
2744
2745 static int __init tegra_dc_module_init(void)
2746 {
2747         int ret = tegra_dc_ext_module_init();
2748         if (ret)
2749                 return ret;
2750         return platform_driver_register(&tegra_dc_driver);
2751 }
2752
2753 static void __exit tegra_dc_module_exit(void)
2754 {
2755         platform_driver_unregister(&tegra_dc_driver);
2756         tegra_dc_ext_module_exit();
2757 }
2758
2759 module_exit(tegra_dc_module_exit);
2760 module_init(tegra_dc_module_init);