2ee5860f0f917fd90262c91d10c96009ba7aded0
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134         case TEGRA_WIN_FMT_YCbCr422R:
135         case TEGRA_WIN_FMT_YUV422R:
136         case TEGRA_WIN_FMT_YCbCr422RA:
137         case TEGRA_WIN_FMT_YUV422RA:
138                 return 8;
139
140         case TEGRA_WIN_FMT_YCbCr422:
141         case TEGRA_WIN_FMT_YUV422:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155         case TEGRA_WIN_FMT_YCbCr422R:
156         case TEGRA_WIN_FMT_YUV422R:
157         case TEGRA_WIN_FMT_YCbCr422RA:
158         case TEGRA_WIN_FMT_YUV422RA:
159                 return true;
160         }
161         return false;
162 }
163
164 #define DUMP_REG(a) do {                        \
165         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
166                  #a, a, tegra_dc_readl(dc, a));               \
167         print(data, buff);                                    \
168         } while (0)
169
170 static void _dump_regs(struct tegra_dc *dc, void *data,
171                        void (* print)(void *data, const char *str))
172 {
173         int i;
174         char buff[256];
175
176         tegra_dc_io_start(dc);
177         clk_enable(dc->clk);
178
179         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
180         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
181         DUMP_REG(DC_CMD_SIGNAL_RAISE);
182         DUMP_REG(DC_CMD_INT_STATUS);
183         DUMP_REG(DC_CMD_INT_MASK);
184         DUMP_REG(DC_CMD_INT_ENABLE);
185         DUMP_REG(DC_CMD_INT_TYPE);
186         DUMP_REG(DC_CMD_INT_POLARITY);
187         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
188         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
190         DUMP_REG(DC_CMD_STATE_ACCESS);
191         DUMP_REG(DC_CMD_STATE_CONTROL);
192         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
193         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
194
195         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
196         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
197         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
198         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
199         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
200         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
201         DUMP_REG(DC_DISP_REF_TO_SYNC);
202         DUMP_REG(DC_DISP_SYNC_WIDTH);
203         DUMP_REG(DC_DISP_BACK_PORCH);
204         DUMP_REG(DC_DISP_DISP_ACTIVE);
205         DUMP_REG(DC_DISP_FRONT_PORCH);
206         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
211         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
212         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
213         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
216         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
217         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
218         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
221         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
229         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
230         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
231         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
233         DUMP_REG(DC_DISP_M0_CONTROL);
234         DUMP_REG(DC_DISP_M1_CONTROL);
235         DUMP_REG(DC_DISP_DI_CONTROL);
236         DUMP_REG(DC_DISP_PP_CONTROL);
237         DUMP_REG(DC_DISP_PP_SELECT_A);
238         DUMP_REG(DC_DISP_PP_SELECT_B);
239         DUMP_REG(DC_DISP_PP_SELECT_C);
240         DUMP_REG(DC_DISP_PP_SELECT_D);
241         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
242         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
243         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
244         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
245         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
246         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
247         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
248         DUMP_REG(DC_DISP_BORDER_COLOR);
249         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
250         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
251         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
253         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
254         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
255         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
256         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
257         DUMP_REG(DC_DISP_CURSOR_POSITION);
258         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
259         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
260         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
261         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
264         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
265         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
266         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
269         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
270         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
271
272
273         for (i = 0; i < 3; i++) {
274                 print(data, "\n");
275                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
276                 print(data, buff);
277
278                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
279                                 DC_CMD_DISPLAY_WINDOW_HEADER);
280                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
281                 DUMP_REG(DC_WIN_WIN_OPTIONS);
282                 DUMP_REG(DC_WIN_BYTE_SWAP);
283                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
284                 DUMP_REG(DC_WIN_COLOR_DEPTH);
285                 DUMP_REG(DC_WIN_POSITION);
286                 DUMP_REG(DC_WIN_SIZE);
287                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
288                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
289                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
290                 DUMP_REG(DC_WIN_DDA_INCREMENT);
291                 DUMP_REG(DC_WIN_LINE_STRIDE);
292                 DUMP_REG(DC_WIN_BUF_STRIDE);
293                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
294                 DUMP_REG(DC_WIN_BLEND_NOKEY);
295                 DUMP_REG(DC_WIN_BLEND_1WIN);
296                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
297                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
298                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
299                 DUMP_REG(DC_WINBUF_START_ADDR);
300                 DUMP_REG(DC_WINBUF_START_ADDR_U);
301                 DUMP_REG(DC_WINBUF_START_ADDR_V);
302                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
303                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
304                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
305                 DUMP_REG(DC_WIN_CSC_YOF);
306                 DUMP_REG(DC_WIN_CSC_KYRGB);
307                 DUMP_REG(DC_WIN_CSC_KUR);
308                 DUMP_REG(DC_WIN_CSC_KVR);
309                 DUMP_REG(DC_WIN_CSC_KUG);
310                 DUMP_REG(DC_WIN_CSC_KVG);
311                 DUMP_REG(DC_WIN_CSC_KUB);
312                 DUMP_REG(DC_WIN_CSC_KVB);
313         }
314
315         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
316         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
317         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
318         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
319         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
321         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
322         DUMP_REG(DC_DISP_M1_CONTROL);
323         DUMP_REG(DC_COM_PM1_CONTROL);
324         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
325         DUMP_REG(DC_DISP_SD_CONTROL);
326
327         clk_disable(dc->clk);
328         tegra_dc_io_end(dc);
329 }
330
331 #undef DUMP_REG
332
333 #ifdef DEBUG
334 static void dump_regs_print(void *data, const char *str)
335 {
336         struct tegra_dc *dc = data;
337         dev_dbg(&dc->ndev->dev, "%s", str);
338 }
339
340 static void dump_regs(struct tegra_dc *dc)
341 {
342         _dump_regs(dc, dc, dump_regs_print);
343 }
344 #else /* !DEBUG */
345
346 static void dump_regs(struct tegra_dc *dc) {}
347
348 #endif /* DEBUG */
349
350 #ifdef CONFIG_DEBUG_FS
351
352 static void dbg_regs_print(void *data, const char *str)
353 {
354         struct seq_file *s = data;
355
356         seq_printf(s, "%s", str);
357 }
358
359 #undef DUMP_REG
360
361 static int dbg_dc_show(struct seq_file *s, void *unused)
362 {
363         struct tegra_dc *dc = s->private;
364
365         _dump_regs(dc, s, dbg_regs_print);
366
367         return 0;
368 }
369
370
371 static int dbg_dc_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_show, inode->i_private);
374 }
375
376 static const struct file_operations regs_fops = {
377         .open           = dbg_dc_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386         struct tegra_dc_mode *m;
387
388         mutex_lock(&dc->lock);
389         m = &dc->mode;
390         seq_printf(s,
391                 "pclk: %d\n"
392                 "h_ref_to_sync: %d\n"
393                 "v_ref_to_sync: %d\n"
394                 "h_sync_width: %d\n"
395                 "v_sync_width: %d\n"
396                 "h_back_porch: %d\n"
397                 "v_back_porch: %d\n"
398                 "h_active: %d\n"
399                 "v_active: %d\n"
400                 "h_front_porch: %d\n"
401                 "v_front_porch: %d\n"
402                 "stereo_mode: %d\n",
403                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
404                 m->h_sync_width, m->v_sync_width,
405                 m->h_back_porch, m->v_back_porch,
406                 m->h_active, m->v_active,
407                 m->h_front_porch, m->v_front_porch,
408                 m->stereo_mode);
409         mutex_unlock(&dc->lock);
410         return 0;
411 }
412
413 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
414 {
415         return single_open(file, dbg_dc_mode_show, inode->i_private);
416 }
417
418 static const struct file_operations mode_fops = {
419         .open           = dbg_dc_mode_open,
420         .read           = seq_read,
421         .llseek         = seq_lseek,
422         .release        = single_release,
423 };
424
425 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
426 {
427         struct tegra_dc *dc = s->private;
428
429         mutex_lock(&dc->lock);
430         seq_printf(s,
431                 "underflows: %llu\n"
432                 "underflows_a: %llu\n"
433                 "underflows_b: %llu\n"
434                 "underflows_c: %llu\n",
435                 dc->stats.underflows,
436                 dc->stats.underflows_a,
437                 dc->stats.underflows_b,
438                 dc->stats.underflows_c);
439         mutex_unlock(&dc->lock);
440
441         return 0;
442 }
443
444 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
445 {
446         return single_open(file, dbg_dc_stats_show, inode->i_private);
447 }
448
449 static const struct file_operations stats_fops = {
450         .open           = dbg_dc_stats_open,
451         .read           = seq_read,
452         .llseek         = seq_lseek,
453         .release        = single_release,
454 };
455
456 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
457 {
458         if (dc->debugdir)
459                 debugfs_remove_recursive(dc->debugdir);
460         dc->debugdir = NULL;
461 }
462
463 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
464 {
465         struct dentry *retval;
466
467         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
468         if (!dc->debugdir)
469                 goto remove_out;
470
471         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
472                 &regs_fops);
473         if (!retval)
474                 goto remove_out;
475
476         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
477                 &mode_fops);
478         if (!retval)
479                 goto remove_out;
480
481         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
482                 &stats_fops);
483         if (!retval)
484                 goto remove_out;
485
486         return;
487 remove_out:
488         dev_err(&dc->ndev->dev, "could not create debugfs\n");
489         tegra_dc_remove_debugfs(dc);
490 }
491
492 #else /* !CONFIG_DEBUGFS */
493 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
494 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
495 #endif /* CONFIG_DEBUGFS */
496
497 static int tegra_dc_set(struct tegra_dc *dc, int index)
498 {
499         int ret = 0;
500
501         mutex_lock(&tegra_dc_lock);
502         if (index >= TEGRA_MAX_DC) {
503                 ret = -EINVAL;
504                 goto out;
505         }
506
507         if (dc != NULL && tegra_dcs[index] != NULL) {
508                 ret = -EBUSY;
509                 goto out;
510         }
511
512         tegra_dcs[index] = dc;
513
514 out:
515         mutex_unlock(&tegra_dc_lock);
516
517         return ret;
518 }
519
520 unsigned int tegra_dc_has_multiple_dc(void)
521 {
522         unsigned int idx;
523         unsigned int cnt = 0;
524         struct tegra_dc *dc;
525
526         mutex_lock(&tegra_dc_lock);
527         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
528                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
529         mutex_unlock(&tegra_dc_lock);
530
531         return (cnt > 1);
532 }
533
534 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
535 {
536         if (idx < TEGRA_MAX_DC)
537                 return tegra_dcs[idx];
538         else
539                 return NULL;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_dc);
542
543 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
544 {
545         if (win >= dc->n_windows)
546                 return NULL;
547
548         return &dc->windows[win];
549 }
550 EXPORT_SYMBOL(tegra_dc_get_window);
551
552 static int get_topmost_window(u32 *depths, unsigned long *wins)
553 {
554         int idx, best = -1;
555
556         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
557                 if (best == -1 || depths[idx] < depths[best])
558                         best = idx;
559         }
560         clear_bit(best, wins);
561         return best;
562 }
563
564 bool tegra_dc_get_connected(struct tegra_dc *dc)
565 {
566         return dc->connected;
567 }
568 EXPORT_SYMBOL(tegra_dc_get_connected);
569
570 static u32 blend_topwin(u32 flags)
571 {
572         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
573                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
574         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
575                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
576         else
577                 return BLEND(NOKEY, FIX, 0xff, 0xff);
578 }
579
580 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
581 {
582         int other;
583
584         for (other = 0; other < DC_N_WINDOWS; other++) {
585                 if (other != idx && (xy-- == 0))
586                         break;
587         }
588         if (BIT(other) & behind_mask)
589                 return blend_topwin(flags[idx]);
590         else if (flags[other])
591                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
592         else
593                 return BLEND(NOKEY, FIX, 0x00, 0x00);
594 }
595
596 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
597 {
598         unsigned long infront_mask;
599         int first;
600
601         infront_mask = ~(behind_mask | BIT(idx));
602         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
603         first = ffs(infront_mask) - 1;
604
605         if (!infront_mask)
606                 return blend_topwin(flags[idx]);
607         else if (behind_mask && first != -1 && flags[first])
608                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
609         else
610                 return BLEND(NOKEY, FIX, 0x0, 0x0);
611 }
612
613 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
614 {
615         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
616
617         while (mask) {
618                 int idx = get_topmost_window(blend->z, &mask);
619
620                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
621                                 DC_CMD_DISPLAY_WINDOW_HEADER);
622                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
623                                 DC_WIN_BLEND_NOKEY);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_1WIN);
626                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
627                                 DC_WIN_BLEND_2WIN_X);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
629                                 DC_WIN_BLEND_2WIN_Y);
630                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
631                                 DC_WIN_BLEND_3WIN_XY);
632         }
633 }
634
635 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 {
637         csc->yof   = 0x00f0;
638         csc->kyrgb = 0x012a;
639         csc->kur   = 0x0000;
640         csc->kvr   = 0x0198;
641         csc->kug   = 0x039b;
642         csc->kvg   = 0x032f;
643         csc->kub   = 0x0204;
644         csc->kvb   = 0x0000;
645 }
646
647 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
648 {
649         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
650         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
651         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
652         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
653         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
654         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
655         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
656         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
657 }
658
659 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
660 {
661         mutex_lock(&dc->lock);
662
663         if (!dc->enabled) {
664                 mutex_unlock(&dc->lock);
665                 return -EFAULT;
666         }
667
668         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
669                         DC_CMD_DISPLAY_WINDOW_HEADER);
670
671         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
672
673         mutex_unlock(&dc->lock);
674
675         return 0;
676 }
677 EXPORT_SYMBOL(tegra_dc_update_csc);
678
679 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
680 {
681         int i;
682         for (i = 0; i < 256; i++)
683                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
684 }
685
686 static int tegra_dc_loop_lut(struct tegra_dc *dc,
687                              struct tegra_dc_win *win,
688                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
689 {
690         struct tegra_dc_lut *lut = &win->lut;
691         struct tegra_dc_lut *global_lut = &dc->fb_lut;
692         int i;
693         for (i = 0; i < 256; i++) {
694
695                 u32 r = (u32)lut->r[i];
696                 u32 g = (u32)lut->g[i];
697                 u32 b = (u32)lut->b[i];
698
699                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
700                         r = (u32)global_lut->r[r];
701                         g = (u32)global_lut->g[g];
702                         b = (u32)global_lut->b[b];
703                 }
704
705                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
706                         return 0;
707         }
708         return 1;
709 }
710
711 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
712 {
713         if (rgb != (i | (i<<8) | (i<<16)))
714                 return 0;
715         return 1;
716 }
717
718 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
719 {
720         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
721         return 1;
722 }
723
724 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
725 {
726         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
727
728         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
729
730         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
731                 val |= CP_ENABLE;
732         else
733                 val &= ~CP_ENABLE;
734
735         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
736 }
737
738 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
739 {
740         struct tegra_dc_win *win = &dc->windows[win_idx];
741
742         mutex_lock(&dc->lock);
743
744         if (!dc->enabled) {
745                 mutex_unlock(&dc->lock);
746                 return -EFAULT;
747         }
748
749         if (fbovr > 0)
750                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
751         else if (fbovr == 0)
752                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753
754         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
756         else
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
758
759         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
760                         DC_CMD_DISPLAY_WINDOW_HEADER);
761
762         tegra_dc_set_lut(dc, win);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768
769 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
770 {
771         if (win_idx > -1)
772                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
773
774         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
775                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
776                 if (err)
777                         return err;
778         }
779
780         return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_update_lut);
783
784 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
785 {
786         unsigned i;
787         unsigned v0 = 128;
788         unsigned v1 = 0;
789         /* linear horizontal and vertical filters */
790         for (i = 0; i < 16; i++) {
791                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
792                                 DC_WIN_H_FILTER_P(i));
793
794                 tegra_dc_writel(dc, v0,
795                                 DC_WIN_V_FILTER_P(i));
796                 v0 -= 8;
797                 v1 += 8;
798         }
799 }
800
801 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
802         struct tegra_dc_win *w)
803 {
804         /* windows A, B, C for first and second display */
805         static const enum tegra_la_id la_id_tab[2][3] = {
806                 /* first display */
807                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
808                         TEGRA_LA_DISPLAY_0C },
809                 /* second display */
810                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
811                         TEGRA_LA_DISPLAY_0CB },
812         };
813         /* window B V-filter tap for first and second display. */
814         static const enum tegra_la_id vfilter_tab[2] = {
815                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
816         };
817         unsigned long bw;
818
819         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
820         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
821         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
822
823         bw = w->new_bandwidth;
824
825         /* tegra_dc_get_bandwidth() treats V filter windows as double
826          * bandwidth, but LA has a seperate client for V filter */
827         if (w->idx == 1 && win_use_v_filter(w))
828                 bw /= 2;
829
830         /* our bandwidth is in bytes/sec, but LA takes MBps.
831          * round up bandwidth to 1MBps */
832         bw = bw / 1000000 + 1;
833
834 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
835         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
836         /* if window B, also set the 1B client for the 2-tap V filter. */
837         if (w->idx == 1)
838                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
839 #endif
840
841         w->bandwidth = w->new_bandwidth;
842 }
843
844 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
845                                                    struct tegra_dc_win *b)
846 {
847         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
848                 return 0;
849
850         /* because memory access to load the fifo can overlap, only care
851          * if windows overlap vertically */
852         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
853                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
854 }
855
856 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
857                                                  int n)
858 {
859         unsigned i;
860         unsigned j;
861         unsigned overlap_count;
862         unsigned max_bw = 0;
863
864         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
865                          "inaccurate.\n");
866
867         /* If we had a large number of windows, we would compute adjacency
868          * graph representing 2 window overlaps, find all cliques in the graph,
869          * assign bandwidth to each clique, and then select the clique with
870          * maximum bandwidth. But because we have at most 3 windows,
871          * implementing proper Bron-Kerbosh algorithm would be an overkill,
872          * brute force will suffice.
873          *
874          * Thus: find maximum bandwidth for either single or a pair of windows
875          * and count number of window pair overlaps. If there are three
876          * pairs, all 3 window overlap.
877          */
878
879         overlap_count = 0;
880         for (i = 0; i < n; i++) {
881                 unsigned int bw1;
882
883                 if (wins[i] == NULL)
884                         continue;
885                 bw1 = wins[i]->new_bandwidth;
886                 if (bw1 > max_bw)
887                         /* Single window */
888                         max_bw = bw1;
889
890                 for (j = i + 1; j < n; j++) {
891                         if (wins[j] == NULL)
892                                 continue;
893                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
894                                 unsigned int bw2 = wins[j]->new_bandwidth;
895                                 if (bw1 + bw2 > max_bw)
896                                         /* Window pair overlaps */
897                                         max_bw = bw1 + bw2;
898                                 overlap_count++;
899                         }
900                 }
901         }
902
903         if (overlap_count == 3)
904                 /* All three windows overlap */
905                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
906                          wins[2]->new_bandwidth;
907
908         return max_bw;
909 }
910
911 /*
912  * Calculate peak EMC bandwidth for each enabled window =
913  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
914  * (windows_tiling ? 2 : 1)
915  *
916  *
917  * note:
918  * (*) We use 2 tap V filter, so need double BW if use V filter
919  * (*) Tiling mode on T30 and DDR3 requires double BW
920  */
921 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
922         struct tegra_dc_win *w)
923 {
924         unsigned long ret;
925         int tiled_windows_bw_multiplier;
926         unsigned long bpp;
927
928         if (!WIN_IS_ENABLED(w))
929                 return 0;
930
931         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
932             w->out_w == 0 || w->out_h == 0)
933                 return 0;
934
935         tiled_windows_bw_multiplier =
936                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
937
938         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
939          * but the size reported by tegra_dc_fmt_bpp for the planar version
940          * is of the luma plane's size only. */
941         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
942                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
943         /* perform calculations with most significant bits of pixel clock
944          * to prevent overflow of long. */
945         ret = (unsigned long)(dc->mode.pclk >> 16) *
946                 bpp / 8 *
947                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
948                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
949
950 /*
951  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
952  * will request 147MBps from EMC.
953  */
954         ret = ret * 2 + ret / 10;
955
956         /* if overflowed */
957         if (ret > (1UL << 31))
958                 return ULONG_MAX;
959
960         return ret << 16; /* restore the scaling we did above */
961 }
962
963 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
964 {
965         int i;
966
967         BUG_ON(n > DC_N_WINDOWS);
968
969         /* emc rate and latency allowance both need to know per window
970          * bandwidths */
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *w = windows[i];
973                 if (w)
974                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
975         }
976
977         return tegra_dc_find_max_bandwidth(windows, n);
978 }
979
980 /* to save power, call when display memory clients would be idle */
981 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
982 {
983         if (dc->emc_clk_rate)
984                 clk_disable(dc->emc_clk);
985         dc->emc_clk_rate = 0;
986 }
987
988 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
989 {
990         unsigned i;
991
992         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
993                 if (!dc->emc_clk_rate) /* going from 0 to non-zero */
994                         clk_enable(dc->emc_clk);
995                 dc->emc_clk_rate = dc->new_emc_clk_rate;
996                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
997         }
998
999         for (i = 0; i < DC_N_WINDOWS; i++) {
1000                 struct tegra_dc_win *w = &dc->windows[i];
1001                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1002                         tegra_dc_set_latency_allowance(dc, w);
1003         }
1004 }
1005
1006 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1007 {
1008         unsigned long new_rate;
1009         struct tegra_dc *dc;
1010
1011         if (!use_dynamic_emc)
1012                 return 0;
1013
1014         dc = windows[0]->dc;
1015
1016         /* calculate the new rate based on this POST */
1017         new_rate = tegra_dc_get_bandwidth(windows, n);
1018         new_rate = EMC_BW_TO_FREQ(new_rate);
1019
1020         if (tegra_dc_has_multiple_dc())
1021                 new_rate = ULONG_MAX;
1022
1023         dc->new_emc_clk_rate = new_rate;
1024
1025         return 0;
1026 }
1027
1028 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1029                                   bool v, unsigned Bpp)
1030 {
1031         /*
1032          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1033          *           (post_scaled_size_in_pixels - 1)), MAX)
1034          * Where the value of MAX is as follows:
1035          * For V_DDA_INCREMENT: 15.0 (0xF000)
1036          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1037          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1038          */
1039
1040         fixed20_12 out = dfixed_init(out_int);
1041         u32 dda_inc;
1042         int max;
1043
1044         if (v) {
1045                 max = 15;
1046         } else {
1047                 switch (Bpp) {
1048                 default:
1049                         WARN_ON_ONCE(1);
1050                         /* fallthrough */
1051                 case 4:
1052                         max = 4;
1053                         break;
1054                 case 2:
1055                         max = 8;
1056                         break;
1057                 }
1058         }
1059
1060         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1061         in.full -= dfixed_const(1);
1062
1063         dda_inc = dfixed_div(in, out);
1064
1065         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1066
1067         return dda_inc;
1068 }
1069
1070 static inline u32 compute_initial_dda(fixed20_12 in)
1071 {
1072         return dfixed_frac(in);
1073 }
1074
1075 /* does not support updating windows on multiple dcs in one call */
1076 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1077 {
1078         struct tegra_dc *dc;
1079         unsigned long update_mask = GENERAL_ACT_REQ;
1080         unsigned long val;
1081         bool update_blend = false;
1082         int i;
1083
1084         dc = windows[0]->dc;
1085
1086         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1087                 cancel_delayed_work_sync(&dc->one_shot_work);
1088
1089         mutex_lock(&dc->lock);
1090
1091         if (!dc->enabled) {
1092                 mutex_unlock(&dc->lock);
1093                 return -EFAULT;
1094         }
1095
1096         if (no_vsync)
1097                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1098         else
1099                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1100
1101         for (i = 0; i < n; i++) {
1102                 struct tegra_dc_win *win = windows[i];
1103                 unsigned h_dda;
1104                 unsigned v_dda;
1105                 fixed20_12 h_offset, v_offset;
1106                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1107                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1108                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1109                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1110                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1111                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1112                 const bool filter_h = win_use_h_filter(win);
1113                 const bool filter_v = win_use_v_filter(win);
1114
1115                 if (win->z != dc->blend.z[win->idx]) {
1116                         dc->blend.z[win->idx] = win->z;
1117                         update_blend = true;
1118                 }
1119                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1120                         dc->blend.flags[win->idx]) {
1121                         dc->blend.flags[win->idx] =
1122                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1123                         update_blend = true;
1124                 }
1125
1126                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1127                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1128
1129                 if (!no_vsync)
1130                         update_mask |= WIN_A_ACT_REQ << win->idx;
1131
1132                 if (!WIN_IS_ENABLED(win)) {
1133                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1134                         continue;
1135                 }
1136
1137                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1138                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1139
1140                 tegra_dc_writel(dc,
1141                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1142                                 DC_WIN_POSITION);
1143                 tegra_dc_writel(dc,
1144                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1145                                 DC_WIN_SIZE);
1146                 tegra_dc_writel(dc,
1147                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1148                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1149                                 DC_WIN_PRESCALED_SIZE);
1150
1151                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1152                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1153                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1154                                 DC_WIN_DDA_INCREMENT);
1155                 h_dda = compute_initial_dda(win->x);
1156                 v_dda = compute_initial_dda(win->y);
1157                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1158                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1159
1160                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1161                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1162                 tegra_dc_writel(dc,
1163                                 (unsigned long)win->phys_addr,
1164                                 DC_WINBUF_START_ADDR);
1165
1166                 if (!yuvp) {
1167                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1168                 } else {
1169                         tegra_dc_writel(dc,
1170                                         (unsigned long)win->phys_addr_u,
1171                                         DC_WINBUF_START_ADDR_U);
1172                         tegra_dc_writel(dc,
1173                                         (unsigned long)win->phys_addr_v,
1174                                         DC_WINBUF_START_ADDR_V);
1175                         tegra_dc_writel(dc,
1176                                         LINE_STRIDE(win->stride) |
1177                                         UV_LINE_STRIDE(win->stride_uv),
1178                                         DC_WIN_LINE_STRIDE);
1179                 }
1180
1181                 h_offset = win->x;
1182                 if (invert_h) {
1183                         h_offset.full += win->w.full - dfixed_const(1);
1184                 }
1185
1186                 v_offset = win->y;
1187                 if (invert_v) {
1188                         v_offset.full += win->h.full - dfixed_const(1);
1189                 }
1190
1191                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1192                                 DC_WINBUF_ADDR_H_OFFSET);
1193                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1194                                 DC_WINBUF_ADDR_V_OFFSET);
1195
1196                 if (WIN_IS_TILED(win))
1197                         tegra_dc_writel(dc,
1198                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1199                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1200                                         DC_WIN_BUFFER_ADDR_MODE);
1201                 else
1202                         tegra_dc_writel(dc,
1203                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1204                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1205                                         DC_WIN_BUFFER_ADDR_MODE);
1206
1207                 val = WIN_ENABLE;
1208                 if (yuvp)
1209                         val |= CSC_ENABLE;
1210                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1211                         val |= COLOR_EXPAND;
1212
1213                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1214                         val |= CP_ENABLE;
1215
1216                 if (filter_h)
1217                         val |= H_FILTER_ENABLE;
1218                 if (filter_v)
1219                         val |= V_FILTER_ENABLE;
1220
1221                 if (invert_h)
1222                         val |= H_DIRECTION_DECREMENT;
1223                 if (invert_v)
1224                         val |= V_DIRECTION_DECREMENT;
1225
1226                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1227
1228                 win->dirty = no_vsync ? 0 : 1;
1229
1230                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1231                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1232                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1233                         __func__, win->idx, win->z,
1234                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1235                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1236                         win->out_x, win->out_y, win->out_w, win->out_h,
1237                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1238         }
1239
1240         if (update_blend) {
1241                 tegra_dc_set_blending(dc, &dc->blend);
1242                 for (i = 0; i < DC_N_WINDOWS; i++) {
1243                         if (!no_vsync)
1244                                 dc->windows[i].dirty = 1;
1245                         update_mask |= WIN_A_ACT_REQ << i;
1246                 }
1247         }
1248
1249         tegra_dc_set_dynamic_emc(windows, n);
1250
1251         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1252
1253         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1254         if (!no_vsync) {
1255                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1256                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1257                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1258         } else {
1259                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1260                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1261                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1262         }
1263
1264         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1265                 schedule_delayed_work(&dc->one_shot_work,
1266                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1267
1268         /* update EMC clock if calculated bandwidth has changed */
1269         tegra_dc_program_bandwidth(dc);
1270
1271         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1272                 update_mask |= NC_HOST_TRIG;
1273
1274         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1275
1276         mutex_unlock(&dc->lock);
1277
1278         return 0;
1279 }
1280 EXPORT_SYMBOL(tegra_dc_update_windows);
1281
1282 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1283 {
1284         return dc->syncpt[i].id;
1285 }
1286 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1287
1288 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1289 {
1290         u32 max;
1291
1292         mutex_lock(&dc->lock);
1293         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1294                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1295         dc->syncpt[i].max = max;
1296         mutex_unlock(&dc->lock);
1297
1298         return max;
1299 }
1300
1301 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1302 {
1303         mutex_lock(&dc->lock);
1304         if ( dc->enabled )
1305                 while (dc->syncpt[i].min < val) {
1306                         dc->syncpt[i].min++;
1307                         nvhost_syncpt_cpu_incr(
1308                                         &nvhost_get_host(dc->ndev)->syncpt,
1309                                         dc->syncpt[i].id);
1310                 }
1311         mutex_unlock(&dc->lock);
1312 }
1313
1314 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1315                                              int n)
1316 {
1317         int i;
1318
1319         for (i = 0; i < n; i++) {
1320                 if (windows[i]->dirty)
1321                         return false;
1322         }
1323
1324         return true;
1325 }
1326
1327 /* does not support syncing windows on multiple dcs in one call */
1328 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1329 {
1330         if (n < 1 || n > DC_N_WINDOWS)
1331                 return -EINVAL;
1332
1333         if (!windows[0]->dc->enabled)
1334                 return -EFAULT;
1335
1336 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1337         /* Don't want to timeout on simulator */
1338         return wait_event_interruptible(windows[0]->dc->wq,
1339                 tegra_dc_windows_are_clean(windows, n));
1340 #else
1341         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1342                                          tegra_dc_windows_are_clean(windows, n),
1343                                          HZ);
1344 #endif
1345 }
1346 EXPORT_SYMBOL(tegra_dc_sync_windows);
1347
1348 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1349 {
1350 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1351         return clk_get_rate(dc->clk);
1352 #else
1353         return 27000000;
1354 #endif
1355 }
1356
1357 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1358 {
1359         unsigned long rate;
1360         unsigned long div;
1361
1362         rate = tegra_dc_clk_get_rate(dc);
1363
1364         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1365
1366         if (div < 2)
1367                 return 0;
1368
1369         return rate * 2 / div;
1370 }
1371
1372 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1373 {
1374         unsigned long rate;
1375         unsigned long div;
1376
1377         rate = clk_get_rate(parent);
1378
1379         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1380
1381         if (div < 2)
1382                 return 0;
1383
1384         return rate * 2 / div;
1385 }
1386
1387 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1388 {
1389         int pclk;
1390
1391         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1392                 unsigned long rate;
1393                 struct clk *parent_clk =
1394                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1395
1396                 if (dc->out->parent_clk_backup &&
1397                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1398                         rate = tegra_dc_pclk_predict_rate(
1399                                 parent_clk, dc->mode.pclk);
1400                         /* use pll_d as last resort */
1401                         if (rate < (dc->mode.pclk / 100 * 99) ||
1402                             rate > (dc->mode.pclk / 100 * 109))
1403                                 parent_clk = clk_get_sys(
1404                                         NULL, dc->out->parent_clk_backup);
1405                 }
1406
1407                 if (clk_get_parent(clk) != parent_clk)
1408                         clk_set_parent(clk, parent_clk);
1409
1410                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1411                         struct clk *base_clk = clk_get_parent(parent_clk);
1412
1413                         /* Assuming either pll_d or pll_d2 is used */
1414                         rate = dc->mode.pclk * 2;
1415
1416                         if (rate != clk_get_rate(base_clk))
1417                                 clk_set_rate(base_clk, rate);
1418                 }
1419         }
1420
1421         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1422                 unsigned long rate;
1423                 struct clk *parent_clk =
1424                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1425                 struct clk *base_clk = clk_get_parent(parent_clk);
1426
1427                 /* needs to match tegra_dc_hdmi_supported_modes[]
1428                 and tegra_pll_d_freq_table[] */
1429                 if (dc->mode.pclk > 70000000)
1430                         rate = 594000000;
1431                 else if (dc->mode.pclk > 25200000)
1432                         rate = 216000000;
1433                 else
1434                         rate = 504000000;
1435
1436                 if (rate != clk_get_rate(base_clk))
1437                         clk_set_rate(base_clk, rate);
1438
1439                 if (clk_get_parent(clk) != parent_clk)
1440                         clk_set_parent(clk, parent_clk);
1441         }
1442
1443         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1444                 unsigned long rate;
1445                 struct clk *parent_clk;
1446                 struct clk *base_clk;
1447
1448                 if (clk == dc->clk) {
1449                         parent_clk = clk_get_sys(NULL,
1450                                         dc->out->parent_clk ? : "pll_d_out0");
1451                         base_clk = clk_get_parent(parent_clk);
1452                         tegra_clk_cfg_ex(base_clk,
1453                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1454                 } else {
1455                         if (dc->pdata->default_out->dsi->dsi_instance) {
1456                                 parent_clk = clk_get_sys(NULL,
1457                                         dc->out->parent_clk ? : "pll_d2_out0");
1458                                 base_clk = clk_get_parent(parent_clk);
1459                                 tegra_clk_cfg_ex(base_clk,
1460                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1461                         } else {
1462                                 parent_clk = clk_get_sys(NULL,
1463                                         dc->out->parent_clk ? : "pll_d_out0");
1464                                 base_clk = clk_get_parent(parent_clk);
1465                                 tegra_clk_cfg_ex(base_clk,
1466                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1467                         }
1468                 }
1469
1470                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1471                 if (rate != clk_get_rate(base_clk))
1472                         clk_set_rate(base_clk, rate);
1473
1474                 if (clk_get_parent(clk) != parent_clk)
1475                         clk_set_parent(clk, parent_clk);
1476         }
1477
1478         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1479         tegra_dvfs_set_rate(clk, pclk);
1480 }
1481
1482 /* return non-zero if constraint is violated */
1483 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1484 {
1485         long a, b;
1486
1487         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1488         a = 0;
1489
1490         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1491         b = mode->h_front_porch - 1;
1492
1493         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1494         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1495                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1496         /* check Constraint 1 and 6 */
1497         if (a > b)
1498                 return 1;
1499
1500         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1501         if (mode->h_sync_width < 1)
1502                 return 4;
1503
1504         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1505         if (mode->h_active < 16)
1506                 return 7;
1507
1508         if (href) {
1509                 if (b > a && a % 2)
1510                         *href = a + 1; /* use smallest even value */
1511                 else
1512                         *href = a; /* even or only possible value */
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1519 {
1520         long a;
1521         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1522
1523         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1524         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1525                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1526
1527         /* Constraint 6 */
1528         if (mode->v_front_porch < a + 1)
1529                 a = mode->v_front_porch - 1;
1530
1531         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1532         if (mode->v_sync_width < 1)
1533                 return 4;
1534
1535         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1536         if (mode->v_active < 16)
1537                 return 7;
1538
1539         if (vref)
1540                 *vref = a;
1541         return 0;
1542 }
1543
1544 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1545 {
1546         int ret;
1547         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1548         if (ret)
1549                 return ret;
1550         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1551         if (ret)
1552                 return ret;
1553
1554         return 0;
1555 }
1556
1557 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1558 {
1559         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1560         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1561                 return false;
1562
1563         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1564         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1565                 return false;
1566
1567         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1568          * (vertical blank). */
1569         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1570                 return false;
1571
1572         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1573         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1574                 return false;
1575
1576         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1577         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1578                 return false;
1579
1580         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1581          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1582         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1583                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1584                 return false;
1585
1586         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1587         if (mode->h_active < 16 || mode->v_active < 16)
1588                 return false;
1589
1590         return true;
1591 }
1592
1593 #ifdef DEBUG
1594 /* return in 1000ths of a Hertz */
1595 static int calc_refresh(const struct tegra_dc_mode *m)
1596 {
1597         long h_total, v_total, refresh;
1598         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1599                 m->h_sync_width;
1600         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1601                 m->v_sync_width;
1602         refresh = m->pclk / h_total;
1603         refresh *= 1000;
1604         refresh /= v_total;
1605         return refresh;
1606 }
1607
1608 static void print_mode(struct tegra_dc *dc,
1609                         const struct tegra_dc_mode *mode, const char *note)
1610 {
1611         if (mode) {
1612                 int refresh = calc_refresh(dc, mode);
1613                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1614                         note ? note : "",
1615                         mode->h_active, mode->v_active,
1616                         refresh / 1000, refresh % 1000,
1617                         mode->pclk);
1618         }
1619 }
1620 #else /* !DEBUG */
1621 static inline void print_mode(struct tegra_dc *dc,
1622                         const struct tegra_dc_mode *mode, const char *note) { }
1623 #endif /* DEBUG */
1624
1625 static inline void enable_dc_irq(unsigned int irq)
1626 {
1627 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1628         enable_irq(irq);
1629 #else
1630         /* Always disable DC interrupts on FPGA. */
1631         disable_irq(irq);
1632 #endif
1633 }
1634
1635 static inline void disable_dc_irq(unsigned int irq)
1636 {
1637         disable_irq(irq);
1638 }
1639
1640 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1641 {
1642         unsigned long val;
1643         unsigned long rate;
1644         unsigned long div;
1645         unsigned long pclk;
1646
1647         print_mode(dc, mode, __func__);
1648
1649         /* use default EMC rate when switching modes */
1650         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1651         tegra_dc_program_bandwidth(dc);
1652
1653         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1654         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1655                         DC_DISP_REF_TO_SYNC);
1656         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1657                         DC_DISP_SYNC_WIDTH);
1658         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1659                         DC_DISP_BACK_PORCH);
1660         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1661                         DC_DISP_DISP_ACTIVE);
1662         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1663                         DC_DISP_FRONT_PORCH);
1664
1665         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1666                         DC_DISP_DATA_ENABLE_OPTIONS);
1667
1668         /* TODO: MIPI/CRT/HDMI clock cals */
1669
1670         val = DISP_DATA_FORMAT_DF1P1C;
1671
1672         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1673                 val |= DISP_DATA_ALIGNMENT_MSB;
1674         else
1675                 val |= DISP_DATA_ALIGNMENT_LSB;
1676
1677         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1678                 val |= DISP_DATA_ORDER_RED_BLUE;
1679         else
1680                 val |= DISP_DATA_ORDER_BLUE_RED;
1681
1682         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1683
1684         rate = tegra_dc_clk_get_rate(dc);
1685
1686         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1687         if (pclk < (mode->pclk / 100 * 99) ||
1688             pclk > (mode->pclk / 100 * 109)) {
1689                 dev_err(&dc->ndev->dev,
1690                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1691                         rate, mode->pclk,
1692                         pclk, (mode->pclk / 100 * 99),
1693                         (mode->pclk / 100 * 109));
1694                 return -EINVAL;
1695         }
1696
1697         div = (rate * 2 / pclk) - 2;
1698
1699         tegra_dc_writel(dc, 0x00010001,
1700                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1701         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1702                         DC_DISP_DISP_CLOCK_CONTROL);
1703
1704 #ifdef CONFIG_SWITCH
1705         switch_set_state(&dc->modeset_switch,
1706                          (mode->h_active << 16) | mode->v_active);
1707 #endif
1708
1709         return 0;
1710 }
1711
1712
1713 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1714 {
1715         memcpy(&dc->mode, mode, sizeof(dc->mode));
1716
1717         print_mode(dc, mode, __func__);
1718
1719         return 0;
1720 }
1721 EXPORT_SYMBOL(tegra_dc_set_mode);
1722
1723 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1724                 const struct fb_videomode *fbmode, bool stereo_mode)
1725 {
1726         struct tegra_dc_mode mode;
1727
1728         if (!fbmode->pixclock)
1729                 return -EINVAL;
1730
1731         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1732         mode.h_sync_width = fbmode->hsync_len;
1733         mode.v_sync_width = fbmode->vsync_len;
1734         mode.h_back_porch = fbmode->left_margin;
1735         mode.v_back_porch = fbmode->upper_margin;
1736         mode.h_active = fbmode->xres;
1737         mode.v_active = fbmode->yres;
1738         mode.h_front_porch = fbmode->right_margin;
1739         mode.v_front_porch = fbmode->lower_margin;
1740         mode.stereo_mode = stereo_mode;
1741         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1742                 /* HDMI controller requires h_ref=1, v_ref=1 */
1743                 mode.h_ref_to_sync = 1;
1744                 mode.v_ref_to_sync = 1;
1745         } else {
1746                 calc_ref_to_sync(&mode);
1747         }
1748         if (!check_ref_to_sync(&mode)) {
1749                 dev_err(&dc->ndev->dev,
1750                                 "Display timing doesn't meet restrictions.\n");
1751                 return -EINVAL;
1752         }
1753         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1754                 mode.h_active, mode.v_active, mode.pclk,
1755                 mode.h_ref_to_sync, mode.v_ref_to_sync
1756         );
1757
1758 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1759         /* Double the pixel clock and update v_active only for frame packed mode */
1760         if (mode.stereo_mode) {
1761                 mode.pclk *= 2;
1762                 /* total v_active = yres*2 + activespace */
1763                 mode.v_active = fbmode->yres*2 +
1764                                 fbmode->vsync_len +
1765                                 fbmode->upper_margin +
1766                                 fbmode->lower_margin;
1767         }
1768 #endif
1769
1770         mode.flags = 0;
1771
1772         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1773                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1774
1775         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1776                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1777
1778         return tegra_dc_set_mode(dc, &mode);
1779 }
1780 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1781
1782 void
1783 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1784 {
1785         unsigned int ctrl;
1786         unsigned long out_sel;
1787         unsigned long cmd_state;
1788
1789         mutex_lock(&dc->lock);
1790         if (!dc->enabled) {
1791                 mutex_unlock(&dc->lock);
1792                 return;
1793         }
1794
1795         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1796                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1797                 cfg->clk_select);
1798
1799         /* The new value should be effected immediately */
1800         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1801         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1802
1803         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1804                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1805         else
1806                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1807
1808         switch (cfg->which_pwm) {
1809         case TEGRA_PWM_PM0:
1810                 /* Select the LM0 on PM0 */
1811                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1812                 out_sel &= ~(7 << 0);
1813                 out_sel |= (3 << 0);
1814                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1815                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1816                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1817                 break;
1818         case TEGRA_PWM_PM1:
1819                 /* Select the LM1 on PM1 */
1820                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1821                 out_sel &= ~(7 << 4);
1822                 out_sel |= (3 << 4);
1823                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1824                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1825                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1826                 break;
1827         default:
1828                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1829                 break;
1830         }
1831         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1832         mutex_unlock(&dc->lock);
1833 }
1834 EXPORT_SYMBOL(tegra_dc_config_pwm);
1835
1836 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1837                                 const struct tegra_dc_out_pin *pins,
1838                                 const unsigned int n_pins)
1839 {
1840         unsigned int i;
1841
1842         int name;
1843         int pol;
1844
1845         u32 pol1, pol3;
1846
1847         u32 set1, unset1;
1848         u32 set3, unset3;
1849
1850         set1 = set3 = unset1 = unset3 = 0;
1851
1852         for (i = 0; i < n_pins; i++) {
1853                 name = (pins + i)->name;
1854                 pol  = (pins + i)->pol;
1855
1856                 /* set polarity by name */
1857                 switch (name) {
1858                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1859                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1860                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1861                         else
1862                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1863                         break;
1864                 case TEGRA_DC_OUT_PIN_H_SYNC:
1865                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1866                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1867                         else
1868                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1869                         break;
1870                 case TEGRA_DC_OUT_PIN_V_SYNC:
1871                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1872                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1873                         else
1874                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1875                         break;
1876                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1877                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1878                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1879                         else
1880                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1881                         break;
1882                 default:
1883                         printk("Invalid argument in function %s\n",
1884                                __FUNCTION__);
1885                         break;
1886                 }
1887         }
1888
1889         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1890         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1891
1892         pol1 |= set1;
1893         pol1 &= ~unset1;
1894
1895         pol3 |= set3;
1896         pol3 &= ~unset3;
1897
1898         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1899         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1900 }
1901
1902 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1903 {
1904         dc->out = out;
1905
1906         if (out->n_modes > 0)
1907                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1908
1909         switch (out->type) {
1910         case TEGRA_DC_OUT_RGB:
1911                 dc->out_ops = &tegra_dc_rgb_ops;
1912                 break;
1913
1914         case TEGRA_DC_OUT_HDMI:
1915                 dc->out_ops = &tegra_dc_hdmi_ops;
1916                 break;
1917
1918         case TEGRA_DC_OUT_DSI:
1919                 dc->out_ops = &tegra_dc_dsi_ops;
1920                 break;
1921
1922         default:
1923                 dc->out_ops = NULL;
1924                 break;
1925         }
1926
1927         if (dc->out_ops && dc->out_ops->init)
1928                 dc->out_ops->init(dc);
1929
1930 }
1931
1932 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1933 {
1934         if (dc->out)
1935                 return dc->out->height;
1936         else
1937                 return 0;
1938 }
1939 EXPORT_SYMBOL(tegra_dc_get_out_height);
1940
1941 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1942 {
1943         if (dc->out)
1944                 return dc->out->width;
1945         else
1946                 return 0;
1947 }
1948 EXPORT_SYMBOL(tegra_dc_get_out_width);
1949
1950 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1951 {
1952         if (dc->out && dc->out->max_pixclock)
1953                 return dc->out->max_pixclock;
1954         else
1955                 return 0;
1956 }
1957 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1958
1959 void tegra_dc_enable_crc(struct tegra_dc *dc)
1960 {
1961         u32 val;
1962         tegra_dc_io_start(dc);
1963
1964         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1965                 CRC_ENABLE_ENABLE;
1966         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1967         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1968         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1969 }
1970
1971 void tegra_dc_disable_crc(struct tegra_dc *dc)
1972 {
1973         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1974         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1975         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1976
1977         tegra_dc_io_end(dc);
1978 }
1979
1980 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1981 {
1982         int crc = 0;
1983
1984         if(!dc) {
1985                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1986                 goto crc_error;
1987         }
1988
1989         /* TODO: Replace mdelay with code to sync VBlANK, since
1990          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1991         mdelay(TEGRA_CRC_LATCHED_DELAY);
1992
1993         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1994 crc_error:
1995         return crc;
1996 }
1997
1998 static void tegra_dc_vblank(struct work_struct *work)
1999 {
2000         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2001         bool nvsd_updated = false;
2002
2003         mutex_lock(&dc->lock);
2004
2005         /* Update the SD brightness */
2006         if (dc->enabled && dc->out->sd_settings)
2007                 nvsd_updated = nvsd_update_brightness(dc);
2008
2009         mutex_unlock(&dc->lock);
2010
2011         /* Do the actual brightness update outside of the mutex */
2012         if (nvsd_updated && dc->out->sd_settings &&
2013             dc->out->sd_settings->bl_device) {
2014
2015                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2016                 struct backlight_device *bl = platform_get_drvdata(pdev);
2017                 if (bl)
2018                         backlight_update_status(bl);
2019         }
2020 }
2021
2022 /* Must acquire dc lock before invoking this function. */
2023 void tegra_dc_host_trigger(struct tegra_dc *dc)
2024 {
2025         /* We release the lock here to prevent deadlock between
2026          * cancel_delayed_work_sync and one-shot work. */
2027         mutex_unlock(&dc->lock);
2028         cancel_delayed_work_sync(&dc->one_shot_work);
2029         mutex_lock(&dc->lock);
2030         schedule_delayed_work(&dc->one_shot_work,
2031                                 msecs_to_jiffies(dc->one_shot_delay_ms));
2032         tegra_dc_program_bandwidth(dc);
2033         tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
2034 }
2035
2036 static void tegra_dc_one_shot_worker(struct work_struct *work)
2037 {
2038         struct tegra_dc *dc = container_of(
2039                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2040         mutex_lock(&dc->lock);
2041         /* memory client has gone idle */
2042         tegra_dc_clear_bandwidth(dc);
2043         mutex_unlock(&dc->lock);
2044 }
2045
2046 /* return an arbitrarily large number if count overflow occurs.
2047  * make it a nice base-10 number to show up in stats output */
2048 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2049 {
2050         unsigned count = tegra_dc_readl(dc, reg);
2051         tegra_dc_writel(dc, 0, reg);
2052         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2053 }
2054
2055 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2056 {
2057         u32 val;
2058         int i;
2059
2060         dc->stats.underflows++;
2061         if (dc->underflow_mask & WIN_A_UF_INT)
2062                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2063                         DC_WINBUF_AD_UFLOW_STATUS);
2064         if (dc->underflow_mask & WIN_B_UF_INT)
2065                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2066                         DC_WINBUF_BD_UFLOW_STATUS);
2067         if (dc->underflow_mask & WIN_C_UF_INT)
2068                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2069                         DC_WINBUF_CD_UFLOW_STATUS);
2070
2071         /* Check for any underflow reset conditions */
2072         for (i = 0; i < DC_N_WINDOWS; i++) {
2073                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2074                         dc->windows[i].underflows++;
2075
2076 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2077                         if (dc->windows[i].underflows > 4)
2078                                 schedule_work(&dc->reset_work);
2079 #endif
2080                 } else {
2081                         dc->windows[i].underflows = 0;
2082                 }
2083         }
2084
2085         /* Clear the underflow mask now that we've checked it. */
2086         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2087         dc->underflow_mask = 0;
2088         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2089         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2090 }
2091
2092 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2093 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2094 {
2095 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2096         u32 val;
2097
2098         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2099         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2100             return true;
2101 #endif
2102         return false;
2103 }
2104
2105 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2106 {
2107         u32 val, i;
2108         u32 completed = 0;
2109         u32 dirty = 0;
2110
2111         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2112         for (i = 0; i < DC_N_WINDOWS; i++) {
2113 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2114                 /* FIXME: this is not needed when the simulator
2115                    clears WIN_x_UPDATE bits as in HW */
2116                 dc->windows[i].dirty = 0;
2117                 completed = 1;
2118 #else
2119                 if (!(val & (WIN_A_UPDATE << i))) {
2120                         dc->windows[i].dirty = 0;
2121                         completed = 1;
2122                 } else {
2123                         dirty = 1;
2124                 }
2125 #endif
2126         }
2127
2128         if (!dirty) {
2129                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2130                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2131                         val &= ~V_BLANK_INT;
2132                 else
2133                         val &= ~FRAME_END_INT;
2134                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2135         }
2136
2137         if (completed) {
2138                 if (!dirty) {
2139                         /* With the last completed window, go ahead
2140                            and enable the vblank interrupt for nvsd. */
2141                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2142                         val |= V_BLANK_INT;
2143                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2144                 }
2145
2146                 wake_up(&dc->wq);
2147         }
2148 }
2149
2150 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2151 {
2152         if (status & V_BLANK_INT) {
2153                 /* Sync up windows. */
2154                 tegra_dc_trigger_windows(dc);
2155
2156                 /* Schedule any additional bottom-half vblank actvities. */
2157                 schedule_work(&dc->vblank_work);
2158         }
2159
2160         if (status & FRAME_END_INT) {
2161                 /* Mark the frame_end as complete. */
2162                 if (!completion_done(&dc->frame_end_complete))
2163                         complete(&dc->frame_end_complete);
2164         }
2165 }
2166
2167 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2168 {
2169         if (status & V_BLANK_INT) {
2170                 /* Schedule any additional bottom-half vblank actvities. */
2171                 schedule_work(&dc->vblank_work);
2172
2173                 /* All windows updated. Mask subsequent V_BLANK interrupts */
2174                 if (!tegra_dc_windows_are_dirty(dc)) {
2175                         u32 val;
2176
2177                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2178                         val &= ~V_BLANK_INT;
2179                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2180                 }
2181         }
2182
2183         if (status & FRAME_END_INT) {
2184                 /* Mark the frame_end as complete. */
2185                 if (!completion_done(&dc->frame_end_complete))
2186                         complete(&dc->frame_end_complete);
2187
2188                 tegra_dc_trigger_windows(dc);
2189         }
2190 }
2191 #endif
2192
2193 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2194 {
2195 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2196         struct tegra_dc *dc = ptr;
2197         unsigned long status;
2198         unsigned long underflow_mask;
2199         u32 val;
2200
2201         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2202                 WARN(1, "IRQ when DC not powered!\n");
2203                 tegra_dc_io_start(dc);
2204                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2205                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2206                 tegra_dc_io_end(dc);
2207                 return IRQ_HANDLED;
2208         }
2209
2210         /* clear all status flags except underflow, save those for the worker */
2211         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2212         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2213         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2214         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2215
2216         /*
2217          * Overlays can get thier internal state corrupted during and underflow
2218          * condition.  The only way to fix this state is to reset the DC.
2219          * if we get 4 consecutive frames with underflows, assume we're
2220          * hosed and reset.
2221          */
2222         underflow_mask = status & ALL_UF_INT;
2223
2224         /* Check underflow */
2225         if (underflow_mask) {
2226                 dc->underflow_mask |= underflow_mask;
2227                 schedule_delayed_work(&dc->underflow_work,
2228                         msecs_to_jiffies(1));
2229         }
2230
2231         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2232                 tegra_dc_one_shot_irq(dc, status);
2233         else
2234                 tegra_dc_continuous_irq(dc, status);
2235
2236         return IRQ_HANDLED;
2237 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2238         return IRQ_NONE;
2239 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2240 }
2241
2242 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2243 {
2244         u32 color_control;
2245
2246         switch (dc->out->depth) {
2247         case 3:
2248                 color_control = BASE_COLOR_SIZE111;
2249                 break;
2250
2251         case 6:
2252                 color_control = BASE_COLOR_SIZE222;
2253                 break;
2254
2255         case 8:
2256                 color_control = BASE_COLOR_SIZE332;
2257                 break;
2258
2259         case 9:
2260                 color_control = BASE_COLOR_SIZE333;
2261                 break;
2262
2263         case 12:
2264                 color_control = BASE_COLOR_SIZE444;
2265                 break;
2266
2267         case 15:
2268                 color_control = BASE_COLOR_SIZE555;
2269                 break;
2270
2271         case 16:
2272                 color_control = BASE_COLOR_SIZE565;
2273                 break;
2274
2275         case 18:
2276                 color_control = BASE_COLOR_SIZE666;
2277                 break;
2278
2279         default:
2280                 color_control = BASE_COLOR_SIZE888;
2281                 break;
2282         }
2283
2284         switch (dc->out->dither) {
2285         case TEGRA_DC_DISABLE_DITHER:
2286                 color_control |= DITHER_CONTROL_DISABLE;
2287                 break;
2288         case TEGRA_DC_ORDERED_DITHER:
2289                 color_control |= DITHER_CONTROL_ORDERED;
2290                 break;
2291         case TEGRA_DC_ERRDIFF_DITHER:
2292                 /* The line buffer for error-diffusion dither is limited
2293                  * to 1280 pixels per line. This limits the maximum
2294                  * horizontal active area size to 1280 pixels when error
2295                  * diffusion is enabled.
2296                  */
2297                 BUG_ON(dc->mode.h_active > 1280);
2298                 color_control |= DITHER_CONTROL_ERRDIFF;
2299                 break;
2300         }
2301
2302         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2303 }
2304
2305 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2306 {
2307         u32 syncpt_id;
2308
2309         switch (dc->ndev->id) {
2310         case 0:
2311                 switch (idx) {
2312                 case 0:
2313                         syncpt_id = NVSYNCPT_DISP0_A;
2314                         break;
2315                 case 1:
2316                         syncpt_id = NVSYNCPT_DISP0_B;
2317                         break;
2318                 case 2:
2319                         syncpt_id = NVSYNCPT_DISP0_C;
2320                         break;
2321                 default:
2322                         BUG();
2323                         break;
2324                 }
2325                 break;
2326         case 1:
2327                 switch (idx) {
2328                 case 0:
2329                         syncpt_id = NVSYNCPT_DISP1_A;
2330                         break;
2331                 case 1:
2332                         syncpt_id = NVSYNCPT_DISP1_B;
2333                         break;
2334                 case 2:
2335                         syncpt_id = NVSYNCPT_DISP1_C;
2336                         break;
2337                 default:
2338                         BUG();
2339                         break;
2340                 }
2341                 break;
2342         default:
2343                 BUG();
2344                 break;
2345         }
2346
2347         return syncpt_id;
2348 }
2349
2350 static void tegra_dc_init(struct tegra_dc *dc)
2351 {
2352         int i;
2353
2354         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2355         if (dc->ndev->id == 0) {
2356                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2357                                       TEGRA_MC_PRIO_MED);
2358                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2359                                       TEGRA_MC_PRIO_MED);
2360                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2361                                       TEGRA_MC_PRIO_MED);
2362                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2363                                       TEGRA_MC_PRIO_MED);
2364                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2365                                       TEGRA_MC_PRIO_HIGH);
2366         } else if (dc->ndev->id == 1) {
2367                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2368                                       TEGRA_MC_PRIO_MED);
2369                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2370                                       TEGRA_MC_PRIO_MED);
2371                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2372                                       TEGRA_MC_PRIO_MED);
2373                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2374                                       TEGRA_MC_PRIO_MED);
2375                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2376                                       TEGRA_MC_PRIO_HIGH);
2377         }
2378         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2379                         DC_CMD_CONT_SYNCPT_VSYNC);
2380         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2381         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2382         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2383         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2384
2385         /* enable interrupts for vblank, frame_end and underflows */
2386         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2387                 DC_CMD_INT_ENABLE);
2388         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2389
2390         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2391
2392         tegra_dc_set_color_control(dc);
2393         for (i = 0; i < DC_N_WINDOWS; i++) {
2394                 struct tegra_dc_win *win = &dc->windows[i];
2395                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2396                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2397                 tegra_dc_set_csc(dc, &win->csc);
2398                 tegra_dc_set_lut(dc, win);
2399                 tegra_dc_set_scaling_filter(dc);
2400         }
2401
2402
2403         for (i = 0; i < dc->n_windows; i++) {
2404                 u32 syncpt = get_syncpt(dc, i);
2405
2406                 dc->syncpt[i].id = syncpt;
2407
2408                 dc->syncpt[i].min = dc->syncpt[i].max =
2409                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2410                                         syncpt);
2411         }
2412
2413         print_mode(dc, &dc->mode, __func__);
2414
2415         if (dc->mode.pclk)
2416                 tegra_dc_program_mode(dc, &dc->mode);
2417
2418         /* Initialize SD AFTER the modeset.
2419            nvsd_init handles the sd_settings = NULL case. */
2420         nvsd_init(dc, dc->out->sd_settings);
2421 }
2422
2423 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2424 {
2425         if (dc->out->enable)
2426                 dc->out->enable();
2427
2428         tegra_dc_setup_clk(dc, dc->clk);
2429         clk_enable(dc->clk);
2430
2431         /* do not accept interrupts during initialization */
2432         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2433         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2434
2435         enable_dc_irq(dc->irq);
2436
2437         tegra_dc_init(dc);
2438
2439         if (dc->out_ops && dc->out_ops->enable)
2440                 dc->out_ops->enable(dc);
2441
2442         if (dc->out->postpoweron)
2443                 dc->out->postpoweron();
2444
2445         /* force a full blending update */
2446         dc->blend.z[0] = -1;
2447
2448         tegra_dc_ext_enable(dc->ext);
2449
2450         return true;
2451 }
2452
2453 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2454 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2455 {
2456         if (dc->out->enable)
2457                 dc->out->enable();
2458
2459         tegra_dc_setup_clk(dc, dc->clk);
2460         clk_enable(dc->clk);
2461
2462         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2463                 mutex_lock(&tegra_dcs[1]->lock);
2464                 disable_irq(tegra_dcs[1]->irq);
2465         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2466                 mutex_lock(&tegra_dcs[0]->lock);
2467                 disable_irq(tegra_dcs[0]->irq);
2468         }
2469
2470         msleep(5);
2471         tegra_periph_reset_assert(dc->clk);
2472         msleep(2);
2473 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2474         tegra_periph_reset_deassert(dc->clk);
2475         msleep(1);
2476 #endif
2477
2478         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2479                 enable_dc_irq(tegra_dcs[1]->irq);
2480                 mutex_unlock(&tegra_dcs[1]->lock);
2481         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2482                 enable_dc_irq(tegra_dcs[0]->irq);
2483                 mutex_unlock(&tegra_dcs[0]->lock);
2484         }
2485
2486         enable_dc_irq(dc->irq);
2487
2488         tegra_dc_init(dc);
2489
2490         if (dc->out_ops && dc->out_ops->enable)
2491                 dc->out_ops->enable(dc);
2492
2493         if (dc->out->postpoweron)
2494                 dc->out->postpoweron();
2495
2496         /* force a full blending update */
2497         dc->blend.z[0] = -1;
2498
2499         tegra_dc_ext_enable(dc->ext);
2500
2501         return true;
2502 }
2503 #endif
2504
2505 static bool _tegra_dc_enable(struct tegra_dc *dc)
2506 {
2507         if (dc->mode.pclk == 0)
2508                 return false;
2509
2510         if (!dc->out)
2511                 return false;
2512
2513         tegra_dc_io_start(dc);
2514
2515         return _tegra_dc_controller_enable(dc);
2516 }
2517
2518 void tegra_dc_enable(struct tegra_dc *dc)
2519 {
2520         mutex_lock(&dc->lock);
2521
2522         if (!dc->enabled)
2523                 dc->enabled = _tegra_dc_enable(dc);
2524
2525         mutex_unlock(&dc->lock);
2526 }
2527
2528 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2529 {
2530         unsigned i;
2531
2532         if (dc->out_ops && dc->out_ops->disable)
2533                 dc->out_ops->disable(dc);
2534
2535         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2536         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2537         disable_irq(dc->irq);
2538
2539         tegra_dc_clear_bandwidth(dc);
2540         clk_disable(dc->clk);
2541         tegra_dvfs_set_rate(dc->clk, 0);
2542
2543         if (dc->out && dc->out->disable)
2544                 dc->out->disable();
2545
2546         for (i = 0; i < dc->n_windows; i++) {
2547                 struct tegra_dc_win *w = &dc->windows[i];
2548
2549                 /* reset window bandwidth */
2550                 w->bandwidth = 0;
2551                 w->new_bandwidth = 0;
2552
2553                 /* disable windows */
2554                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2555
2556                 /* flush any pending syncpt waits */
2557                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2558                         dc->syncpt[i].min++;
2559                         nvhost_syncpt_cpu_incr(
2560                                 &nvhost_get_host(dc->ndev)->syncpt,
2561                                 dc->syncpt[i].id);
2562                 }
2563         }
2564 }
2565
2566 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2567 {
2568 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2569         u32 val;
2570         if (dc->enabled)  {
2571                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2572                 if (enable)
2573                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2574                 else
2575                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2576                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2577         }
2578 #endif
2579 }
2580
2581 bool tegra_dc_stats_get(struct tegra_dc *dc)
2582 {
2583 #if 0 /* right now it is always enabled */
2584         u32 val;
2585         bool res;
2586
2587         if (dc->enabled)  {
2588                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2589                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2590         } else {
2591                 res = false;
2592         }
2593
2594         return res;
2595 #endif
2596         return true;
2597 }
2598
2599 /* make the screen blank by disabling all windows */
2600 void tegra_dc_blank(struct tegra_dc *dc)
2601 {
2602         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2603         unsigned i;
2604
2605         for (i = 0; i < DC_N_WINDOWS; i++) {
2606                 dcwins[i] = tegra_dc_get_window(dc, i);
2607                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2608         }
2609
2610         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2611         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2612 }
2613
2614 static void _tegra_dc_disable(struct tegra_dc *dc)
2615 {
2616         _tegra_dc_controller_disable(dc);
2617         tegra_dc_io_end(dc);
2618 }
2619
2620 void tegra_dc_disable(struct tegra_dc *dc)
2621 {
2622         if (dc->overlay)
2623                 tegra_overlay_disable(dc->overlay);
2624
2625         tegra_dc_ext_disable(dc->ext);
2626
2627         /* it's important that new underflow work isn't scheduled before the
2628          * lock is acquired. */
2629         cancel_delayed_work_sync(&dc->underflow_work);
2630         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2631                 cancel_delayed_work_sync(&dc->one_shot_work);
2632
2633         mutex_lock(&dc->lock);
2634
2635         if (dc->enabled) {
2636                 dc->enabled = false;
2637
2638                 if (!dc->suspended)
2639                         _tegra_dc_disable(dc);
2640         }
2641
2642 #ifdef CONFIG_SWITCH
2643         switch_set_state(&dc->modeset_switch, 0);
2644 #endif
2645
2646         mutex_unlock(&dc->lock);
2647 }
2648
2649 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2650 static void tegra_dc_reset_worker(struct work_struct *work)
2651 {
2652         struct tegra_dc *dc =
2653                 container_of(work, struct tegra_dc, reset_work);
2654
2655         unsigned long val = 0;
2656
2657         mutex_lock(&shared_lock);
2658
2659         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2660
2661         tegra_dc_ext_disable(dc->ext);
2662
2663         mutex_lock(&dc->lock);
2664
2665         if (dc->enabled == false)
2666                 goto unlock;
2667
2668         dc->enabled = false;
2669
2670         /*
2671          * off host read bus
2672          */
2673         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2674         val &= ~(0x00000100);
2675         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2676
2677         /*
2678          * set DC to STOP mode
2679          */
2680         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2681
2682         msleep(10);
2683
2684         _tegra_dc_controller_disable(dc);
2685
2686         /* _tegra_dc_controller_reset_enable deasserts reset */
2687         _tegra_dc_controller_reset_enable(dc);
2688
2689         dc->enabled = true;
2690 unlock:
2691         mutex_unlock(&dc->lock);
2692         mutex_unlock(&shared_lock);
2693 }
2694 #endif
2695
2696 static void tegra_dc_underflow_worker(struct work_struct *work)
2697 {
2698         struct tegra_dc *dc = container_of(
2699                 to_delayed_work(work), struct tegra_dc, underflow_work);
2700
2701         mutex_lock(&dc->lock);
2702         if (dc->enabled) {
2703                 tegra_dc_underflow_handler(dc);
2704         }
2705         mutex_unlock(&dc->lock);
2706 }
2707
2708 #ifdef CONFIG_SWITCH
2709 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2710 {
2711         struct tegra_dc *dc =
2712                 container_of(sdev, struct tegra_dc, modeset_switch);
2713
2714         if (!sdev->state)
2715                 return sprintf(buf, "offline\n");
2716
2717         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2718 }
2719 #endif
2720
2721 static int tegra_dc_probe(struct nvhost_device *ndev)
2722 {
2723         struct tegra_dc *dc;
2724         struct clk *clk;
2725         struct clk *emc_clk;
2726         struct resource *res;
2727         struct resource *base_res;
2728         struct resource *fb_mem = NULL;
2729         int ret = 0;
2730         void __iomem *base;
2731         int irq;
2732         int i;
2733
2734         if (!ndev->dev.platform_data) {
2735                 dev_err(&ndev->dev, "no platform data\n");
2736                 return -ENOENT;
2737         }
2738
2739         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2740         if (!dc) {
2741                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2742                 return -ENOMEM;
2743         }
2744
2745         irq = nvhost_get_irq_byname(ndev, "irq");
2746         if (irq <= 0) {
2747                 dev_err(&ndev->dev, "no irq\n");
2748                 ret = -ENOENT;
2749                 goto err_free;
2750         }
2751
2752         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2753         if (!res) {
2754                 dev_err(&ndev->dev, "no mem resource\n");
2755                 ret = -ENOENT;
2756                 goto err_free;
2757         }
2758
2759         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2760         if (!base_res) {
2761                 dev_err(&ndev->dev, "request_mem_region failed\n");
2762                 ret = -EBUSY;
2763                 goto err_free;
2764         }
2765
2766         base = ioremap(res->start, resource_size(res));
2767         if (!base) {
2768                 dev_err(&ndev->dev, "registers can't be mapped\n");
2769                 ret = -EBUSY;
2770                 goto err_release_resource_reg;
2771         }
2772
2773         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2774
2775         clk = clk_get(&ndev->dev, NULL);
2776         if (IS_ERR_OR_NULL(clk)) {
2777                 dev_err(&ndev->dev, "can't get clock\n");
2778                 ret = -ENOENT;
2779                 goto err_iounmap_reg;
2780         }
2781
2782         emc_clk = clk_get(&ndev->dev, "emc");
2783         if (IS_ERR_OR_NULL(emc_clk)) {
2784                 dev_err(&ndev->dev, "can't get emc clock\n");
2785                 ret = -ENOENT;
2786                 goto err_put_clk;
2787         }
2788
2789         dc->clk = clk;
2790         dc->emc_clk = emc_clk;
2791         dc->shift_clk_div = 1;
2792         /* Initialize one shot work delay, it will be assigned by dsi
2793          * according to refresh rate later. */
2794         dc->one_shot_delay_ms = 40;
2795
2796         dc->base_res = base_res;
2797         dc->base = base;
2798         dc->irq = irq;
2799         dc->ndev = ndev;
2800         dc->pdata = ndev->dev.platform_data;
2801
2802         /*
2803          * The emc is a shared clock, it will be set based on
2804          * the requirements for each user on the bus.
2805          */
2806         dc->emc_clk_rate = 0;
2807
2808         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2809                 dc->enabled = true;
2810
2811         mutex_init(&dc->lock);
2812         init_completion(&dc->frame_end_complete);
2813         init_waitqueue_head(&dc->wq);
2814 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2815         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2816 #endif
2817         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2818         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2819         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2820
2821         tegra_dc_init_lut_defaults(&dc->fb_lut);
2822
2823         dc->n_windows = DC_N_WINDOWS;
2824         for (i = 0; i < dc->n_windows; i++) {
2825                 struct tegra_dc_win *win = &dc->windows[i];
2826                 win->idx = i;
2827                 win->dc = dc;
2828                 tegra_dc_init_csc_defaults(&win->csc);
2829                 tegra_dc_init_lut_defaults(&win->lut);
2830         }
2831
2832         ret = tegra_dc_set(dc, ndev->id);
2833         if (ret < 0) {
2834                 dev_err(&ndev->dev, "can't add dc\n");
2835                 goto err_free_irq;
2836         }
2837
2838         nvhost_set_drvdata(ndev, dc);
2839
2840 #ifdef CONFIG_SWITCH
2841         dc->modeset_switch.name = dev_name(&ndev->dev);
2842         dc->modeset_switch.state = 0;
2843         dc->modeset_switch.print_state = switch_modeset_print_mode;
2844         switch_dev_register(&dc->modeset_switch);
2845 #endif
2846
2847         if (dc->pdata->default_out)
2848                 tegra_dc_set_out(dc, dc->pdata->default_out);
2849         else
2850                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2851
2852         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2853                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2854
2855         dc->ext = tegra_dc_ext_register(ndev, dc);
2856         if (IS_ERR_OR_NULL(dc->ext)) {
2857                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2858                 dc->ext = NULL;
2859         }
2860
2861         /* interrupt handler must be registered before tegra_fb_register() */
2862         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2863                         dev_name(&ndev->dev), dc)) {
2864                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2865                 ret = -EBUSY;
2866                 goto err_put_emc_clk;
2867         }
2868
2869         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2870         disable_dc_irq(dc->irq);
2871
2872         mutex_lock(&dc->lock);
2873         if (dc->enabled)
2874                 _tegra_dc_enable(dc);
2875         mutex_unlock(&dc->lock);
2876
2877         tegra_dc_create_debugfs(dc);
2878
2879         dev_info(&ndev->dev, "probed\n");
2880
2881         if (dc->pdata->fb) {
2882                 if (dc->pdata->fb->bits_per_pixel == -1) {
2883                         unsigned long fmt;
2884                         tegra_dc_writel(dc,
2885                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2886                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2887
2888                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2889                         dc->pdata->fb->bits_per_pixel =
2890                                 tegra_dc_fmt_bpp(fmt);
2891                 }
2892
2893                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2894                 if (IS_ERR_OR_NULL(dc->fb))
2895                         dc->fb = NULL;
2896         }
2897
2898         if (dc->fb) {
2899                 dc->overlay = tegra_overlay_register(ndev, dc);
2900                 if (IS_ERR_OR_NULL(dc->overlay))
2901                         dc->overlay = NULL;
2902         }
2903
2904         if (dc->out && dc->out->hotplug_init)
2905                 dc->out->hotplug_init();
2906
2907         if (dc->out_ops && dc->out_ops->detect)
2908                 dc->out_ops->detect(dc);
2909         else
2910                 dc->connected = true;
2911
2912         tegra_dc_create_sysfs(&dc->ndev->dev);
2913
2914         return 0;
2915
2916 err_free_irq:
2917         free_irq(irq, dc);
2918 err_put_emc_clk:
2919         clk_put(emc_clk);
2920 err_put_clk:
2921         clk_put(clk);
2922 err_iounmap_reg:
2923         iounmap(base);
2924         if (fb_mem)
2925                 release_resource(fb_mem);
2926 err_release_resource_reg:
2927         release_resource(base_res);
2928 err_free:
2929         kfree(dc);
2930
2931         return ret;
2932 }
2933
2934 static int tegra_dc_remove(struct nvhost_device *ndev)
2935 {
2936         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2937
2938         tegra_dc_remove_sysfs(&dc->ndev->dev);
2939         tegra_dc_remove_debugfs(dc);
2940
2941         if (dc->overlay) {
2942                 tegra_overlay_unregister(dc->overlay);
2943         }
2944
2945         if (dc->fb) {
2946                 tegra_fb_unregister(dc->fb);
2947                 if (dc->fb_mem)
2948                         release_resource(dc->fb_mem);
2949         }
2950
2951         tegra_dc_ext_disable(dc->ext);
2952
2953         if (dc->ext)
2954                 tegra_dc_ext_unregister(dc->ext);
2955
2956         if (dc->enabled)
2957                 _tegra_dc_disable(dc);
2958
2959 #ifdef CONFIG_SWITCH
2960         switch_dev_unregister(&dc->modeset_switch);
2961 #endif
2962         free_irq(dc->irq, dc);
2963         clk_put(dc->emc_clk);
2964         clk_put(dc->clk);
2965         iounmap(dc->base);
2966         if (dc->fb_mem)
2967                 release_resource(dc->base_res);
2968         kfree(dc);
2969         tegra_dc_set(NULL, ndev->id);
2970         return 0;
2971 }
2972
2973 #ifdef CONFIG_PM
2974 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2975 {
2976         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2977
2978         dev_info(&ndev->dev, "suspend\n");
2979
2980         if (dc->overlay)
2981                 tegra_overlay_disable(dc->overlay);
2982
2983         tegra_dc_ext_disable(dc->ext);
2984
2985         mutex_lock(&dc->lock);
2986
2987         if (dc->out_ops && dc->out_ops->suspend)
2988                 dc->out_ops->suspend(dc);
2989
2990         if (dc->enabled) {
2991                 _tegra_dc_disable(dc);
2992
2993                 dc->suspended = true;
2994         }
2995
2996         if (dc->out && dc->out->postsuspend) {
2997                 dc->out->postsuspend();
2998                 msleep(100); /* avoid resume event due to voltage falling */
2999         }
3000
3001         mutex_unlock(&dc->lock);
3002
3003         return 0;
3004 }
3005
3006 static int tegra_dc_resume(struct nvhost_device *ndev)
3007 {
3008         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3009
3010         dev_info(&ndev->dev, "resume\n");
3011
3012         mutex_lock(&dc->lock);
3013         dc->suspended = false;
3014
3015         if (dc->enabled)
3016                 _tegra_dc_enable(dc);
3017
3018         if (dc->out && dc->out->hotplug_init)
3019                 dc->out->hotplug_init();
3020
3021         if (dc->out_ops && dc->out_ops->resume)
3022                 dc->out_ops->resume(dc);
3023         mutex_unlock(&dc->lock);
3024
3025         return 0;
3026 }
3027
3028 #endif /* CONFIG_PM */
3029
3030 extern int suspend_set(const char *val, struct kernel_param *kp)
3031 {
3032         if (!strcmp(val, "dump"))
3033                 dump_regs(tegra_dcs[0]);
3034 #ifdef CONFIG_PM
3035         else if (!strcmp(val, "suspend"))
3036                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3037         else if (!strcmp(val, "resume"))
3038                 tegra_dc_resume(tegra_dcs[0]->ndev);
3039 #endif
3040
3041         return 0;
3042 }
3043
3044 extern int suspend_get(char *buffer, struct kernel_param *kp)
3045 {
3046         return 0;
3047 }
3048
3049 int suspend;
3050
3051 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3052
3053 struct nvhost_driver tegra_dc_driver = {
3054         .driver = {
3055                 .name = "tegradc",
3056                 .owner = THIS_MODULE,
3057         },
3058         .probe = tegra_dc_probe,
3059         .remove = tegra_dc_remove,
3060 #ifdef CONFIG_PM
3061         .suspend = tegra_dc_suspend,
3062         .resume = tegra_dc_resume,
3063 #endif
3064 };
3065
3066 static int __init tegra_dc_module_init(void)
3067 {
3068         int ret = tegra_dc_ext_module_init();
3069         if (ret)
3070                 return ret;
3071         return nvhost_driver_register(&tegra_dc_driver);
3072 }
3073
3074 static void __exit tegra_dc_module_exit(void)
3075 {
3076         nvhost_driver_unregister(&tegra_dc_driver);
3077         tegra_dc_ext_module_exit();
3078 }
3079
3080 module_exit(tegra_dc_module_exit);
3081 module_init(tegra_dc_module_init);