1c0ff2a51bea23aadbe645a4be562960d3f51d43
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134                 return 8;
135
136         case TEGRA_WIN_FMT_YCbCr422:
137         case TEGRA_WIN_FMT_YUV422:
138         case TEGRA_WIN_FMT_YCbCr422R:
139         case TEGRA_WIN_FMT_YUV422R:
140         case TEGRA_WIN_FMT_YCbCr422RA:
141         case TEGRA_WIN_FMT_YUV422RA:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155                 return true;
156         }
157         return false;
158 }
159
160 #define DUMP_REG(a) do {                        \
161         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
162                  #a, a, tegra_dc_readl(dc, a));               \
163         print(data, buff);                                    \
164         } while (0)
165
166 static void _dump_regs(struct tegra_dc *dc, void *data,
167                        void (* print)(void *data, const char *str))
168 {
169         int i;
170         char buff[256];
171
172         tegra_dc_io_start(dc);
173         clk_enable(dc->clk);
174
175         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
176         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
177         DUMP_REG(DC_CMD_SIGNAL_RAISE);
178         DUMP_REG(DC_CMD_INT_STATUS);
179         DUMP_REG(DC_CMD_INT_MASK);
180         DUMP_REG(DC_CMD_INT_ENABLE);
181         DUMP_REG(DC_CMD_INT_TYPE);
182         DUMP_REG(DC_CMD_INT_POLARITY);
183         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
184         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
185         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
186         DUMP_REG(DC_CMD_STATE_ACCESS);
187         DUMP_REG(DC_CMD_STATE_CONTROL);
188         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
189         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
190
191         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
192         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
193         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
194         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
195         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
196         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
197         DUMP_REG(DC_DISP_REF_TO_SYNC);
198         DUMP_REG(DC_DISP_SYNC_WIDTH);
199         DUMP_REG(DC_DISP_BACK_PORCH);
200         DUMP_REG(DC_DISP_DISP_ACTIVE);
201         DUMP_REG(DC_DISP_FRONT_PORCH);
202         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
203         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
204         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
205         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
206         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
207         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
208         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
209         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
210         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
211         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
212         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
213         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
214         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
215         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
216         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
217         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
218         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
219         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
220         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
221         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
228         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
229         DUMP_REG(DC_DISP_M0_CONTROL);
230         DUMP_REG(DC_DISP_M1_CONTROL);
231         DUMP_REG(DC_DISP_DI_CONTROL);
232         DUMP_REG(DC_DISP_PP_CONTROL);
233         DUMP_REG(DC_DISP_PP_SELECT_A);
234         DUMP_REG(DC_DISP_PP_SELECT_B);
235         DUMP_REG(DC_DISP_PP_SELECT_C);
236         DUMP_REG(DC_DISP_PP_SELECT_D);
237         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
238         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
239         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
240         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
241         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
242         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
243         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
244         DUMP_REG(DC_DISP_BORDER_COLOR);
245         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
246         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
247         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
248         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
249         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
250         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
251         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
252         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
253         DUMP_REG(DC_DISP_CURSOR_POSITION);
254         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
255         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
256         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
257         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
258         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
259         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
260         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
261         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
262         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
263         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
264         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
265         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
266         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
267
268
269         for (i = 0; i < 3; i++) {
270                 print(data, "\n");
271                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
272                 print(data, buff);
273
274                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
275                                 DC_CMD_DISPLAY_WINDOW_HEADER);
276                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
277                 DUMP_REG(DC_WIN_WIN_OPTIONS);
278                 DUMP_REG(DC_WIN_BYTE_SWAP);
279                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
280                 DUMP_REG(DC_WIN_COLOR_DEPTH);
281                 DUMP_REG(DC_WIN_POSITION);
282                 DUMP_REG(DC_WIN_SIZE);
283                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
284                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
285                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
286                 DUMP_REG(DC_WIN_DDA_INCREMENT);
287                 DUMP_REG(DC_WIN_LINE_STRIDE);
288                 DUMP_REG(DC_WIN_BUF_STRIDE);
289                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
290                 DUMP_REG(DC_WIN_BLEND_NOKEY);
291                 DUMP_REG(DC_WIN_BLEND_1WIN);
292                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
293                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
294                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
295                 DUMP_REG(DC_WINBUF_START_ADDR);
296                 DUMP_REG(DC_WINBUF_START_ADDR_U);
297                 DUMP_REG(DC_WINBUF_START_ADDR_V);
298                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
299                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
300                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
301                 DUMP_REG(DC_WIN_CSC_YOF);
302                 DUMP_REG(DC_WIN_CSC_KYRGB);
303                 DUMP_REG(DC_WIN_CSC_KUR);
304                 DUMP_REG(DC_WIN_CSC_KVR);
305                 DUMP_REG(DC_WIN_CSC_KUG);
306                 DUMP_REG(DC_WIN_CSC_KVG);
307                 DUMP_REG(DC_WIN_CSC_KUB);
308                 DUMP_REG(DC_WIN_CSC_KVB);
309         }
310
311         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
312         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
313         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
314         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
315         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
316         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
317         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
318         DUMP_REG(DC_DISP_M1_CONTROL);
319         DUMP_REG(DC_COM_PM1_CONTROL);
320         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
321         DUMP_REG(DC_DISP_SD_CONTROL);
322
323         clk_disable(dc->clk);
324         tegra_dc_io_end(dc);
325 }
326
327 #undef DUMP_REG
328
329 #ifdef DEBUG
330 static void dump_regs_print(void *data, const char *str)
331 {
332         struct tegra_dc *dc = data;
333         dev_dbg(&dc->ndev->dev, "%s", str);
334 }
335
336 static void dump_regs(struct tegra_dc *dc)
337 {
338         _dump_regs(dc, dc, dump_regs_print);
339 }
340 #else /* !DEBUG */
341
342 static void dump_regs(struct tegra_dc *dc) {}
343
344 #endif /* DEBUG */
345
346 #ifdef CONFIG_DEBUG_FS
347
348 static void dbg_regs_print(void *data, const char *str)
349 {
350         struct seq_file *s = data;
351
352         seq_printf(s, "%s", str);
353 }
354
355 #undef DUMP_REG
356
357 static int dbg_dc_show(struct seq_file *s, void *unused)
358 {
359         struct tegra_dc *dc = s->private;
360
361         _dump_regs(dc, s, dbg_regs_print);
362
363         return 0;
364 }
365
366
367 static int dbg_dc_open(struct inode *inode, struct file *file)
368 {
369         return single_open(file, dbg_dc_show, inode->i_private);
370 }
371
372 static const struct file_operations regs_fops = {
373         .open           = dbg_dc_open,
374         .read           = seq_read,
375         .llseek         = seq_lseek,
376         .release        = single_release,
377 };
378
379 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
380 {
381         struct tegra_dc *dc = s->private;
382         struct tegra_dc_mode *m;
383
384         mutex_lock(&dc->lock);
385         m = &dc->mode;
386         seq_printf(s,
387                 "pclk: %d\n"
388                 "h_ref_to_sync: %d\n"
389                 "v_ref_to_sync: %d\n"
390                 "h_sync_width: %d\n"
391                 "v_sync_width: %d\n"
392                 "h_back_porch: %d\n"
393                 "v_back_porch: %d\n"
394                 "h_active: %d\n"
395                 "v_active: %d\n"
396                 "h_front_porch: %d\n"
397                 "v_front_porch: %d\n"
398                 "stereo_mode: %d\n",
399                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
400                 m->h_sync_width, m->v_sync_width,
401                 m->h_back_porch, m->v_back_porch,
402                 m->h_active, m->v_active,
403                 m->h_front_porch, m->v_front_porch,
404                 m->stereo_mode);
405         mutex_unlock(&dc->lock);
406         return 0;
407 }
408
409 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
410 {
411         return single_open(file, dbg_dc_mode_show, inode->i_private);
412 }
413
414 static const struct file_operations mode_fops = {
415         .open           = dbg_dc_mode_open,
416         .read           = seq_read,
417         .llseek         = seq_lseek,
418         .release        = single_release,
419 };
420
421 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
422 {
423         struct tegra_dc *dc = s->private;
424
425         mutex_lock(&dc->lock);
426         seq_printf(s,
427                 "underflows: %llu\n"
428                 "underflows_a: %llu\n"
429                 "underflows_b: %llu\n"
430                 "underflows_c: %llu\n",
431                 dc->stats.underflows,
432                 dc->stats.underflows_a,
433                 dc->stats.underflows_b,
434                 dc->stats.underflows_c);
435         mutex_unlock(&dc->lock);
436
437         return 0;
438 }
439
440 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
441 {
442         return single_open(file, dbg_dc_stats_show, inode->i_private);
443 }
444
445 static const struct file_operations stats_fops = {
446         .open           = dbg_dc_stats_open,
447         .read           = seq_read,
448         .llseek         = seq_lseek,
449         .release        = single_release,
450 };
451
452 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
453 {
454         if (dc->debugdir)
455                 debugfs_remove_recursive(dc->debugdir);
456         dc->debugdir = NULL;
457 }
458
459 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
460 {
461         struct dentry *retval;
462
463         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
464         if (!dc->debugdir)
465                 goto remove_out;
466
467         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
468                 &regs_fops);
469         if (!retval)
470                 goto remove_out;
471
472         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
473                 &mode_fops);
474         if (!retval)
475                 goto remove_out;
476
477         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
478                 &stats_fops);
479         if (!retval)
480                 goto remove_out;
481
482         return;
483 remove_out:
484         dev_err(&dc->ndev->dev, "could not create debugfs\n");
485         tegra_dc_remove_debugfs(dc);
486 }
487
488 #else /* !CONFIG_DEBUGFS */
489 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
490 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
491 #endif /* CONFIG_DEBUGFS */
492
493 static int tegra_dc_set(struct tegra_dc *dc, int index)
494 {
495         int ret = 0;
496
497         mutex_lock(&tegra_dc_lock);
498         if (index >= TEGRA_MAX_DC) {
499                 ret = -EINVAL;
500                 goto out;
501         }
502
503         if (dc != NULL && tegra_dcs[index] != NULL) {
504                 ret = -EBUSY;
505                 goto out;
506         }
507
508         tegra_dcs[index] = dc;
509
510 out:
511         mutex_unlock(&tegra_dc_lock);
512
513         return ret;
514 }
515
516 unsigned int tegra_dc_has_multiple_dc(void)
517 {
518         unsigned int idx;
519         unsigned int cnt = 0;
520         struct tegra_dc *dc;
521
522         mutex_lock(&tegra_dc_lock);
523         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
524                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
525         mutex_unlock(&tegra_dc_lock);
526
527         return (cnt > 1);
528 }
529
530 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
531 {
532         if (idx < TEGRA_MAX_DC)
533                 return tegra_dcs[idx];
534         else
535                 return NULL;
536 }
537 EXPORT_SYMBOL(tegra_dc_get_dc);
538
539 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
540 {
541         if (win >= dc->n_windows)
542                 return NULL;
543
544         return &dc->windows[win];
545 }
546 EXPORT_SYMBOL(tegra_dc_get_window);
547
548 static int get_topmost_window(u32 *depths, unsigned long *wins)
549 {
550         int idx, best = -1;
551
552         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
553                 if (best == -1 || depths[idx] < depths[best])
554                         best = idx;
555         }
556         clear_bit(best, wins);
557         return best;
558 }
559
560 bool tegra_dc_get_connected(struct tegra_dc *dc)
561 {
562         return dc->connected;
563 }
564 EXPORT_SYMBOL(tegra_dc_get_connected);
565
566 static u32 blend_topwin(u32 flags)
567 {
568         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
569                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
570         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
571                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
572         else
573                 return BLEND(NOKEY, FIX, 0xff, 0xff);
574 }
575
576 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
577 {
578         int other;
579
580         for (other = 0; other < DC_N_WINDOWS; other++) {
581                 if (other != idx && (xy-- == 0))
582                         break;
583         }
584         if (BIT(other) & behind_mask)
585                 return blend_topwin(flags[idx]);
586         else if (flags[other])
587                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
588         else
589                 return BLEND(NOKEY, FIX, 0x00, 0x00);
590 }
591
592 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
593 {
594         unsigned long infront_mask;
595         int first;
596
597         infront_mask = ~(behind_mask | BIT(idx));
598         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
599         first = ffs(infront_mask) - 1;
600
601         if (!infront_mask)
602                 return blend_topwin(flags[idx]);
603         else if (behind_mask && first != -1 && flags[first])
604                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
605         else
606                 return BLEND(NOKEY, FIX, 0x0, 0x0);
607 }
608
609 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
610 {
611         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
612
613         while (mask) {
614                 int idx = get_topmost_window(blend->z, &mask);
615
616                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
617                                 DC_CMD_DISPLAY_WINDOW_HEADER);
618                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
619                                 DC_WIN_BLEND_NOKEY);
620                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
621                                 DC_WIN_BLEND_1WIN);
622                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
623                                 DC_WIN_BLEND_2WIN_X);
624                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
625                                 DC_WIN_BLEND_2WIN_Y);
626                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
627                                 DC_WIN_BLEND_3WIN_XY);
628         }
629 }
630
631 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
632 {
633         csc->yof   = 0x00f0;
634         csc->kyrgb = 0x012a;
635         csc->kur   = 0x0000;
636         csc->kvr   = 0x0198;
637         csc->kug   = 0x039b;
638         csc->kvg   = 0x032f;
639         csc->kub   = 0x0204;
640         csc->kvb   = 0x0000;
641 }
642
643 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
644 {
645         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
646         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
647         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
648         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
649         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
650         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
651         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
652         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
653 }
654
655 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
656 {
657         mutex_lock(&dc->lock);
658
659         if (!dc->enabled) {
660                 mutex_unlock(&dc->lock);
661                 return -EFAULT;
662         }
663
664         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
665                         DC_CMD_DISPLAY_WINDOW_HEADER);
666
667         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
668
669         mutex_unlock(&dc->lock);
670
671         return 0;
672 }
673 EXPORT_SYMBOL(tegra_dc_update_csc);
674
675 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
676 {
677         int i;
678         for (i = 0; i < 256; i++)
679                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
680 }
681
682 static int tegra_dc_loop_lut(struct tegra_dc *dc,
683                              struct tegra_dc_win *win,
684                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
685 {
686         struct tegra_dc_lut *lut = &win->lut;
687         struct tegra_dc_lut *global_lut = &dc->fb_lut;
688         int i;
689         for (i = 0; i < 256; i++) {
690
691                 u32 r = (u32)lut->r[i];
692                 u32 g = (u32)lut->g[i];
693                 u32 b = (u32)lut->b[i];
694
695                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
696                         r = (u32)global_lut->r[r];
697                         g = (u32)global_lut->g[g];
698                         b = (u32)global_lut->b[b];
699                 }
700
701                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
702                         return 0;
703         }
704         return 1;
705 }
706
707 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
708 {
709         if (rgb != (i | (i<<8) | (i<<16)))
710                 return 0;
711         return 1;
712 }
713
714 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
715 {
716         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
717         return 1;
718 }
719
720 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
721 {
722         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
723
724         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
725
726         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
727                 val |= CP_ENABLE;
728         else
729                 val &= ~CP_ENABLE;
730
731         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
732 }
733
734 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
735 {
736         struct tegra_dc_win *win = &dc->windows[win_idx];
737
738         mutex_lock(&dc->lock);
739
740         if (!dc->enabled) {
741                 mutex_unlock(&dc->lock);
742                 return -EFAULT;
743         }
744
745         if (fbovr > 0)
746                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
747         else if (fbovr == 0)
748                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
749
750         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
751                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
752         else
753                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
754
755         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
756                         DC_CMD_DISPLAY_WINDOW_HEADER);
757
758         tegra_dc_set_lut(dc, win);
759
760         mutex_unlock(&dc->lock);
761
762         return 0;
763 }
764
765 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
766 {
767         if (win_idx > -1)
768                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
769
770         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
771                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
772                 if (err)
773                         return err;
774         }
775
776         return 0;
777 }
778 EXPORT_SYMBOL(tegra_dc_update_lut);
779
780 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
781 {
782         unsigned i;
783         unsigned v0 = 128;
784         unsigned v1 = 0;
785         /* linear horizontal and vertical filters */
786         for (i = 0; i < 16; i++) {
787                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
788                                 DC_WIN_H_FILTER_P(i));
789
790                 tegra_dc_writel(dc, v0,
791                                 DC_WIN_V_FILTER_P(i));
792                 v0 -= 8;
793                 v1 += 8;
794         }
795 }
796
797 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
798         struct tegra_dc_win *w)
799 {
800         /* windows A, B, C for first and second display */
801         static const enum tegra_la_id la_id_tab[2][3] = {
802                 /* first display */
803                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
804                         TEGRA_LA_DISPLAY_0C },
805                 /* second display */
806                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
807                         TEGRA_LA_DISPLAY_0CB },
808         };
809         /* window B V-filter tap for first and second display. */
810         static const enum tegra_la_id vfilter_tab[2] = {
811                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
812         };
813         unsigned long bw;
814
815         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
816         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
817         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
818
819         bw = w->new_bandwidth;
820
821         /* tegra_dc_get_bandwidth() treats V filter windows as double
822          * bandwidth, but LA has a seperate client for V filter */
823         if (w->idx == 1 && win_use_v_filter(w))
824                 bw /= 2;
825
826         /* our bandwidth is in bytes/sec, but LA takes MBps.
827          * round up bandwidth to 1MBps */
828         bw = bw / 1000000 + 1;
829
830 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
831         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
832         /* if window B, also set the 1B client for the 2-tap V filter. */
833         if (w->idx == 1)
834                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
835 #endif
836
837         w->bandwidth = w->new_bandwidth;
838 }
839
840 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
841                                                    struct tegra_dc_win *b)
842 {
843         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
844                 return 0;
845
846         /* because memory access to load the fifo can overlap, only care
847          * if windows overlap vertically */
848         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
849                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
850 }
851
852 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
853                                                  int n)
854 {
855         unsigned i;
856         unsigned j;
857         unsigned overlap_count;
858         unsigned max_bw = 0;
859
860         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
861                          "inaccurate.\n");
862
863         /* If we had a large number of windows, we would compute adjacency
864          * graph representing 2 window overlaps, find all cliques in the graph,
865          * assign bandwidth to each clique, and then select the clique with
866          * maximum bandwidth. But because we have at most 3 windows,
867          * implementing proper Bron-Kerbosh algorithm would be an overkill,
868          * brute force will suffice.
869          *
870          * Thus: find maximum bandwidth for either single or a pair of windows
871          * and count number of window pair overlaps. If there are three
872          * pairs, all 3 window overlap.
873          */
874
875         overlap_count = 0;
876         for (i = 0; i < n; i++) {
877                 unsigned int bw1;
878
879                 if (wins[i] == NULL)
880                         continue;
881                 bw1 = wins[i]->new_bandwidth;
882                 if (bw1 > max_bw)
883                         /* Single window */
884                         max_bw = bw1;
885
886                 for (j = i + 1; j < n; j++) {
887                         if (wins[j] == NULL)
888                                 continue;
889                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
890                                 unsigned int bw2 = wins[j]->new_bandwidth;
891                                 if (bw1 + bw2 > max_bw)
892                                         /* Window pair overlaps */
893                                         max_bw = bw1 + bw2;
894                                 overlap_count++;
895                         }
896                 }
897         }
898
899         if (overlap_count == 3)
900                 /* All three windows overlap */
901                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
902                          wins[2]->new_bandwidth;
903
904         return max_bw;
905 }
906
907 /*
908  * Calculate peak EMC bandwidth for each enabled window =
909  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
910  * (windows_tiling ? 2 : 1)
911  *
912  *
913  * note:
914  * (*) We use 2 tap V filter, so need double BW if use V filter
915  * (*) Tiling mode on T30 and DDR3 requires double BW
916  */
917 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
918         struct tegra_dc_win *w)
919 {
920         unsigned long ret;
921         int tiled_windows_bw_multiplier;
922         unsigned long bpp;
923
924         if (!WIN_IS_ENABLED(w))
925                 return 0;
926
927         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
928             w->out_w == 0 || w->out_h == 0)
929                 return 0;
930
931         tiled_windows_bw_multiplier =
932                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
933
934         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
935          * but the size reported by tegra_dc_fmt_bpp for the planar version
936          * is of the luma plane's size only. */
937         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
938                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
939         /* perform calculations with most significant bits of pixel clock
940          * to prevent overflow of long. */
941         ret = (unsigned long)(dc->pixel_clk >> 16) *
942                 bpp / 8 *
943                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
944                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
945
946 /*
947  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
948  * will request 147MBps from EMC.
949  */
950         ret = ret * 2 + ret / 10;
951
952         /* if overflowed */
953         if (ret > (1UL << 31))
954                 return ULONG_MAX;
955
956         return ret << 16; /* restore the scaling we did above */
957 }
958
959 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
960 {
961         int i;
962
963         BUG_ON(n > DC_N_WINDOWS);
964
965         /* emc rate and latency allowance both need to know per window
966          * bandwidths */
967         for (i = 0; i < n; i++) {
968                 struct tegra_dc_win *w = windows[i];
969                 if (w)
970                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
971         }
972
973         return tegra_dc_find_max_bandwidth(windows, n);
974 }
975
976 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
977 {
978         unsigned i;
979
980         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
981                 dc->emc_clk_rate = dc->new_emc_clk_rate;
982                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
983         }
984
985         for (i = 0; i < DC_N_WINDOWS; i++) {
986                 struct tegra_dc_win *w = &dc->windows[i];
987                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
988                         tegra_dc_set_latency_allowance(dc, w);
989         }
990 }
991
992 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
993 {
994         unsigned long new_rate;
995         struct tegra_dc *dc;
996
997         if (!use_dynamic_emc)
998                 return 0;
999
1000         dc = windows[0]->dc;
1001
1002         /* calculate the new rate based on this POST */
1003         new_rate = tegra_dc_get_bandwidth(windows, n);
1004         new_rate = EMC_BW_TO_FREQ(new_rate);
1005
1006         if (tegra_dc_has_multiple_dc())
1007                 new_rate = ULONG_MAX;
1008
1009         dc->new_emc_clk_rate = new_rate;
1010
1011         return 0;
1012 }
1013
1014 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1015                                   bool v, unsigned Bpp)
1016 {
1017         /*
1018          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1019          *           (post_scaled_size_in_pixels - 1)), MAX)
1020          * Where the value of MAX is as follows:
1021          * For V_DDA_INCREMENT: 15.0 (0xF000)
1022          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1023          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1024          */
1025
1026         fixed20_12 out = dfixed_init(out_int);
1027         u32 dda_inc;
1028         int max;
1029
1030         if (v) {
1031                 max = 15;
1032         } else {
1033                 switch (Bpp) {
1034                 default:
1035                         WARN_ON_ONCE(1);
1036                         /* fallthrough */
1037                 case 4:
1038                         max = 4;
1039                         break;
1040                 case 2:
1041                         max = 8;
1042                         break;
1043                 }
1044         }
1045
1046         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1047         in.full -= dfixed_const(1);
1048
1049         dda_inc = dfixed_div(in, out);
1050
1051         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1052
1053         return dda_inc;
1054 }
1055
1056 static inline u32 compute_initial_dda(fixed20_12 in)
1057 {
1058         return dfixed_frac(in);
1059 }
1060
1061 /* does not support updating windows on multiple dcs in one call */
1062 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1063 {
1064         struct tegra_dc *dc;
1065         unsigned long update_mask = GENERAL_ACT_REQ;
1066         unsigned long val;
1067         bool update_blend = false;
1068         int i;
1069
1070         dc = windows[0]->dc;
1071
1072         mutex_lock(&dc->lock);
1073
1074         if (!dc->enabled) {
1075                 mutex_unlock(&dc->lock);
1076                 return -EFAULT;
1077         }
1078
1079         if (no_vsync)
1080                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1081         else
1082                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1083
1084         for (i = 0; i < n; i++) {
1085                 struct tegra_dc_win *win = windows[i];
1086                 unsigned h_dda;
1087                 unsigned v_dda;
1088                 fixed20_12 h_offset, v_offset;
1089                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1090                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1091                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1092                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1093                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1094                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1095                 const bool filter_h = win_use_h_filter(win);
1096                 const bool filter_v = win_use_v_filter(win);
1097
1098                 if (win->z != dc->blend.z[win->idx]) {
1099                         dc->blend.z[win->idx] = win->z;
1100                         update_blend = true;
1101                 }
1102                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1103                         dc->blend.flags[win->idx]) {
1104                         dc->blend.flags[win->idx] =
1105                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1106                         update_blend = true;
1107                 }
1108
1109                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1110                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1111
1112                 if (!no_vsync)
1113                         update_mask |= WIN_A_ACT_REQ << win->idx;
1114
1115                 if (!WIN_IS_ENABLED(win)) {
1116                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1117                         continue;
1118                 }
1119
1120                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1121                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1122
1123                 tegra_dc_writel(dc,
1124                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1125                                 DC_WIN_POSITION);
1126                 tegra_dc_writel(dc,
1127                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1128                                 DC_WIN_SIZE);
1129                 tegra_dc_writel(dc,
1130                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1131                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1132                                 DC_WIN_PRESCALED_SIZE);
1133
1134                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1135                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1136                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1137                                 DC_WIN_DDA_INCREMENT);
1138                 h_dda = compute_initial_dda(win->x);
1139                 v_dda = compute_initial_dda(win->y);
1140                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1141                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1142
1143                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1144                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1145                 tegra_dc_writel(dc,
1146                                 (unsigned long)win->phys_addr,
1147                                 DC_WINBUF_START_ADDR);
1148
1149                 if (!yuvp) {
1150                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1151                 } else {
1152                         tegra_dc_writel(dc,
1153                                         (unsigned long)win->phys_addr_u,
1154                                         DC_WINBUF_START_ADDR_U);
1155                         tegra_dc_writel(dc,
1156                                         (unsigned long)win->phys_addr_v,
1157                                         DC_WINBUF_START_ADDR_V);
1158                         tegra_dc_writel(dc,
1159                                         LINE_STRIDE(win->stride) |
1160                                         UV_LINE_STRIDE(win->stride_uv),
1161                                         DC_WIN_LINE_STRIDE);
1162                 }
1163
1164                 h_offset = win->x;
1165                 if (invert_h) {
1166                         h_offset.full += win->w.full - dfixed_const(1);
1167                 }
1168
1169                 v_offset = win->y;
1170                 if (invert_v) {
1171                         v_offset.full += win->h.full - dfixed_const(1);
1172                 }
1173
1174                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1175                                 DC_WINBUF_ADDR_H_OFFSET);
1176                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1177                                 DC_WINBUF_ADDR_V_OFFSET);
1178
1179                 if (WIN_IS_TILED(win))
1180                         tegra_dc_writel(dc,
1181                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1182                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1183                                         DC_WIN_BUFFER_ADDR_MODE);
1184                 else
1185                         tegra_dc_writel(dc,
1186                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1187                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1188                                         DC_WIN_BUFFER_ADDR_MODE);
1189
1190                 val = WIN_ENABLE;
1191                 if (yuvp)
1192                         val |= CSC_ENABLE;
1193                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1194                         val |= COLOR_EXPAND;
1195
1196                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1197                         val |= CP_ENABLE;
1198
1199                 if (filter_h)
1200                         val |= H_FILTER_ENABLE;
1201                 if (filter_v)
1202                         val |= V_FILTER_ENABLE;
1203
1204                 if (invert_h)
1205                         val |= H_DIRECTION_DECREMENT;
1206                 if (invert_v)
1207                         val |= V_DIRECTION_DECREMENT;
1208
1209                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1210
1211                 win->dirty = no_vsync ? 0 : 1;
1212
1213                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1214                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1215                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1216                         __func__, win->idx, win->z,
1217                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1218                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1219                         win->out_x, win->out_y, win->out_w, win->out_h,
1220                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1221         }
1222
1223         if (update_blend) {
1224                 tegra_dc_set_blending(dc, &dc->blend);
1225                 for (i = 0; i < DC_N_WINDOWS; i++) {
1226                         if (!no_vsync)
1227                                 dc->windows[i].dirty = 1;
1228                         update_mask |= WIN_A_ACT_REQ << i;
1229                 }
1230         }
1231
1232         tegra_dc_set_dynamic_emc(windows, n);
1233
1234         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1235
1236         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1237         if (!no_vsync) {
1238                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1239                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1240                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1241         } else {
1242                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1243                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1244                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1245         }
1246
1247         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1248
1249         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1250                 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1251
1252         mutex_unlock(&dc->lock);
1253
1254         return 0;
1255 }
1256 EXPORT_SYMBOL(tegra_dc_update_windows);
1257
1258 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1259 {
1260         return dc->syncpt[i].id;
1261 }
1262 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1263
1264 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1265 {
1266         u32 max;
1267
1268         mutex_lock(&dc->lock);
1269         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1270                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1271         dc->syncpt[i].max = max;
1272         mutex_unlock(&dc->lock);
1273
1274         return max;
1275 }
1276
1277 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1278 {
1279         mutex_lock(&dc->lock);
1280         if ( dc->enabled )
1281                 while (dc->syncpt[i].min < val) {
1282                         dc->syncpt[i].min++;
1283                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1284                                         dc->syncpt[i].id);
1285                 }
1286         mutex_unlock(&dc->lock);
1287 }
1288
1289 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1290                                              int n)
1291 {
1292         int i;
1293
1294         for (i = 0; i < n; i++) {
1295                 if (windows[i]->dirty)
1296                         return false;
1297         }
1298
1299         return true;
1300 }
1301
1302 /* does not support syncing windows on multiple dcs in one call */
1303 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1304 {
1305         if (n < 1 || n > DC_N_WINDOWS)
1306                 return -EINVAL;
1307
1308         if (!windows[0]->dc->enabled)
1309                 return -EFAULT;
1310
1311 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1312         /* Don't want to timeout on simulator */
1313         return wait_event_interruptible(windows[0]->dc->wq,
1314                 tegra_dc_windows_are_clean(windows, n));
1315 #else
1316         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1317                                          tegra_dc_windows_are_clean(windows, n),
1318                                          HZ);
1319 #endif
1320 }
1321 EXPORT_SYMBOL(tegra_dc_sync_windows);
1322
1323 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1324 {
1325 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1326         return clk_get_rate(dc->clk);
1327 #else
1328         return 27000000;
1329 #endif
1330 }
1331
1332 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1333 {
1334         unsigned long rate;
1335         unsigned long div;
1336
1337         rate = tegra_dc_clk_get_rate(dc);
1338
1339         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1340
1341         if (div < 2)
1342                 return 0;
1343
1344         return rate * 2 / div;
1345 }
1346
1347 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1348 {
1349         int pclk;
1350
1351         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1352                 unsigned long rate;
1353                 struct clk *parent_clk =
1354                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1355
1356                 if (clk_get_parent(clk) != parent_clk)
1357                         clk_set_parent(clk, parent_clk);
1358
1359                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1360                         struct clk *base_clk = clk_get_parent(parent_clk);
1361
1362                         /* Assuming either pll_d or pll_d2 is used */
1363                         rate = dc->mode.pclk * 2;
1364
1365                         if (rate != clk_get_rate(base_clk))
1366                                 clk_set_rate(base_clk, rate);
1367                 }
1368         }
1369
1370         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1371                 unsigned long rate;
1372                 struct clk *parent_clk =
1373                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1374                 struct clk *base_clk = clk_get_parent(parent_clk);
1375
1376                 /* needs to match tegra_dc_hdmi_supported_modes[]
1377                 and tegra_pll_d_freq_table[] */
1378                 if (dc->mode.pclk > 70000000)
1379                         rate = 594000000;
1380                 else if (dc->mode.pclk > 25200000)
1381                         rate = 216000000;
1382                 else
1383                         rate = 504000000;
1384
1385                 if (rate != clk_get_rate(base_clk))
1386                         clk_set_rate(base_clk, rate);
1387
1388                 if (clk_get_parent(clk) != parent_clk)
1389                         clk_set_parent(clk, parent_clk);
1390         }
1391
1392         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1393                 unsigned long rate;
1394                 struct clk *parent_clk;
1395                 struct clk *base_clk;
1396
1397                 if (clk == dc->clk) {
1398                         parent_clk = clk_get_sys(NULL,
1399                                         dc->out->parent_clk ? : "pll_d_out0");
1400                         base_clk = clk_get_parent(parent_clk);
1401                         tegra_clk_cfg_ex(base_clk,
1402                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1403                 } else {
1404                         if (dc->pdata->default_out->dsi->dsi_instance) {
1405                                 parent_clk = clk_get_sys(NULL,
1406                                         dc->out->parent_clk ? : "pll_d2_out0");
1407                                 base_clk = clk_get_parent(parent_clk);
1408                                 tegra_clk_cfg_ex(base_clk,
1409                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1410                         } else {
1411                                 parent_clk = clk_get_sys(NULL,
1412                                         dc->out->parent_clk ? : "pll_d_out0");
1413                                 base_clk = clk_get_parent(parent_clk);
1414                                 tegra_clk_cfg_ex(base_clk,
1415                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1416                         }
1417                 }
1418
1419                 rate = dc->mode.pclk * 2;
1420                 if (rate != clk_get_rate(base_clk))
1421                         clk_set_rate(base_clk, rate);
1422
1423                 if (clk_get_parent(clk) != parent_clk)
1424                         clk_set_parent(clk, parent_clk);
1425         }
1426
1427         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1428         tegra_dvfs_set_rate(clk, pclk);
1429 }
1430
1431 /* return non-zero if constraint is violated */
1432 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1433 {
1434         long a, b;
1435
1436         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1437         a = 0;
1438
1439         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1440         b = mode->h_front_porch - 1;
1441
1442         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1443         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1444                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1445         /* check Constraint 1 and 6 */
1446         if (a > b)
1447                 return 1;
1448
1449         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1450         if (mode->h_sync_width < 1)
1451                 return 4;
1452
1453         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1454         if (mode->h_active < 16)
1455                 return 7;
1456
1457         if (href) {
1458                 if (b > a && a % 2)
1459                         *href = a + 1; /* use smallest even value */
1460                 else
1461                         *href = a; /* even or only possible value */
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1468 {
1469         long a;
1470         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1471
1472         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1473         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1474                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1475
1476         /* Constraint 6 */
1477         if (mode->v_front_porch < a + 1)
1478                 a = mode->v_front_porch - 1;
1479
1480         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1481         if (mode->v_sync_width < 1)
1482                 return 4;
1483
1484         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1485         if (mode->v_active < 16)
1486                 return 7;
1487
1488         if (vref)
1489                 *vref = a;
1490         return 0;
1491 }
1492
1493 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1494 {
1495         int ret;
1496         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1497         if (ret)
1498                 return ret;
1499         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1500         if (ret)
1501                 return ret;
1502
1503         return 0;
1504 }
1505
1506 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1507 {
1508         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1509         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1510                 return false;
1511
1512         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1513         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1514                 return false;
1515
1516         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1517          * (vertical blank). */
1518         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1519                 return false;
1520
1521         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1522         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1523                 return false;
1524
1525         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1526         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1527                 return false;
1528
1529         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1530          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1531         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1532                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1533                 return false;
1534
1535         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1536         if (mode->h_active < 16 || mode->v_active < 16)
1537                 return false;
1538
1539         return true;
1540 }
1541
1542 #ifdef DEBUG
1543 /* return in 1000ths of a Hertz */
1544 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1545 {
1546         long h_total, v_total, refresh;
1547         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1548                 m->h_sync_width;
1549         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1550                 m->v_sync_width;
1551         refresh = dc->pixel_clk / h_total;
1552         refresh *= 1000;
1553         refresh /= v_total;
1554         return refresh;
1555 }
1556
1557 static void print_mode(struct tegra_dc *dc,
1558                         const struct tegra_dc_mode *mode, const char *note)
1559 {
1560         if (mode) {
1561                 int refresh = calc_refresh(dc, mode);
1562                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1563                         note ? note : "",
1564                         mode->h_active, mode->v_active,
1565                         refresh / 1000, refresh % 1000,
1566                         mode->pclk);
1567         }
1568 }
1569 #else /* !DEBUG */
1570 static inline void print_mode(struct tegra_dc *dc,
1571                         const struct tegra_dc_mode *mode, const char *note) { }
1572 #endif /* DEBUG */
1573
1574 static inline void enable_dc_irq(unsigned int irq)
1575 {
1576 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1577         enable_irq(irq);
1578 #else
1579         /* Always disable DC interrupts on FPGA. */
1580         disable_irq(irq);
1581 #endif
1582 }
1583
1584 static inline void disable_dc_irq(unsigned int irq)
1585 {
1586         disable_irq(irq);
1587 }
1588
1589 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1590 {
1591         unsigned long val;
1592         unsigned long rate;
1593         unsigned long div;
1594         unsigned long pclk;
1595
1596         print_mode(dc, mode, __func__);
1597
1598         /* use default EMC rate when switching modes */
1599         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1600         tegra_dc_program_bandwidth(dc);
1601
1602         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1603         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1604                         DC_DISP_REF_TO_SYNC);
1605         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1606                         DC_DISP_SYNC_WIDTH);
1607         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1608                         DC_DISP_BACK_PORCH);
1609         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1610                         DC_DISP_DISP_ACTIVE);
1611         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1612                         DC_DISP_FRONT_PORCH);
1613
1614         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1615                         DC_DISP_DATA_ENABLE_OPTIONS);
1616
1617         /* TODO: MIPI/CRT/HDMI clock cals */
1618
1619         val = DISP_DATA_FORMAT_DF1P1C;
1620
1621         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1622                 val |= DISP_DATA_ALIGNMENT_MSB;
1623         else
1624                 val |= DISP_DATA_ALIGNMENT_LSB;
1625
1626         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1627                 val |= DISP_DATA_ORDER_RED_BLUE;
1628         else
1629                 val |= DISP_DATA_ORDER_BLUE_RED;
1630
1631         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1632
1633         rate = tegra_dc_clk_get_rate(dc);
1634
1635         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1636         if (pclk < (mode->pclk / 100 * 99) ||
1637             pclk > (mode->pclk / 100 * 109)) {
1638                 dev_err(&dc->ndev->dev,
1639                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1640                         rate, mode->pclk,
1641                         pclk, (mode->pclk / 100 * 99),
1642                         (mode->pclk / 100 * 109));
1643                 return -EINVAL;
1644         }
1645
1646         div = (rate * 2 / pclk) - 2;
1647
1648         tegra_dc_writel(dc, 0x00010001,
1649                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1650         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1651                         DC_DISP_DISP_CLOCK_CONTROL);
1652
1653 #ifdef CONFIG_SWITCH
1654         switch_set_state(&dc->modeset_switch,
1655                          (mode->h_active << 16) | mode->v_active);
1656 #endif
1657
1658         dc->pixel_clk = dc->mode.pclk;
1659
1660         return 0;
1661 }
1662
1663
1664 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1665 {
1666         memcpy(&dc->mode, mode, sizeof(dc->mode));
1667
1668         print_mode(dc, mode, __func__);
1669
1670         return 0;
1671 }
1672 EXPORT_SYMBOL(tegra_dc_set_mode);
1673
1674 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1675                 const struct fb_videomode *fbmode, bool stereo_mode)
1676 {
1677         struct tegra_dc_mode mode;
1678
1679         if (!fbmode->pixclock)
1680                 return -EINVAL;
1681
1682         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1683         mode.h_sync_width = fbmode->hsync_len;
1684         mode.v_sync_width = fbmode->vsync_len;
1685         mode.h_back_porch = fbmode->left_margin;
1686         mode.v_back_porch = fbmode->upper_margin;
1687         mode.h_active = fbmode->xres;
1688         mode.v_active = fbmode->yres;
1689         mode.h_front_porch = fbmode->right_margin;
1690         mode.v_front_porch = fbmode->lower_margin;
1691         mode.stereo_mode = stereo_mode;
1692         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1693                 /* HDMI controller requires h_ref=1, v_ref=1 */
1694                 mode.h_ref_to_sync = 1;
1695                 mode.v_ref_to_sync = 1;
1696         } else {
1697                 calc_ref_to_sync(&mode);
1698         }
1699         if (!check_ref_to_sync(&mode)) {
1700                 dev_err(&dc->ndev->dev,
1701                                 "Display timing doesn't meet restrictions.\n");
1702                 return -EINVAL;
1703         }
1704         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1705                 mode.h_active, mode.v_active, mode.pclk,
1706                 mode.h_ref_to_sync, mode.v_ref_to_sync
1707         );
1708
1709         if (mode.stereo_mode) {
1710                 mode.pclk *= 2;
1711                 /* total v_active = yres*2 + activespace */
1712                 mode.v_active = fbmode->yres*2 +
1713                                 fbmode->vsync_len +
1714                                 fbmode->upper_margin +
1715                                 fbmode->lower_margin;
1716         }
1717
1718         mode.flags = 0;
1719
1720         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1721                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1722
1723         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1724                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1725
1726         return tegra_dc_set_mode(dc, &mode);
1727 }
1728 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1729
1730 void
1731 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1732 {
1733         unsigned int ctrl;
1734         unsigned long out_sel;
1735         unsigned long cmd_state;
1736
1737         mutex_lock(&dc->lock);
1738         if (!dc->enabled) {
1739                 mutex_unlock(&dc->lock);
1740                 return;
1741         }
1742
1743         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1744                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1745                 cfg->clk_select);
1746
1747         /* The new value should be effected immediately */
1748         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1749         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1750
1751         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1752                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1753         else
1754                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1755
1756         switch (cfg->which_pwm) {
1757         case TEGRA_PWM_PM0:
1758                 /* Select the LM0 on PM0 */
1759                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1760                 out_sel &= ~(7 << 0);
1761                 out_sel |= (3 << 0);
1762                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1763                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1764                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1765                 break;
1766         case TEGRA_PWM_PM1:
1767                 /* Select the LM1 on PM1 */
1768                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1769                 out_sel &= ~(7 << 4);
1770                 out_sel |= (3 << 4);
1771                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1772                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1773                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1774                 break;
1775         default:
1776                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1777                 break;
1778         }
1779         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1780         mutex_unlock(&dc->lock);
1781 }
1782 EXPORT_SYMBOL(tegra_dc_config_pwm);
1783
1784 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1785                                 const struct tegra_dc_out_pin *pins,
1786                                 const unsigned int n_pins)
1787 {
1788         unsigned int i;
1789
1790         int name;
1791         int pol;
1792
1793         u32 pol1, pol3;
1794
1795         u32 set1, unset1;
1796         u32 set3, unset3;
1797
1798         set1 = set3 = unset1 = unset3 = 0;
1799
1800         for (i = 0; i < n_pins; i++) {
1801                 name = (pins + i)->name;
1802                 pol  = (pins + i)->pol;
1803
1804                 /* set polarity by name */
1805                 switch (name) {
1806                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1807                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1808                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1809                         else
1810                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1811                         break;
1812                 case TEGRA_DC_OUT_PIN_H_SYNC:
1813                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1814                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1815                         else
1816                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1817                         break;
1818                 case TEGRA_DC_OUT_PIN_V_SYNC:
1819                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1820                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1821                         else
1822                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1823                         break;
1824                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1825                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1826                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1827                         else
1828                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1829                         break;
1830                 default:
1831                         printk("Invalid argument in function %s\n",
1832                                __FUNCTION__);
1833                         break;
1834                 }
1835         }
1836
1837         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1838         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1839
1840         pol1 |= set1;
1841         pol1 &= ~unset1;
1842
1843         pol3 |= set3;
1844         pol3 &= ~unset3;
1845
1846         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1847         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1848 }
1849
1850 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1851 {
1852         dc->out = out;
1853
1854         if (out->n_modes > 0)
1855                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1856
1857         switch (out->type) {
1858         case TEGRA_DC_OUT_RGB:
1859                 dc->out_ops = &tegra_dc_rgb_ops;
1860                 break;
1861
1862         case TEGRA_DC_OUT_HDMI:
1863                 dc->out_ops = &tegra_dc_hdmi_ops;
1864                 break;
1865
1866         case TEGRA_DC_OUT_DSI:
1867                 dc->out_ops = &tegra_dc_dsi_ops;
1868                 break;
1869
1870         default:
1871                 dc->out_ops = NULL;
1872                 break;
1873         }
1874
1875         if (dc->out_ops && dc->out_ops->init)
1876                 dc->out_ops->init(dc);
1877
1878 }
1879
1880 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1881 {
1882         if (dc->out)
1883                 return dc->out->height;
1884         else
1885                 return 0;
1886 }
1887 EXPORT_SYMBOL(tegra_dc_get_out_height);
1888
1889 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1890 {
1891         if (dc->out)
1892                 return dc->out->width;
1893         else
1894                 return 0;
1895 }
1896 EXPORT_SYMBOL(tegra_dc_get_out_width);
1897
1898 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1899 {
1900         if (dc->out && dc->out->max_pixclock)
1901                 return dc->out->max_pixclock;
1902         else
1903                 return 0;
1904 }
1905 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1906
1907 void tegra_dc_enable_crc(struct tegra_dc *dc)
1908 {
1909         u32 val;
1910         tegra_dc_io_start(dc);
1911
1912         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1913                 CRC_ENABLE_ENABLE;
1914         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1915         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1916         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1917 }
1918
1919 void tegra_dc_disable_crc(struct tegra_dc *dc)
1920 {
1921         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1922         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1923         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1924
1925         tegra_dc_io_end(dc);
1926 }
1927
1928 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1929 {
1930         int crc = 0;
1931
1932         if(!dc) {
1933                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1934                 goto crc_error;
1935         }
1936
1937         /* TODO: Replace mdelay with code to sync VBlANK, since
1938          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1939         mdelay(TEGRA_CRC_LATCHED_DELAY);
1940
1941         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1942 crc_error:
1943         return crc;
1944 }
1945
1946 static void tegra_dc_vblank(struct work_struct *work)
1947 {
1948         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1949         bool nvsd_updated = false;
1950
1951         mutex_lock(&dc->lock);
1952
1953         /* update EMC clock if calculated bandwidth has changed */
1954         tegra_dc_program_bandwidth(dc);
1955
1956         /* Update the SD brightness */
1957         if (dc->enabled && dc->out->sd_settings)
1958                 nvsd_updated = nvsd_update_brightness(dc);
1959
1960         mutex_unlock(&dc->lock);
1961
1962         /* Do the actual brightness update outside of the mutex */
1963         if (nvsd_updated && dc->out->sd_settings &&
1964             dc->out->sd_settings->bl_device) {
1965
1966                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1967                 struct backlight_device *bl = platform_get_drvdata(pdev);
1968                 if (bl)
1969                         backlight_update_status(bl);
1970         }
1971 }
1972
1973 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1974 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1975 {
1976         u32 val, i;
1977
1978         /* Check for any underflow reset conditions */
1979         for (i = 0; i < DC_N_WINDOWS; i++) {
1980                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1981                         dc->windows[i].underflows++;
1982
1983 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1984                         if (dc->windows[i].underflows > 4)
1985                                 schedule_work(&dc->reset_work);
1986 #endif
1987                 } else {
1988                         dc->windows[i].underflows = 0;
1989                 }
1990         }
1991
1992         if (!dc->underflow_mask) {
1993                 /* If we have no underflow to check, go ahead
1994                    and disable the interrupt */
1995                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1996                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1997                         val &= ~FRAME_END_INT;
1998                 else
1999                         val &= ~V_BLANK_INT;
2000                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2001         }
2002
2003         /* Clear the underflow mask now that we've checked it. */
2004         dc->underflow_mask = 0;
2005 }
2006
2007 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2008 {
2009         u32 val, i;
2010         u32 completed = 0;
2011         u32 dirty = 0;
2012
2013         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2014         for (i = 0; i < DC_N_WINDOWS; i++) {
2015 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2016                 /* FIXME: this is not needed when the simulator
2017                    clears WIN_x_UPDATE bits as in HW */
2018                 dc->windows[i].dirty = 0;
2019                 completed = 1;
2020 #else
2021                 if (!(val & (WIN_A_UPDATE << i))) {
2022                         dc->windows[i].dirty = 0;
2023                         completed = 1;
2024                 } else {
2025                         dirty = 1;
2026                 }
2027 #endif
2028         }
2029
2030         if (!dirty) {
2031                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2032                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2033                         val &= ~V_BLANK_INT;
2034                 else
2035                         val &= ~FRAME_END_INT;
2036                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2037         }
2038
2039         if (completed) {
2040                 if (!dirty) {
2041                         /* With the last completed window, go ahead
2042                            and enable the vblank interrupt for nvsd. */
2043                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2044                         val |= V_BLANK_INT;
2045                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2046                 }
2047
2048                 wake_up(&dc->wq);
2049         }
2050 }
2051
2052 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2053 {
2054         if (status & V_BLANK_INT) {
2055                 /* Sync up windows. */
2056                 tegra_dc_trigger_windows(dc);
2057
2058                 /* Schedule any additional bottom-half vblank actvities. */
2059                 schedule_work(&dc->vblank_work);
2060         }
2061
2062         /* Check underflow at frame end */
2063         if (status & FRAME_END_INT) {
2064                 tegra_dc_underflow_handler(dc);
2065
2066                 /* Mark the frame_end as complete. */
2067                 if (!completion_done(&dc->frame_end_complete))
2068                         complete(&dc->frame_end_complete);
2069         }
2070 }
2071
2072 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2073 {
2074         if (status & V_BLANK_INT) {
2075                 /* Check underflow */
2076                 tegra_dc_underflow_handler(dc);
2077
2078                 /* Schedule any additional bottom-half vblank actvities. */
2079                 schedule_work(&dc->vblank_work);
2080         }
2081
2082         if (status & FRAME_END_INT) {
2083                 /* Mark the frame_end as complete. */
2084                 if (!completion_done(&dc->frame_end_complete))
2085                         complete(&dc->frame_end_complete);
2086
2087                 tegra_dc_trigger_windows(dc);
2088         }
2089 }
2090 #endif
2091
2092 /* return an arbitrarily large number if count overflow occurs.
2093  * make it a nice base-10 number to show up in stats output */
2094 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2095 {
2096         unsigned count = tegra_dc_readl(dc, reg);
2097         tegra_dc_writel(dc, 0, reg);
2098         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2099 }
2100
2101 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2102 {
2103 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2104         struct tegra_dc *dc = ptr;
2105         unsigned long status;
2106         unsigned long val;
2107         unsigned long underflow_mask;
2108
2109         if (!nvhost_module_powered(&dc->ndev->host->mod)) {
2110                 WARN(1, "IRQ when DC not powered!\n");
2111                 tegra_dc_io_start(dc);
2112                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2113                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2114                 tegra_dc_io_end(dc);
2115                 return IRQ_HANDLED;
2116         }
2117
2118         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2119         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2120
2121         /*
2122          * Overlays can get thier internal state corrupted during and underflow
2123          * condition.  The only way to fix this state is to reset the DC.
2124          * if we get 4 consecutive frames with underflows, assume we're
2125          * hosed and reset.
2126          */
2127         underflow_mask = status & ALL_UF_INT;
2128
2129         if (underflow_mask) {
2130                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2131                 val |= V_BLANK_INT;
2132                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2133                 dc->underflow_mask |= underflow_mask;
2134                 dc->stats.underflows++;
2135                 if (status & WIN_A_UF_INT)
2136                         dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2137                                 DC_WINBUF_AD_UFLOW_STATUS);
2138                 if (status & WIN_B_UF_INT)
2139                         dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2140                                 DC_WINBUF_BD_UFLOW_STATUS);
2141                 if (status & WIN_C_UF_INT)
2142                         dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2143                                 DC_WINBUF_CD_UFLOW_STATUS);
2144         }
2145
2146         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2147                 tegra_dc_one_shot_irq(dc, status);
2148         else
2149                 tegra_dc_continuous_irq(dc, status);
2150
2151         return IRQ_HANDLED;
2152 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2153         return IRQ_NONE;
2154 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2155 }
2156
2157 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2158 {
2159         u32 color_control;
2160
2161         switch (dc->out->depth) {
2162         case 3:
2163                 color_control = BASE_COLOR_SIZE111;
2164                 break;
2165
2166         case 6:
2167                 color_control = BASE_COLOR_SIZE222;
2168                 break;
2169
2170         case 8:
2171                 color_control = BASE_COLOR_SIZE332;
2172                 break;
2173
2174         case 9:
2175                 color_control = BASE_COLOR_SIZE333;
2176                 break;
2177
2178         case 12:
2179                 color_control = BASE_COLOR_SIZE444;
2180                 break;
2181
2182         case 15:
2183                 color_control = BASE_COLOR_SIZE555;
2184                 break;
2185
2186         case 16:
2187                 color_control = BASE_COLOR_SIZE565;
2188                 break;
2189
2190         case 18:
2191                 color_control = BASE_COLOR_SIZE666;
2192                 break;
2193
2194         default:
2195                 color_control = BASE_COLOR_SIZE888;
2196                 break;
2197         }
2198
2199         switch (dc->out->dither) {
2200         case TEGRA_DC_DISABLE_DITHER:
2201                 color_control |= DITHER_CONTROL_DISABLE;
2202                 break;
2203         case TEGRA_DC_ORDERED_DITHER:
2204                 color_control |= DITHER_CONTROL_ORDERED;
2205                 break;
2206         case TEGRA_DC_ERRDIFF_DITHER:
2207                 /* The line buffer for error-diffusion dither is limited
2208                  * to 1280 pixels per line. This limits the maximum
2209                  * horizontal active area size to 1280 pixels when error
2210                  * diffusion is enabled.
2211                  */
2212                 BUG_ON(dc->mode.h_active > 1280);
2213                 color_control |= DITHER_CONTROL_ERRDIFF;
2214                 break;
2215         }
2216
2217         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2218 }
2219
2220 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2221 {
2222         u32 syncpt_id;
2223
2224         switch (dc->ndev->id) {
2225         case 0:
2226                 switch (idx) {
2227                 case 0:
2228                         syncpt_id = NVSYNCPT_DISP0_A;
2229                         break;
2230                 case 1:
2231                         syncpt_id = NVSYNCPT_DISP0_B;
2232                         break;
2233                 case 2:
2234                         syncpt_id = NVSYNCPT_DISP0_C;
2235                         break;
2236                 default:
2237                         BUG();
2238                         break;
2239                 }
2240                 break;
2241         case 1:
2242                 switch (idx) {
2243                 case 0:
2244                         syncpt_id = NVSYNCPT_DISP1_A;
2245                         break;
2246                 case 1:
2247                         syncpt_id = NVSYNCPT_DISP1_B;
2248                         break;
2249                 case 2:
2250                         syncpt_id = NVSYNCPT_DISP1_C;
2251                         break;
2252                 default:
2253                         BUG();
2254                         break;
2255                 }
2256                 break;
2257         default:
2258                 BUG();
2259                 break;
2260         }
2261
2262         return syncpt_id;
2263 }
2264
2265 static void tegra_dc_init(struct tegra_dc *dc)
2266 {
2267         int i;
2268
2269         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2270         if (dc->ndev->id == 0) {
2271                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2272                                       TEGRA_MC_PRIO_MED);
2273                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2274                                       TEGRA_MC_PRIO_MED);
2275                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2276                                       TEGRA_MC_PRIO_MED);
2277                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2278                                       TEGRA_MC_PRIO_MED);
2279                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2280                                       TEGRA_MC_PRIO_HIGH);
2281         } else if (dc->ndev->id == 1) {
2282                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2283                                       TEGRA_MC_PRIO_MED);
2284                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2285                                       TEGRA_MC_PRIO_MED);
2286                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2287                                       TEGRA_MC_PRIO_MED);
2288                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2289                                       TEGRA_MC_PRIO_MED);
2290                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2291                                       TEGRA_MC_PRIO_HIGH);
2292         }
2293         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2294                         DC_CMD_CONT_SYNCPT_VSYNC);
2295         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2296         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2297         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2298         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2299
2300         /* enable interrupts for vblank, frame_end and underflows */
2301         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2302                 DC_CMD_INT_ENABLE);
2303         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2304
2305         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2306
2307         tegra_dc_set_color_control(dc);
2308         for (i = 0; i < DC_N_WINDOWS; i++) {
2309                 struct tegra_dc_win *win = &dc->windows[i];
2310                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2311                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2312                 tegra_dc_set_csc(dc, &win->csc);
2313                 tegra_dc_set_lut(dc, win);
2314                 tegra_dc_set_scaling_filter(dc);
2315         }
2316
2317
2318         for (i = 0; i < dc->n_windows; i++) {
2319                 u32 syncpt = get_syncpt(dc, i);
2320
2321                 dc->syncpt[i].id = syncpt;
2322
2323                 dc->syncpt[i].min = dc->syncpt[i].max =
2324                         nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2325         }
2326
2327         print_mode(dc, &dc->mode, __func__);
2328
2329         if (dc->mode.pclk)
2330                 tegra_dc_program_mode(dc, &dc->mode);
2331
2332         /* Initialize SD AFTER the modeset.
2333            nvsd_init handles the sd_settings = NULL case. */
2334         nvsd_init(dc, dc->out->sd_settings);
2335 }
2336
2337 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2338 {
2339         if (dc->out->enable)
2340                 dc->out->enable();
2341
2342         tegra_dc_setup_clk(dc, dc->clk);
2343         clk_enable(dc->clk);
2344         clk_enable(dc->emc_clk);
2345
2346         /* do not accept interrupts during initialization */
2347         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2348         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2349
2350         enable_dc_irq(dc->irq);
2351
2352         tegra_dc_init(dc);
2353
2354         if (dc->out_ops && dc->out_ops->enable)
2355                 dc->out_ops->enable(dc);
2356
2357         if (dc->out->postpoweron)
2358                 dc->out->postpoweron();
2359
2360         /* force a full blending update */
2361         dc->blend.z[0] = -1;
2362
2363         tegra_dc_ext_enable(dc->ext);
2364
2365         return true;
2366 }
2367
2368 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2369 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2370 {
2371         if (dc->out->enable)
2372                 dc->out->enable();
2373
2374         tegra_dc_setup_clk(dc, dc->clk);
2375         clk_enable(dc->clk);
2376         clk_enable(dc->emc_clk);
2377
2378         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2379                 mutex_lock(&tegra_dcs[1]->lock);
2380                 disable_irq(tegra_dcs[1]->irq);
2381         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2382                 mutex_lock(&tegra_dcs[0]->lock);
2383                 disable_irq(tegra_dcs[0]->irq);
2384         }
2385
2386         msleep(5);
2387         tegra_periph_reset_assert(dc->clk);
2388         msleep(2);
2389 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2390         tegra_periph_reset_deassert(dc->clk);
2391         msleep(1);
2392 #endif
2393
2394         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2395                 enable_dc_irq(tegra_dcs[1]->irq);
2396                 mutex_unlock(&tegra_dcs[1]->lock);
2397         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2398                 enable_dc_irq(tegra_dcs[0]->irq);
2399                 mutex_unlock(&tegra_dcs[0]->lock);
2400         }
2401
2402         enable_dc_irq(dc->irq);
2403
2404         tegra_dc_init(dc);
2405
2406         if (dc->out_ops && dc->out_ops->enable)
2407                 dc->out_ops->enable(dc);
2408
2409         if (dc->out->postpoweron)
2410                 dc->out->postpoweron();
2411
2412         /* force a full blending update */
2413         dc->blend.z[0] = -1;
2414
2415         return true;
2416 }
2417 #endif
2418
2419 static bool _tegra_dc_enable(struct tegra_dc *dc)
2420 {
2421         if (dc->mode.pclk == 0)
2422                 return false;
2423
2424         if (!dc->out)
2425                 return false;
2426
2427         tegra_dc_io_start(dc);
2428
2429         return _tegra_dc_controller_enable(dc);
2430 }
2431
2432 void tegra_dc_enable(struct tegra_dc *dc)
2433 {
2434         mutex_lock(&dc->lock);
2435
2436         if (!dc->enabled)
2437                 dc->enabled = _tegra_dc_enable(dc);
2438
2439         mutex_unlock(&dc->lock);
2440 }
2441
2442 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2443 {
2444         unsigned i;
2445
2446         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2447         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2448         disable_irq(dc->irq);
2449
2450         if (dc->out_ops && dc->out_ops->disable)
2451                 dc->out_ops->disable(dc);
2452
2453         clk_disable(dc->emc_clk);
2454         clk_disable(dc->clk);
2455         tegra_dvfs_set_rate(dc->clk, 0);
2456
2457         if (dc->out && dc->out->disable)
2458                 dc->out->disable();
2459
2460         for (i = 0; i < dc->n_windows; i++) {
2461                 struct tegra_dc_win *w = &dc->windows[i];
2462
2463                 /* reset window bandwidth */
2464                 w->bandwidth = 0;
2465                 w->new_bandwidth = 0;
2466
2467                 /* disable windows */
2468                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2469
2470                 /* flush any pending syncpt waits */
2471                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2472                         dc->syncpt[i].min++;
2473                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2474                                 dc->syncpt[i].id);
2475                 }
2476         }
2477 }
2478
2479 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2480 {
2481 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2482         u32 val;
2483         if (dc->enabled)  {
2484                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2485                 if (enable)
2486                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2487                 else
2488                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2489                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2490         }
2491 #endif
2492 }
2493
2494 bool tegra_dc_stats_get(struct tegra_dc *dc)
2495 {
2496 #if 0 /* right now it is always enabled */
2497         u32 val;
2498         bool res;
2499
2500         if (dc->enabled)  {
2501                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2502                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2503         } else {
2504                 res = false;
2505         }
2506
2507         return res;
2508 #endif
2509         return true;
2510 }
2511
2512 /* make the screen blank by disabling all windows */
2513 void tegra_dc_blank(struct tegra_dc *dc)
2514 {
2515         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2516         unsigned i;
2517
2518         for (i = 0; i < DC_N_WINDOWS; i++) {
2519                 dcwins[i] = tegra_dc_get_window(dc, i);
2520                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2521         }
2522
2523         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2524         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2525 }
2526
2527 static void _tegra_dc_disable(struct tegra_dc *dc)
2528 {
2529         _tegra_dc_controller_disable(dc);
2530         tegra_dc_io_end(dc);
2531 }
2532
2533 void tegra_dc_disable(struct tegra_dc *dc)
2534 {
2535         if (dc->overlay)
2536                 tegra_overlay_disable(dc->overlay);
2537
2538         tegra_dc_ext_disable(dc->ext);
2539
2540         mutex_lock(&dc->lock);
2541
2542         if (dc->enabled) {
2543                 dc->enabled = false;
2544
2545                 if (!dc->suspended)
2546                         _tegra_dc_disable(dc);
2547         }
2548
2549 #ifdef CONFIG_SWITCH
2550         switch_set_state(&dc->modeset_switch, 0);
2551 #endif
2552
2553         mutex_unlock(&dc->lock);
2554 }
2555
2556 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2557 static void tegra_dc_reset_worker(struct work_struct *work)
2558 {
2559         struct tegra_dc *dc =
2560                 container_of(work, struct tegra_dc, reset_work);
2561
2562         unsigned long val = 0;
2563
2564         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2565
2566         tegra_dc_ext_disable(dc->ext);
2567
2568         mutex_lock(&shared_lock);
2569         mutex_lock(&dc->lock);
2570
2571         if (dc->enabled == false)
2572                 goto unlock;
2573
2574         dc->enabled = false;
2575
2576         /*
2577          * off host read bus
2578          */
2579         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2580         val &= ~(0x00000100);
2581         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2582
2583         /*
2584          * set DC to STOP mode
2585          */
2586         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2587
2588         msleep(10);
2589
2590         _tegra_dc_controller_disable(dc);
2591
2592         /* _tegra_dc_controller_reset_enable deasserts reset */
2593         _tegra_dc_controller_reset_enable(dc);
2594
2595         dc->enabled = true;
2596 unlock:
2597         mutex_unlock(&dc->lock);
2598         mutex_unlock(&shared_lock);
2599 }
2600 #endif
2601
2602 #ifdef CONFIG_SWITCH
2603 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2604 {
2605         struct tegra_dc *dc =
2606                 container_of(sdev, struct tegra_dc, modeset_switch);
2607
2608         if (!sdev->state)
2609                 return sprintf(buf, "offline\n");
2610
2611         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2612 }
2613 #endif
2614
2615 static int tegra_dc_probe(struct nvhost_device *ndev)
2616 {
2617         struct tegra_dc *dc;
2618         struct clk *clk;
2619         struct clk *emc_clk;
2620         struct resource *res;
2621         struct resource *base_res;
2622         struct resource *fb_mem = NULL;
2623         int ret = 0;
2624         void __iomem *base;
2625         int irq;
2626         int i;
2627
2628         if (!ndev->dev.platform_data) {
2629                 dev_err(&ndev->dev, "no platform data\n");
2630                 return -ENOENT;
2631         }
2632
2633         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2634         if (!dc) {
2635                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2636                 return -ENOMEM;
2637         }
2638
2639         irq = nvhost_get_irq_byname(ndev, "irq");
2640         if (irq <= 0) {
2641                 dev_err(&ndev->dev, "no irq\n");
2642                 ret = -ENOENT;
2643                 goto err_free;
2644         }
2645
2646         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2647         if (!res) {
2648                 dev_err(&ndev->dev, "no mem resource\n");
2649                 ret = -ENOENT;
2650                 goto err_free;
2651         }
2652
2653         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2654         if (!base_res) {
2655                 dev_err(&ndev->dev, "request_mem_region failed\n");
2656                 ret = -EBUSY;
2657                 goto err_free;
2658         }
2659
2660         base = ioremap(res->start, resource_size(res));
2661         if (!base) {
2662                 dev_err(&ndev->dev, "registers can't be mapped\n");
2663                 ret = -EBUSY;
2664                 goto err_release_resource_reg;
2665         }
2666
2667         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2668
2669         clk = clk_get(&ndev->dev, NULL);
2670         if (IS_ERR_OR_NULL(clk)) {
2671                 dev_err(&ndev->dev, "can't get clock\n");
2672                 ret = -ENOENT;
2673                 goto err_iounmap_reg;
2674         }
2675
2676         emc_clk = clk_get(&ndev->dev, "emc");
2677         if (IS_ERR_OR_NULL(emc_clk)) {
2678                 dev_err(&ndev->dev, "can't get emc clock\n");
2679                 ret = -ENOENT;
2680                 goto err_put_clk;
2681         }
2682
2683         dc->clk = clk;
2684         dc->emc_clk = emc_clk;
2685
2686         dc->base_res = base_res;
2687         dc->base = base;
2688         dc->irq = irq;
2689         dc->ndev = ndev;
2690         dc->pdata = ndev->dev.platform_data;
2691
2692         /*
2693          * The emc is a shared clock, it will be set based on
2694          * the requirements for each user on the bus.
2695          */
2696         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2697         clk_set_rate(emc_clk, dc->emc_clk_rate);
2698
2699         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2700                 dc->enabled = true;
2701
2702         mutex_init(&dc->lock);
2703         init_completion(&dc->frame_end_complete);
2704         init_waitqueue_head(&dc->wq);
2705 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2706         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2707 #endif
2708         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2709
2710         tegra_dc_init_lut_defaults(&dc->fb_lut);
2711
2712         dc->n_windows = DC_N_WINDOWS;
2713         for (i = 0; i < dc->n_windows; i++) {
2714                 struct tegra_dc_win *win = &dc->windows[i];
2715                 win->idx = i;
2716                 win->dc = dc;
2717                 tegra_dc_init_csc_defaults(&win->csc);
2718                 tegra_dc_init_lut_defaults(&win->lut);
2719         }
2720
2721         ret = tegra_dc_set(dc, ndev->id);
2722         if (ret < 0) {
2723                 dev_err(&ndev->dev, "can't add dc\n");
2724                 goto err_free_irq;
2725         }
2726
2727         nvhost_set_drvdata(ndev, dc);
2728
2729 #ifdef CONFIG_SWITCH
2730         dc->modeset_switch.name = dev_name(&ndev->dev);
2731         dc->modeset_switch.state = 0;
2732         dc->modeset_switch.print_state = switch_modeset_print_mode;
2733         switch_dev_register(&dc->modeset_switch);
2734 #endif
2735
2736         if (dc->pdata->default_out)
2737                 tegra_dc_set_out(dc, dc->pdata->default_out);
2738         else
2739                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2740
2741         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2742                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2743
2744         dc->ext = tegra_dc_ext_register(ndev, dc);
2745         if (IS_ERR_OR_NULL(dc->ext)) {
2746                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2747                 dc->ext = NULL;
2748         }
2749
2750         /* interrupt handler must be registered before tegra_fb_register() */
2751         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2752                         dev_name(&ndev->dev), dc)) {
2753                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2754                 ret = -EBUSY;
2755                 goto err_put_emc_clk;
2756         }
2757
2758         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2759         disable_dc_irq(dc->irq);
2760
2761         mutex_lock(&dc->lock);
2762         if (dc->enabled)
2763                 _tegra_dc_enable(dc);
2764         mutex_unlock(&dc->lock);
2765
2766         tegra_dc_create_debugfs(dc);
2767
2768         dev_info(&ndev->dev, "probed\n");
2769
2770         if (dc->pdata->fb) {
2771                 if (dc->pdata->fb->bits_per_pixel == -1) {
2772                         unsigned long fmt;
2773                         tegra_dc_writel(dc,
2774                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2775                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2776
2777                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2778                         dc->pdata->fb->bits_per_pixel =
2779                                 tegra_dc_fmt_bpp(fmt);
2780                 }
2781
2782                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2783                 if (IS_ERR_OR_NULL(dc->fb))
2784                         dc->fb = NULL;
2785         }
2786
2787         if (dc->fb) {
2788                 dc->overlay = tegra_overlay_register(ndev, dc);
2789                 if (IS_ERR_OR_NULL(dc->overlay))
2790                         dc->overlay = NULL;
2791         }
2792
2793         if (dc->out && dc->out->hotplug_init)
2794                 dc->out->hotplug_init();
2795
2796         if (dc->out_ops && dc->out_ops->detect)
2797                 dc->out_ops->detect(dc);
2798         else
2799                 dc->connected = true;
2800
2801         tegra_dc_create_sysfs(&dc->ndev->dev);
2802
2803         return 0;
2804
2805 err_free_irq:
2806         free_irq(irq, dc);
2807 err_put_emc_clk:
2808         clk_put(emc_clk);
2809 err_put_clk:
2810         clk_put(clk);
2811 err_iounmap_reg:
2812         iounmap(base);
2813         if (fb_mem)
2814                 release_resource(fb_mem);
2815 err_release_resource_reg:
2816         release_resource(base_res);
2817 err_free:
2818         kfree(dc);
2819
2820         return ret;
2821 }
2822
2823 static int tegra_dc_remove(struct nvhost_device *ndev)
2824 {
2825         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2826
2827         tegra_dc_remove_sysfs(&dc->ndev->dev);
2828         tegra_dc_remove_debugfs(dc);
2829
2830         if (dc->overlay) {
2831                 tegra_overlay_unregister(dc->overlay);
2832         }
2833
2834         if (dc->fb) {
2835                 tegra_fb_unregister(dc->fb);
2836                 if (dc->fb_mem)
2837                         release_resource(dc->fb_mem);
2838         }
2839
2840         tegra_dc_ext_disable(dc->ext);
2841
2842         if (dc->ext)
2843                 tegra_dc_ext_unregister(dc->ext);
2844
2845         if (dc->enabled)
2846                 _tegra_dc_disable(dc);
2847
2848 #ifdef CONFIG_SWITCH
2849         switch_dev_unregister(&dc->modeset_switch);
2850 #endif
2851         free_irq(dc->irq, dc);
2852         clk_put(dc->emc_clk);
2853         clk_put(dc->clk);
2854         iounmap(dc->base);
2855         if (dc->fb_mem)
2856                 release_resource(dc->base_res);
2857         kfree(dc);
2858         tegra_dc_set(NULL, ndev->id);
2859         return 0;
2860 }
2861
2862 #ifdef CONFIG_PM
2863 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2864 {
2865         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2866
2867         dev_info(&ndev->dev, "suspend\n");
2868
2869         if (dc->overlay)
2870                 tegra_overlay_disable(dc->overlay);
2871
2872         tegra_dc_ext_disable(dc->ext);
2873
2874         mutex_lock(&dc->lock);
2875
2876         if (dc->out_ops && dc->out_ops->suspend)
2877                 dc->out_ops->suspend(dc);
2878
2879         if (dc->enabled) {
2880                 _tegra_dc_disable(dc);
2881
2882                 dc->suspended = true;
2883         }
2884
2885         if (dc->out && dc->out->postsuspend) {
2886                 dc->out->postsuspend();
2887                 msleep(100); /* avoid resume event due to voltage falling */
2888         }
2889
2890         mutex_unlock(&dc->lock);
2891
2892         return 0;
2893 }
2894
2895 static int tegra_dc_resume(struct nvhost_device *ndev)
2896 {
2897         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2898
2899         dev_info(&ndev->dev, "resume\n");
2900
2901         mutex_lock(&dc->lock);
2902         dc->suspended = false;
2903
2904         if (dc->enabled)
2905                 _tegra_dc_enable(dc);
2906
2907         if (dc->out && dc->out->hotplug_init)
2908                 dc->out->hotplug_init();
2909
2910         if (dc->out_ops && dc->out_ops->resume)
2911                 dc->out_ops->resume(dc);
2912         mutex_unlock(&dc->lock);
2913
2914         return 0;
2915 }
2916
2917 #endif /* CONFIG_PM */
2918
2919 extern int suspend_set(const char *val, struct kernel_param *kp)
2920 {
2921         if (!strcmp(val, "dump"))
2922                 dump_regs(tegra_dcs[0]);
2923 #ifdef CONFIG_PM
2924         else if (!strcmp(val, "suspend"))
2925                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2926         else if (!strcmp(val, "resume"))
2927                 tegra_dc_resume(tegra_dcs[0]->ndev);
2928 #endif
2929
2930         return 0;
2931 }
2932
2933 extern int suspend_get(char *buffer, struct kernel_param *kp)
2934 {
2935         return 0;
2936 }
2937
2938 int suspend;
2939
2940 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2941
2942 struct nvhost_driver tegra_dc_driver = {
2943         .driver = {
2944                 .name = "tegradc",
2945                 .owner = THIS_MODULE,
2946         },
2947         .probe = tegra_dc_probe,
2948         .remove = tegra_dc_remove,
2949 #ifdef CONFIG_PM
2950         .suspend = tegra_dc_suspend,
2951         .resume = tegra_dc_resume,
2952 #endif
2953 };
2954
2955 static int __init tegra_dc_module_init(void)
2956 {
2957         int ret = tegra_dc_ext_module_init();
2958         if (ret)
2959                 return ret;
2960         return nvhost_driver_register(&tegra_dc_driver);
2961 }
2962
2963 static void __exit tegra_dc_module_exit(void)
2964 {
2965         nvhost_driver_unregister(&tegra_dc_driver);
2966         tegra_dc_ext_module_exit();
2967 }
2968
2969 module_exit(tegra_dc_module_exit);
2970 module_init(tegra_dc_module_init);