video: tegra: dc: power optimize DC and host1x clk
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "nvsd.h"
55
56 #define TEGRA_CRC_LATCHED_DELAY         34
57
58 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
59 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
60
61 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
62         .refresh = 60,
63         .xres = 640,
64         .yres = 480,
65         .pixclock = KHZ2PICOS(25200),
66         .hsync_len = 96,        /* h_sync_width */
67         .vsync_len = 2,         /* v_sync_width */
68         .left_margin = 48,      /* h_back_porch */
69         .upper_margin = 33,     /* v_back_porch */
70         .right_margin = 16,     /* h_front_porch */
71         .lower_margin = 10,     /* v_front_porch */
72         .vmode = 0,
73         .sync = 0,
74 };
75
76 static struct tegra_dc_mode override_disp_mode[3];
77
78 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
79
80 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
81
82 DEFINE_MUTEX(tegra_dc_lock);
83 DEFINE_MUTEX(shared_lock);
84
85 void tegra_dc_clk_enable(struct tegra_dc *dc)
86 {
87         if (!tegra_is_clk_enabled(dc->clk)) {
88                 clk_enable(dc->clk);
89                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
90         }
91 }
92
93 void tegra_dc_clk_disable(struct tegra_dc *dc)
94 {
95         if (tegra_is_clk_enabled(dc->clk)) {
96                 clk_disable(dc->clk);
97                 tegra_dvfs_set_rate(dc->clk, 0);
98         }
99 }
100
101 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
102 {
103         if (dc->out_ops->hold)
104                 dc->out_ops->hold(dc);
105 }
106
107 void tegra_dc_release_dc_out(struct tegra_dc *dc)
108 {
109         if (dc->out_ops->release)
110                 dc->out_ops->release(dc);
111 }
112
113 #define DUMP_REG(a) do {                        \
114         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
115                  #a, a, tegra_dc_readl(dc, a));               \
116         print(data, buff);                                    \
117         } while (0)
118
119 #define print_underflow_info(dc) do {                 \
120         trace_printk("%s:Underflow stats: underflows : %llu, "      \
121                         "undeflows_a : %llu, "                          \
122                         "underflows_b : %llu, "                         \
123                         "underflows_c : %llu\n",                        \
124                         dc->ndev->name,                                 \
125                         dc->stats.underflows,                           \
126                         dc->stats.underflows_a, dc->stats.underflows_b, \
127                         dc->stats.underflows_c);                        \
128         } while (0)
129
130 static void _dump_regs(struct tegra_dc *dc, void *data,
131                        void (* print)(void *data, const char *str))
132 {
133         int i;
134         char buff[256];
135
136         mutex_lock(&dc->lock);
137         tegra_dc_io_start(dc);
138         tegra_dc_hold_dc_out(dc);
139
140         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
141         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
142         DUMP_REG(DC_CMD_SIGNAL_RAISE);
143         DUMP_REG(DC_CMD_INT_STATUS);
144         DUMP_REG(DC_CMD_INT_MASK);
145         DUMP_REG(DC_CMD_INT_ENABLE);
146         DUMP_REG(DC_CMD_INT_TYPE);
147         DUMP_REG(DC_CMD_INT_POLARITY);
148         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
149         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
150         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
151         DUMP_REG(DC_CMD_STATE_ACCESS);
152         DUMP_REG(DC_CMD_STATE_CONTROL);
153         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
154         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
155
156         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
157         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
158         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
159         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
160         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
161         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
162         DUMP_REG(DC_DISP_REF_TO_SYNC);
163         DUMP_REG(DC_DISP_SYNC_WIDTH);
164         DUMP_REG(DC_DISP_BACK_PORCH);
165         DUMP_REG(DC_DISP_DISP_ACTIVE);
166         DUMP_REG(DC_DISP_FRONT_PORCH);
167         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
168         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
169         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
170         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
171         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
172         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
173         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
174         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
175         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
176         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
177         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
178         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
179         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
180         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
181         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
182         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
183         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
184         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
185         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
186         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
187         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
188         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
189         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
190         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
191         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
192         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
193         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
194         DUMP_REG(DC_DISP_M0_CONTROL);
195         DUMP_REG(DC_DISP_M1_CONTROL);
196         DUMP_REG(DC_DISP_DI_CONTROL);
197         DUMP_REG(DC_DISP_PP_CONTROL);
198         DUMP_REG(DC_DISP_PP_SELECT_A);
199         DUMP_REG(DC_DISP_PP_SELECT_B);
200         DUMP_REG(DC_DISP_PP_SELECT_C);
201         DUMP_REG(DC_DISP_PP_SELECT_D);
202         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
203         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
204         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
205         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
206         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
207         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
208         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
209         DUMP_REG(DC_DISP_BORDER_COLOR);
210         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
211         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
212         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
213         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
214         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
215         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
216         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
217         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
218         DUMP_REG(DC_DISP_CURSOR_POSITION);
219         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
220         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
221         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
222         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
223         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
224         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
225         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
226         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
227         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
228         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
229         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
230         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
231         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
232
233
234         for (i = 0; i < 3; i++) {
235                 print(data, "\n");
236                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
237                 print(data, buff);
238
239                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
240                                 DC_CMD_DISPLAY_WINDOW_HEADER);
241                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
242                 DUMP_REG(DC_WIN_WIN_OPTIONS);
243                 DUMP_REG(DC_WIN_BYTE_SWAP);
244                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
245                 DUMP_REG(DC_WIN_COLOR_DEPTH);
246                 DUMP_REG(DC_WIN_POSITION);
247                 DUMP_REG(DC_WIN_SIZE);
248                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
249                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
250                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
251                 DUMP_REG(DC_WIN_DDA_INCREMENT);
252                 DUMP_REG(DC_WIN_LINE_STRIDE);
253                 DUMP_REG(DC_WIN_BUF_STRIDE);
254                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
255                 DUMP_REG(DC_WIN_BLEND_NOKEY);
256                 DUMP_REG(DC_WIN_BLEND_1WIN);
257                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
258                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
259                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
260                 DUMP_REG(DC_WINBUF_START_ADDR);
261                 DUMP_REG(DC_WINBUF_START_ADDR_U);
262                 DUMP_REG(DC_WINBUF_START_ADDR_V);
263                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
264                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
265                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
266                 DUMP_REG(DC_WIN_CSC_YOF);
267                 DUMP_REG(DC_WIN_CSC_KYRGB);
268                 DUMP_REG(DC_WIN_CSC_KUR);
269                 DUMP_REG(DC_WIN_CSC_KVR);
270                 DUMP_REG(DC_WIN_CSC_KUG);
271                 DUMP_REG(DC_WIN_CSC_KVG);
272                 DUMP_REG(DC_WIN_CSC_KUB);
273                 DUMP_REG(DC_WIN_CSC_KVB);
274         }
275
276         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
277         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
278         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
279         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
280         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
281         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
282         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
283         DUMP_REG(DC_DISP_M1_CONTROL);
284         DUMP_REG(DC_COM_PM1_CONTROL);
285         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
286         DUMP_REG(DC_DISP_SD_CONTROL);
287
288         tegra_dc_release_dc_out(dc);
289         tegra_dc_io_end(dc);
290         mutex_unlock(&dc->lock);
291 }
292
293 #undef DUMP_REG
294
295 #ifdef DEBUG
296 static void dump_regs_print(void *data, const char *str)
297 {
298         struct tegra_dc *dc = data;
299         dev_dbg(&dc->ndev->dev, "%s", str);
300 }
301
302 static void dump_regs(struct tegra_dc *dc)
303 {
304         _dump_regs(dc, dc, dump_regs_print);
305 }
306 #else /* !DEBUG */
307
308 static void dump_regs(struct tegra_dc *dc) {}
309
310 #endif /* DEBUG */
311
312 #ifdef CONFIG_DEBUG_FS
313
314 static void dbg_regs_print(void *data, const char *str)
315 {
316         struct seq_file *s = data;
317
318         seq_printf(s, "%s", str);
319 }
320
321 #undef DUMP_REG
322
323 static int dbg_dc_show(struct seq_file *s, void *unused)
324 {
325         struct tegra_dc *dc = s->private;
326
327         _dump_regs(dc, s, dbg_regs_print);
328
329         return 0;
330 }
331
332
333 static int dbg_dc_open(struct inode *inode, struct file *file)
334 {
335         return single_open(file, dbg_dc_show, inode->i_private);
336 }
337
338 static const struct file_operations regs_fops = {
339         .open           = dbg_dc_open,
340         .read           = seq_read,
341         .llseek         = seq_lseek,
342         .release        = single_release,
343 };
344
345 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
346 {
347         struct tegra_dc *dc = s->private;
348         struct tegra_dc_mode *m;
349
350         mutex_lock(&dc->lock);
351         m = &dc->mode;
352         seq_printf(s,
353                 "pclk: %d\n"
354                 "h_ref_to_sync: %d\n"
355                 "v_ref_to_sync: %d\n"
356                 "h_sync_width: %d\n"
357                 "v_sync_width: %d\n"
358                 "h_back_porch: %d\n"
359                 "v_back_porch: %d\n"
360                 "h_active: %d\n"
361                 "v_active: %d\n"
362                 "h_front_porch: %d\n"
363                 "v_front_porch: %d\n"
364                 "stereo_mode: %d\n",
365                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
366                 m->h_sync_width, m->v_sync_width,
367                 m->h_back_porch, m->v_back_porch,
368                 m->h_active, m->v_active,
369                 m->h_front_porch, m->v_front_porch,
370                 m->stereo_mode);
371         mutex_unlock(&dc->lock);
372         return 0;
373 }
374
375 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
376 {
377         return single_open(file, dbg_dc_mode_show, inode->i_private);
378 }
379
380 static const struct file_operations mode_fops = {
381         .open           = dbg_dc_mode_open,
382         .read           = seq_read,
383         .llseek         = seq_lseek,
384         .release        = single_release,
385 };
386
387 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
388 {
389         struct tegra_dc *dc = s->private;
390
391         mutex_lock(&dc->lock);
392         seq_printf(s,
393                 "underflows: %llu\n"
394                 "underflows_a: %llu\n"
395                 "underflows_b: %llu\n"
396                 "underflows_c: %llu\n",
397                 dc->stats.underflows,
398                 dc->stats.underflows_a,
399                 dc->stats.underflows_b,
400                 dc->stats.underflows_c);
401         mutex_unlock(&dc->lock);
402
403         return 0;
404 }
405
406 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
407 {
408         return single_open(file, dbg_dc_stats_show, inode->i_private);
409 }
410
411 static const struct file_operations stats_fops = {
412         .open           = dbg_dc_stats_open,
413         .read           = seq_read,
414         .llseek         = seq_lseek,
415         .release        = single_release,
416 };
417
418 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
419 {
420         if (dc->debugdir)
421                 debugfs_remove_recursive(dc->debugdir);
422         dc->debugdir = NULL;
423 }
424
425 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
426 {
427         struct dentry *retval;
428
429         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
430         if (!dc->debugdir)
431                 goto remove_out;
432
433         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
434                 &regs_fops);
435         if (!retval)
436                 goto remove_out;
437
438         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
439                 &mode_fops);
440         if (!retval)
441                 goto remove_out;
442
443         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
444                 &stats_fops);
445         if (!retval)
446                 goto remove_out;
447
448         return;
449 remove_out:
450         dev_err(&dc->ndev->dev, "could not create debugfs\n");
451         tegra_dc_remove_debugfs(dc);
452 }
453
454 #else /* !CONFIG_DEBUGFS */
455 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
456 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
457 #endif /* CONFIG_DEBUGFS */
458
459 static int tegra_dc_set(struct tegra_dc *dc, int index)
460 {
461         int ret = 0;
462
463         mutex_lock(&tegra_dc_lock);
464         if (index >= TEGRA_MAX_DC) {
465                 ret = -EINVAL;
466                 goto out;
467         }
468
469         if (dc != NULL && tegra_dcs[index] != NULL) {
470                 ret = -EBUSY;
471                 goto out;
472         }
473
474         tegra_dcs[index] = dc;
475
476 out:
477         mutex_unlock(&tegra_dc_lock);
478
479         return ret;
480 }
481
482 unsigned int tegra_dc_has_multiple_dc(void)
483 {
484         unsigned int idx;
485         unsigned int cnt = 0;
486         struct tegra_dc *dc;
487
488         mutex_lock(&tegra_dc_lock);
489         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
490                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
491         mutex_unlock(&tegra_dc_lock);
492
493         return (cnt > 1);
494 }
495
496 /* get the stride size of a window.
497  * return: stride size in bytes for window win. or 0 if unavailble. */
498 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
499 {
500         u32 stride;
501
502         if (!dc->enabled)
503                 return 0;
504         BUG_ON(win > DC_N_WINDOWS);
505         mutex_lock(&dc->lock);
506         tegra_dc_io_start(dc);
507         tegra_dc_hold_dc_out(dc);
508         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
509                 DC_CMD_DISPLAY_WINDOW_HEADER);
510         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
511         tegra_dc_release_dc_out(dc);
512         tegra_dc_io_end(dc);
513         mutex_unlock(&dc->lock);
514         return GET_LINE_STRIDE(stride);
515 }
516 EXPORT_SYMBOL(tegra_dc_get_stride);
517
518 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
519 {
520         if (idx < TEGRA_MAX_DC)
521                 return tegra_dcs[idx];
522         else
523                 return NULL;
524 }
525 EXPORT_SYMBOL(tegra_dc_get_dc);
526
527 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
528 {
529         if (win >= dc->n_windows)
530                 return NULL;
531
532         return &dc->windows[win];
533 }
534 EXPORT_SYMBOL(tegra_dc_get_window);
535
536 bool tegra_dc_get_connected(struct tegra_dc *dc)
537 {
538         return dc->connected;
539 }
540 EXPORT_SYMBOL(tegra_dc_get_connected);
541
542 bool tegra_dc_hpd(struct tegra_dc *dc)
543 {
544         int sense;
545         int level;
546
547         level = gpio_get_value(dc->out->hotplug_gpio);
548
549         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
550
551         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
552                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
553 }
554 EXPORT_SYMBOL(tegra_dc_hpd);
555
556 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
557 {
558         unsigned i;
559         unsigned v0 = 128;
560         unsigned v1 = 0;
561
562         /* linear horizontal and vertical filters */
563         for (i = 0; i < 16; i++) {
564                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
565                                 DC_WIN_H_FILTER_P(i));
566
567                 tegra_dc_writel(dc, v0,
568                                 DC_WIN_V_FILTER_P(i));
569                 v0 -= 8;
570                 v1 += 8;
571         }
572 }
573
574 /* disable_irq() blocks until handler completes, calling this function while
575  * holding dc->lock can deadlock. */
576 static inline void disable_dc_irq(const struct tegra_dc *dc)
577 {
578         disable_irq(dc->irq);
579 }
580
581 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
582 {
583         return dc->syncpt[i].id;
584 }
585 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
586
587 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
588 {
589         u32 max;
590
591         mutex_lock(&dc->lock);
592         tegra_dc_io_start(dc);
593         tegra_dc_hold_dc_out(dc);
594         max = nvhost_syncpt_incr_max_ext(dc->ndev,
595                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
596         dc->syncpt[i].max = max;
597         tegra_dc_release_dc_out(dc);
598         tegra_dc_io_end(dc);
599         mutex_unlock(&dc->lock);
600
601         return max;
602 }
603
604 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
605 {
606         mutex_lock(&dc->lock);
607         if (dc->enabled) {
608                 tegra_dc_io_start(dc);
609                 tegra_dc_hold_dc_out(dc);
610                 while (dc->syncpt[i].min < val) {
611                         dc->syncpt[i].min++;
612                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
613                 }
614                 tegra_dc_release_dc_out(dc);
615                 tegra_dc_io_end(dc);
616         }
617         mutex_unlock(&dc->lock);
618 }
619
620 void
621 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
622 {
623         unsigned int ctrl;
624         unsigned long out_sel;
625         unsigned long cmd_state;
626
627         mutex_lock(&dc->lock);
628         if (!dc->enabled) {
629                 mutex_unlock(&dc->lock);
630                 return;
631         }
632
633         tegra_dc_io_start(dc);
634         tegra_dc_hold_dc_out(dc);
635
636         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
637                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
638                 cfg->clk_select);
639
640         /* The new value should be effected immediately */
641         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
642         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
643
644         switch (cfg->which_pwm) {
645         case TEGRA_PWM_PM0:
646                 /* Select the LM0 on PM0 */
647                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
648                 out_sel &= ~(7 << 0);
649                 out_sel |= (3 << 0);
650                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
651                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
652                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
653                 break;
654         case TEGRA_PWM_PM1:
655                 /* Select the LM1 on PM1 */
656                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
657                 out_sel &= ~(7 << 4);
658                 out_sel |= (3 << 4);
659                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
660                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
661                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
662                 break;
663         default:
664                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
665                 break;
666         }
667         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
668         tegra_dc_release_dc_out(dc);
669         tegra_dc_io_end(dc);
670         mutex_unlock(&dc->lock);
671 }
672 EXPORT_SYMBOL(tegra_dc_config_pwm);
673
674 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
675                                 const struct tegra_dc_out_pin *pins,
676                                 const unsigned int n_pins)
677 {
678         unsigned int i;
679
680         int name;
681         int pol;
682
683         u32 pol1, pol3;
684
685         u32 set1, unset1;
686         u32 set3, unset3;
687
688         set1 = set3 = unset1 = unset3 = 0;
689
690         for (i = 0; i < n_pins; i++) {
691                 name = (pins + i)->name;
692                 pol  = (pins + i)->pol;
693
694                 /* set polarity by name */
695                 switch (name) {
696                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
697                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
698                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
699                         else
700                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
701                         break;
702                 case TEGRA_DC_OUT_PIN_H_SYNC:
703                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
704                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
705                         else
706                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
707                         break;
708                 case TEGRA_DC_OUT_PIN_V_SYNC:
709                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
710                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
711                         else
712                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
713                         break;
714                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
715                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
716                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
717                         else
718                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
719                         break;
720                 default:
721                         printk("Invalid argument in function %s\n",
722                                __FUNCTION__);
723                         break;
724                 }
725         }
726
727         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
728         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
729
730         pol1 |= set1;
731         pol1 &= ~unset1;
732
733         pol3 |= set3;
734         pol3 &= ~unset3;
735
736         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
737         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
738 }
739
740 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
741 {
742         if (dc->out->type == TEGRA_DC_OUT_RGB ||
743                 dc->out->type == TEGRA_DC_OUT_HDMI ||
744                 dc->out->type == TEGRA_DC_OUT_DSI)
745                 return override_disp_mode[dc->out->type].pclk ?
746                         &override_disp_mode[dc->out->type] : NULL;
747         else
748                 return NULL;
749 }
750
751 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
752 {
753         struct tegra_dc_mode *mode;
754
755         dc->out = out;
756         mode = tegra_dc_get_override_mode(dc);
757
758         if (mode)
759                 tegra_dc_set_mode(dc, mode);
760         else if (out->n_modes > 0)
761                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
762
763         switch (out->type) {
764         case TEGRA_DC_OUT_RGB:
765                 dc->out_ops = &tegra_dc_rgb_ops;
766                 break;
767
768         case TEGRA_DC_OUT_HDMI:
769                 dc->out_ops = &tegra_dc_hdmi_ops;
770                 break;
771
772         case TEGRA_DC_OUT_DSI:
773                 dc->out_ops = &tegra_dc_dsi_ops;
774                 break;
775
776         default:
777                 dc->out_ops = NULL;
778                 break;
779         }
780
781         if (dc->out_ops && dc->out_ops->init)
782                 dc->out_ops->init(dc);
783
784 }
785
786 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
787 {
788         if (dc->out)
789                 return dc->out->height;
790         else
791                 return 0;
792 }
793 EXPORT_SYMBOL(tegra_dc_get_out_height);
794
795 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
796 {
797         if (dc->out)
798                 return dc->out->width;
799         else
800                 return 0;
801 }
802 EXPORT_SYMBOL(tegra_dc_get_out_width);
803
804 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
805 {
806         if (dc->out && dc->out->max_pixclock)
807                 return dc->out->max_pixclock;
808         else
809                 return 0;
810 }
811 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
812
813 void tegra_dc_enable_crc(struct tegra_dc *dc)
814 {
815         u32 val;
816
817         mutex_lock(&dc->lock);
818         tegra_dc_io_start(dc);
819         tegra_dc_hold_dc_out(dc);
820
821         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
822                 CRC_ENABLE_ENABLE;
823         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
824         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
825         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
826         tegra_dc_release_dc_out(dc);
827         tegra_dc_io_end(dc);
828         mutex_unlock(&dc->lock);
829 }
830
831 void tegra_dc_disable_crc(struct tegra_dc *dc)
832 {
833         mutex_lock(&dc->lock);
834         tegra_dc_io_start(dc);
835         tegra_dc_hold_dc_out(dc);
836         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
837         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
838         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
839
840         tegra_dc_release_dc_out(dc);
841         tegra_dc_io_end(dc);
842         mutex_unlock(&dc->lock);
843 }
844
845 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
846 {
847         int crc = 0;
848
849         if (!dc) {
850                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
851                 goto crc_error;
852         }
853
854         /* TODO: Replace mdelay with code to sync VBlANK, since
855          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
856         mdelay(TEGRA_CRC_LATCHED_DELAY);
857
858         mutex_lock(&dc->lock);
859         tegra_dc_io_start(dc);
860         tegra_dc_hold_dc_out(dc);
861         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
862         tegra_dc_release_dc_out(dc);
863         tegra_dc_io_end(dc);
864         mutex_unlock(&dc->lock);
865 crc_error:
866         return crc;
867 }
868
869 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
870 {
871 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
872         u32 val;
873
874         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
875         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
876             return true;
877 #endif
878         return false;
879 }
880
881 static inline void enable_dc_irq(const struct tegra_dc *dc)
882 {
883 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
884         enable_irq(dc->irq);
885 #else
886         /* Always disable DC interrupts on FPGA. */
887         disable_irq(dc->irq);
888 #endif
889 }
890
891 static void tegra_dc_vblank(struct work_struct *work)
892 {
893         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
894         bool nvsd_updated = false;
895
896         mutex_lock(&dc->lock);
897
898         if (!dc->enabled) {
899                 mutex_unlock(&dc->lock);
900                 return;
901         }
902
903         tegra_dc_io_start(dc);
904         tegra_dc_hold_dc_out(dc);
905         /* use the new frame's bandwidth setting instead of max(current, new),
906          * skip this if we're using tegra_dc_one_shot_worker() */
907         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
908                 tegra_dc_program_bandwidth(dc, true);
909
910         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
911         if (!tegra_dc_windows_are_dirty(dc))
912                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
913
914         /* Update the SD brightness */
915         if (dc->enabled && dc->out->sd_settings) {
916                 nvsd_updated = nvsd_update_brightness(dc);
917                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
918                  * V_BLANK_NVSD bit of vblank ref-count. */
919                 if (nvsd_updated) {
920                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
921                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
922                 } else {
923                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
924                 }
925         }
926
927         /* Mask vblank interrupt if ref-count is zero. */
928         if (!dc->vblank_ref_count)
929                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
930
931         tegra_dc_release_dc_out(dc);
932         tegra_dc_io_end(dc);
933         mutex_unlock(&dc->lock);
934
935         /* Do the actual brightness update outside of the mutex */
936         if (nvsd_updated && dc->out->sd_settings &&
937             dc->out->sd_settings->bl_device) {
938
939                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
940                 struct backlight_device *bl = platform_get_drvdata(pdev);
941                 if (bl)
942                         backlight_update_status(bl);
943         }
944 }
945
946 static void tegra_dc_one_shot_worker(struct work_struct *work)
947 {
948         struct tegra_dc *dc = container_of(
949                 to_delayed_work(work), struct tegra_dc, one_shot_work);
950         mutex_lock(&dc->lock);
951
952         /* memory client has gone idle */
953         tegra_dc_clear_bandwidth(dc);
954
955         if (dc->out_ops->idle) {
956                 tegra_dc_io_start(dc);
957                 dc->out_ops->idle(dc);
958                 tegra_dc_io_end(dc);
959         }
960
961         mutex_unlock(&dc->lock);
962 }
963
964 /* return an arbitrarily large number if count overflow occurs.
965  * make it a nice base-10 number to show up in stats output */
966 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
967 {
968         unsigned count = tegra_dc_readl(dc, reg);
969
970         tegra_dc_writel(dc, 0, reg);
971         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
972 }
973
974 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
975 {
976         int i;
977
978         dc->stats.underflows++;
979         if (dc->underflow_mask & WIN_A_UF_INT) {
980                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
981                         DC_WINBUF_AD_UFLOW_STATUS);
982                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
983         }
984         if (dc->underflow_mask & WIN_B_UF_INT) {
985                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
986                         DC_WINBUF_BD_UFLOW_STATUS);
987                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
988         }
989         if (dc->underflow_mask & WIN_C_UF_INT) {
990                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
991                         DC_WINBUF_CD_UFLOW_STATUS);
992                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
993         }
994
995         /* Check for any underflow reset conditions */
996         for (i = 0; i < DC_N_WINDOWS; i++) {
997                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
998                         dc->windows[i].underflows++;
999
1000 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1001                         if (dc->windows[i].underflows > 4) {
1002                                 schedule_work(&dc->reset_work);
1003                                 /* reset counter */
1004                                 dc->windows[i].underflows = 0;
1005                                 trace_printk("%s:Reset work scheduled for "
1006                                                 "window %c\n",
1007                                                 dc->ndev->name, (65 + i));
1008                         }
1009 #endif
1010 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1011                         if (dc->windows[i].underflows > 4) {
1012                                 trace_printk("%s:window %c in underflow state."
1013                                         " enable UF_LINE_FLUSH to clear up\n",
1014                                         dc->ndev->name, (65 + i));
1015                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1016                                                 DC_DISP_DISP_MISC_CONTROL);
1017                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1018                                                 DC_CMD_STATE_CONTROL);
1019                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1020                                                 DC_CMD_STATE_CONTROL);
1021
1022                                 tegra_dc_writel(dc, 0,
1023                                                 DC_DISP_DISP_MISC_CONTROL);
1024                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1025                                                 DC_CMD_STATE_CONTROL);
1026                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1027                                                 DC_CMD_STATE_CONTROL);
1028                         }
1029 #endif
1030                 } else {
1031                         dc->windows[i].underflows = 0;
1032                 }
1033         }
1034
1035         /* Clear the underflow mask now that we've checked it. */
1036         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1037         dc->underflow_mask = 0;
1038         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1039         print_underflow_info(dc);
1040 }
1041
1042 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1043 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1044 {
1045         if (status & V_BLANK_INT) {
1046                 /* Sync up windows. */
1047                 tegra_dc_trigger_windows(dc);
1048
1049                 /* Schedule any additional bottom-half vblank actvities. */
1050                 queue_work(system_freezable_wq, &dc->vblank_work);
1051         }
1052
1053         if (status & FRAME_END_INT) {
1054                 /* Mark the frame_end as complete. */
1055                 if (!completion_done(&dc->frame_end_complete))
1056                         complete(&dc->frame_end_complete);
1057         }
1058 }
1059
1060 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1061 {
1062         /* Schedule any additional bottom-half vblank actvities. */
1063         if (status & V_BLANK_INT)
1064                 queue_work(system_freezable_wq, &dc->vblank_work);
1065
1066         if (status & FRAME_END_INT) {
1067                 /* Mark the frame_end as complete. */
1068                 if (!completion_done(&dc->frame_end_complete))
1069                         complete(&dc->frame_end_complete);
1070
1071                 tegra_dc_trigger_windows(dc);
1072         }
1073 }
1074 #endif
1075
1076 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1077 {
1078 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1079         struct tegra_dc *dc = ptr;
1080         unsigned long status;
1081         unsigned long underflow_mask;
1082         u32 val;
1083
1084         mutex_lock(&dc->lock);
1085         clk_enable(dc->clk);
1086         tegra_dc_io_start(dc);
1087         tegra_dc_hold_dc_out(dc);
1088
1089         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1090                 WARN(1, "IRQ when DC not powered!\n");
1091                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1092                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1093                 tegra_dc_release_dc_out(dc);
1094                 tegra_dc_io_end(dc);
1095                 clk_disable(dc->clk);
1096                 mutex_unlock(&dc->lock);
1097                 return IRQ_HANDLED;
1098         }
1099
1100         /* clear all status flags except underflow, save those for the worker */
1101         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1102         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1103         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1104         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1105
1106         /*
1107          * Overlays can get thier internal state corrupted during and underflow
1108          * condition.  The only way to fix this state is to reset the DC.
1109          * if we get 4 consecutive frames with underflows, assume we're
1110          * hosed and reset.
1111          */
1112         underflow_mask = status & ALL_UF_INT;
1113
1114         /* Check underflow */
1115         if (underflow_mask) {
1116                 dc->underflow_mask |= underflow_mask;
1117                 schedule_delayed_work(&dc->underflow_work,
1118                         msecs_to_jiffies(1));
1119         }
1120
1121         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1122                 tegra_dc_one_shot_irq(dc, status);
1123         else
1124                 tegra_dc_continuous_irq(dc, status);
1125
1126         tegra_dc_release_dc_out(dc);
1127         tegra_dc_io_end(dc);
1128         clk_disable(dc->clk);
1129         mutex_unlock(&dc->lock);
1130
1131         return IRQ_HANDLED;
1132 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1133         return IRQ_NONE;
1134 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1135 }
1136
1137 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1138 {
1139         u32 color_control;
1140
1141         switch (dc->out->depth) {
1142         case 3:
1143                 color_control = BASE_COLOR_SIZE111;
1144                 break;
1145
1146         case 6:
1147                 color_control = BASE_COLOR_SIZE222;
1148                 break;
1149
1150         case 8:
1151                 color_control = BASE_COLOR_SIZE332;
1152                 break;
1153
1154         case 9:
1155                 color_control = BASE_COLOR_SIZE333;
1156                 break;
1157
1158         case 12:
1159                 color_control = BASE_COLOR_SIZE444;
1160                 break;
1161
1162         case 15:
1163                 color_control = BASE_COLOR_SIZE555;
1164                 break;
1165
1166         case 16:
1167                 color_control = BASE_COLOR_SIZE565;
1168                 break;
1169
1170         case 18:
1171                 color_control = BASE_COLOR_SIZE666;
1172                 break;
1173
1174         default:
1175                 color_control = BASE_COLOR_SIZE888;
1176                 break;
1177         }
1178
1179         switch (dc->out->dither) {
1180         case TEGRA_DC_DISABLE_DITHER:
1181                 color_control |= DITHER_CONTROL_DISABLE;
1182                 break;
1183         case TEGRA_DC_ORDERED_DITHER:
1184                 color_control |= DITHER_CONTROL_ORDERED;
1185                 break;
1186         case TEGRA_DC_ERRDIFF_DITHER:
1187                 /* The line buffer for error-diffusion dither is limited
1188                  * to 1280 pixels per line. This limits the maximum
1189                  * horizontal active area size to 1280 pixels when error
1190                  * diffusion is enabled.
1191                  */
1192                 BUG_ON(dc->mode.h_active > 1280);
1193                 color_control |= DITHER_CONTROL_ERRDIFF;
1194                 break;
1195         }
1196
1197         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1198 }
1199
1200 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1201 {
1202         u32 syncpt_id;
1203
1204         switch (dc->ndev->id) {
1205         case 0:
1206                 switch (idx) {
1207                 case 0:
1208                         syncpt_id = NVSYNCPT_DISP0_A;
1209                         break;
1210                 case 1:
1211                         syncpt_id = NVSYNCPT_DISP0_B;
1212                         break;
1213                 case 2:
1214                         syncpt_id = NVSYNCPT_DISP0_C;
1215                         break;
1216                 default:
1217                         BUG();
1218                         break;
1219                 }
1220                 break;
1221         case 1:
1222                 switch (idx) {
1223                 case 0:
1224                         syncpt_id = NVSYNCPT_DISP1_A;
1225                         break;
1226                 case 1:
1227                         syncpt_id = NVSYNCPT_DISP1_B;
1228                         break;
1229                 case 2:
1230                         syncpt_id = NVSYNCPT_DISP1_C;
1231                         break;
1232                 default:
1233                         BUG();
1234                         break;
1235                 }
1236                 break;
1237         default:
1238                 BUG();
1239                 break;
1240         }
1241
1242         return syncpt_id;
1243 }
1244
1245 static int tegra_dc_init(struct tegra_dc *dc)
1246 {
1247         int i;
1248
1249         tegra_dc_io_start(dc);
1250         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1251         if (dc->ndev->id == 0) {
1252                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1253                                       TEGRA_MC_PRIO_MED);
1254                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1255                                       TEGRA_MC_PRIO_MED);
1256                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1257                                       TEGRA_MC_PRIO_MED);
1258                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1259                                       TEGRA_MC_PRIO_MED);
1260                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1261                                       TEGRA_MC_PRIO_HIGH);
1262         } else if (dc->ndev->id == 1) {
1263                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1264                                       TEGRA_MC_PRIO_MED);
1265                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1266                                       TEGRA_MC_PRIO_MED);
1267                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1268                                       TEGRA_MC_PRIO_MED);
1269                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1270                                       TEGRA_MC_PRIO_MED);
1271                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1272                                       TEGRA_MC_PRIO_HIGH);
1273         }
1274         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1275                         DC_CMD_CONT_SYNCPT_VSYNC);
1276         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1277         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1278         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1279         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1280 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1281         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1282 #endif
1283         /* enable interrupts for vblank, frame_end and underflows */
1284         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1285                 DC_CMD_INT_ENABLE);
1286         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1287
1288         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1289
1290         tegra_dc_set_color_control(dc);
1291         for (i = 0; i < DC_N_WINDOWS; i++) {
1292                 struct tegra_dc_win *win = &dc->windows[i];
1293                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1294                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1295                 tegra_dc_set_csc(dc, &win->csc);
1296                 tegra_dc_set_lut(dc, win);
1297                 tegra_dc_set_scaling_filter(dc);
1298         }
1299
1300
1301         for (i = 0; i < dc->n_windows; i++) {
1302                 u32 syncpt = get_syncpt(dc, i);
1303
1304                 dc->syncpt[i].id = syncpt;
1305
1306                 dc->syncpt[i].min = dc->syncpt[i].max =
1307                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1308         }
1309
1310         print_mode_info(dc, dc->mode);
1311
1312         if (dc->mode.pclk) {
1313                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1314                         tegra_dc_io_end(dc);
1315                         return -EINVAL;
1316                 }
1317         }
1318
1319         /* Initialize SD AFTER the modeset.
1320            nvsd_init handles the sd_settings = NULL case. */
1321         nvsd_init(dc, dc->out->sd_settings);
1322
1323         tegra_dc_io_end(dc);
1324
1325         return 0;
1326 }
1327
1328 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1329 {
1330         int failed_init = 0;
1331
1332         if (dc->out->enable)
1333                 dc->out->enable();
1334
1335         tegra_dc_setup_clk(dc, dc->clk);
1336         tegra_dc_clk_enable(dc);
1337         tegra_dc_io_start(dc);
1338
1339         /* do not accept interrupts during initialization */
1340         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1341
1342         enable_dc_irq(dc);
1343
1344         failed_init = tegra_dc_init(dc);
1345         if (failed_init) {
1346                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1347                 disable_irq_nosync(dc->irq);
1348                 tegra_dc_clear_bandwidth(dc);
1349                 tegra_dc_clk_disable(dc);
1350                 if (dc->out && dc->out->disable)
1351                         dc->out->disable();
1352                 tegra_dc_io_end(dc);
1353                 return false;
1354         }
1355
1356         if (dc->out_ops && dc->out_ops->enable)
1357                 dc->out_ops->enable(dc);
1358
1359         /* force a full blending update */
1360         dc->blend.z[0] = -1;
1361
1362         tegra_dc_ext_enable(dc->ext);
1363
1364         trace_printk("%s:enable\n", dc->ndev->name);
1365
1366         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1367         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1368
1369         if (dc->out->postpoweron)
1370                 dc->out->postpoweron();
1371
1372         tegra_dc_io_end(dc);
1373         return true;
1374 }
1375
1376 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1377 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1378 {
1379         bool ret = true;
1380
1381         if (dc->out->enable)
1382                 dc->out->enable();
1383
1384         tegra_dc_setup_clk(dc, dc->clk);
1385         tegra_dc_clk_enable(dc);
1386
1387         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1388                 mutex_lock(&tegra_dcs[1]->lock);
1389                 disable_irq_nosync(tegra_dcs[1]->irq);
1390         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1391                 mutex_lock(&tegra_dcs[0]->lock);
1392                 disable_irq_nosync(tegra_dcs[0]->irq);
1393         }
1394
1395         msleep(5);
1396         tegra_periph_reset_assert(dc->clk);
1397         msleep(2);
1398 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1399         tegra_periph_reset_deassert(dc->clk);
1400         msleep(1);
1401 #endif
1402
1403         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1404                 enable_dc_irq(tegra_dcs[1]);
1405                 mutex_unlock(&tegra_dcs[1]->lock);
1406         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1407                 enable_dc_irq(tegra_dcs[0]);
1408                 mutex_unlock(&tegra_dcs[0]->lock);
1409         }
1410
1411         enable_dc_irq(dc);
1412
1413         if (tegra_dc_init(dc)) {
1414                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1415                 ret = false;
1416         }
1417
1418         if (dc->out_ops && dc->out_ops->enable)
1419                 dc->out_ops->enable(dc);
1420
1421         if (dc->out->postpoweron)
1422                 dc->out->postpoweron();
1423
1424         /* force a full blending update */
1425         dc->blend.z[0] = -1;
1426
1427         tegra_dc_ext_enable(dc->ext);
1428
1429         if (!ret) {
1430                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1431                 _tegra_dc_controller_disable(dc);
1432         }
1433
1434         trace_printk("%s:reset enable\n", dc->ndev->name);
1435         return ret;
1436 }
1437 #endif
1438
1439 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1440 {
1441         if (dc->mode.pclk == 0) {
1442                 switch (dc->out->type) {
1443                 case TEGRA_DC_OUT_HDMI:
1444                 /* DC enable called but no videomode is loaded.
1445                      Check if HDMI is connected, then set fallback mdoe */
1446                 if (tegra_dc_hpd(dc)) {
1447                         return tegra_dc_set_fb_mode(dc,
1448                                         &tegra_dc_hdmi_fallback_mode, 0);
1449                 } else
1450                         return false;
1451
1452                 break;
1453
1454                 /* Do nothing for other outputs for now */
1455                 case TEGRA_DC_OUT_RGB:
1456
1457                 case TEGRA_DC_OUT_DSI:
1458
1459                 default:
1460                         return false;
1461                 }
1462         }
1463
1464         return false;
1465 }
1466
1467 static bool _tegra_dc_enable(struct tegra_dc *dc)
1468 {
1469         if (dc->enabled)
1470                 return true;
1471
1472         if (dc->mode.pclk == 0)
1473                 return false;
1474
1475         if (!dc->out)
1476                 return false;
1477
1478         if (!_tegra_dc_controller_enable(dc)) {
1479                 return false;
1480         }
1481         return true;
1482 }
1483
1484 void tegra_dc_enable(struct tegra_dc *dc)
1485 {
1486         mutex_lock(&dc->lock);
1487
1488         if (!dc->enabled)
1489                 dc->enabled = _tegra_dc_enable(dc);
1490
1491         mutex_unlock(&dc->lock);
1492         print_mode_info(dc, dc->mode);
1493 }
1494
1495 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1496 {
1497         unsigned i;
1498
1499         tegra_dc_hold_dc_out(dc);
1500
1501         if (dc->out && dc->out->prepoweroff)
1502                 dc->out->prepoweroff();
1503
1504         if (dc->out_ops && dc->out_ops->disable)
1505                 dc->out_ops->disable(dc);
1506
1507         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1508
1509         disable_irq_nosync(dc->irq);
1510
1511         tegra_dc_clear_bandwidth(dc);
1512         if (dc->out_ops->release) /* ugly hack */
1513                 tegra_dc_release_dc_out(dc);
1514         else
1515                 tegra_dc_clk_disable(dc);
1516
1517         if (dc->out && dc->out->disable)
1518                 dc->out->disable();
1519
1520         for (i = 0; i < dc->n_windows; i++) {
1521                 struct tegra_dc_win *w = &dc->windows[i];
1522
1523                 /* reset window bandwidth */
1524                 w->bandwidth = 0;
1525                 w->new_bandwidth = 0;
1526
1527                 /* disable windows */
1528                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1529
1530                 /* flush any pending syncpt waits */
1531                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1532                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1533                                 dc->syncpt[i].id);
1534                         dc->syncpt[i].min++;
1535                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1536                 }
1537         }
1538         trace_printk("%s:disabled\n", dc->ndev->name);
1539 }
1540
1541 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1542 {
1543 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1544         u32 val;
1545         if (dc->enabled)  {
1546                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1547                 if (enable)
1548                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1549                 else
1550                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1551                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1552         }
1553 #endif
1554 }
1555
1556 bool tegra_dc_stats_get(struct tegra_dc *dc)
1557 {
1558 #if 0 /* right now it is always enabled */
1559         u32 val;
1560         bool res;
1561
1562         if (dc->enabled)  {
1563                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1564                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1565         } else {
1566                 res = false;
1567         }
1568
1569         return res;
1570 #endif
1571         return true;
1572 }
1573
1574 /* make the screen blank by disabling all windows */
1575 void tegra_dc_blank(struct tegra_dc *dc)
1576 {
1577         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1578         unsigned i;
1579
1580         for (i = 0; i < DC_N_WINDOWS; i++) {
1581                 dcwins[i] = tegra_dc_get_window(dc, i);
1582                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1583         }
1584
1585         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1586         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1587 }
1588
1589 static void _tegra_dc_disable(struct tegra_dc *dc)
1590 {
1591         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1592                 mutex_lock(&dc->one_shot_lock);
1593                 cancel_delayed_work_sync(&dc->one_shot_work);
1594         }
1595
1596         tegra_dc_io_start(dc);
1597         _tegra_dc_controller_disable(dc);
1598         tegra_dc_io_end(dc);
1599
1600         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1601                 mutex_unlock(&dc->one_shot_lock);
1602 }
1603
1604 void tegra_dc_disable(struct tegra_dc *dc)
1605 {
1606         tegra_dc_ext_disable(dc->ext);
1607
1608         /* it's important that new underflow work isn't scheduled before the
1609          * lock is acquired. */
1610         cancel_delayed_work_sync(&dc->underflow_work);
1611
1612         mutex_lock(&dc->lock);
1613
1614         if (dc->enabled) {
1615                 dc->enabled = false;
1616
1617                 if (!dc->suspended)
1618                         _tegra_dc_disable(dc);
1619         }
1620
1621 #ifdef CONFIG_SWITCH
1622         switch_set_state(&dc->modeset_switch, 0);
1623 #endif
1624
1625         mutex_unlock(&dc->lock);
1626         synchronize_irq(dc->irq);
1627         print_mode_info(dc, dc->mode);
1628 }
1629
1630 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1631 static void tegra_dc_reset_worker(struct work_struct *work)
1632 {
1633         struct tegra_dc *dc =
1634                 container_of(work, struct tegra_dc, reset_work);
1635
1636         unsigned long val = 0;
1637
1638         mutex_lock(&shared_lock);
1639
1640         dev_warn(&dc->ndev->dev,
1641                 "overlay stuck in underflow state.  resetting.\n");
1642
1643         tegra_dc_ext_disable(dc->ext);
1644
1645         mutex_lock(&dc->lock);
1646
1647         if (dc->enabled == false)
1648                 goto unlock;
1649
1650         dc->enabled = false;
1651
1652         /*
1653          * off host read bus
1654          */
1655         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1656         val &= ~(0x00000100);
1657         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1658
1659         /*
1660          * set DC to STOP mode
1661          */
1662         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1663
1664         msleep(10);
1665
1666         _tegra_dc_controller_disable(dc);
1667
1668         /* _tegra_dc_controller_reset_enable deasserts reset */
1669         _tegra_dc_controller_reset_enable(dc);
1670
1671         dc->enabled = true;
1672
1673         /* reopen host read bus */
1674         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1675         val &= ~(0x00000100);
1676         val |= 0x100;
1677         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1678
1679 unlock:
1680         mutex_unlock(&dc->lock);
1681         mutex_unlock(&shared_lock);
1682         trace_printk("%s:reset complete\n", dc->ndev->name);
1683 }
1684 #endif
1685
1686 static void tegra_dc_underflow_worker(struct work_struct *work)
1687 {
1688         struct tegra_dc *dc = container_of(
1689                 to_delayed_work(work), struct tegra_dc, underflow_work);
1690
1691         mutex_lock(&dc->lock);
1692         tegra_dc_io_start(dc);
1693         tegra_dc_hold_dc_out(dc);
1694
1695         if (dc->enabled) {
1696                 tegra_dc_underflow_handler(dc);
1697         }
1698         tegra_dc_release_dc_out(dc);
1699         tegra_dc_io_end(dc);
1700         mutex_unlock(&dc->lock);
1701 }
1702
1703 #ifdef CONFIG_SWITCH
1704 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1705 {
1706         struct tegra_dc *dc =
1707                 container_of(sdev, struct tegra_dc, modeset_switch);
1708
1709         if (!sdev->state)
1710                 return sprintf(buf, "offline\n");
1711
1712         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1713 }
1714 #endif
1715
1716 static int tegra_dc_probe(struct nvhost_device *ndev,
1717         struct nvhost_device_id *id_table)
1718 {
1719         struct tegra_dc *dc;
1720         struct tegra_dc_mode *mode;
1721         struct clk *clk;
1722         struct clk *emc_clk;
1723         struct resource *res;
1724         struct resource *base_res;
1725         struct resource *fb_mem = NULL;
1726         int ret = 0;
1727         void __iomem *base;
1728         int irq;
1729         int i;
1730
1731         if (!ndev->dev.platform_data) {
1732                 dev_err(&ndev->dev, "no platform data\n");
1733                 return -ENOENT;
1734         }
1735
1736         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1737         if (!dc) {
1738                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1739                 return -ENOMEM;
1740         }
1741
1742         irq = nvhost_get_irq_byname(ndev, "irq");
1743         if (irq <= 0) {
1744                 dev_err(&ndev->dev, "no irq\n");
1745                 ret = -ENOENT;
1746                 goto err_free;
1747         }
1748
1749         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1750         if (!res) {
1751                 dev_err(&ndev->dev, "no mem resource\n");
1752                 ret = -ENOENT;
1753                 goto err_free;
1754         }
1755
1756         base_res = request_mem_region(res->start, resource_size(res),
1757                 ndev->name);
1758         if (!base_res) {
1759                 dev_err(&ndev->dev, "request_mem_region failed\n");
1760                 ret = -EBUSY;
1761                 goto err_free;
1762         }
1763
1764         base = ioremap(res->start, resource_size(res));
1765         if (!base) {
1766                 dev_err(&ndev->dev, "registers can't be mapped\n");
1767                 ret = -EBUSY;
1768                 goto err_release_resource_reg;
1769         }
1770
1771         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1772
1773         clk = clk_get(&ndev->dev, NULL);
1774         if (IS_ERR_OR_NULL(clk)) {
1775                 dev_err(&ndev->dev, "can't get clock\n");
1776                 ret = -ENOENT;
1777                 goto err_iounmap_reg;
1778         }
1779
1780         emc_clk = clk_get(&ndev->dev, "emc");
1781         if (IS_ERR_OR_NULL(emc_clk)) {
1782                 dev_err(&ndev->dev, "can't get emc clock\n");
1783                 ret = -ENOENT;
1784                 goto err_put_clk;
1785         }
1786
1787         dc->clk = clk;
1788         dc->emc_clk = emc_clk;
1789         dc->shift_clk_div = 1;
1790         /* Initialize one shot work delay, it will be assigned by dsi
1791          * according to refresh rate later. */
1792         dc->one_shot_delay_ms = 40;
1793
1794         dc->base_res = base_res;
1795         dc->base = base;
1796         dc->irq = irq;
1797         dc->ndev = ndev;
1798         dc->pdata = ndev->dev.platform_data;
1799
1800         /*
1801          * The emc is a shared clock, it will be set based on
1802          * the requirements for each user on the bus.
1803          */
1804         dc->emc_clk_rate = 0;
1805
1806         mutex_init(&dc->lock);
1807         mutex_init(&dc->one_shot_lock);
1808         init_completion(&dc->frame_end_complete);
1809         init_waitqueue_head(&dc->wq);
1810 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1811         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
1812 #endif
1813         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
1814         dc->vblank_ref_count = 0;
1815         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
1816         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
1817
1818         tegra_dc_init_lut_defaults(&dc->fb_lut);
1819
1820         dc->n_windows = DC_N_WINDOWS;
1821         for (i = 0; i < dc->n_windows; i++) {
1822                 struct tegra_dc_win *win = &dc->windows[i];
1823                 win->idx = i;
1824                 win->dc = dc;
1825                 tegra_dc_init_csc_defaults(&win->csc);
1826                 tegra_dc_init_lut_defaults(&win->lut);
1827         }
1828
1829         ret = tegra_dc_set(dc, ndev->id);
1830         if (ret < 0) {
1831                 dev_err(&ndev->dev, "can't add dc\n");
1832                 goto err_free_irq;
1833         }
1834
1835         nvhost_set_drvdata(ndev, dc);
1836
1837 #ifdef CONFIG_SWITCH
1838         dc->modeset_switch.name = dev_name(&ndev->dev);
1839         dc->modeset_switch.state = 0;
1840         dc->modeset_switch.print_state = switch_modeset_print_mode;
1841         switch_dev_register(&dc->modeset_switch);
1842 #endif
1843
1844         tegra_dc_feature_register(dc);
1845
1846         if (dc->pdata->default_out)
1847                 tegra_dc_set_out(dc, dc->pdata->default_out);
1848         else
1849                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
1850
1851         dc->vblank_syncpt = (dc->ndev->id == 0) ?
1852                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
1853
1854         dc->ext = tegra_dc_ext_register(ndev, dc);
1855         if (IS_ERR_OR_NULL(dc->ext)) {
1856                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
1857                 dc->ext = NULL;
1858         }
1859
1860         /* interrupt handler must be registered before tegra_fb_register() */
1861         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
1862                         dev_name(&ndev->dev), dc)) {
1863                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
1864                 ret = -EBUSY;
1865                 goto err_put_emc_clk;
1866         }
1867         disable_dc_irq(dc);
1868
1869         mutex_lock(&dc->lock);
1870         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
1871                 _tegra_dc_set_default_videomode(dc);
1872                 dc->enabled = _tegra_dc_enable(dc);
1873         }
1874         mutex_unlock(&dc->lock);
1875
1876         tegra_dc_create_debugfs(dc);
1877
1878         dev_info(&ndev->dev, "probed\n");
1879
1880         if (dc->pdata->fb) {
1881                 if (dc->pdata->fb->bits_per_pixel == -1) {
1882                         unsigned long fmt;
1883                         tegra_dc_writel(dc,
1884                                         WINDOW_A_SELECT << dc->pdata->fb->win,
1885                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1886
1887                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
1888                         dc->pdata->fb->bits_per_pixel =
1889                                 tegra_dc_fmt_bpp(fmt);
1890                 }
1891
1892                 mode = tegra_dc_get_override_mode(dc);
1893                 if (mode) {
1894                         dc->pdata->fb->xres = mode->h_active;
1895                         dc->pdata->fb->yres = mode->v_active;
1896                 }
1897
1898                 tegra_dc_io_start(dc);
1899                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
1900                 if (IS_ERR_OR_NULL(dc->fb))
1901                         dc->fb = NULL;
1902                 tegra_dc_io_end(dc);
1903         }
1904
1905         if (dc->out && dc->out->hotplug_init)
1906                 dc->out->hotplug_init();
1907
1908         if (dc->out_ops && dc->out_ops->detect)
1909                 dc->out_ops->detect(dc);
1910         else
1911                 dc->connected = true;
1912
1913         tegra_dc_create_sysfs(&dc->ndev->dev);
1914
1915         return 0;
1916
1917 err_free_irq:
1918         free_irq(irq, dc);
1919 err_put_emc_clk:
1920         clk_put(emc_clk);
1921 err_put_clk:
1922         clk_put(clk);
1923 err_iounmap_reg:
1924         iounmap(base);
1925         if (fb_mem)
1926                 release_resource(fb_mem);
1927 err_release_resource_reg:
1928         release_resource(base_res);
1929 err_free:
1930         kfree(dc);
1931
1932         return ret;
1933 }
1934
1935 static int tegra_dc_remove(struct nvhost_device *ndev)
1936 {
1937         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1938
1939         tegra_dc_remove_sysfs(&dc->ndev->dev);
1940         tegra_dc_remove_debugfs(dc);
1941
1942         if (dc->fb) {
1943                 tegra_fb_unregister(dc->fb);
1944                 if (dc->fb_mem)
1945                         release_resource(dc->fb_mem);
1946         }
1947
1948         tegra_dc_ext_disable(dc->ext);
1949
1950         if (dc->ext)
1951                 tegra_dc_ext_unregister(dc->ext);
1952
1953         mutex_lock(&dc->lock);
1954         if (dc->enabled)
1955                 _tegra_dc_disable(dc);
1956         dc->enabled = false;
1957         mutex_unlock(&dc->lock);
1958         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
1959
1960 #ifdef CONFIG_SWITCH
1961         switch_dev_unregister(&dc->modeset_switch);
1962 #endif
1963         free_irq(dc->irq, dc);
1964         clk_put(dc->emc_clk);
1965         clk_put(dc->clk);
1966         iounmap(dc->base);
1967         if (dc->fb_mem)
1968                 release_resource(dc->base_res);
1969         kfree(dc);
1970         tegra_dc_set(NULL, ndev->id);
1971         return 0;
1972 }
1973
1974 #ifdef CONFIG_PM
1975 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
1976 {
1977         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
1978
1979         trace_printk("%s:suspend\n", dc->ndev->name);
1980         dev_info(&ndev->dev, "suspend\n");
1981
1982         tegra_dc_ext_disable(dc->ext);
1983
1984         mutex_lock(&dc->lock);
1985         tegra_dc_io_start(dc);
1986
1987         if (dc->out_ops && dc->out_ops->suspend)
1988                 dc->out_ops->suspend(dc);
1989
1990         if (dc->enabled) {
1991                 _tegra_dc_disable(dc);
1992
1993                 dc->suspended = true;
1994         }
1995
1996         if (dc->out && dc->out->postsuspend) {
1997                 dc->out->postsuspend();
1998                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
1999                         /*
2000                          * avoid resume event due to voltage falling
2001                          */
2002                         msleep(100);
2003         }
2004
2005         tegra_dc_io_end(dc);
2006         mutex_unlock(&dc->lock);
2007         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2008
2009         return 0;
2010 }
2011
2012 static int tegra_dc_resume(struct nvhost_device *ndev)
2013 {
2014         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2015
2016         trace_printk("%s:resume\n", dc->ndev->name);
2017         dev_info(&ndev->dev, "resume\n");
2018
2019         mutex_lock(&dc->lock);
2020         dc->suspended = false;
2021
2022         if (dc->enabled) {
2023                 dc->enabled = false;
2024                 _tegra_dc_set_default_videomode(dc);
2025                 dc->enabled = _tegra_dc_enable(dc);
2026         }
2027
2028         if (dc->out && dc->out->hotplug_init)
2029                 dc->out->hotplug_init();
2030
2031         if (dc->out_ops && dc->out_ops->resume)
2032                 dc->out_ops->resume(dc);
2033         mutex_unlock(&dc->lock);
2034
2035         return 0;
2036 }
2037
2038 #endif /* CONFIG_PM */
2039
2040 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2041 {
2042         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2043
2044         if (!dc || !dc->enabled)
2045                 return;
2046
2047         tegra_dc_blank(dc);
2048         tegra_dc_disable(dc);
2049 }
2050
2051 extern int suspend_set(const char *val, struct kernel_param *kp)
2052 {
2053         if (!strcmp(val, "dump"))
2054                 dump_regs(tegra_dcs[0]);
2055 #ifdef CONFIG_PM
2056         else if (!strcmp(val, "suspend"))
2057                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2058         else if (!strcmp(val, "resume"))
2059                 tegra_dc_resume(tegra_dcs[0]->ndev);
2060 #endif
2061
2062         return 0;
2063 }
2064
2065 extern int suspend_get(char *buffer, struct kernel_param *kp)
2066 {
2067         return 0;
2068 }
2069
2070 int suspend;
2071
2072 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2073
2074 struct nvhost_driver tegra_dc_driver = {
2075         .driver = {
2076                 .name = "tegradc",
2077                 .owner = THIS_MODULE,
2078         },
2079         .probe = tegra_dc_probe,
2080         .remove = tegra_dc_remove,
2081 #ifdef CONFIG_PM
2082         .suspend = tegra_dc_suspend,
2083         .resume = tegra_dc_resume,
2084 #endif
2085         .shutdown = tegra_dc_shutdown,
2086 };
2087
2088 #ifndef MODULE
2089 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2090 {
2091         int i, params[11];
2092         char *p;
2093
2094         for (i = 0; i < ARRAY_SIZE(params); i++) {
2095                 if ((p = strsep(&options, ",")) != NULL) {
2096                         if (*p)
2097                                 params[i] = simple_strtoul(p, &p, 10);
2098                 } else
2099                         return -EINVAL;
2100         }
2101
2102         if ((mode->pclk = params[0]) == 0)
2103                 return -EINVAL;
2104
2105         mode->h_active      = params[1];
2106         mode->v_active      = params[2];
2107         mode->h_ref_to_sync = params[3];
2108         mode->v_ref_to_sync = params[4];
2109         mode->h_sync_width  = params[5];
2110         mode->v_sync_width  = params[6];
2111         mode->h_back_porch  = params[7];
2112         mode->v_back_porch  = params[8];
2113         mode->h_front_porch = params[9];
2114         mode->v_front_porch = params[10];
2115
2116         return 0;
2117 }
2118
2119 static int __init tegra_dc_mode_override(char *str)
2120 {
2121         char *p = str, *options;
2122
2123         if (!p || !*p)
2124                 return -EINVAL;
2125
2126         p = strstr(str, "hdmi:");
2127         if (p) {
2128                 p += 5;
2129                 options = strsep(&p, ";");
2130                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2131                         return -EINVAL;
2132         }
2133
2134         p = strstr(str, "rgb:");
2135         if (p) {
2136                 p += 4;
2137                 options = strsep(&p, ";");
2138                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2139                         return -EINVAL;
2140         }
2141
2142         p = strstr(str, "dsi:");
2143         if (p) {
2144                 p += 4;
2145                 options = strsep(&p, ";");
2146                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2147                         return -EINVAL;
2148         }
2149
2150         return 0;
2151 }
2152
2153 __setup("disp_params=", tegra_dc_mode_override);
2154 #endif
2155
2156 static int __init tegra_dc_module_init(void)
2157 {
2158         int ret = tegra_dc_ext_module_init();
2159         if (ret)
2160                 return ret;
2161         return nvhost_driver_register(&tegra_dc_driver);
2162 }
2163
2164 static void __exit tegra_dc_module_exit(void)
2165 {
2166         nvhost_driver_unregister(&tegra_dc_driver);
2167         tegra_dc_ext_module_exit();
2168 }
2169
2170 module_exit(tegra_dc_module_exit);
2171 module_init(tegra_dc_module_init);