115e33f16df064bba41b7075fa6b5ca565105eec
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
38 #ifdef CONFIG_SWITCH
39 #include <linux/switch.h>
40 #endif
41
42
43 #include <mach/clk.h>
44 #include <mach/dc.h>
45 #include <mach/fb.h>
46 #include <mach/mc.h>
47 #include <linux/nvhost.h>
48 #include <mach/latency_allowance.h>
49
50 #include "dc_reg.h"
51 #include "dc_priv.h"
52 #include "overlay.h"
53 #include "nvsd.h"
54
55 #define TEGRA_CRC_LATCHED_DELAY         34
56
57 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
58 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
59
60 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
61 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
62 #else
63 /* ignore underflows when on simulation and fpga platform */
64 #define ALL_UF_INT (0)
65 #endif
66
67 static int no_vsync;
68
69 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
70
71 static int use_dynamic_emc = 1;
72
73 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
74
75 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
76
77 DEFINE_MUTEX(tegra_dc_lock);
78 DEFINE_MUTEX(shared_lock);
79
80 static const struct {
81         bool h;
82         bool v;
83 } can_filter[] = {
84         /* Window A has no filtering */
85         { false, false },
86         /* Window B has both H and V filtering */
87         { true,  true  },
88         /* Window C has only H filtering */
89         { false, true  },
90 };
91 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
92 {
93         return can_filter[win->idx].v &&
94                 win->h.full != dfixed_const(win->out_h);
95 }
96 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
97 {
98         return can_filter[win->idx].h &&
99                 win->w.full != dfixed_const(win->out_w);
100 }
101
102 static inline int tegra_dc_fmt_bpp(int fmt)
103 {
104         switch (fmt) {
105         case TEGRA_WIN_FMT_P1:
106                 return 1;
107
108         case TEGRA_WIN_FMT_P2:
109                 return 2;
110
111         case TEGRA_WIN_FMT_P4:
112                 return 4;
113
114         case TEGRA_WIN_FMT_P8:
115                 return 8;
116
117         case TEGRA_WIN_FMT_B4G4R4A4:
118         case TEGRA_WIN_FMT_B5G5R5A:
119         case TEGRA_WIN_FMT_B5G6R5:
120         case TEGRA_WIN_FMT_AB5G5R5:
121                 return 16;
122
123         case TEGRA_WIN_FMT_B8G8R8A8:
124         case TEGRA_WIN_FMT_R8G8B8A8:
125         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
126         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
127                 return 32;
128
129         /* for planar formats, size of the Y plane, 8bit */
130         case TEGRA_WIN_FMT_YCbCr420P:
131         case TEGRA_WIN_FMT_YUV420P:
132         case TEGRA_WIN_FMT_YCbCr422P:
133         case TEGRA_WIN_FMT_YUV422P:
134         case TEGRA_WIN_FMT_YCbCr422R:
135         case TEGRA_WIN_FMT_YUV422R:
136         case TEGRA_WIN_FMT_YCbCr422RA:
137         case TEGRA_WIN_FMT_YUV422RA:
138                 return 8;
139
140         case TEGRA_WIN_FMT_YCbCr422:
141         case TEGRA_WIN_FMT_YUV422:
142                 /* FIXME: need to know the bpp of these formats */
143                 return 0;
144         }
145         return 0;
146 }
147
148 static inline bool tegra_dc_is_yuv_planar(int fmt)
149 {
150         switch (fmt) {
151         case TEGRA_WIN_FMT_YUV420P:
152         case TEGRA_WIN_FMT_YCbCr420P:
153         case TEGRA_WIN_FMT_YCbCr422P:
154         case TEGRA_WIN_FMT_YUV422P:
155         case TEGRA_WIN_FMT_YCbCr422R:
156         case TEGRA_WIN_FMT_YUV422R:
157         case TEGRA_WIN_FMT_YCbCr422RA:
158         case TEGRA_WIN_FMT_YUV422RA:
159                 return true;
160         }
161         return false;
162 }
163
164 #define DUMP_REG(a) do {                        \
165         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
166                  #a, a, tegra_dc_readl(dc, a));               \
167         print(data, buff);                                    \
168         } while (0)
169
170 static void _dump_regs(struct tegra_dc *dc, void *data,
171                        void (* print)(void *data, const char *str))
172 {
173         int i;
174         char buff[256];
175
176         tegra_dc_io_start(dc);
177         clk_enable(dc->clk);
178
179         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
180         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
181         DUMP_REG(DC_CMD_SIGNAL_RAISE);
182         DUMP_REG(DC_CMD_INT_STATUS);
183         DUMP_REG(DC_CMD_INT_MASK);
184         DUMP_REG(DC_CMD_INT_ENABLE);
185         DUMP_REG(DC_CMD_INT_TYPE);
186         DUMP_REG(DC_CMD_INT_POLARITY);
187         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
188         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
189         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
190         DUMP_REG(DC_CMD_STATE_ACCESS);
191         DUMP_REG(DC_CMD_STATE_CONTROL);
192         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
193         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
194
195         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
196         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
197         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
198         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
199         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
200         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
201         DUMP_REG(DC_DISP_REF_TO_SYNC);
202         DUMP_REG(DC_DISP_SYNC_WIDTH);
203         DUMP_REG(DC_DISP_BACK_PORCH);
204         DUMP_REG(DC_DISP_DISP_ACTIVE);
205         DUMP_REG(DC_DISP_FRONT_PORCH);
206         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
207         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
208         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
209         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
210         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
211         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
212         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
213         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
214         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
215         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
216         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
217         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
218         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
219         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
220         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
221         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
222         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
223         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
224         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
225         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
226         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
227         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
228         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
229         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
230         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
231         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
232         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
233         DUMP_REG(DC_DISP_M0_CONTROL);
234         DUMP_REG(DC_DISP_M1_CONTROL);
235         DUMP_REG(DC_DISP_DI_CONTROL);
236         DUMP_REG(DC_DISP_PP_CONTROL);
237         DUMP_REG(DC_DISP_PP_SELECT_A);
238         DUMP_REG(DC_DISP_PP_SELECT_B);
239         DUMP_REG(DC_DISP_PP_SELECT_C);
240         DUMP_REG(DC_DISP_PP_SELECT_D);
241         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
242         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
243         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
244         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
245         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
246         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
247         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
248         DUMP_REG(DC_DISP_BORDER_COLOR);
249         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
250         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
251         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
252         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
253         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
254         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
255         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
256         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
257         DUMP_REG(DC_DISP_CURSOR_POSITION);
258         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
259         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
260         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
261         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
262         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
263         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
264         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
265         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
266         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
267         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
268         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
269         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
270         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
271
272
273         for (i = 0; i < 3; i++) {
274                 print(data, "\n");
275                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
276                 print(data, buff);
277
278                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
279                                 DC_CMD_DISPLAY_WINDOW_HEADER);
280                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
281                 DUMP_REG(DC_WIN_WIN_OPTIONS);
282                 DUMP_REG(DC_WIN_BYTE_SWAP);
283                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
284                 DUMP_REG(DC_WIN_COLOR_DEPTH);
285                 DUMP_REG(DC_WIN_POSITION);
286                 DUMP_REG(DC_WIN_SIZE);
287                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
288                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
289                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
290                 DUMP_REG(DC_WIN_DDA_INCREMENT);
291                 DUMP_REG(DC_WIN_LINE_STRIDE);
292                 DUMP_REG(DC_WIN_BUF_STRIDE);
293                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
294                 DUMP_REG(DC_WIN_BLEND_NOKEY);
295                 DUMP_REG(DC_WIN_BLEND_1WIN);
296                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
297                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
298                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
299                 DUMP_REG(DC_WINBUF_START_ADDR);
300                 DUMP_REG(DC_WINBUF_START_ADDR_U);
301                 DUMP_REG(DC_WINBUF_START_ADDR_V);
302                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
303                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
304                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
305                 DUMP_REG(DC_WIN_CSC_YOF);
306                 DUMP_REG(DC_WIN_CSC_KYRGB);
307                 DUMP_REG(DC_WIN_CSC_KUR);
308                 DUMP_REG(DC_WIN_CSC_KVR);
309                 DUMP_REG(DC_WIN_CSC_KUG);
310                 DUMP_REG(DC_WIN_CSC_KVG);
311                 DUMP_REG(DC_WIN_CSC_KUB);
312                 DUMP_REG(DC_WIN_CSC_KVB);
313         }
314
315         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
316         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
317         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
318         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
319         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
320         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
321         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
322         DUMP_REG(DC_DISP_M1_CONTROL);
323         DUMP_REG(DC_COM_PM1_CONTROL);
324         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
325         DUMP_REG(DC_DISP_SD_CONTROL);
326
327         clk_disable(dc->clk);
328         tegra_dc_io_end(dc);
329 }
330
331 #undef DUMP_REG
332
333 #ifdef DEBUG
334 static void dump_regs_print(void *data, const char *str)
335 {
336         struct tegra_dc *dc = data;
337         dev_dbg(&dc->ndev->dev, "%s", str);
338 }
339
340 static void dump_regs(struct tegra_dc *dc)
341 {
342         _dump_regs(dc, dc, dump_regs_print);
343 }
344 #else /* !DEBUG */
345
346 static void dump_regs(struct tegra_dc *dc) {}
347
348 #endif /* DEBUG */
349
350 #ifdef CONFIG_DEBUG_FS
351
352 static void dbg_regs_print(void *data, const char *str)
353 {
354         struct seq_file *s = data;
355
356         seq_printf(s, "%s", str);
357 }
358
359 #undef DUMP_REG
360
361 static int dbg_dc_show(struct seq_file *s, void *unused)
362 {
363         struct tegra_dc *dc = s->private;
364
365         _dump_regs(dc, s, dbg_regs_print);
366
367         return 0;
368 }
369
370
371 static int dbg_dc_open(struct inode *inode, struct file *file)
372 {
373         return single_open(file, dbg_dc_show, inode->i_private);
374 }
375
376 static const struct file_operations regs_fops = {
377         .open           = dbg_dc_open,
378         .read           = seq_read,
379         .llseek         = seq_lseek,
380         .release        = single_release,
381 };
382
383 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
384 {
385         struct tegra_dc *dc = s->private;
386         struct tegra_dc_mode *m;
387
388         mutex_lock(&dc->lock);
389         m = &dc->mode;
390         seq_printf(s,
391                 "pclk: %d\n"
392                 "h_ref_to_sync: %d\n"
393                 "v_ref_to_sync: %d\n"
394                 "h_sync_width: %d\n"
395                 "v_sync_width: %d\n"
396                 "h_back_porch: %d\n"
397                 "v_back_porch: %d\n"
398                 "h_active: %d\n"
399                 "v_active: %d\n"
400                 "h_front_porch: %d\n"
401                 "v_front_porch: %d\n"
402                 "stereo_mode: %d\n",
403                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
404                 m->h_sync_width, m->v_sync_width,
405                 m->h_back_porch, m->v_back_porch,
406                 m->h_active, m->v_active,
407                 m->h_front_porch, m->v_front_porch,
408                 m->stereo_mode);
409         mutex_unlock(&dc->lock);
410         return 0;
411 }
412
413 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
414 {
415         return single_open(file, dbg_dc_mode_show, inode->i_private);
416 }
417
418 static const struct file_operations mode_fops = {
419         .open           = dbg_dc_mode_open,
420         .read           = seq_read,
421         .llseek         = seq_lseek,
422         .release        = single_release,
423 };
424
425 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
426 {
427         struct tegra_dc *dc = s->private;
428
429         mutex_lock(&dc->lock);
430         seq_printf(s,
431                 "underflows: %llu\n"
432                 "underflows_a: %llu\n"
433                 "underflows_b: %llu\n"
434                 "underflows_c: %llu\n",
435                 dc->stats.underflows,
436                 dc->stats.underflows_a,
437                 dc->stats.underflows_b,
438                 dc->stats.underflows_c);
439         mutex_unlock(&dc->lock);
440
441         return 0;
442 }
443
444 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
445 {
446         return single_open(file, dbg_dc_stats_show, inode->i_private);
447 }
448
449 static const struct file_operations stats_fops = {
450         .open           = dbg_dc_stats_open,
451         .read           = seq_read,
452         .llseek         = seq_lseek,
453         .release        = single_release,
454 };
455
456 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
457 {
458         if (dc->debugdir)
459                 debugfs_remove_recursive(dc->debugdir);
460         dc->debugdir = NULL;
461 }
462
463 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
464 {
465         struct dentry *retval;
466
467         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
468         if (!dc->debugdir)
469                 goto remove_out;
470
471         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
472                 &regs_fops);
473         if (!retval)
474                 goto remove_out;
475
476         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
477                 &mode_fops);
478         if (!retval)
479                 goto remove_out;
480
481         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
482                 &stats_fops);
483         if (!retval)
484                 goto remove_out;
485
486         return;
487 remove_out:
488         dev_err(&dc->ndev->dev, "could not create debugfs\n");
489         tegra_dc_remove_debugfs(dc);
490 }
491
492 #else /* !CONFIG_DEBUGFS */
493 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
494 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
495 #endif /* CONFIG_DEBUGFS */
496
497 static int tegra_dc_set(struct tegra_dc *dc, int index)
498 {
499         int ret = 0;
500
501         mutex_lock(&tegra_dc_lock);
502         if (index >= TEGRA_MAX_DC) {
503                 ret = -EINVAL;
504                 goto out;
505         }
506
507         if (dc != NULL && tegra_dcs[index] != NULL) {
508                 ret = -EBUSY;
509                 goto out;
510         }
511
512         tegra_dcs[index] = dc;
513
514 out:
515         mutex_unlock(&tegra_dc_lock);
516
517         return ret;
518 }
519
520 unsigned int tegra_dc_has_multiple_dc(void)
521 {
522         unsigned int idx;
523         unsigned int cnt = 0;
524         struct tegra_dc *dc;
525
526         mutex_lock(&tegra_dc_lock);
527         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
528                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
529         mutex_unlock(&tegra_dc_lock);
530
531         return (cnt > 1);
532 }
533
534 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
535 {
536         if (idx < TEGRA_MAX_DC)
537                 return tegra_dcs[idx];
538         else
539                 return NULL;
540 }
541 EXPORT_SYMBOL(tegra_dc_get_dc);
542
543 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
544 {
545         if (win >= dc->n_windows)
546                 return NULL;
547
548         return &dc->windows[win];
549 }
550 EXPORT_SYMBOL(tegra_dc_get_window);
551
552 static int get_topmost_window(u32 *depths, unsigned long *wins)
553 {
554         int idx, best = -1;
555
556         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
557                 if (best == -1 || depths[idx] < depths[best])
558                         best = idx;
559         }
560         clear_bit(best, wins);
561         return best;
562 }
563
564 bool tegra_dc_get_connected(struct tegra_dc *dc)
565 {
566         return dc->connected;
567 }
568 EXPORT_SYMBOL(tegra_dc_get_connected);
569
570 static u32 blend_topwin(u32 flags)
571 {
572         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
573                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
574         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
575                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
576         else
577                 return BLEND(NOKEY, FIX, 0xff, 0xff);
578 }
579
580 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
581 {
582         int other;
583
584         for (other = 0; other < DC_N_WINDOWS; other++) {
585                 if (other != idx && (xy-- == 0))
586                         break;
587         }
588         if (BIT(other) & behind_mask)
589                 return blend_topwin(flags[idx]);
590         else if (flags[other])
591                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
592         else
593                 return BLEND(NOKEY, FIX, 0x00, 0x00);
594 }
595
596 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
597 {
598         unsigned long infront_mask;
599         int first;
600
601         infront_mask = ~(behind_mask | BIT(idx));
602         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
603         first = ffs(infront_mask) - 1;
604
605         if (!infront_mask)
606                 return blend_topwin(flags[idx]);
607         else if (behind_mask && first != -1 && flags[first])
608                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
609         else
610                 return BLEND(NOKEY, FIX, 0x0, 0x0);
611 }
612
613 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
614 {
615         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
616
617         while (mask) {
618                 int idx = get_topmost_window(blend->z, &mask);
619
620                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
621                                 DC_CMD_DISPLAY_WINDOW_HEADER);
622                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
623                                 DC_WIN_BLEND_NOKEY);
624                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
625                                 DC_WIN_BLEND_1WIN);
626                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
627                                 DC_WIN_BLEND_2WIN_X);
628                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
629                                 DC_WIN_BLEND_2WIN_Y);
630                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
631                                 DC_WIN_BLEND_3WIN_XY);
632         }
633 }
634
635 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 {
637         csc->yof   = 0x00f0;
638         csc->kyrgb = 0x012a;
639         csc->kur   = 0x0000;
640         csc->kvr   = 0x0198;
641         csc->kug   = 0x039b;
642         csc->kvg   = 0x032f;
643         csc->kub   = 0x0204;
644         csc->kvb   = 0x0000;
645 }
646
647 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
648 {
649         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
650         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
651         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
652         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
653         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
654         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
655         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
656         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
657 }
658
659 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
660 {
661         mutex_lock(&dc->lock);
662
663         if (!dc->enabled) {
664                 mutex_unlock(&dc->lock);
665                 return -EFAULT;
666         }
667
668         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
669                         DC_CMD_DISPLAY_WINDOW_HEADER);
670
671         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
672
673         mutex_unlock(&dc->lock);
674
675         return 0;
676 }
677 EXPORT_SYMBOL(tegra_dc_update_csc);
678
679 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
680 {
681         int i;
682         for (i = 0; i < 256; i++)
683                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
684 }
685
686 static int tegra_dc_loop_lut(struct tegra_dc *dc,
687                              struct tegra_dc_win *win,
688                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
689 {
690         struct tegra_dc_lut *lut = &win->lut;
691         struct tegra_dc_lut *global_lut = &dc->fb_lut;
692         int i;
693         for (i = 0; i < 256; i++) {
694
695                 u32 r = (u32)lut->r[i];
696                 u32 g = (u32)lut->g[i];
697                 u32 b = (u32)lut->b[i];
698
699                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
700                         r = (u32)global_lut->r[r];
701                         g = (u32)global_lut->g[g];
702                         b = (u32)global_lut->b[b];
703                 }
704
705                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
706                         return 0;
707         }
708         return 1;
709 }
710
711 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
712 {
713         if (rgb != (i | (i<<8) | (i<<16)))
714                 return 0;
715         return 1;
716 }
717
718 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
719 {
720         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
721         return 1;
722 }
723
724 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
725 {
726         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
727
728         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
729
730         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
731                 val |= CP_ENABLE;
732         else
733                 val &= ~CP_ENABLE;
734
735         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
736 }
737
738 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
739 {
740         struct tegra_dc_win *win = &dc->windows[win_idx];
741
742         mutex_lock(&dc->lock);
743
744         if (!dc->enabled) {
745                 mutex_unlock(&dc->lock);
746                 return -EFAULT;
747         }
748
749         if (fbovr > 0)
750                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
751         else if (fbovr == 0)
752                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
753
754         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
755                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
756         else
757                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
758
759         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
760                         DC_CMD_DISPLAY_WINDOW_HEADER);
761
762         tegra_dc_set_lut(dc, win);
763
764         mutex_unlock(&dc->lock);
765
766         return 0;
767 }
768
769 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
770 {
771         if (win_idx > -1)
772                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
773
774         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
775                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
776                 if (err)
777                         return err;
778         }
779
780         return 0;
781 }
782 EXPORT_SYMBOL(tegra_dc_update_lut);
783
784 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
785 {
786         unsigned i;
787         unsigned v0 = 128;
788         unsigned v1 = 0;
789         /* linear horizontal and vertical filters */
790         for (i = 0; i < 16; i++) {
791                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
792                                 DC_WIN_H_FILTER_P(i));
793
794                 tegra_dc_writel(dc, v0,
795                                 DC_WIN_V_FILTER_P(i));
796                 v0 -= 8;
797                 v1 += 8;
798         }
799 }
800
801 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
802         struct tegra_dc_win *w)
803 {
804         /* windows A, B, C for first and second display */
805         static const enum tegra_la_id la_id_tab[2][3] = {
806                 /* first display */
807                 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
808                         TEGRA_LA_DISPLAY_0C },
809                 /* second display */
810                 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
811                         TEGRA_LA_DISPLAY_0CB },
812         };
813         /* window B V-filter tap for first and second display. */
814         static const enum tegra_la_id vfilter_tab[2] = {
815                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
816         };
817         unsigned long bw;
818
819         BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
820         BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
821         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
822
823         bw = w->new_bandwidth;
824
825         /* tegra_dc_get_bandwidth() treats V filter windows as double
826          * bandwidth, but LA has a seperate client for V filter */
827         if (w->idx == 1 && win_use_v_filter(w))
828                 bw /= 2;
829
830         /* our bandwidth is in bytes/sec, but LA takes MBps.
831          * round up bandwidth to 1MBps */
832         bw = bw / 1000000 + 1;
833
834 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
835         tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
836         /* if window B, also set the 1B client for the 2-tap V filter. */
837         if (w->idx == 1)
838                 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
839 #endif
840
841         w->bandwidth = w->new_bandwidth;
842 }
843
844 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
845                                                    struct tegra_dc_win *b)
846 {
847         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
848                 return 0;
849
850         /* because memory access to load the fifo can overlap, only care
851          * if windows overlap vertically */
852         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
853                 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
854 }
855
856 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
857                                                  int n)
858 {
859         unsigned i;
860         unsigned j;
861         unsigned overlap_count;
862         unsigned max_bw = 0;
863
864         WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
865                          "inaccurate.\n");
866
867         /* If we had a large number of windows, we would compute adjacency
868          * graph representing 2 window overlaps, find all cliques in the graph,
869          * assign bandwidth to each clique, and then select the clique with
870          * maximum bandwidth. But because we have at most 3 windows,
871          * implementing proper Bron-Kerbosh algorithm would be an overkill,
872          * brute force will suffice.
873          *
874          * Thus: find maximum bandwidth for either single or a pair of windows
875          * and count number of window pair overlaps. If there are three
876          * pairs, all 3 window overlap.
877          */
878
879         overlap_count = 0;
880         for (i = 0; i < n; i++) {
881                 unsigned int bw1;
882
883                 if (wins[i] == NULL)
884                         continue;
885                 bw1 = wins[i]->new_bandwidth;
886                 if (bw1 > max_bw)
887                         /* Single window */
888                         max_bw = bw1;
889
890                 for (j = i + 1; j < n; j++) {
891                         if (wins[j] == NULL)
892                                 continue;
893                         if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
894                                 unsigned int bw2 = wins[j]->new_bandwidth;
895                                 if (bw1 + bw2 > max_bw)
896                                         /* Window pair overlaps */
897                                         max_bw = bw1 + bw2;
898                                 overlap_count++;
899                         }
900                 }
901         }
902
903         if (overlap_count == 3)
904                 /* All three windows overlap */
905                 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
906                          wins[2]->new_bandwidth;
907
908         return max_bw;
909 }
910
911 /*
912  * Calculate peak EMC bandwidth for each enabled window =
913  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
914  * (windows_tiling ? 2 : 1)
915  *
916  *
917  * note:
918  * (*) We use 2 tap V filter, so need double BW if use V filter
919  * (*) Tiling mode on T30 and DDR3 requires double BW
920  */
921 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
922         struct tegra_dc_win *w)
923 {
924         unsigned long ret;
925         int tiled_windows_bw_multiplier;
926         unsigned long bpp;
927
928         if (!WIN_IS_ENABLED(w))
929                 return 0;
930
931         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
932             w->out_w == 0 || w->out_h == 0)
933                 return 0;
934
935         tiled_windows_bw_multiplier =
936                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
937
938         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
939          * but the size reported by tegra_dc_fmt_bpp for the planar version
940          * is of the luma plane's size only. */
941         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
942                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
943         /* perform calculations with most significant bits of pixel clock
944          * to prevent overflow of long. */
945         ret = (unsigned long)(dc->mode.pclk >> 16) *
946                 bpp / 8 *
947                 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
948                 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
949
950 /*
951  * Assuming 48% efficiency: i.e. if we calculate we need 70MBps, we
952  * will request 147MBps from EMC.
953  */
954         ret = ret * 2 + ret / 10;
955
956         /* if overflowed */
957         if (ret > (1UL << 31))
958                 return ULONG_MAX;
959
960         return ret << 16; /* restore the scaling we did above */
961 }
962
963 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
964 {
965         int i;
966
967         BUG_ON(n > DC_N_WINDOWS);
968
969         /* emc rate and latency allowance both need to know per window
970          * bandwidths */
971         for (i = 0; i < n; i++) {
972                 struct tegra_dc_win *w = windows[i];
973                 if (w)
974                         w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
975         }
976
977         return tegra_dc_find_max_bandwidth(windows, n);
978 }
979
980 /* to save power, call when display memory clients would be idle */
981 static void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
982 {
983         if (dc->emc_clk_rate)
984                 clk_disable(dc->emc_clk);
985         dc->emc_clk_rate = 0;
986 }
987
988 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
989 {
990         unsigned i;
991
992         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
993                 if (!dc->emc_clk_rate) /* going from 0 to non-zero */
994                         clk_enable(dc->emc_clk);
995                 dc->emc_clk_rate = dc->new_emc_clk_rate;
996                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
997         }
998
999         for (i = 0; i < DC_N_WINDOWS; i++) {
1000                 struct tegra_dc_win *w = &dc->windows[i];
1001                 if (w->bandwidth != w->new_bandwidth && w->new_bandwidth != 0)
1002                         tegra_dc_set_latency_allowance(dc, w);
1003         }
1004 }
1005
1006 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
1007 {
1008         unsigned long new_rate;
1009         struct tegra_dc *dc;
1010
1011         if (!use_dynamic_emc)
1012                 return 0;
1013
1014         dc = windows[0]->dc;
1015
1016         /* calculate the new rate based on this POST */
1017         new_rate = tegra_dc_get_bandwidth(windows, n);
1018         new_rate = EMC_BW_TO_FREQ(new_rate);
1019
1020         if (tegra_dc_has_multiple_dc())
1021                 new_rate = ULONG_MAX;
1022
1023         dc->new_emc_clk_rate = new_rate;
1024
1025         return 0;
1026 }
1027
1028 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1029                                   bool v, unsigned Bpp)
1030 {
1031         /*
1032          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1033          *           (post_scaled_size_in_pixels - 1)), MAX)
1034          * Where the value of MAX is as follows:
1035          * For V_DDA_INCREMENT: 15.0 (0xF000)
1036          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1037          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1038          */
1039
1040         fixed20_12 out = dfixed_init(out_int);
1041         u32 dda_inc;
1042         int max;
1043
1044         if (v) {
1045                 max = 15;
1046         } else {
1047                 switch (Bpp) {
1048                 default:
1049                         WARN_ON_ONCE(1);
1050                         /* fallthrough */
1051                 case 4:
1052                         max = 4;
1053                         break;
1054                 case 2:
1055                         max = 8;
1056                         break;
1057                 }
1058         }
1059
1060         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1061         in.full -= dfixed_const(1);
1062
1063         dda_inc = dfixed_div(in, out);
1064
1065         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1066
1067         return dda_inc;
1068 }
1069
1070 static inline u32 compute_initial_dda(fixed20_12 in)
1071 {
1072         return dfixed_frac(in);
1073 }
1074
1075 /* does not support updating windows on multiple dcs in one call */
1076 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1077 {
1078         struct tegra_dc *dc;
1079         unsigned long update_mask = GENERAL_ACT_REQ;
1080         unsigned long val;
1081         bool update_blend = false;
1082         int i;
1083
1084         dc = windows[0]->dc;
1085
1086         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1087                 /* Acquire one_shot_lock to avoid race condition between
1088                  * cancellation of old delayed work and schedule of new
1089                  * delayed work. */
1090                 mutex_lock(&dc->one_shot_lock);
1091                 cancel_delayed_work_sync(&dc->one_shot_work);
1092         }
1093         mutex_lock(&dc->lock);
1094
1095         if (!dc->enabled) {
1096                 mutex_unlock(&dc->lock);
1097                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1098                         mutex_unlock(&dc->one_shot_lock);
1099                 return -EFAULT;
1100         }
1101
1102         if (no_vsync)
1103                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1104         else
1105                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1106
1107         for (i = 0; i < DC_N_WINDOWS; i++) {
1108                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1109                                         DC_CMD_DISPLAY_WINDOW_HEADER);
1110                 tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1111                 if (!no_vsync)
1112                         update_mask |= WIN_A_ACT_REQ << i;
1113         }
1114
1115         for (i = 0; i < n; i++) {
1116                 struct tegra_dc_win *win = windows[i];
1117                 unsigned h_dda;
1118                 unsigned v_dda;
1119                 fixed20_12 h_offset, v_offset;
1120                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1121                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1122                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1123                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1124                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1125                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1126                 const bool filter_h = win_use_h_filter(win);
1127                 const bool filter_v = win_use_v_filter(win);
1128
1129                 if (win->z != dc->blend.z[win->idx]) {
1130                         dc->blend.z[win->idx] = win->z;
1131                         update_blend = true;
1132                 }
1133                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1134                         dc->blend.flags[win->idx]) {
1135                         dc->blend.flags[win->idx] =
1136                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1137                         update_blend = true;
1138                 }
1139
1140                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1141                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1142
1143                 if (!no_vsync)
1144                         update_mask |= WIN_A_ACT_REQ << win->idx;
1145
1146                 if (!WIN_IS_ENABLED(win)) {
1147                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1148                         continue;
1149                 }
1150
1151                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1152                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1153
1154                 tegra_dc_writel(dc,
1155                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1156                                 DC_WIN_POSITION);
1157                 tegra_dc_writel(dc,
1158                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1159                                 DC_WIN_SIZE);
1160                 tegra_dc_writel(dc,
1161                                 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1162                                 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1163                                 DC_WIN_PRESCALED_SIZE);
1164
1165                 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1166                 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1167                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1168                                 DC_WIN_DDA_INCREMENT);
1169                 h_dda = compute_initial_dda(win->x);
1170                 v_dda = compute_initial_dda(win->y);
1171                 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1172                 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1173
1174                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1175                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1176                 tegra_dc_writel(dc,
1177                                 (unsigned long)win->phys_addr,
1178                                 DC_WINBUF_START_ADDR);
1179
1180                 if (!yuvp) {
1181                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1182                 } else {
1183                         tegra_dc_writel(dc,
1184                                         (unsigned long)win->phys_addr_u,
1185                                         DC_WINBUF_START_ADDR_U);
1186                         tegra_dc_writel(dc,
1187                                         (unsigned long)win->phys_addr_v,
1188                                         DC_WINBUF_START_ADDR_V);
1189                         tegra_dc_writel(dc,
1190                                         LINE_STRIDE(win->stride) |
1191                                         UV_LINE_STRIDE(win->stride_uv),
1192                                         DC_WIN_LINE_STRIDE);
1193                 }
1194
1195                 h_offset = win->x;
1196                 if (invert_h) {
1197                         h_offset.full += win->w.full - dfixed_const(1);
1198                 }
1199
1200                 v_offset = win->y;
1201                 if (invert_v) {
1202                         v_offset.full += win->h.full - dfixed_const(1);
1203                 }
1204
1205                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1206                                 DC_WINBUF_ADDR_H_OFFSET);
1207                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1208                                 DC_WINBUF_ADDR_V_OFFSET);
1209
1210                 if (WIN_IS_TILED(win))
1211                         tegra_dc_writel(dc,
1212                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
1213                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1214                                         DC_WIN_BUFFER_ADDR_MODE);
1215                 else
1216                         tegra_dc_writel(dc,
1217                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1218                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1219                                         DC_WIN_BUFFER_ADDR_MODE);
1220
1221                 val = WIN_ENABLE;
1222                 if (yuvp)
1223                         val |= CSC_ENABLE;
1224                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1225                         val |= COLOR_EXPAND;
1226
1227                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1228                         val |= CP_ENABLE;
1229
1230                 if (filter_h)
1231                         val |= H_FILTER_ENABLE;
1232                 if (filter_v)
1233                         val |= V_FILTER_ENABLE;
1234
1235                 if (invert_h)
1236                         val |= H_DIRECTION_DECREMENT;
1237                 if (invert_v)
1238                         val |= V_DIRECTION_DECREMENT;
1239
1240                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1241
1242                 win->dirty = no_vsync ? 0 : 1;
1243
1244                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1245                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1246                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1247                         __func__, win->idx, win->z,
1248                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1249                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1250                         win->out_x, win->out_y, win->out_w, win->out_h,
1251                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1252         }
1253
1254         if (update_blend) {
1255                 tegra_dc_set_blending(dc, &dc->blend);
1256                 for (i = 0; i < DC_N_WINDOWS; i++) {
1257                         if (!no_vsync)
1258                                 dc->windows[i].dirty = 1;
1259                         update_mask |= WIN_A_ACT_REQ << i;
1260                 }
1261         }
1262
1263         tegra_dc_set_dynamic_emc(windows, n);
1264
1265         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1266
1267         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1268         if (!no_vsync) {
1269                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1270                 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1271                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1272         } else {
1273                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1274                 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1275                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1276         }
1277
1278         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1279                 schedule_delayed_work(&dc->one_shot_work,
1280                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1281
1282         /* update EMC clock if calculated bandwidth has changed */
1283         tegra_dc_program_bandwidth(dc);
1284
1285         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1286                 update_mask |= NC_HOST_TRIG;
1287
1288         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1289
1290         mutex_unlock(&dc->lock);
1291         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1292                 mutex_unlock(&dc->one_shot_lock);
1293
1294         return 0;
1295 }
1296 EXPORT_SYMBOL(tegra_dc_update_windows);
1297
1298 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1299 {
1300         return dc->syncpt[i].id;
1301 }
1302 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1303
1304 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1305 {
1306         u32 max;
1307
1308         mutex_lock(&dc->lock);
1309         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1310                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1311         dc->syncpt[i].max = max;
1312         mutex_unlock(&dc->lock);
1313
1314         return max;
1315 }
1316
1317 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1318 {
1319         mutex_lock(&dc->lock);
1320         if ( dc->enabled )
1321                 while (dc->syncpt[i].min < val) {
1322                         dc->syncpt[i].min++;
1323                         nvhost_syncpt_cpu_incr(
1324                                         &nvhost_get_host(dc->ndev)->syncpt,
1325                                         dc->syncpt[i].id);
1326                 }
1327         mutex_unlock(&dc->lock);
1328 }
1329
1330 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1331                                              int n)
1332 {
1333         int i;
1334
1335         for (i = 0; i < n; i++) {
1336                 if (windows[i]->dirty)
1337                         return false;
1338         }
1339
1340         return true;
1341 }
1342
1343 /* does not support syncing windows on multiple dcs in one call */
1344 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1345 {
1346         if (n < 1 || n > DC_N_WINDOWS)
1347                 return -EINVAL;
1348
1349         if (!windows[0]->dc->enabled)
1350                 return -EFAULT;
1351
1352 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1353         /* Don't want to timeout on simulator */
1354         return wait_event_interruptible(windows[0]->dc->wq,
1355                 tegra_dc_windows_are_clean(windows, n));
1356 #else
1357         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1358                                          tegra_dc_windows_are_clean(windows, n),
1359                                          HZ);
1360 #endif
1361 }
1362 EXPORT_SYMBOL(tegra_dc_sync_windows);
1363
1364 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1365 {
1366 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1367         return clk_get_rate(dc->clk);
1368 #else
1369         return 27000000;
1370 #endif
1371 }
1372
1373 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1374 {
1375         unsigned long rate;
1376         unsigned long div;
1377
1378         rate = tegra_dc_clk_get_rate(dc);
1379
1380         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1381
1382         if (div < 2)
1383                 return 0;
1384
1385         return rate * 2 / div;
1386 }
1387
1388 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1389 {
1390         unsigned long rate;
1391         unsigned long div;
1392
1393         rate = clk_get_rate(parent);
1394
1395         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1396
1397         if (div < 2)
1398                 return 0;
1399
1400         return rate * 2 / div;
1401 }
1402
1403 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1404 {
1405         int pclk;
1406
1407         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1408                 unsigned long rate;
1409                 struct clk *parent_clk =
1410                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1411
1412                 if (dc->out->parent_clk_backup &&
1413                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1414                         rate = tegra_dc_pclk_predict_rate(
1415                                 parent_clk, dc->mode.pclk);
1416                         /* use pll_d as last resort */
1417                         if (rate < (dc->mode.pclk / 100 * 99) ||
1418                             rate > (dc->mode.pclk / 100 * 109))
1419                                 parent_clk = clk_get_sys(
1420                                         NULL, dc->out->parent_clk_backup);
1421                 }
1422
1423                 if (clk_get_parent(clk) != parent_clk)
1424                         clk_set_parent(clk, parent_clk);
1425
1426                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1427                         struct clk *base_clk = clk_get_parent(parent_clk);
1428
1429                         /* Assuming either pll_d or pll_d2 is used */
1430                         rate = dc->mode.pclk * 2;
1431
1432                         if (rate != clk_get_rate(base_clk))
1433                                 clk_set_rate(base_clk, rate);
1434                 }
1435         }
1436
1437         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1438                 unsigned long rate;
1439                 struct clk *parent_clk =
1440                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1441                 struct clk *base_clk = clk_get_parent(parent_clk);
1442
1443                 /* needs to match tegra_dc_hdmi_supported_modes[]
1444                 and tegra_pll_d_freq_table[] */
1445                 if (dc->mode.pclk > 70000000)
1446                         rate = 594000000;
1447                 else if (dc->mode.pclk > 25200000)
1448                         rate = 216000000;
1449                 else
1450                         rate = 504000000;
1451
1452                 if (rate != clk_get_rate(base_clk))
1453                         clk_set_rate(base_clk, rate);
1454
1455                 if (clk_get_parent(clk) != parent_clk)
1456                         clk_set_parent(clk, parent_clk);
1457         }
1458
1459         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1460                 unsigned long rate;
1461                 struct clk *parent_clk;
1462                 struct clk *base_clk;
1463
1464                 if (clk == dc->clk) {
1465                         parent_clk = clk_get_sys(NULL,
1466                                         dc->out->parent_clk ? : "pll_d_out0");
1467                         base_clk = clk_get_parent(parent_clk);
1468                         tegra_clk_cfg_ex(base_clk,
1469                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1470                 } else {
1471                         if (dc->pdata->default_out->dsi->dsi_instance) {
1472                                 parent_clk = clk_get_sys(NULL,
1473                                         dc->out->parent_clk ? : "pll_d2_out0");
1474                                 base_clk = clk_get_parent(parent_clk);
1475                                 tegra_clk_cfg_ex(base_clk,
1476                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1477                         } else {
1478                                 parent_clk = clk_get_sys(NULL,
1479                                         dc->out->parent_clk ? : "pll_d_out0");
1480                                 base_clk = clk_get_parent(parent_clk);
1481                                 tegra_clk_cfg_ex(base_clk,
1482                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1483                         }
1484                 }
1485
1486                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1487                 if (rate != clk_get_rate(base_clk))
1488                         clk_set_rate(base_clk, rate);
1489
1490                 if (clk_get_parent(clk) != parent_clk)
1491                         clk_set_parent(clk, parent_clk);
1492         }
1493
1494         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1495         tegra_dvfs_set_rate(clk, pclk);
1496 }
1497
1498 /* return non-zero if constraint is violated */
1499 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1500 {
1501         long a, b;
1502
1503         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1504         a = 0;
1505
1506         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1507         b = mode->h_front_porch - 1;
1508
1509         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1510         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1511                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1512         /* check Constraint 1 and 6 */
1513         if (a > b)
1514                 return 1;
1515
1516         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1517         if (mode->h_sync_width < 1)
1518                 return 4;
1519
1520         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1521         if (mode->h_active < 16)
1522                 return 7;
1523
1524         if (href) {
1525                 if (b > a && a % 2)
1526                         *href = a + 1; /* use smallest even value */
1527                 else
1528                         *href = a; /* even or only possible value */
1529         }
1530
1531         return 0;
1532 }
1533
1534 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1535 {
1536         long a;
1537         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1538
1539         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1540         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1541                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1542
1543         /* Constraint 6 */
1544         if (mode->v_front_porch < a + 1)
1545                 a = mode->v_front_porch - 1;
1546
1547         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1548         if (mode->v_sync_width < 1)
1549                 return 4;
1550
1551         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1552         if (mode->v_active < 16)
1553                 return 7;
1554
1555         if (vref)
1556                 *vref = a;
1557         return 0;
1558 }
1559
1560 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1561 {
1562         int ret;
1563         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1564         if (ret)
1565                 return ret;
1566         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1567         if (ret)
1568                 return ret;
1569
1570         return 0;
1571 }
1572
1573 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1574 {
1575         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1576         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1577                 return false;
1578
1579         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1580         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1581                 return false;
1582
1583         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1584          * (vertical blank). */
1585         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1586                 return false;
1587
1588         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1589         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1590                 return false;
1591
1592         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1593         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1594                 return false;
1595
1596         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1597          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1598         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1599                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1600                 return false;
1601
1602         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1603         if (mode->h_active < 16 || mode->v_active < 16)
1604                 return false;
1605
1606         return true;
1607 }
1608
1609 #ifdef DEBUG
1610 /* return in 1000ths of a Hertz */
1611 static int calc_refresh(const struct tegra_dc_mode *m)
1612 {
1613         long h_total, v_total, refresh;
1614         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1615                 m->h_sync_width;
1616         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1617                 m->v_sync_width;
1618         refresh = m->pclk / h_total;
1619         refresh *= 1000;
1620         refresh /= v_total;
1621         return refresh;
1622 }
1623
1624 static void print_mode(struct tegra_dc *dc,
1625                         const struct tegra_dc_mode *mode, const char *note)
1626 {
1627         if (mode) {
1628                 int refresh = calc_refresh(dc, mode);
1629                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1630                         note ? note : "",
1631                         mode->h_active, mode->v_active,
1632                         refresh / 1000, refresh % 1000,
1633                         mode->pclk);
1634         }
1635 }
1636 #else /* !DEBUG */
1637 static inline void print_mode(struct tegra_dc *dc,
1638                         const struct tegra_dc_mode *mode, const char *note) { }
1639 #endif /* DEBUG */
1640
1641 static inline void enable_dc_irq(unsigned int irq)
1642 {
1643 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1644         enable_irq(irq);
1645 #else
1646         /* Always disable DC interrupts on FPGA. */
1647         disable_irq(irq);
1648 #endif
1649 }
1650
1651 static inline void disable_dc_irq(unsigned int irq)
1652 {
1653         disable_irq(irq);
1654 }
1655
1656 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1657 {
1658         unsigned long val;
1659         unsigned long rate;
1660         unsigned long div;
1661         unsigned long pclk;
1662
1663         print_mode(dc, mode, __func__);
1664
1665         /* use default EMC rate when switching modes */
1666         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1667         tegra_dc_program_bandwidth(dc);
1668
1669         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1670         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1671                         DC_DISP_REF_TO_SYNC);
1672         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1673                         DC_DISP_SYNC_WIDTH);
1674         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1675                         DC_DISP_BACK_PORCH);
1676         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1677                         DC_DISP_DISP_ACTIVE);
1678         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1679                         DC_DISP_FRONT_PORCH);
1680
1681         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1682                         DC_DISP_DATA_ENABLE_OPTIONS);
1683
1684         /* TODO: MIPI/CRT/HDMI clock cals */
1685
1686         val = DISP_DATA_FORMAT_DF1P1C;
1687
1688         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1689                 val |= DISP_DATA_ALIGNMENT_MSB;
1690         else
1691                 val |= DISP_DATA_ALIGNMENT_LSB;
1692
1693         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1694                 val |= DISP_DATA_ORDER_RED_BLUE;
1695         else
1696                 val |= DISP_DATA_ORDER_BLUE_RED;
1697
1698         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1699
1700         rate = tegra_dc_clk_get_rate(dc);
1701
1702         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1703         if (pclk < (mode->pclk / 100 * 99) ||
1704             pclk > (mode->pclk / 100 * 109)) {
1705                 dev_err(&dc->ndev->dev,
1706                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1707                         rate, mode->pclk,
1708                         pclk, (mode->pclk / 100 * 99),
1709                         (mode->pclk / 100 * 109));
1710                 return -EINVAL;
1711         }
1712
1713         div = (rate * 2 / pclk) - 2;
1714
1715         tegra_dc_writel(dc, 0x00010001,
1716                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1717         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1718                         DC_DISP_DISP_CLOCK_CONTROL);
1719
1720 #ifdef CONFIG_SWITCH
1721         switch_set_state(&dc->modeset_switch,
1722                          (mode->h_active << 16) | mode->v_active);
1723 #endif
1724
1725         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1726         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1727
1728         return 0;
1729 }
1730
1731
1732 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1733 {
1734         memcpy(&dc->mode, mode, sizeof(dc->mode));
1735
1736         print_mode(dc, mode, __func__);
1737
1738         return 0;
1739 }
1740 EXPORT_SYMBOL(tegra_dc_set_mode);
1741
1742 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1743                 const struct fb_videomode *fbmode, bool stereo_mode)
1744 {
1745         struct tegra_dc_mode mode;
1746
1747         if (!fbmode->pixclock)
1748                 return -EINVAL;
1749
1750         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1751         mode.h_sync_width = fbmode->hsync_len;
1752         mode.v_sync_width = fbmode->vsync_len;
1753         mode.h_back_porch = fbmode->left_margin;
1754         mode.v_back_porch = fbmode->upper_margin;
1755         mode.h_active = fbmode->xres;
1756         mode.v_active = fbmode->yres;
1757         mode.h_front_porch = fbmode->right_margin;
1758         mode.v_front_porch = fbmode->lower_margin;
1759         mode.stereo_mode = stereo_mode;
1760         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1761                 /* HDMI controller requires h_ref=1, v_ref=1 */
1762                 mode.h_ref_to_sync = 1;
1763                 mode.v_ref_to_sync = 1;
1764         } else {
1765                 calc_ref_to_sync(&mode);
1766         }
1767         if (!check_ref_to_sync(&mode)) {
1768                 dev_err(&dc->ndev->dev,
1769                                 "Display timing doesn't meet restrictions.\n");
1770                 return -EINVAL;
1771         }
1772         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1773                 mode.h_active, mode.v_active, mode.pclk,
1774                 mode.h_ref_to_sync, mode.v_ref_to_sync
1775         );
1776
1777 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1778         /* Double the pixel clock and update v_active only for frame packed mode */
1779         if (mode.stereo_mode) {
1780                 mode.pclk *= 2;
1781                 /* total v_active = yres*2 + activespace */
1782                 mode.v_active = fbmode->yres*2 +
1783                                 fbmode->vsync_len +
1784                                 fbmode->upper_margin +
1785                                 fbmode->lower_margin;
1786         }
1787 #endif
1788
1789         mode.flags = 0;
1790
1791         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1792                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1793
1794         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1795                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1796
1797         return tegra_dc_set_mode(dc, &mode);
1798 }
1799 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1800
1801 void
1802 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1803 {
1804         unsigned int ctrl;
1805         unsigned long out_sel;
1806         unsigned long cmd_state;
1807
1808         mutex_lock(&dc->lock);
1809         if (!dc->enabled) {
1810                 mutex_unlock(&dc->lock);
1811                 return;
1812         }
1813
1814         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1815                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1816                 cfg->clk_select);
1817
1818         /* The new value should be effected immediately */
1819         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1820         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1821
1822         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1823                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1824         else
1825                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1826
1827         switch (cfg->which_pwm) {
1828         case TEGRA_PWM_PM0:
1829                 /* Select the LM0 on PM0 */
1830                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1831                 out_sel &= ~(7 << 0);
1832                 out_sel |= (3 << 0);
1833                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1834                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1835                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1836                 break;
1837         case TEGRA_PWM_PM1:
1838                 /* Select the LM1 on PM1 */
1839                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1840                 out_sel &= ~(7 << 4);
1841                 out_sel |= (3 << 4);
1842                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1843                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1844                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1845                 break;
1846         default:
1847                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1848                 break;
1849         }
1850         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1851         mutex_unlock(&dc->lock);
1852 }
1853 EXPORT_SYMBOL(tegra_dc_config_pwm);
1854
1855 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1856                                 const struct tegra_dc_out_pin *pins,
1857                                 const unsigned int n_pins)
1858 {
1859         unsigned int i;
1860
1861         int name;
1862         int pol;
1863
1864         u32 pol1, pol3;
1865
1866         u32 set1, unset1;
1867         u32 set3, unset3;
1868
1869         set1 = set3 = unset1 = unset3 = 0;
1870
1871         for (i = 0; i < n_pins; i++) {
1872                 name = (pins + i)->name;
1873                 pol  = (pins + i)->pol;
1874
1875                 /* set polarity by name */
1876                 switch (name) {
1877                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1878                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1879                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1880                         else
1881                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1882                         break;
1883                 case TEGRA_DC_OUT_PIN_H_SYNC:
1884                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1885                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1886                         else
1887                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1888                         break;
1889                 case TEGRA_DC_OUT_PIN_V_SYNC:
1890                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1891                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1892                         else
1893                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1894                         break;
1895                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1896                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1897                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1898                         else
1899                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1900                         break;
1901                 default:
1902                         printk("Invalid argument in function %s\n",
1903                                __FUNCTION__);
1904                         break;
1905                 }
1906         }
1907
1908         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1909         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1910
1911         pol1 |= set1;
1912         pol1 &= ~unset1;
1913
1914         pol3 |= set3;
1915         pol3 &= ~unset3;
1916
1917         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1918         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1919 }
1920
1921 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1922 {
1923         dc->out = out;
1924
1925         if (out->n_modes > 0)
1926                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1927
1928         switch (out->type) {
1929         case TEGRA_DC_OUT_RGB:
1930                 dc->out_ops = &tegra_dc_rgb_ops;
1931                 break;
1932
1933         case TEGRA_DC_OUT_HDMI:
1934                 dc->out_ops = &tegra_dc_hdmi_ops;
1935                 break;
1936
1937         case TEGRA_DC_OUT_DSI:
1938                 dc->out_ops = &tegra_dc_dsi_ops;
1939                 break;
1940
1941         default:
1942                 dc->out_ops = NULL;
1943                 break;
1944         }
1945
1946         if (dc->out_ops && dc->out_ops->init)
1947                 dc->out_ops->init(dc);
1948
1949 }
1950
1951 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1952 {
1953         if (dc->out)
1954                 return dc->out->height;
1955         else
1956                 return 0;
1957 }
1958 EXPORT_SYMBOL(tegra_dc_get_out_height);
1959
1960 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1961 {
1962         if (dc->out)
1963                 return dc->out->width;
1964         else
1965                 return 0;
1966 }
1967 EXPORT_SYMBOL(tegra_dc_get_out_width);
1968
1969 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1970 {
1971         if (dc->out && dc->out->max_pixclock)
1972                 return dc->out->max_pixclock;
1973         else
1974                 return 0;
1975 }
1976 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1977
1978 void tegra_dc_enable_crc(struct tegra_dc *dc)
1979 {
1980         u32 val;
1981         tegra_dc_io_start(dc);
1982
1983         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1984                 CRC_ENABLE_ENABLE;
1985         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1986         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1987         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1988 }
1989
1990 void tegra_dc_disable_crc(struct tegra_dc *dc)
1991 {
1992         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1993         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1994         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1995
1996         tegra_dc_io_end(dc);
1997 }
1998
1999 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2000 {
2001         int crc = 0;
2002
2003         if(!dc) {
2004                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2005                 goto crc_error;
2006         }
2007
2008         /* TODO: Replace mdelay with code to sync VBlANK, since
2009          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2010         mdelay(TEGRA_CRC_LATCHED_DELAY);
2011
2012         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2013 crc_error:
2014         return crc;
2015 }
2016
2017 static void tegra_dc_vblank(struct work_struct *work)
2018 {
2019         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2020         bool nvsd_updated = false;
2021
2022         mutex_lock(&dc->lock);
2023
2024         /* Update the SD brightness */
2025         if (dc->enabled && dc->out->sd_settings)
2026                 nvsd_updated = nvsd_update_brightness(dc);
2027
2028         mutex_unlock(&dc->lock);
2029
2030         /* Do the actual brightness update outside of the mutex */
2031         if (nvsd_updated && dc->out->sd_settings &&
2032             dc->out->sd_settings->bl_device) {
2033
2034                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2035                 struct backlight_device *bl = platform_get_drvdata(pdev);
2036                 if (bl)
2037                         backlight_update_status(bl);
2038         }
2039 }
2040
2041 /* Must acquire dc lock and dc one-shot lock before invoking this function.
2042  * Acquire dc one-shot lock first and then dc lock. */
2043 void tegra_dc_host_trigger(struct tegra_dc *dc)
2044 {
2045         /* We release the lock here to prevent deadlock between
2046          * cancel_delayed_work_sync and one-shot work. */
2047         mutex_unlock(&dc->lock);
2048
2049         cancel_delayed_work_sync(&dc->one_shot_work);
2050         mutex_lock(&dc->lock);
2051
2052         schedule_delayed_work(&dc->one_shot_work,
2053                                 msecs_to_jiffies(dc->one_shot_delay_ms));
2054         tegra_dc_program_bandwidth(dc);
2055         tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
2056 }
2057
2058 static void tegra_dc_one_shot_worker(struct work_struct *work)
2059 {
2060         struct tegra_dc *dc = container_of(
2061                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2062         mutex_lock(&dc->lock);
2063         /* memory client has gone idle */
2064         tegra_dc_clear_bandwidth(dc);
2065         mutex_unlock(&dc->lock);
2066 }
2067
2068 /* return an arbitrarily large number if count overflow occurs.
2069  * make it a nice base-10 number to show up in stats output */
2070 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2071 {
2072         unsigned count = tegra_dc_readl(dc, reg);
2073         tegra_dc_writel(dc, 0, reg);
2074         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2075 }
2076
2077 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2078 {
2079         u32 val;
2080         int i;
2081
2082         dc->stats.underflows++;
2083         if (dc->underflow_mask & WIN_A_UF_INT)
2084                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2085                         DC_WINBUF_AD_UFLOW_STATUS);
2086         if (dc->underflow_mask & WIN_B_UF_INT)
2087                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2088                         DC_WINBUF_BD_UFLOW_STATUS);
2089         if (dc->underflow_mask & WIN_C_UF_INT)
2090                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2091                         DC_WINBUF_CD_UFLOW_STATUS);
2092
2093         /* Check for any underflow reset conditions */
2094         for (i = 0; i < DC_N_WINDOWS; i++) {
2095                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2096                         dc->windows[i].underflows++;
2097
2098 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2099                         if (dc->windows[i].underflows > 4)
2100                                 schedule_work(&dc->reset_work);
2101 #endif
2102                 } else {
2103                         dc->windows[i].underflows = 0;
2104                 }
2105         }
2106
2107         /* Clear the underflow mask now that we've checked it. */
2108         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2109         dc->underflow_mask = 0;
2110         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2111         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2112 }
2113
2114 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2115 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2116 {
2117 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2118         u32 val;
2119
2120         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2121         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2122             return true;
2123 #endif
2124         return false;
2125 }
2126
2127 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2128 {
2129         u32 val, i;
2130         u32 completed = 0;
2131         u32 dirty = 0;
2132
2133         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2134         for (i = 0; i < DC_N_WINDOWS; i++) {
2135 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2136                 /* FIXME: this is not needed when the simulator
2137                    clears WIN_x_UPDATE bits as in HW */
2138                 dc->windows[i].dirty = 0;
2139                 completed = 1;
2140 #else
2141                 if (!(val & (WIN_A_UPDATE << i))) {
2142                         dc->windows[i].dirty = 0;
2143                         completed = 1;
2144                 } else {
2145                         dirty = 1;
2146                 }
2147 #endif
2148         }
2149
2150         if (!dirty) {
2151                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2152                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2153                         val &= ~V_BLANK_INT;
2154                 else
2155                         val &= ~FRAME_END_INT;
2156                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2157         }
2158
2159         if (completed) {
2160                 if (!dirty) {
2161                         /* With the last completed window, go ahead
2162                            and enable the vblank interrupt for nvsd. */
2163                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2164                         val |= V_BLANK_INT;
2165                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2166                 }
2167
2168                 wake_up(&dc->wq);
2169         }
2170 }
2171
2172 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2173 {
2174         if (status & V_BLANK_INT) {
2175                 /* Sync up windows. */
2176                 tegra_dc_trigger_windows(dc);
2177
2178                 /* Schedule any additional bottom-half vblank actvities. */
2179                 schedule_work(&dc->vblank_work);
2180         }
2181
2182         if (status & FRAME_END_INT) {
2183                 /* Mark the frame_end as complete. */
2184                 if (!completion_done(&dc->frame_end_complete))
2185                         complete(&dc->frame_end_complete);
2186         }
2187 }
2188
2189 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2190 {
2191         if (status & V_BLANK_INT) {
2192                 /* Schedule any additional bottom-half vblank actvities. */
2193                 schedule_work(&dc->vblank_work);
2194
2195                 /* All windows updated. Mask subsequent V_BLANK interrupts */
2196                 if (!tegra_dc_windows_are_dirty(dc)) {
2197                         u32 val;
2198
2199                         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2200                         val &= ~V_BLANK_INT;
2201                         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
2202                 }
2203         }
2204
2205         if (status & FRAME_END_INT) {
2206                 /* Mark the frame_end as complete. */
2207                 if (!completion_done(&dc->frame_end_complete))
2208                         complete(&dc->frame_end_complete);
2209
2210                 tegra_dc_trigger_windows(dc);
2211         }
2212 }
2213 #endif
2214
2215 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2216 {
2217 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2218         struct tegra_dc *dc = ptr;
2219         unsigned long status;
2220         unsigned long underflow_mask;
2221         u32 val;
2222
2223         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2224                 WARN(1, "IRQ when DC not powered!\n");
2225                 tegra_dc_io_start(dc);
2226                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2227                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2228                 tegra_dc_io_end(dc);
2229                 return IRQ_HANDLED;
2230         }
2231
2232         /* clear all status flags except underflow, save those for the worker */
2233         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2234         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2235         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2236         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2237
2238         /*
2239          * Overlays can get thier internal state corrupted during and underflow
2240          * condition.  The only way to fix this state is to reset the DC.
2241          * if we get 4 consecutive frames with underflows, assume we're
2242          * hosed and reset.
2243          */
2244         underflow_mask = status & ALL_UF_INT;
2245
2246         /* Check underflow */
2247         if (underflow_mask) {
2248                 dc->underflow_mask |= underflow_mask;
2249                 schedule_delayed_work(&dc->underflow_work,
2250                         msecs_to_jiffies(1));
2251         }
2252
2253         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2254                 tegra_dc_one_shot_irq(dc, status);
2255         else
2256                 tegra_dc_continuous_irq(dc, status);
2257
2258         return IRQ_HANDLED;
2259 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2260         return IRQ_NONE;
2261 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2262 }
2263
2264 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2265 {
2266         u32 color_control;
2267
2268         switch (dc->out->depth) {
2269         case 3:
2270                 color_control = BASE_COLOR_SIZE111;
2271                 break;
2272
2273         case 6:
2274                 color_control = BASE_COLOR_SIZE222;
2275                 break;
2276
2277         case 8:
2278                 color_control = BASE_COLOR_SIZE332;
2279                 break;
2280
2281         case 9:
2282                 color_control = BASE_COLOR_SIZE333;
2283                 break;
2284
2285         case 12:
2286                 color_control = BASE_COLOR_SIZE444;
2287                 break;
2288
2289         case 15:
2290                 color_control = BASE_COLOR_SIZE555;
2291                 break;
2292
2293         case 16:
2294                 color_control = BASE_COLOR_SIZE565;
2295                 break;
2296
2297         case 18:
2298                 color_control = BASE_COLOR_SIZE666;
2299                 break;
2300
2301         default:
2302                 color_control = BASE_COLOR_SIZE888;
2303                 break;
2304         }
2305
2306         switch (dc->out->dither) {
2307         case TEGRA_DC_DISABLE_DITHER:
2308                 color_control |= DITHER_CONTROL_DISABLE;
2309                 break;
2310         case TEGRA_DC_ORDERED_DITHER:
2311                 color_control |= DITHER_CONTROL_ORDERED;
2312                 break;
2313         case TEGRA_DC_ERRDIFF_DITHER:
2314                 /* The line buffer for error-diffusion dither is limited
2315                  * to 1280 pixels per line. This limits the maximum
2316                  * horizontal active area size to 1280 pixels when error
2317                  * diffusion is enabled.
2318                  */
2319                 BUG_ON(dc->mode.h_active > 1280);
2320                 color_control |= DITHER_CONTROL_ERRDIFF;
2321                 break;
2322         }
2323
2324         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2325 }
2326
2327 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2328 {
2329         u32 syncpt_id;
2330
2331         switch (dc->ndev->id) {
2332         case 0:
2333                 switch (idx) {
2334                 case 0:
2335                         syncpt_id = NVSYNCPT_DISP0_A;
2336                         break;
2337                 case 1:
2338                         syncpt_id = NVSYNCPT_DISP0_B;
2339                         break;
2340                 case 2:
2341                         syncpt_id = NVSYNCPT_DISP0_C;
2342                         break;
2343                 default:
2344                         BUG();
2345                         break;
2346                 }
2347                 break;
2348         case 1:
2349                 switch (idx) {
2350                 case 0:
2351                         syncpt_id = NVSYNCPT_DISP1_A;
2352                         break;
2353                 case 1:
2354                         syncpt_id = NVSYNCPT_DISP1_B;
2355                         break;
2356                 case 2:
2357                         syncpt_id = NVSYNCPT_DISP1_C;
2358                         break;
2359                 default:
2360                         BUG();
2361                         break;
2362                 }
2363                 break;
2364         default:
2365                 BUG();
2366                 break;
2367         }
2368
2369         return syncpt_id;
2370 }
2371
2372 static void tegra_dc_init(struct tegra_dc *dc)
2373 {
2374         int i;
2375
2376         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2377         if (dc->ndev->id == 0) {
2378                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2379                                       TEGRA_MC_PRIO_MED);
2380                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2381                                       TEGRA_MC_PRIO_MED);
2382                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2383                                       TEGRA_MC_PRIO_MED);
2384                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2385                                       TEGRA_MC_PRIO_MED);
2386                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2387                                       TEGRA_MC_PRIO_HIGH);
2388         } else if (dc->ndev->id == 1) {
2389                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2390                                       TEGRA_MC_PRIO_MED);
2391                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2392                                       TEGRA_MC_PRIO_MED);
2393                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2394                                       TEGRA_MC_PRIO_MED);
2395                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2396                                       TEGRA_MC_PRIO_MED);
2397                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2398                                       TEGRA_MC_PRIO_HIGH);
2399         }
2400         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2401                         DC_CMD_CONT_SYNCPT_VSYNC);
2402         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2403         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2404         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2405         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2406
2407         /* enable interrupts for vblank, frame_end and underflows */
2408         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2409                 DC_CMD_INT_ENABLE);
2410         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2411
2412         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2413
2414         tegra_dc_set_color_control(dc);
2415         for (i = 0; i < DC_N_WINDOWS; i++) {
2416                 struct tegra_dc_win *win = &dc->windows[i];
2417                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2418                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2419                 tegra_dc_set_csc(dc, &win->csc);
2420                 tegra_dc_set_lut(dc, win);
2421                 tegra_dc_set_scaling_filter(dc);
2422         }
2423
2424
2425         for (i = 0; i < dc->n_windows; i++) {
2426                 u32 syncpt = get_syncpt(dc, i);
2427
2428                 dc->syncpt[i].id = syncpt;
2429
2430                 dc->syncpt[i].min = dc->syncpt[i].max =
2431                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2432                                         syncpt);
2433         }
2434
2435         print_mode(dc, &dc->mode, __func__);
2436
2437         if (dc->mode.pclk)
2438                 tegra_dc_program_mode(dc, &dc->mode);
2439
2440         /* Initialize SD AFTER the modeset.
2441            nvsd_init handles the sd_settings = NULL case. */
2442         nvsd_init(dc, dc->out->sd_settings);
2443 }
2444
2445 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2446 {
2447         if (dc->out->enable)
2448                 dc->out->enable();
2449
2450         tegra_dc_setup_clk(dc, dc->clk);
2451         clk_enable(dc->clk);
2452
2453         /* do not accept interrupts during initialization */
2454         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2455         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2456
2457         enable_dc_irq(dc->irq);
2458
2459         tegra_dc_init(dc);
2460
2461         if (dc->out_ops && dc->out_ops->enable)
2462                 dc->out_ops->enable(dc);
2463
2464         if (dc->out->postpoweron)
2465                 dc->out->postpoweron();
2466
2467         /* force a full blending update */
2468         dc->blend.z[0] = -1;
2469
2470         tegra_dc_ext_enable(dc->ext);
2471
2472         return true;
2473 }
2474
2475 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2476 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2477 {
2478         if (dc->out->enable)
2479                 dc->out->enable();
2480
2481         tegra_dc_setup_clk(dc, dc->clk);
2482         clk_enable(dc->clk);
2483
2484         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2485                 mutex_lock(&tegra_dcs[1]->lock);
2486                 disable_irq(tegra_dcs[1]->irq);
2487         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2488                 mutex_lock(&tegra_dcs[0]->lock);
2489                 disable_irq(tegra_dcs[0]->irq);
2490         }
2491
2492         msleep(5);
2493         tegra_periph_reset_assert(dc->clk);
2494         msleep(2);
2495 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2496         tegra_periph_reset_deassert(dc->clk);
2497         msleep(1);
2498 #endif
2499
2500         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2501                 enable_dc_irq(tegra_dcs[1]->irq);
2502                 mutex_unlock(&tegra_dcs[1]->lock);
2503         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2504                 enable_dc_irq(tegra_dcs[0]->irq);
2505                 mutex_unlock(&tegra_dcs[0]->lock);
2506         }
2507
2508         enable_dc_irq(dc->irq);
2509
2510         tegra_dc_init(dc);
2511
2512         if (dc->out_ops && dc->out_ops->enable)
2513                 dc->out_ops->enable(dc);
2514
2515         if (dc->out->postpoweron)
2516                 dc->out->postpoweron();
2517
2518         /* force a full blending update */
2519         dc->blend.z[0] = -1;
2520
2521         tegra_dc_ext_enable(dc->ext);
2522
2523         return true;
2524 }
2525 #endif
2526
2527 static bool _tegra_dc_enable(struct tegra_dc *dc)
2528 {
2529         if (dc->mode.pclk == 0)
2530                 return false;
2531
2532         if (!dc->out)
2533                 return false;
2534
2535         tegra_dc_io_start(dc);
2536
2537         return _tegra_dc_controller_enable(dc);
2538 }
2539
2540 void tegra_dc_enable(struct tegra_dc *dc)
2541 {
2542         mutex_lock(&dc->lock);
2543
2544         if (!dc->enabled)
2545                 dc->enabled = _tegra_dc_enable(dc);
2546
2547         mutex_unlock(&dc->lock);
2548 }
2549
2550 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2551 {
2552         unsigned i;
2553
2554         if (dc->out_ops && dc->out_ops->disable)
2555                 dc->out_ops->disable(dc);
2556
2557         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2558         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2559         disable_irq(dc->irq);
2560
2561         tegra_dc_clear_bandwidth(dc);
2562         clk_disable(dc->clk);
2563         tegra_dvfs_set_rate(dc->clk, 0);
2564
2565         if (dc->out && dc->out->disable)
2566                 dc->out->disable();
2567
2568         for (i = 0; i < dc->n_windows; i++) {
2569                 struct tegra_dc_win *w = &dc->windows[i];
2570
2571                 /* reset window bandwidth */
2572                 w->bandwidth = 0;
2573                 w->new_bandwidth = 0;
2574
2575                 /* disable windows */
2576                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2577
2578                 /* flush any pending syncpt waits */
2579                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2580                         dc->syncpt[i].min++;
2581                         nvhost_syncpt_cpu_incr(
2582                                 &nvhost_get_host(dc->ndev)->syncpt,
2583                                 dc->syncpt[i].id);
2584                 }
2585         }
2586 }
2587
2588 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2589 {
2590 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2591         u32 val;
2592         if (dc->enabled)  {
2593                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2594                 if (enable)
2595                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2596                 else
2597                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2598                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2599         }
2600 #endif
2601 }
2602
2603 bool tegra_dc_stats_get(struct tegra_dc *dc)
2604 {
2605 #if 0 /* right now it is always enabled */
2606         u32 val;
2607         bool res;
2608
2609         if (dc->enabled)  {
2610                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2611                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2612         } else {
2613                 res = false;
2614         }
2615
2616         return res;
2617 #endif
2618         return true;
2619 }
2620
2621 /* make the screen blank by disabling all windows */
2622 void tegra_dc_blank(struct tegra_dc *dc)
2623 {
2624         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2625         unsigned i;
2626
2627         for (i = 0; i < DC_N_WINDOWS; i++) {
2628                 dcwins[i] = tegra_dc_get_window(dc, i);
2629                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2630         }
2631
2632         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2633         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2634 }
2635
2636 static void _tegra_dc_disable(struct tegra_dc *dc)
2637 {
2638         _tegra_dc_controller_disable(dc);
2639         tegra_dc_io_end(dc);
2640 }
2641
2642 void tegra_dc_disable(struct tegra_dc *dc)
2643 {
2644         if (dc->overlay)
2645                 tegra_overlay_disable(dc->overlay);
2646
2647         tegra_dc_ext_disable(dc->ext);
2648
2649         /* it's important that new underflow work isn't scheduled before the
2650          * lock is acquired. */
2651         cancel_delayed_work_sync(&dc->underflow_work);
2652         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2653                 mutex_lock(&dc->one_shot_lock);
2654                 cancel_delayed_work_sync(&dc->one_shot_work);
2655         }
2656
2657         mutex_lock(&dc->lock);
2658
2659         if (dc->enabled) {
2660                 dc->enabled = false;
2661
2662                 if (!dc->suspended)
2663                         _tegra_dc_disable(dc);
2664         }
2665
2666 #ifdef CONFIG_SWITCH
2667         switch_set_state(&dc->modeset_switch, 0);
2668 #endif
2669
2670         mutex_unlock(&dc->lock);
2671         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2672                 mutex_unlock(&dc->one_shot_lock);
2673 }
2674
2675 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2676 static void tegra_dc_reset_worker(struct work_struct *work)
2677 {
2678         struct tegra_dc *dc =
2679                 container_of(work, struct tegra_dc, reset_work);
2680
2681         unsigned long val = 0;
2682
2683         mutex_lock(&shared_lock);
2684
2685         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2686
2687         tegra_dc_ext_disable(dc->ext);
2688
2689         mutex_lock(&dc->lock);
2690
2691         if (dc->enabled == false)
2692                 goto unlock;
2693
2694         dc->enabled = false;
2695
2696         /*
2697          * off host read bus
2698          */
2699         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2700         val &= ~(0x00000100);
2701         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2702
2703         /*
2704          * set DC to STOP mode
2705          */
2706         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2707
2708         msleep(10);
2709
2710         _tegra_dc_controller_disable(dc);
2711
2712         /* _tegra_dc_controller_reset_enable deasserts reset */
2713         _tegra_dc_controller_reset_enable(dc);
2714
2715         dc->enabled = true;
2716 unlock:
2717         mutex_unlock(&dc->lock);
2718         mutex_unlock(&shared_lock);
2719 }
2720 #endif
2721
2722 static void tegra_dc_underflow_worker(struct work_struct *work)
2723 {
2724         struct tegra_dc *dc = container_of(
2725                 to_delayed_work(work), struct tegra_dc, underflow_work);
2726
2727         mutex_lock(&dc->lock);
2728         if (dc->enabled) {
2729                 tegra_dc_underflow_handler(dc);
2730         }
2731         mutex_unlock(&dc->lock);
2732 }
2733
2734 #ifdef CONFIG_SWITCH
2735 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2736 {
2737         struct tegra_dc *dc =
2738                 container_of(sdev, struct tegra_dc, modeset_switch);
2739
2740         if (!sdev->state)
2741                 return sprintf(buf, "offline\n");
2742
2743         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2744 }
2745 #endif
2746
2747 static int tegra_dc_probe(struct nvhost_device *ndev)
2748 {
2749         struct tegra_dc *dc;
2750         struct clk *clk;
2751         struct clk *emc_clk;
2752         struct resource *res;
2753         struct resource *base_res;
2754         struct resource *fb_mem = NULL;
2755         int ret = 0;
2756         void __iomem *base;
2757         int irq;
2758         int i;
2759
2760         if (!ndev->dev.platform_data) {
2761                 dev_err(&ndev->dev, "no platform data\n");
2762                 return -ENOENT;
2763         }
2764
2765         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2766         if (!dc) {
2767                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2768                 return -ENOMEM;
2769         }
2770
2771         irq = nvhost_get_irq_byname(ndev, "irq");
2772         if (irq <= 0) {
2773                 dev_err(&ndev->dev, "no irq\n");
2774                 ret = -ENOENT;
2775                 goto err_free;
2776         }
2777
2778         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2779         if (!res) {
2780                 dev_err(&ndev->dev, "no mem resource\n");
2781                 ret = -ENOENT;
2782                 goto err_free;
2783         }
2784
2785         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2786         if (!base_res) {
2787                 dev_err(&ndev->dev, "request_mem_region failed\n");
2788                 ret = -EBUSY;
2789                 goto err_free;
2790         }
2791
2792         base = ioremap(res->start, resource_size(res));
2793         if (!base) {
2794                 dev_err(&ndev->dev, "registers can't be mapped\n");
2795                 ret = -EBUSY;
2796                 goto err_release_resource_reg;
2797         }
2798
2799         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2800
2801         clk = clk_get(&ndev->dev, NULL);
2802         if (IS_ERR_OR_NULL(clk)) {
2803                 dev_err(&ndev->dev, "can't get clock\n");
2804                 ret = -ENOENT;
2805                 goto err_iounmap_reg;
2806         }
2807
2808         emc_clk = clk_get(&ndev->dev, "emc");
2809         if (IS_ERR_OR_NULL(emc_clk)) {
2810                 dev_err(&ndev->dev, "can't get emc clock\n");
2811                 ret = -ENOENT;
2812                 goto err_put_clk;
2813         }
2814
2815         dc->clk = clk;
2816         dc->emc_clk = emc_clk;
2817         dc->shift_clk_div = 1;
2818         /* Initialize one shot work delay, it will be assigned by dsi
2819          * according to refresh rate later. */
2820         dc->one_shot_delay_ms = 40;
2821
2822         dc->base_res = base_res;
2823         dc->base = base;
2824         dc->irq = irq;
2825         dc->ndev = ndev;
2826         dc->pdata = ndev->dev.platform_data;
2827
2828         /*
2829          * The emc is a shared clock, it will be set based on
2830          * the requirements for each user on the bus.
2831          */
2832         dc->emc_clk_rate = 0;
2833
2834         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2835                 dc->enabled = true;
2836
2837         mutex_init(&dc->lock);
2838         mutex_init(&dc->one_shot_lock);
2839         init_completion(&dc->frame_end_complete);
2840         init_waitqueue_head(&dc->wq);
2841 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2842         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2843 #endif
2844         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2845         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2846         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2847
2848         tegra_dc_init_lut_defaults(&dc->fb_lut);
2849
2850         dc->n_windows = DC_N_WINDOWS;
2851         for (i = 0; i < dc->n_windows; i++) {
2852                 struct tegra_dc_win *win = &dc->windows[i];
2853                 win->idx = i;
2854                 win->dc = dc;
2855                 tegra_dc_init_csc_defaults(&win->csc);
2856                 tegra_dc_init_lut_defaults(&win->lut);
2857         }
2858
2859         ret = tegra_dc_set(dc, ndev->id);
2860         if (ret < 0) {
2861                 dev_err(&ndev->dev, "can't add dc\n");
2862                 goto err_free_irq;
2863         }
2864
2865         nvhost_set_drvdata(ndev, dc);
2866
2867 #ifdef CONFIG_SWITCH
2868         dc->modeset_switch.name = dev_name(&ndev->dev);
2869         dc->modeset_switch.state = 0;
2870         dc->modeset_switch.print_state = switch_modeset_print_mode;
2871         switch_dev_register(&dc->modeset_switch);
2872 #endif
2873
2874         if (dc->pdata->default_out)
2875                 tegra_dc_set_out(dc, dc->pdata->default_out);
2876         else
2877                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2878
2879         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2880                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2881
2882         dc->ext = tegra_dc_ext_register(ndev, dc);
2883         if (IS_ERR_OR_NULL(dc->ext)) {
2884                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2885                 dc->ext = NULL;
2886         }
2887
2888         /* interrupt handler must be registered before tegra_fb_register() */
2889         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2890                         dev_name(&ndev->dev), dc)) {
2891                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2892                 ret = -EBUSY;
2893                 goto err_put_emc_clk;
2894         }
2895
2896         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2897         disable_dc_irq(dc->irq);
2898
2899         mutex_lock(&dc->lock);
2900         if (dc->enabled)
2901                 _tegra_dc_enable(dc);
2902         mutex_unlock(&dc->lock);
2903
2904         tegra_dc_create_debugfs(dc);
2905
2906         dev_info(&ndev->dev, "probed\n");
2907
2908         if (dc->pdata->fb) {
2909                 if (dc->pdata->fb->bits_per_pixel == -1) {
2910                         unsigned long fmt;
2911                         tegra_dc_writel(dc,
2912                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2913                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2914
2915                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2916                         dc->pdata->fb->bits_per_pixel =
2917                                 tegra_dc_fmt_bpp(fmt);
2918                 }
2919
2920                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2921                 if (IS_ERR_OR_NULL(dc->fb))
2922                         dc->fb = NULL;
2923         }
2924
2925         if (dc->fb) {
2926                 dc->overlay = tegra_overlay_register(ndev, dc);
2927                 if (IS_ERR_OR_NULL(dc->overlay))
2928                         dc->overlay = NULL;
2929         }
2930
2931         if (dc->out && dc->out->hotplug_init)
2932                 dc->out->hotplug_init();
2933
2934         if (dc->out_ops && dc->out_ops->detect)
2935                 dc->out_ops->detect(dc);
2936         else
2937                 dc->connected = true;
2938
2939         tegra_dc_create_sysfs(&dc->ndev->dev);
2940
2941         return 0;
2942
2943 err_free_irq:
2944         free_irq(irq, dc);
2945 err_put_emc_clk:
2946         clk_put(emc_clk);
2947 err_put_clk:
2948         clk_put(clk);
2949 err_iounmap_reg:
2950         iounmap(base);
2951         if (fb_mem)
2952                 release_resource(fb_mem);
2953 err_release_resource_reg:
2954         release_resource(base_res);
2955 err_free:
2956         kfree(dc);
2957
2958         return ret;
2959 }
2960
2961 static int tegra_dc_remove(struct nvhost_device *ndev)
2962 {
2963         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2964
2965         tegra_dc_remove_sysfs(&dc->ndev->dev);
2966         tegra_dc_remove_debugfs(dc);
2967
2968         if (dc->overlay) {
2969                 tegra_overlay_unregister(dc->overlay);
2970         }
2971
2972         if (dc->fb) {
2973                 tegra_fb_unregister(dc->fb);
2974                 if (dc->fb_mem)
2975                         release_resource(dc->fb_mem);
2976         }
2977
2978         tegra_dc_ext_disable(dc->ext);
2979
2980         if (dc->ext)
2981                 tegra_dc_ext_unregister(dc->ext);
2982
2983         if (dc->enabled)
2984                 _tegra_dc_disable(dc);
2985
2986 #ifdef CONFIG_SWITCH
2987         switch_dev_unregister(&dc->modeset_switch);
2988 #endif
2989         free_irq(dc->irq, dc);
2990         clk_put(dc->emc_clk);
2991         clk_put(dc->clk);
2992         iounmap(dc->base);
2993         if (dc->fb_mem)
2994                 release_resource(dc->base_res);
2995         kfree(dc);
2996         tegra_dc_set(NULL, ndev->id);
2997         return 0;
2998 }
2999
3000 #ifdef CONFIG_PM
3001 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3002 {
3003         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3004
3005         dev_info(&ndev->dev, "suspend\n");
3006
3007         if (dc->overlay)
3008                 tegra_overlay_disable(dc->overlay);
3009
3010         tegra_dc_ext_disable(dc->ext);
3011
3012         mutex_lock(&dc->lock);
3013
3014         if (dc->out_ops && dc->out_ops->suspend)
3015                 dc->out_ops->suspend(dc);
3016
3017         if (dc->enabled) {
3018                 _tegra_dc_disable(dc);
3019
3020                 dc->suspended = true;
3021         }
3022
3023         if (dc->out && dc->out->postsuspend) {
3024                 dc->out->postsuspend();
3025                 msleep(100); /* avoid resume event due to voltage falling */
3026         }
3027
3028         mutex_unlock(&dc->lock);
3029
3030         return 0;
3031 }
3032
3033 static int tegra_dc_resume(struct nvhost_device *ndev)
3034 {
3035         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3036
3037         dev_info(&ndev->dev, "resume\n");
3038
3039         mutex_lock(&dc->lock);
3040         dc->suspended = false;
3041
3042         if (dc->enabled)
3043                 _tegra_dc_enable(dc);
3044
3045         if (dc->out && dc->out->hotplug_init)
3046                 dc->out->hotplug_init();
3047
3048         if (dc->out_ops && dc->out_ops->resume)
3049                 dc->out_ops->resume(dc);
3050         mutex_unlock(&dc->lock);
3051
3052         return 0;
3053 }
3054
3055 #endif /* CONFIG_PM */
3056
3057 extern int suspend_set(const char *val, struct kernel_param *kp)
3058 {
3059         if (!strcmp(val, "dump"))
3060                 dump_regs(tegra_dcs[0]);
3061 #ifdef CONFIG_PM
3062         else if (!strcmp(val, "suspend"))
3063                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3064         else if (!strcmp(val, "resume"))
3065                 tegra_dc_resume(tegra_dcs[0]->ndev);
3066 #endif
3067
3068         return 0;
3069 }
3070
3071 extern int suspend_get(char *buffer, struct kernel_param *kp)
3072 {
3073         return 0;
3074 }
3075
3076 int suspend;
3077
3078 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3079
3080 struct nvhost_driver tegra_dc_driver = {
3081         .driver = {
3082                 .name = "tegradc",
3083                 .owner = THIS_MODULE,
3084         },
3085         .probe = tegra_dc_probe,
3086         .remove = tegra_dc_remove,
3087 #ifdef CONFIG_PM
3088         .suspend = tegra_dc_suspend,
3089         .resume = tegra_dc_resume,
3090 #endif
3091 };
3092
3093 static int __init tegra_dc_module_init(void)
3094 {
3095         int ret = tegra_dc_ext_module_init();
3096         if (ret)
3097                 return ret;
3098         return nvhost_driver_register(&tegra_dc_driver);
3099 }
3100
3101 static void __exit tegra_dc_module_exit(void)
3102 {
3103         nvhost_driver_unregister(&tegra_dc_driver);
3104         tegra_dc_ext_module_exit();
3105 }
3106
3107 module_exit(tegra_dc_module_exit);
3108 module_init(tegra_dc_module_init);