10768ac60aacc5cabce7f0c3592b3816daadcc73
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2011 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37
38 #include <mach/clk.h>
39 #include <mach/dc.h>
40 #include <mach/fb.h>
41 #include <mach/mc.h>
42 #include <mach/nvhost.h>
43
44 #include "dc_reg.h"
45 #include "dc_priv.h"
46 #include "overlay.h"
47 #include "nvsd.h"
48
49 #define TEGRA_CRC_LATCHED_DELAY         34
50
51 static int no_vsync;
52
53 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
54
55 static int use_dynamic_emc = 1;
56
57 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
58
59 /* set default windows idle time as 2000ms for power saving purpose */
60 static int windows_idle_detection_time = 2000;
61
62 module_param_named(windows_idle_detection_time, windows_idle_detection_time,
63                    int, S_IRUGO | S_IWUSR);
64
65 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
66
67 DEFINE_MUTEX(tegra_dc_lock);
68 DEFINE_MUTEX(shared_lock);
69
70 static inline int tegra_dc_fmt_bpp(int fmt)
71 {
72         switch (fmt) {
73         case TEGRA_WIN_FMT_P1:
74                 return 1;
75
76         case TEGRA_WIN_FMT_P2:
77                 return 2;
78
79         case TEGRA_WIN_FMT_P4:
80                 return 4;
81
82         case TEGRA_WIN_FMT_P8:
83                 return 8;
84
85         case TEGRA_WIN_FMT_B4G4R4A4:
86         case TEGRA_WIN_FMT_B5G5R5A:
87         case TEGRA_WIN_FMT_B5G6R5:
88         case TEGRA_WIN_FMT_AB5G5R5:
89                 return 16;
90
91         case TEGRA_WIN_FMT_B8G8R8A8:
92         case TEGRA_WIN_FMT_R8G8B8A8:
93         case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
94         case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
95                 return 32;
96
97         /* for planar formats, size of the Y plane, 8bit */
98         case TEGRA_WIN_FMT_YCbCr420P:
99         case TEGRA_WIN_FMT_YUV420P:
100         case TEGRA_WIN_FMT_YCbCr422P:
101         case TEGRA_WIN_FMT_YUV422P:
102                 return 8;
103
104         case TEGRA_WIN_FMT_YCbCr422:
105         case TEGRA_WIN_FMT_YUV422:
106         case TEGRA_WIN_FMT_YCbCr422R:
107         case TEGRA_WIN_FMT_YUV422R:
108         case TEGRA_WIN_FMT_YCbCr422RA:
109         case TEGRA_WIN_FMT_YUV422RA:
110                 /* FIXME: need to know the bpp of these formats */
111                 return 0;
112         }
113         return 0;
114 }
115
116 static inline bool tegra_dc_is_yuv_planar(int fmt)
117 {
118         switch (fmt) {
119         case TEGRA_WIN_FMT_YUV420P:
120         case TEGRA_WIN_FMT_YCbCr420P:
121         case TEGRA_WIN_FMT_YCbCr422P:
122         case TEGRA_WIN_FMT_YUV422P:
123                 return true;
124         }
125         return false;
126 }
127
128 #define DUMP_REG(a) do {                        \
129         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
130                  #a, a, tegra_dc_readl(dc, a));               \
131         print(data, buff);                                    \
132         } while (0)
133
134 static void _dump_regs(struct tegra_dc *dc, void *data,
135                        void (* print)(void *data, const char *str))
136 {
137         int i;
138         char buff[256];
139
140         tegra_dc_io_start(dc);
141         clk_enable(dc->clk);
142
143         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
144         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
145         DUMP_REG(DC_CMD_SIGNAL_RAISE);
146         DUMP_REG(DC_CMD_INT_STATUS);
147         DUMP_REG(DC_CMD_INT_MASK);
148         DUMP_REG(DC_CMD_INT_ENABLE);
149         DUMP_REG(DC_CMD_INT_TYPE);
150         DUMP_REG(DC_CMD_INT_POLARITY);
151         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
152         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
153         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
154         DUMP_REG(DC_CMD_STATE_ACCESS);
155         DUMP_REG(DC_CMD_STATE_CONTROL);
156         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
157         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
158
159         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
160         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
161         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
162         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
163         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
164         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
165         DUMP_REG(DC_DISP_REF_TO_SYNC);
166         DUMP_REG(DC_DISP_SYNC_WIDTH);
167         DUMP_REG(DC_DISP_BACK_PORCH);
168         DUMP_REG(DC_DISP_DISP_ACTIVE);
169         DUMP_REG(DC_DISP_FRONT_PORCH);
170         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
171         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
172         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
173         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
174         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
175         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
176         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
177         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
178         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
179         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
180         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
181         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
182         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
183         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
184         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
185         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
186         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
187         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
188         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
189         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
190         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
191         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
192         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
193         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
194         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
195         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
196         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
197         DUMP_REG(DC_DISP_M0_CONTROL);
198         DUMP_REG(DC_DISP_M1_CONTROL);
199         DUMP_REG(DC_DISP_DI_CONTROL);
200         DUMP_REG(DC_DISP_PP_CONTROL);
201         DUMP_REG(DC_DISP_PP_SELECT_A);
202         DUMP_REG(DC_DISP_PP_SELECT_B);
203         DUMP_REG(DC_DISP_PP_SELECT_C);
204         DUMP_REG(DC_DISP_PP_SELECT_D);
205         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
206         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
207         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
208         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
209         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
210         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
211         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
212         DUMP_REG(DC_DISP_BORDER_COLOR);
213         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
214         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
215         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
216         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
217         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
218         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
219         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
220         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
221         DUMP_REG(DC_DISP_CURSOR_POSITION);
222         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
223         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
224         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
225         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
226         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
227         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
228         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
229         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
230         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
231         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
232         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
233         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
234         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
235
236
237         for (i = 0; i < 3; i++) {
238                 print(data, "\n");
239                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
240                 print(data, buff);
241
242                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
243                                 DC_CMD_DISPLAY_WINDOW_HEADER);
244                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
245                 DUMP_REG(DC_WIN_WIN_OPTIONS);
246                 DUMP_REG(DC_WIN_BYTE_SWAP);
247                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
248                 DUMP_REG(DC_WIN_COLOR_DEPTH);
249                 DUMP_REG(DC_WIN_POSITION);
250                 DUMP_REG(DC_WIN_SIZE);
251                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
252                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
253                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
254                 DUMP_REG(DC_WIN_DDA_INCREMENT);
255                 DUMP_REG(DC_WIN_LINE_STRIDE);
256                 DUMP_REG(DC_WIN_BUF_STRIDE);
257                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
258                 DUMP_REG(DC_WIN_BLEND_NOKEY);
259                 DUMP_REG(DC_WIN_BLEND_1WIN);
260                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
261                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
262                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
263                 DUMP_REG(DC_WINBUF_START_ADDR);
264                 DUMP_REG(DC_WINBUF_START_ADDR_U);
265                 DUMP_REG(DC_WINBUF_START_ADDR_V);
266                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
267                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
268                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
269                 DUMP_REG(DC_WIN_CSC_YOF);
270                 DUMP_REG(DC_WIN_CSC_KYRGB);
271                 DUMP_REG(DC_WIN_CSC_KUR);
272                 DUMP_REG(DC_WIN_CSC_KVR);
273                 DUMP_REG(DC_WIN_CSC_KUG);
274                 DUMP_REG(DC_WIN_CSC_KVG);
275                 DUMP_REG(DC_WIN_CSC_KUB);
276                 DUMP_REG(DC_WIN_CSC_KVB);
277         }
278
279         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
280         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
281         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
282         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
283         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
284         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
285         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
286         DUMP_REG(DC_DISP_M1_CONTROL);
287         DUMP_REG(DC_COM_PM1_CONTROL);
288         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
289         DUMP_REG(DC_DISP_SD_CONTROL);
290
291         clk_disable(dc->clk);
292         tegra_dc_io_end(dc);
293 }
294
295 #undef DUMP_REG
296
297 #ifdef DEBUG
298 static void dump_regs_print(void *data, const char *str)
299 {
300         struct tegra_dc *dc = data;
301         dev_dbg(&dc->ndev->dev, "%s", str);
302 }
303
304 static void dump_regs(struct tegra_dc *dc)
305 {
306         _dump_regs(dc, dc, dump_regs_print);
307 }
308 #else /* !DEBUG */
309
310 static void dump_regs(struct tegra_dc *dc) {}
311
312 #endif /* DEBUG */
313
314 #ifdef CONFIG_DEBUG_FS
315
316 static void dbg_regs_print(void *data, const char *str)
317 {
318         struct seq_file *s = data;
319
320         seq_printf(s, "%s", str);
321 }
322
323 #undef DUMP_REG
324
325 static int dbg_dc_show(struct seq_file *s, void *unused)
326 {
327         struct tegra_dc *dc = s->private;
328
329         _dump_regs(dc, s, dbg_regs_print);
330
331         return 0;
332 }
333
334
335 static int dbg_dc_open(struct inode *inode, struct file *file)
336 {
337         return single_open(file, dbg_dc_show, inode->i_private);
338 }
339
340 static const struct file_operations regs_fops = {
341         .open           = dbg_dc_open,
342         .read           = seq_read,
343         .llseek         = seq_lseek,
344         .release        = single_release,
345 };
346
347 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
348 {
349         struct tegra_dc *dc = s->private;
350         struct tegra_dc_mode *m;
351
352         mutex_lock(&dc->lock);
353         m = &dc->mode;
354         seq_printf(s,
355                 "pclk: %d\n"
356                 "h_ref_to_sync: %d\n"
357                 "v_ref_to_sync: %d\n"
358                 "h_sync_width: %d\n"
359                 "v_sync_width: %d\n"
360                 "h_back_porch: %d\n"
361                 "v_back_porch: %d\n"
362                 "h_active: %d\n"
363                 "v_active: %d\n"
364                 "h_front_porch: %d\n"
365                 "v_front_porch: %d\n"
366                 "stereo_mode: %d\n",
367                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
368                 m->h_sync_width, m->v_sync_width,
369                 m->h_back_porch, m->v_back_porch,
370                 m->h_active, m->v_active,
371                 m->h_front_porch, m->v_front_porch,
372                 m->stereo_mode);
373         mutex_unlock(&dc->lock);
374         return 0;
375 }
376
377 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
378 {
379         return single_open(file, dbg_dc_mode_show, inode->i_private);
380 }
381
382 static const struct file_operations mode_fops = {
383         .open           = dbg_dc_mode_open,
384         .read           = seq_read,
385         .llseek         = seq_lseek,
386         .release        = single_release,
387 };
388
389 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
390 {
391         struct tegra_dc *dc = s->private;
392
393         mutex_lock(&dc->lock);
394         seq_printf(s,
395                 "underflows: %u\n"
396                 "underflows_a: %u\n"
397                 "underflows_b: %u\n"
398                 "underflows_c: %u\n",
399                 dc->stats.underflows,
400                 dc->stats.underflows_a,
401                 dc->stats.underflows_b,
402                 dc->stats.underflows_c);
403         mutex_unlock(&dc->lock);
404
405         return 0;
406 }
407
408 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
409 {
410         return single_open(file, dbg_dc_stats_show, inode->i_private);
411 }
412
413 static const struct file_operations stats_fops = {
414         .open           = dbg_dc_stats_open,
415         .read           = seq_read,
416         .llseek         = seq_lseek,
417         .release        = single_release,
418 };
419
420 static void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc)
421 {
422         if (dc->debugdir)
423                 debugfs_remove_recursive(dc->debugdir);
424         dc->debugdir = NULL;
425 }
426
427 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
428 {
429         struct dentry *retval;
430
431         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
432         if (!dc->debugdir)
433                 goto remove_out;
434
435         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
436                 &regs_fops);
437         if (!retval)
438                 goto remove_out;
439
440         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
441                 &mode_fops);
442         if (!retval)
443                 goto remove_out;
444
445         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
446                 &stats_fops);
447         if (!retval)
448                 goto remove_out;
449
450         return;
451 remove_out:
452         dev_err(&dc->ndev->dev, "could not create debugfs\n");
453         tegra_dc_remove_debugfs(dc);
454 }
455
456 #else /* !CONFIG_DEBUGFS */
457 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
458 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
459 #endif /* CONFIG_DEBUGFS */
460
461 static int tegra_dc_set(struct tegra_dc *dc, int index)
462 {
463         int ret = 0;
464
465         mutex_lock(&tegra_dc_lock);
466         if (index >= TEGRA_MAX_DC) {
467                 ret = -EINVAL;
468                 goto out;
469         }
470
471         if (dc != NULL && tegra_dcs[index] != NULL) {
472                 ret = -EBUSY;
473                 goto out;
474         }
475
476         tegra_dcs[index] = dc;
477
478 out:
479         mutex_unlock(&tegra_dc_lock);
480
481         return ret;
482 }
483
484 static unsigned int tegra_dc_has_multiple_dc(void)
485 {
486         unsigned int idx;
487         unsigned int cnt = 0;
488         struct tegra_dc *dc;
489
490         mutex_lock(&tegra_dc_lock);
491         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
492                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
493         mutex_unlock(&tegra_dc_lock);
494
495         return (cnt > 1);
496 }
497
498 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
499 {
500         if (idx < TEGRA_MAX_DC)
501                 return tegra_dcs[idx];
502         else
503                 return NULL;
504 }
505 EXPORT_SYMBOL(tegra_dc_get_dc);
506
507 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
508 {
509         if (win >= dc->n_windows)
510                 return NULL;
511
512         return &dc->windows[win];
513 }
514 EXPORT_SYMBOL(tegra_dc_get_window);
515
516 static int get_topmost_window(u32 *depths, unsigned long *wins)
517 {
518         int idx, best = -1;
519
520         for_each_set_bit(idx, wins, DC_N_WINDOWS) {
521                 if (best == -1 || depths[idx] < depths[best])
522                         best = idx;
523         }
524         clear_bit(best, wins);
525         return best;
526 }
527
528 static u32 blend_topwin(u32 flags)
529 {
530         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
531                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
532         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
533                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
534         else
535                 return BLEND(NOKEY, FIX, 0xff, 0xff);
536 }
537
538 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
539 {
540         int other;
541
542         for (other = 0; other < DC_N_WINDOWS; other++) {
543                 if (other != idx && (xy-- == 0))
544                         break;
545         }
546         if (BIT(other) & behind_mask)
547                 return blend_topwin(flags[idx]);
548         else if (flags[other])
549                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
550         else
551                 return BLEND(NOKEY, FIX, 0x00, 0x00);
552 }
553
554 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
555 {
556         unsigned long infront_mask;
557         int first;
558
559         infront_mask = ~(behind_mask | BIT(idx));
560         infront_mask &= (BIT(DC_N_WINDOWS) - 1);
561         first = ffs(infront_mask) - 1;
562
563         if (!infront_mask)
564                 return blend_topwin(flags[idx]);
565         else if (behind_mask && first != -1 && flags[first])
566                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
567         else
568                 return BLEND(NOKEY, FIX, 0x0, 0x0);
569 }
570
571 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
572 {
573         unsigned long mask = BIT(DC_N_WINDOWS) - 1;
574
575         while (mask) {
576                 int idx = get_topmost_window(blend->z, &mask);
577
578                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
579                                 DC_CMD_DISPLAY_WINDOW_HEADER);
580                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
581                                 DC_WIN_BLEND_NOKEY);
582                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
583                                 DC_WIN_BLEND_1WIN);
584                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
585                                 DC_WIN_BLEND_2WIN_X);
586                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
587                                 DC_WIN_BLEND_2WIN_Y);
588                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
589                                 DC_WIN_BLEND_3WIN_XY);
590         }
591 }
592
593 static void tegra_dc_set_csc(struct tegra_dc *dc)
594 {
595         tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
596         tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
597         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
598         tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
599         tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
600         tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
601         tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
602         tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
603 }
604
605 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
606 {
607         unsigned i;
608         unsigned v0 = 128;
609         unsigned v1 = 0;
610         /* linear horizontal and vertical filters */
611         for (i = 0; i < 16; i++) {
612                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
613                                 DC_WIN_H_FILTER_P(i));
614
615                 tegra_dc_writel(dc, v0,
616                                 DC_WIN_V_FILTER_P(i));
617                 v0 -= 8;
618                 v1 += 8;
619         }
620 }
621
622 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
623                                                    struct tegra_dc_win *b)
624 {
625         if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
626                 return 0;
627         return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
628                ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
629 }
630
631 static unsigned int tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
632                                                 unsigned int bw[], int n)
633 {
634         /* We have n windows and knows their geometries and bandwidthes. If any
635          * of them overlapped vertically, the overlapped area bandwidth get
636          * combined.
637          *
638          * This function will find the maximum bandwidth of overlapped area.
639          * If there is no windows overlapped, then return the maximum
640          * bandwidth of windows.
641          */
642
643         /* We know win_2 is always overlapped with win_0 and win_1. */
644         if (tegra_dc_windows_is_overlapped(wins[0], wins[1]))
645                 return bw[0] + bw[1] + bw[2];
646         else
647                 return max(bw[0], bw[1]) + bw[2];
648
649 }
650
651 /* 8 bits per byte (1 << 3) */
652 #define BIT_TO_BYTE_SHIFT 3
653 /*
654  * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we
655  * will request 140MBps from EMC.
656  */
657 #define MEM_EFFICIENCY_SHIFT 1
658 static unsigned long tegra_dc_get_emc_rate(struct tegra_dc_win *wins[], int n)
659 {
660         int i;
661         unsigned int bw[DC_N_WINDOWS];
662         struct tegra_dc_win *w;
663         struct tegra_dc *dc;
664         unsigned int max;
665         unsigned int ret;
666
667         dc = wins[0]->dc;
668
669         if (tegra_dc_has_multiple_dc())
670                 return tegra_dc_get_default_emc_clk_rate(dc);
671
672         BUG_ON(n > ARRAY_SIZE(bw));
673         /*
674          * Calculate peak EMC bandwidth for each enabled window =
675          * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
676          * (windows_tiling ? 2 : 1)
677          *
678          *
679          * note:
680          * (*) We use 2 tap V filter, so need double BW if use V filter
681          * (*) Tiling mode on T30 and DDR3 requires double BW
682          */
683         for (i = 0; w = wins[i], bw[i] = 0, i < n; i++) {
684                 if (!WIN_IS_ENABLED(w))
685                         continue;
686                 bw[i] = dc->pixel_clk *
687                         (tegra_dc_fmt_bpp(w->fmt) >> BIT_TO_BYTE_SHIFT) *
688                         (WIN_USE_V_FILTER(w) ? 2 : 1) /
689                         w->out_w * w->w *
690                         (WIN_IS_TILED(w) ? TILED_WINDOWS_BW_MULTIPLIER : 1);
691         }
692
693         max = tegra_dc_find_max_bandwidth(wins, bw, n) << MEM_EFFICIENCY_SHIFT;
694
695         ret = EMC_BW_TO_FREQ(max);
696
697         /*
698          * If the calculated peak BW is bigger than board specified BW, then
699          * either the above calculation is wrong, or board specified BW is
700          * wrong.
701          */
702         WARN_ONCE(ret > tegra_dc_get_default_emc_clk_rate(dc),
703                   "Calculated EMC bandwidth is %luHz, "
704                   "maximum allowed EMC bandwidth is %luHz\n",
705                   ret, tegra_dc_get_default_emc_clk_rate(dc));
706
707         return ret;
708 }
709 #undef BIT_TO_BYTE_SHIFT
710 #undef MEM_EFFICIENCY_SHIFT
711
712 static void tegra_dc_change_emc(struct tegra_dc *dc)
713 {
714         if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
715                 dc->emc_clk_rate = dc->new_emc_clk_rate;
716                 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
717         }
718 }
719
720 static void tegra_dc_reduce_emc_worker(struct work_struct *work)
721 {
722         struct tegra_dc *dc;
723
724         dc = container_of(to_delayed_work(work), struct tegra_dc,
725             reduce_emc_clk_work);
726
727         mutex_lock(&dc->lock);
728
729         if (!dc->enabled) {
730                 mutex_unlock(&dc->lock);
731                 return;
732         }
733
734         tegra_dc_change_emc(dc);
735
736         mutex_unlock(&dc->lock);
737 }
738
739 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
740 {
741         unsigned long new_rate;
742         struct tegra_dc *dc;
743
744         if (!use_dynamic_emc)
745                 return 0;
746
747         dc = windows[0]->dc;
748
749         /* calculate the new rate based on this POST */
750         new_rate = tegra_dc_get_emc_rate(windows, n);
751
752         dc->new_emc_clk_rate = new_rate;
753
754         /*
755          * If we don't need set EMC immediately after a frame POST, we schedule
756          * a work_queue to reduce EMC in the future. This work_queue task will
757          * not be executed if the another POST comes before the idle time
758          * expired.
759          */
760         if (NEED_UPDATE_EMC_ON_EVERY_FRAME)
761                 tegra_dc_change_emc(dc);
762         else
763                 schedule_delayed_work(&dc->reduce_emc_clk_work,
764                         msecs_to_jiffies(windows_idle_detection_time));
765
766         return 0;
767 }
768
769 int tegra_dc_set_default_emc(struct tegra_dc *dc)
770 {
771         /*
772          * POST happens whenever this function is called, we first delete any
773          * reduce_emc_clk_work, then we always set the DC EMC clock to default
774          * value.
775          */
776         cancel_delayed_work_sync(&dc->reduce_emc_clk_work);
777
778         if (NEED_UPDATE_EMC_ON_EVERY_FRAME)
779                 return 0;
780
781         mutex_lock(&dc->lock);
782
783         if (!dc->enabled) {
784                 mutex_unlock(&dc->lock);
785                 return -EFAULT;
786         }
787
788         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
789         tegra_dc_change_emc(dc);
790
791         mutex_unlock(&dc->lock);
792
793         return 0;
794 }
795
796 /* does not support updating windows on multiple dcs in one call */
797 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
798 {
799         struct tegra_dc *dc;
800         unsigned long update_mask = GENERAL_ACT_REQ;
801         unsigned long val;
802         bool update_blend = false;
803         int i;
804
805         dc = windows[0]->dc;
806
807         mutex_lock(&dc->lock);
808
809         if (!dc->enabled) {
810                 mutex_unlock(&dc->lock);
811                 return -EFAULT;
812         }
813
814         if (no_vsync)
815                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
816         else
817                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
818
819         for (i = 0; i < n; i++) {
820                 struct tegra_dc_win *win = windows[i];
821                 unsigned h_dda;
822                 unsigned v_dda;
823                 unsigned h_offset;
824                 unsigned v_offset;
825                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
826                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
827                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
828
829                 if (win->z != dc->blend.z[win->idx]) {
830                         dc->blend.z[win->idx] = win->z;
831                         update_blend = true;
832                 }
833                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
834                         dc->blend.flags[win->idx]) {
835                         dc->blend.flags[win->idx] =
836                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
837                         update_blend = true;
838                 }
839
840                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
841                                 DC_CMD_DISPLAY_WINDOW_HEADER);
842
843                 if (!no_vsync)
844                         update_mask |= WIN_A_ACT_REQ << win->idx;
845
846                 if (!WIN_IS_ENABLED(win)) {
847                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
848                         continue;
849                 }
850
851                 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
852                 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
853
854                 tegra_dc_writel(dc,
855                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
856                                 DC_WIN_POSITION);
857                 tegra_dc_writel(dc,
858                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
859                                 DC_WIN_SIZE);
860                 tegra_dc_writel(dc,
861                                 V_PRESCALED_SIZE(win->h) |
862                                 H_PRESCALED_SIZE(win->w * tegra_dc_fmt_bpp(win->fmt) / 8),
863                                 DC_WIN_PRESCALED_SIZE);
864
865                 h_dda = ((win->w - 1) * 0x1000) / max_t(int, win->out_w - 1, 1);
866                 v_dda = ((win->h - 1) * 0x1000) / max_t(int, win->out_h - 1, 1);
867                 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
868                                 DC_WIN_DDA_INCREMENT);
869                 tegra_dc_writel(dc, 0, DC_WIN_H_INITIAL_DDA);
870                 tegra_dc_writel(dc, 0, DC_WIN_V_INITIAL_DDA);
871
872                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
873                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
874                 tegra_dc_writel(dc,
875                                 (unsigned long)win->phys_addr +
876                                 (unsigned long)win->offset,
877                                 DC_WINBUF_START_ADDR);
878
879                 if (!yuvp) {
880                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
881                 } else {
882                         tegra_dc_writel(dc,
883                                         (unsigned long)win->phys_addr +
884                                         (unsigned long)win->offset_u,
885                                         DC_WINBUF_START_ADDR_U);
886                         tegra_dc_writel(dc,
887                                         (unsigned long)win->phys_addr +
888                                         (unsigned long)win->offset_v,
889                                         DC_WINBUF_START_ADDR_V);
890                         tegra_dc_writel(dc,
891                                         LINE_STRIDE(win->stride) |
892                                         UV_LINE_STRIDE(win->stride_uv),
893                                         DC_WIN_LINE_STRIDE);
894                 }
895
896                 h_offset = win->x;
897                 if (invert_h) {
898                         h_offset += win->w - 1;
899                 }
900                 h_offset *= tegra_dc_fmt_bpp(win->fmt) / 8;
901
902                 v_offset = win->y;
903                 if (invert_v) {
904                         v_offset += win->h - 1;
905                 }
906
907                 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
908                 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
909
910                 if (WIN_IS_TILED(win))
911                         tegra_dc_writel(dc,
912                                         DC_WIN_BUFFER_ADDR_MODE_TILE |
913                                         DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
914                                         DC_WIN_BUFFER_ADDR_MODE);
915                 else
916                         tegra_dc_writel(dc,
917                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR |
918                                         DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
919                                         DC_WIN_BUFFER_ADDR_MODE);
920
921                 val = WIN_ENABLE;
922                 if (yuvp)
923                         val |= CSC_ENABLE;
924                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
925                         val |= COLOR_EXPAND;
926
927                 /* only B and C have H filer, force it on if scaling */
928                 if (win->idx != 0 && win->w != win->out_w)
929                         win->flags |= TEGRA_WIN_FLAG_H_FILTER;
930                 /* only B has V filter, set it if scaling */
931                 if (win->idx == 1 && win->h != win->out_h)
932                         win->flags |= TEGRA_WIN_FLAG_V_FILTER;
933
934                 if (WIN_USE_H_FILTER(win))
935                         val |= H_FILTER_ENABLE;
936                 if (WIN_USE_V_FILTER(win))
937                         val |= V_FILTER_ENABLE;
938
939                 if (invert_h)
940                         val |= H_DIRECTION_DECREMENT;
941                 if (invert_v)
942                         val |= V_DIRECTION_DECREMENT;
943
944                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
945
946                 win->dirty = no_vsync ? 0 : 1;
947         }
948
949         if (update_blend) {
950                 tegra_dc_set_blending(dc, &dc->blend);
951                 for (i = 0; i < DC_N_WINDOWS; i++) {
952                         if (!no_vsync)
953                                 dc->windows[i].dirty = 1;
954                         update_mask |= WIN_A_ACT_REQ << i;
955                 }
956         }
957
958         tegra_dc_set_dynamic_emc(windows, n);
959
960         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
961
962         if (!no_vsync) {
963                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
964                 val |= FRAME_END_INT;
965                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
966
967                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
968                 val |= FRAME_END_INT;
969                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
970         }
971
972         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
973
974         mutex_unlock(&dc->lock);
975
976         return 0;
977 }
978 EXPORT_SYMBOL(tegra_dc_update_windows);
979
980 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc)
981 {
982         return dc->syncpt_id;
983 }
984 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
985
986 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc)
987 {
988         u32 max;
989
990         mutex_lock(&dc->lock);
991         max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt, dc->syncpt_id,
992                                         ((dc->enabled) ? 1 : 0) );
993         dc->syncpt_max = max;
994         mutex_unlock(&dc->lock);
995
996         return max;
997 }
998
999 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val)
1000 {
1001         mutex_lock(&dc->lock);
1002         if ( dc->enabled )
1003                 while (dc->syncpt_min < val) {
1004                         dc->syncpt_min++;
1005                         nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1006                                 dc->syncpt_id);
1007                 }
1008         mutex_unlock(&dc->lock);
1009 }
1010
1011 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1012                                              int n)
1013 {
1014         int i;
1015
1016         for (i = 0; i < n; i++) {
1017                 if (windows[i]->dirty)
1018                         return false;
1019         }
1020
1021         return true;
1022 }
1023
1024 /* does not support syncing windows on multiple dcs in one call */
1025 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1026 {
1027         if (n < 1 || n > DC_N_WINDOWS)
1028                 return -EINVAL;
1029
1030         if (!windows[0]->dc->enabled)
1031                 return -EFAULT;
1032
1033         return wait_event_interruptible_timeout(windows[0]->dc->wq,
1034                                          tegra_dc_windows_are_clean(windows, n),
1035                                          HZ);
1036 }
1037 EXPORT_SYMBOL(tegra_dc_sync_windows);
1038
1039 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1040 {
1041 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1042         return clk_get_rate(dc->clk);
1043 #else
1044         return 27000000;
1045 #endif
1046 }
1047
1048 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1049 {
1050         unsigned long rate;
1051         unsigned long div;
1052
1053         rate = tegra_dc_clk_get_rate(dc);
1054
1055         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1056
1057         if (div < 2)
1058                 return 0;
1059
1060         return rate * 2 / div;
1061 }
1062
1063 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1064 {
1065         int pclk;
1066
1067         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1068                 struct clk *parent_clk =
1069                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1070
1071                 if (clk_get_parent(clk) != parent_clk)
1072                         clk_set_parent(clk, parent_clk);
1073         }
1074
1075         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1076                 unsigned long rate;
1077                 struct clk *parent_clk =
1078                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1079                 struct clk *base_clk = clk_get_parent(parent_clk);
1080
1081                 if (dc->mode.pclk > 70000000)
1082                         rate = 594000000;
1083                 else
1084                         rate = 216000000;
1085
1086                 if (rate != clk_get_rate(base_clk))
1087                         clk_set_rate(base_clk, rate);
1088
1089                 if (clk_get_parent(clk) != parent_clk)
1090                         clk_set_parent(clk, parent_clk);
1091         }
1092
1093         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1094                 unsigned long rate;
1095                 struct clk *parent_clk;
1096                 struct clk *base_clk;
1097
1098                 if (clk == dc->clk) {
1099                         parent_clk = clk_get_sys(NULL,
1100                                         dc->out->parent_clk ? : "pll_d_out0");
1101                         base_clk = clk_get_parent(parent_clk);
1102                 } else {
1103                         if (dc->pdata->default_out->dsi->dsi_instance) {
1104                                 parent_clk = clk_get_sys(NULL,
1105                                         dc->out->parent_clk ? : "pll_d2_out0");
1106                                 base_clk = clk_get_parent(parent_clk);
1107                                 tegra_clk_cfg_ex(base_clk,
1108                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1109                         } else {
1110                                 parent_clk = clk_get_sys(NULL,
1111                                         dc->out->parent_clk ? : "pll_d_out0");
1112                                 base_clk = clk_get_parent(parent_clk);
1113                         }
1114                 }
1115
1116                 rate = dc->mode.pclk;
1117                 if (rate != clk_get_rate(base_clk))
1118                         clk_set_rate(base_clk, rate);
1119
1120                 if (clk_get_parent(clk) != parent_clk)
1121                         clk_set_parent(clk, parent_clk);
1122         }
1123
1124         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1125         tegra_dvfs_set_rate(clk, pclk);
1126 }
1127
1128 /* return non-zero if constraint is violated */
1129 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1130 {
1131         long a, b;
1132
1133         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1134         a = 0;
1135
1136         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1137         b = mode->h_front_porch - 1;
1138
1139         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1140         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1141                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1142         /* check Constraint 1 and 6 */
1143         if (a > b)
1144                 return 1;
1145
1146         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1147         if (mode->h_sync_width < 1)
1148                 return 4;
1149
1150         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1151         if (mode->h_active < 16)
1152                 return 7;
1153
1154         if (href) {
1155                 if (b > a && a % 2)
1156                         *href = a + 1; /* use smallest even value */
1157                 else
1158                         *href = a; /* even or only possible value */
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1165 {
1166         long a;
1167         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1168
1169         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1170         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1171                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1172
1173         /* Constraint 6 */
1174         if (mode->v_front_porch < a + 1)
1175                 a = mode->v_front_porch - 1;
1176
1177         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1178         if (mode->v_sync_width < 1)
1179                 return 4;
1180
1181         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1182         if (mode->v_active < 16)
1183                 return 7;
1184
1185         if (vref)
1186                 *vref = a;
1187         return 0;
1188 }
1189
1190 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1191 {
1192         int ret;
1193         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1194         if (ret)
1195                 return ret;
1196         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1197         if (ret)
1198                 return ret;
1199
1200         return 0;
1201 }
1202
1203 #ifdef DEBUG
1204 /* return in 1000ths of a Hertz */
1205 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1206 {
1207         long h_total, v_total, refresh;
1208         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1209                 m->h_sync_width;
1210         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1211                 m->v_sync_width;
1212         refresh = dc->pixel_clk / h_total;
1213         refresh *= 1000;
1214         refresh /= v_total;
1215         return refresh;
1216 }
1217
1218 static void print_mode(struct tegra_dc *dc,
1219                         const struct tegra_dc_mode *mode, const char *note)
1220 {
1221         if (mode) {
1222                 int refresh = calc_refresh(mode);
1223                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1224                         note ? note : "",
1225                         mode->h_active, mode->v_active,
1226                         refresh / 1000, refresh % 1000,
1227                         mode->pclk);
1228         }
1229 }
1230 #else /* !DEBUG */
1231 static inline void print_mode(struct tegra_dc *dc,
1232                         const struct tegra_dc_mode *mode, const char *note) { }
1233 #endif /* DEBUG */
1234
1235 static inline void enable_dc_irq(unsigned int irq)
1236 {
1237 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1238         enable_irq(irq);
1239 #else
1240         /* Always disable DC interrupts on FPGA. */
1241         disable_irq(irq);
1242 #endif
1243 }
1244
1245 static inline void disable_dc_irq(unsigned int irq)
1246 {
1247         disable_irq(irq);
1248 }
1249
1250 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1251 {
1252         unsigned long val;
1253         unsigned long rate;
1254         unsigned long div;
1255         unsigned long pclk;
1256
1257         print_mode(dc, mode, __func__);
1258
1259         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1260         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1261                         DC_DISP_REF_TO_SYNC);
1262         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1263                         DC_DISP_SYNC_WIDTH);
1264         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1265                         DC_DISP_BACK_PORCH);
1266         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1267                         DC_DISP_DISP_ACTIVE);
1268         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1269                         DC_DISP_FRONT_PORCH);
1270
1271         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1272                         DC_DISP_DATA_ENABLE_OPTIONS);
1273
1274         val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1275         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1276                 val |= PIN1_LVS_OUTPUT;
1277         else
1278                 val &= ~PIN1_LVS_OUTPUT;
1279
1280         if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1281                 val |= PIN1_LHS_OUTPUT;
1282         else
1283                 val &= ~PIN1_LHS_OUTPUT;
1284         tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1285
1286         /* TODO: MIPI/CRT/HDMI clock cals */
1287
1288         val = DISP_DATA_FORMAT_DF1P1C;
1289
1290         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1291                 val |= DISP_DATA_ALIGNMENT_MSB;
1292         else
1293                 val |= DISP_DATA_ALIGNMENT_LSB;
1294
1295         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1296                 val |= DISP_DATA_ORDER_RED_BLUE;
1297         else
1298                 val |= DISP_DATA_ORDER_BLUE_RED;
1299
1300         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1301
1302         rate = tegra_dc_clk_get_rate(dc);
1303
1304         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1305         if (pclk < (mode->pclk / 100 * 99) ||
1306             pclk > (mode->pclk / 100 * 109)) {
1307                 dev_err(&dc->ndev->dev,
1308                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1309                         rate, mode->pclk,
1310                         pclk, (mode->pclk / 100 * 99),
1311                         (mode->pclk / 100 * 109));
1312                 return -EINVAL;
1313         }
1314
1315         div = (rate * 2 / pclk) - 2;
1316
1317         tegra_dc_writel(dc, 0x00010001,
1318                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1319         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1320                         DC_DISP_DISP_CLOCK_CONTROL);
1321
1322         dc->pixel_clk = dc->mode.pclk;
1323
1324         return 0;
1325 }
1326
1327
1328 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1329 {
1330         memcpy(&dc->mode, mode, sizeof(dc->mode));
1331
1332         print_mode(dc, mode, __func__);
1333
1334         return 0;
1335 }
1336 EXPORT_SYMBOL(tegra_dc_set_mode);
1337
1338 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1339                 const struct fb_videomode *fbmode, bool stereo_mode)
1340 {
1341         struct tegra_dc_mode mode;
1342
1343         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1344         mode.h_sync_width = fbmode->hsync_len;
1345         mode.v_sync_width = fbmode->vsync_len;
1346         mode.h_back_porch = fbmode->left_margin;
1347         mode.v_back_porch = fbmode->upper_margin;
1348         mode.h_active = fbmode->xres;
1349         mode.v_active = fbmode->yres;
1350         mode.h_front_porch = fbmode->right_margin;
1351         mode.v_front_porch = fbmode->lower_margin;
1352         mode.stereo_mode = stereo_mode;
1353         if (calc_ref_to_sync(&mode)) {
1354                 dev_err(&dc->ndev->dev, "bad href/vref values, overriding.\n");
1355                 mode.h_ref_to_sync = 11;
1356                 mode.v_ref_to_sync = 1;
1357         }
1358         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1359                 mode.h_active, mode.v_active, mode.pclk,
1360                 mode.h_ref_to_sync, mode.v_ref_to_sync
1361         );
1362
1363         if (mode.stereo_mode) {
1364                 mode.pclk *= 2;
1365                 /* total v_active = yres*2 + activespace */
1366                 mode.v_active = fbmode->yres*2 +
1367                                 fbmode->vsync_len +
1368                                 fbmode->upper_margin +
1369                                 fbmode->lower_margin;
1370         }
1371
1372         mode.flags = 0;
1373
1374         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1375                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1376
1377         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1378                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1379
1380         return tegra_dc_set_mode(dc, &mode);
1381 }
1382 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1383
1384 void
1385 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1386 {
1387         unsigned int ctrl;
1388         unsigned long out_sel;
1389         unsigned long cmd_state;
1390
1391         mutex_lock(&dc->lock);
1392         if (!dc->enabled) {
1393                 mutex_unlock(&dc->lock);
1394                 return;
1395         }
1396
1397         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1398                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1399                 cfg->clk_select);
1400
1401         /* The new value should be effected immediately */
1402         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1403         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1404
1405         switch (cfg->which_pwm) {
1406         case TEGRA_PWM_PM0:
1407                 /* Select the LM0 on PM0 */
1408                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1409                 out_sel &= ~(7 << 0);
1410                 out_sel |= (3 << 0);
1411                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1412                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1413                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1414                 break;
1415         case TEGRA_PWM_PM1:
1416                 /* Select the LM1 on PM1 */
1417                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1418                 out_sel &= ~(7 << 4);
1419                 out_sel |= (3 << 4);
1420                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1421                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1422                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1423                 break;
1424         default:
1425                 dev_err(&dc->ndev->dev, "Error\n");
1426                 break;
1427         }
1428         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1429         mutex_unlock(&dc->lock);
1430 }
1431 EXPORT_SYMBOL(tegra_dc_config_pwm);
1432
1433 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1434                                 const struct tegra_dc_out_pin *pins,
1435                                 const unsigned int n_pins)
1436 {
1437         unsigned int i;
1438
1439         int name;
1440         int pol;
1441
1442         u32 pol1, pol3;
1443
1444         u32 set1, unset1;
1445         u32 set3, unset3;
1446
1447         set1 = set3 = unset1 = unset3 = 0;
1448
1449         for (i = 0; i < n_pins; i++) {
1450                 name = (pins + i)->name;
1451                 pol  = (pins + i)->pol;
1452
1453                 /* set polarity by name */
1454                 switch (name) {
1455                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1456                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1457                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1458                         else
1459                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1460                         break;
1461                 case TEGRA_DC_OUT_PIN_H_SYNC:
1462                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1463                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1464                         else
1465                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1466                         break;
1467                 case TEGRA_DC_OUT_PIN_V_SYNC:
1468                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1469                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1470                         else
1471                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1472                         break;
1473                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1474                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1475                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1476                         else
1477                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1478                         break;
1479                 default:
1480                         printk("Invalid argument in function %s\n",
1481                                __FUNCTION__);
1482                         break;
1483                 }
1484         }
1485
1486         pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1487         pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1488
1489         pol1 |= set1;
1490         pol1 &= ~unset1;
1491
1492         pol3 |= set3;
1493         pol3 &= ~unset3;
1494
1495         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1496         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1497 }
1498
1499 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1500 {
1501         dc->out = out;
1502
1503         if (out->n_modes > 0)
1504                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1505
1506         switch (out->type) {
1507         case TEGRA_DC_OUT_RGB:
1508                 dc->out_ops = &tegra_dc_rgb_ops;
1509                 break;
1510
1511         case TEGRA_DC_OUT_HDMI:
1512                 dc->out_ops = &tegra_dc_hdmi_ops;
1513                 break;
1514
1515         case TEGRA_DC_OUT_DSI:
1516                 dc->out_ops = &tegra_dc_dsi_ops;
1517                 break;
1518
1519         default:
1520                 dc->out_ops = NULL;
1521                 break;
1522         }
1523
1524         if (dc->out_ops && dc->out_ops->init)
1525                 dc->out_ops->init(dc);
1526
1527 }
1528
1529 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1530 {
1531         if (dc->out)
1532                 return dc->out->height;
1533         else
1534                 return 0;
1535 }
1536 EXPORT_SYMBOL(tegra_dc_get_out_height);
1537
1538 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1539 {
1540         if (dc->out)
1541                 return dc->out->width;
1542         else
1543                 return 0;
1544 }
1545 EXPORT_SYMBOL(tegra_dc_get_out_width);
1546
1547 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1548 {
1549         if (dc->out && dc->out->max_pixclock)
1550                 return dc->out->max_pixclock;
1551         else
1552                 return 0;
1553 }
1554 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1555
1556 void tegra_dc_enable_crc(struct tegra_dc *dc)
1557 {
1558         u32 val;
1559         tegra_dc_io_start(dc);
1560
1561         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1562                 CRC_ENABLE_ENABLE;
1563         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1564         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1565         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1566 }
1567
1568 void tegra_dc_disable_crc(struct tegra_dc *dc)
1569 {
1570         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1571         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1572         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1573
1574         tegra_dc_io_end(dc);
1575 }
1576
1577 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1578 {
1579         int crc = 0;
1580         u32 val = 0;
1581
1582         if(!dc) {
1583                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1584                 goto crc_error;
1585         }
1586
1587         /* TODO: Replace mdelay with code to sync VBlANK, since
1588          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1589         mdelay(TEGRA_CRC_LATCHED_DELAY);
1590
1591         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1592 crc_error:
1593         return crc;
1594 }
1595
1596 static void tegra_dc_vblank(struct work_struct *work)
1597 {
1598         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1599         bool nvsd_updated = false;
1600
1601         mutex_lock(&dc->lock);
1602
1603         /* Update the SD brightness */
1604         nvsd_updated = nvsd_update_brightness(dc);
1605
1606         mutex_unlock(&dc->lock);
1607
1608         /* Do the actual brightness update outside of the mutex */
1609         if (nvsd_updated && dc->out->sd_settings &&
1610             dc->out->sd_settings->bl_device) {
1611
1612                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1613                 struct backlight_device *bl = platform_get_drvdata(pdev);
1614                 if (bl)
1615                         backlight_update_status(bl);
1616         }
1617 }
1618
1619 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1620 {
1621 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1622         struct tegra_dc *dc = ptr;
1623         unsigned long status;
1624         unsigned long val;
1625         unsigned long underflow_mask;
1626         int i;
1627
1628         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1629         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1630
1631         /*
1632          * Overlays can get thier internal state corrupted during and underflow
1633          * condition.  The only way to fix this state is to reset the DC.
1634          * if we get 4 consecutive frames with underflows, assume we're
1635          * hosed and reset.
1636          */
1637         underflow_mask = status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1638
1639         if (underflow_mask) {
1640                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1641                 val |= V_BLANK_INT;
1642                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1643                 dc->underflow_mask |= underflow_mask;
1644                 dc->stats.underflows++;
1645                 if (status & WIN_A_UF_INT)
1646                         dc->stats.underflows_a++;
1647                 if (status & WIN_B_UF_INT)
1648                         dc->stats.underflows_b++;
1649                 if (status & WIN_C_UF_INT)
1650                         dc->stats.underflows_c++;
1651         }
1652
1653         if (status & V_BLANK_INT) {
1654                 int i;
1655
1656                 /* Check for any underflow reset conditions */
1657                 for (i = 0; i< DC_N_WINDOWS; i++) {
1658                         if (dc->underflow_mask & (WIN_A_UF_INT <<i)) {
1659                                 dc->windows[i].underflows++;
1660
1661 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1662                                 if (dc->windows[i].underflows > 4)
1663                                         schedule_work(&dc->reset_work);
1664 #endif
1665                         } else {
1666                                 dc->windows[i].underflows = 0;
1667                         }
1668                 }
1669
1670                 if (!dc->underflow_mask) {
1671                         /* If we have no underflow to check, go ahead
1672                            and disable the interrupt */
1673                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1674                         val &= ~V_BLANK_INT;
1675                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1676                 }
1677
1678                 /* Clear the underflow mask now that we've checked it. */
1679                 dc->underflow_mask = 0;
1680
1681                 /* Schedule any additional bottom-half vblank actvities. */
1682                 schedule_work(&dc->vblank_work);
1683
1684                 /* Mark the vblank as complete. */
1685                 complete(&dc->vblank_complete);
1686         }
1687
1688         if (status & FRAME_END_INT) {
1689                 int completed = 0;
1690                 int dirty = 0;
1691
1692                 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1693                 for (i = 0; i < DC_N_WINDOWS; i++) {
1694                         if (!(val & (WIN_A_UPDATE << i))) {
1695                                 dc->windows[i].dirty = 0;
1696                                 completed = 1;
1697                         } else {
1698                                 dirty = 1;
1699                         }
1700                 }
1701
1702                 if (!dirty) {
1703                         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1704                         val &= ~FRAME_END_INT;
1705                         tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1706                 }
1707
1708                 if (completed) {
1709                         if (!dirty) {
1710                                 /* With the last completed window, go ahead
1711                                    and enable the vblank interrupt for nvsd. */
1712                                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1713                                 val |= V_BLANK_INT;
1714                                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1715
1716                                 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1717                                 val |= V_BLANK_INT;
1718                                 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1719                         }
1720
1721                         /* Wake up the workqueue regardless. */
1722                         wake_up(&dc->wq);
1723                 }
1724         }
1725
1726         return IRQ_HANDLED;
1727 #else /* CONFIG_TEGRA_SILICON_PLATFORM */
1728         return IRQ_NONE;
1729 #endif /* !CONFIG_TEGRA_SILICON_PLATFORM */
1730 }
1731
1732 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1733 {
1734         u32 color_control;
1735
1736         switch (dc->out->depth) {
1737         case 3:
1738                 color_control = BASE_COLOR_SIZE111;
1739                 break;
1740
1741         case 6:
1742                 color_control = BASE_COLOR_SIZE222;
1743                 break;
1744
1745         case 8:
1746                 color_control = BASE_COLOR_SIZE332;
1747                 break;
1748
1749         case 9:
1750                 color_control = BASE_COLOR_SIZE333;
1751                 break;
1752
1753         case 12:
1754                 color_control = BASE_COLOR_SIZE444;
1755                 break;
1756
1757         case 15:
1758                 color_control = BASE_COLOR_SIZE555;
1759                 break;
1760
1761         case 16:
1762                 color_control = BASE_COLOR_SIZE565;
1763                 break;
1764
1765         case 18:
1766                 color_control = BASE_COLOR_SIZE666;
1767                 break;
1768
1769         default:
1770                 color_control = BASE_COLOR_SIZE888;
1771                 break;
1772         }
1773
1774         switch (dc->out->dither) {
1775         case TEGRA_DC_DISABLE_DITHER:
1776                 color_control |= DITHER_CONTROL_DISABLE;
1777                 break;
1778         case TEGRA_DC_ORDERED_DITHER:
1779                 color_control |= DITHER_CONTROL_ORDERED;
1780                 break;
1781         case TEGRA_DC_ERRDIFF_DITHER:
1782                 /* The line buffer for error-diffusion dither is limited
1783                  * to 640 pixels per line. This limits the maximum
1784                  * horizontal active area size to 640 pixels when error
1785                  * diffusion is enabled.
1786                  */
1787                 BUG_ON(dc->mode.h_active > 640);
1788                 color_control |= DITHER_CONTROL_ERRDIFF;
1789                 break;
1790         }
1791
1792         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1793 }
1794
1795 static void tegra_dc_init(struct tegra_dc *dc)
1796 {
1797         u32 disp_syncpt = 0;
1798         u32 vblank_syncpt = 0;
1799         int i;
1800
1801         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1802         if (dc->ndev->id == 0) {
1803                 disp_syncpt = NVSYNCPT_DISP0;
1804                 vblank_syncpt = NVSYNCPT_VBLANK0;
1805
1806                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1807                                       TEGRA_MC_PRIO_MED);
1808                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1809                                       TEGRA_MC_PRIO_MED);
1810                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1811                                       TEGRA_MC_PRIO_MED);
1812                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1813                                       TEGRA_MC_PRIO_MED);
1814                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1815                                       TEGRA_MC_PRIO_HIGH);
1816         } else if (dc->ndev->id == 1) {
1817                 disp_syncpt = NVSYNCPT_DISP1;
1818                 vblank_syncpt = NVSYNCPT_VBLANK1;
1819
1820                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1821                                       TEGRA_MC_PRIO_MED);
1822                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1823                                       TEGRA_MC_PRIO_MED);
1824                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1825                                       TEGRA_MC_PRIO_MED);
1826                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1827                                       TEGRA_MC_PRIO_MED);
1828                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1829                                       TEGRA_MC_PRIO_HIGH);
1830         }
1831         tegra_dc_writel(dc, 0x00000100 | vblank_syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1832         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1833         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1834         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1835         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1836
1837         tegra_dc_writel(dc, (FRAME_END_INT |
1838                              V_BLANK_INT |
1839                              WIN_A_UF_INT |
1840                              WIN_B_UF_INT |
1841                              WIN_C_UF_INT), DC_CMD_INT_MASK);
1842         tegra_dc_writel(dc, (WIN_A_UF_INT |
1843                              WIN_B_UF_INT |
1844                              WIN_C_UF_INT), DC_CMD_INT_ENABLE);
1845
1846         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1847
1848         tegra_dc_set_color_control(dc);
1849         for (i = 0; i < DC_N_WINDOWS; i++) {
1850                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1851                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1852                 tegra_dc_set_csc(dc);
1853                 tegra_dc_set_scaling_filter(dc);
1854         }
1855
1856
1857         dc->syncpt_id = disp_syncpt;
1858
1859         dc->syncpt_min = dc->syncpt_max =
1860                 nvhost_syncpt_read(&dc->ndev->host->syncpt, disp_syncpt);
1861
1862         print_mode(dc, &dc->mode, __func__);
1863
1864         if (dc->mode.pclk)
1865                 tegra_dc_program_mode(dc, &dc->mode);
1866
1867         /* Initialize SD AFTER the modeset.
1868            nvsd_init handles the sd_settings = NULL case. */
1869         nvsd_init(dc, dc->out->sd_settings);
1870 }
1871
1872 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1873 {
1874         if (dc->out->enable)
1875                 dc->out->enable();
1876
1877         tegra_dc_setup_clk(dc, dc->clk);
1878         tegra_periph_reset_assert(dc->clk);
1879         clk_enable(dc->clk);
1880         clk_enable(dc->emc_clk);
1881         enable_dc_irq(dc->irq);
1882
1883         tegra_dc_init(dc);
1884
1885         if (dc->out_ops && dc->out_ops->enable)
1886                 dc->out_ops->enable(dc);
1887
1888         if (dc->out->out_pins)
1889                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1890                                             dc->out->n_out_pins);
1891
1892         if (dc->out->postpoweron)
1893                 dc->out->postpoweron();
1894
1895         /* force a full blending update */
1896         dc->blend.z[0] = -1;
1897
1898         return true;
1899 }
1900
1901 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1902 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1903 {
1904         if (dc->out->enable)
1905                 dc->out->enable();
1906
1907         tegra_dc_setup_clk(dc, dc->clk);
1908         clk_enable(dc->clk);
1909         clk_enable(dc->emc_clk);
1910
1911         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1912                 mutex_lock(&tegra_dcs[1]->lock);
1913                 disable_irq(tegra_dcs[1]->irq);
1914         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1915                 mutex_lock(&tegra_dcs[0]->lock);
1916                 disable_irq(tegra_dcs[0]->irq);
1917         }
1918
1919         msleep(5);
1920         tegra_periph_reset_assert(dc->clk);
1921         msleep(2);
1922 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1923         tegra_periph_reset_deassert(dc->clk);
1924         msleep(1);
1925 #endif
1926
1927         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1928                 enable_dc_irq(tegra_dcs[1]->irq);
1929                 mutex_unlock(&tegra_dcs[1]->lock);
1930         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1931                 enable_dc_irq(tegra_dcs[0]->irq);
1932                 mutex_unlock(&tegra_dcs[0]->lock);
1933         }
1934
1935         enable_dc_irq(dc->irq);
1936
1937         tegra_dc_init(dc);
1938
1939         if (dc->out_ops && dc->out_ops->enable)
1940                 dc->out_ops->enable(dc);
1941
1942         if (dc->out->out_pins)
1943                 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
1944                                             dc->out->n_out_pins);
1945
1946         if (dc->out->postpoweron)
1947                 dc->out->postpoweron();
1948
1949         /* force a full blending update */
1950         dc->blend.z[0] = -1;
1951
1952         return true;
1953 }
1954 #endif
1955
1956 static bool _tegra_dc_enable(struct tegra_dc *dc)
1957 {
1958         if (dc->mode.pclk == 0)
1959                 return false;
1960
1961         if (!dc->out)
1962                 return false;
1963
1964         tegra_dc_io_start(dc);
1965
1966         return _tegra_dc_controller_enable(dc);
1967 }
1968
1969 void tegra_dc_enable(struct tegra_dc *dc)
1970 {
1971         mutex_lock(&dc->lock);
1972
1973         if (!dc->enabled)
1974                 dc->enabled = _tegra_dc_enable(dc);
1975
1976         mutex_unlock(&dc->lock);
1977 }
1978
1979 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1980 {
1981         disable_irq(dc->irq);
1982
1983         if (dc->out_ops && dc->out_ops->disable)
1984                 dc->out_ops->disable(dc);
1985
1986         clk_disable(dc->emc_clk);
1987         clk_disable(dc->clk);
1988         tegra_dvfs_set_rate(dc->clk, 0);
1989
1990         if (dc->out && dc->out->disable)
1991                 dc->out->disable();
1992
1993         /* flush any pending syncpt waits */
1994         while (dc->syncpt_min < dc->syncpt_max) {
1995                 dc->syncpt_min++;
1996                 nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt, dc->syncpt_id);
1997         }
1998 }
1999
2000 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2001 {
2002 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2003         u32 val;
2004         if (dc->enabled)  {
2005                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2006                 if (enable)
2007                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2008                 else
2009                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2010                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2011         }
2012 #endif
2013 }
2014
2015 bool tegra_dc_stats_get(struct tegra_dc *dc)
2016 {
2017 #if 0 /* right now it is always enabled */
2018         u32 val;
2019         bool res;
2020
2021         if (dc->enabled)  {
2022                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2023                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2024         } else {
2025                 res = false;
2026         }
2027
2028         return res;
2029 #endif
2030         return true;
2031 }
2032
2033 static void _tegra_dc_disable(struct tegra_dc *dc)
2034 {
2035         _tegra_dc_controller_disable(dc);
2036         tegra_dc_io_end(dc);
2037 }
2038
2039 void tegra_dc_disable(struct tegra_dc *dc)
2040 {
2041         if (dc->overlay)
2042                 tegra_overlay_disable(dc->overlay);
2043
2044         mutex_lock(&dc->lock);
2045
2046         if (dc->enabled) {
2047                 dc->enabled = false;
2048
2049                 if (!dc->suspended)
2050                         _tegra_dc_disable(dc);
2051         }
2052
2053         mutex_unlock(&dc->lock);
2054 }
2055
2056 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2057 static void tegra_dc_reset_worker(struct work_struct *work)
2058 {
2059         struct tegra_dc *dc =
2060                 container_of(work, struct tegra_dc, reset_work);
2061
2062         unsigned long val = 0;
2063
2064         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2065
2066         mutex_lock(&shared_lock);
2067         mutex_lock(&dc->lock);
2068
2069         if (dc->enabled == false)
2070                 goto unlock;
2071
2072         dc->enabled = false;
2073
2074         /*
2075          * off host read bus
2076          */
2077         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2078         val &= ~(0x00000100);
2079         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2080
2081         /*
2082          * set DC to STOP mode
2083          */
2084         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2085
2086         msleep(10);
2087
2088         _tegra_dc_controller_disable(dc);
2089
2090         /* _tegra_dc_controller_reset_enable deasserts reset */
2091         _tegra_dc_controller_reset_enable(dc);
2092
2093         dc->enabled = true;
2094 unlock:
2095         mutex_unlock(&dc->lock);
2096         mutex_unlock(&shared_lock);
2097 }
2098 #endif
2099
2100
2101 static int tegra_dc_probe(struct nvhost_device *ndev)
2102 {
2103         struct tegra_dc *dc;
2104         struct clk *clk;
2105         struct clk *emc_clk;
2106         struct resource *res;
2107         struct resource *base_res;
2108         struct resource *fb_mem = NULL;
2109         int ret = 0;
2110         void __iomem *base;
2111         int irq;
2112         int i;
2113
2114         if (!ndev->dev.platform_data) {
2115                 dev_err(&ndev->dev, "no platform data\n");
2116                 return -ENOENT;
2117         }
2118
2119         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2120         if (!dc) {
2121                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2122                 return -ENOMEM;
2123         }
2124
2125         irq = nvhost_get_irq_byname(ndev, "irq");
2126         if (irq <= 0) {
2127                 dev_err(&ndev->dev, "no irq\n");
2128                 ret = -ENOENT;
2129                 goto err_free;
2130         }
2131
2132         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2133         if (!res) {
2134                 dev_err(&ndev->dev, "no mem resource\n");
2135                 ret = -ENOENT;
2136                 goto err_free;
2137         }
2138
2139         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2140         if (!base_res) {
2141                 dev_err(&ndev->dev, "request_mem_region failed\n");
2142                 ret = -EBUSY;
2143                 goto err_free;
2144         }
2145
2146         base = ioremap(res->start, resource_size(res));
2147         if (!base) {
2148                 dev_err(&ndev->dev, "registers can't be mapped\n");
2149                 ret = -EBUSY;
2150                 goto err_release_resource_reg;
2151         }
2152
2153         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2154
2155         clk = clk_get(&ndev->dev, NULL);
2156         if (IS_ERR_OR_NULL(clk)) {
2157                 dev_err(&ndev->dev, "can't get clock\n");
2158                 ret = -ENOENT;
2159                 goto err_iounmap_reg;
2160         }
2161
2162         emc_clk = clk_get(&ndev->dev, "emc");
2163         if (IS_ERR_OR_NULL(emc_clk)) {
2164                 dev_err(&ndev->dev, "can't get emc clock\n");
2165                 ret = -ENOENT;
2166                 goto err_put_clk;
2167         }
2168
2169         dc->clk = clk;
2170         dc->emc_clk = emc_clk;
2171         INIT_DELAYED_WORK(&dc->reduce_emc_clk_work, tegra_dc_reduce_emc_worker);
2172
2173         dc->base_res = base_res;
2174         dc->base = base;
2175         dc->irq = irq;
2176         dc->ndev = ndev;
2177         dc->pdata = ndev->dev.platform_data;
2178
2179         /*
2180          * The emc is a shared clock, it will be set based on
2181          * the requirements for each user on the bus.
2182          */
2183         dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2184         clk_set_rate(emc_clk, dc->emc_clk_rate);
2185
2186         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2187                 dc->enabled = true;
2188
2189         mutex_init(&dc->lock);
2190         init_completion(&dc->vblank_complete);
2191         init_waitqueue_head(&dc->wq);
2192 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2193         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2194 #endif
2195         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2196
2197         dc->n_windows = DC_N_WINDOWS;
2198         for (i = 0; i < dc->n_windows; i++) {
2199                 dc->windows[i].idx = i;
2200                 dc->windows[i].dc = dc;
2201         }
2202
2203         if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2204                         dev_name(&ndev->dev), dc)) {
2205                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2206                 ret = -EBUSY;
2207                 goto err_put_emc_clk;
2208         }
2209
2210         /* hack to balance enable_irq calls in _tegra_dc_enable() */
2211         disable_dc_irq(dc->irq);
2212
2213         ret = tegra_dc_set(dc, ndev->id);
2214         if (ret < 0) {
2215                 dev_err(&ndev->dev, "can't add dc\n");
2216                 goto err_free_irq;
2217         }
2218
2219         nvhost_set_drvdata(ndev, dc);
2220
2221         if (dc->pdata->default_out)
2222                 tegra_dc_set_out(dc, dc->pdata->default_out);
2223         else
2224                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2225
2226         mutex_lock(&dc->lock);
2227         if (dc->enabled)
2228                 _tegra_dc_enable(dc);
2229         mutex_unlock(&dc->lock);
2230
2231         tegra_dc_create_debugfs(dc);
2232
2233         dev_info(&ndev->dev, "probed\n");
2234
2235         if (dc->pdata->fb) {
2236                 if (dc->pdata->fb->bits_per_pixel == -1) {
2237                         unsigned long fmt;
2238                         tegra_dc_writel(dc,
2239                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2240                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2241
2242                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2243                         dc->pdata->fb->bits_per_pixel =
2244                                 tegra_dc_fmt_bpp(fmt);
2245                 }
2246
2247                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2248                 if (IS_ERR_OR_NULL(dc->fb))
2249                         dc->fb = NULL;
2250         }
2251
2252         if (dc->fb) {
2253                 dc->overlay = tegra_overlay_register(ndev, dc);
2254                 if (IS_ERR_OR_NULL(dc->overlay))
2255                         dc->overlay = NULL;
2256         }
2257
2258         if (dc->out && dc->out->hotplug_init)
2259                 dc->out->hotplug_init();
2260
2261         if (dc->out_ops && dc->out_ops->detect)
2262                 dc->out_ops->detect(dc);
2263
2264         tegra_dc_create_sysfs(&dc->ndev->dev);
2265
2266         return 0;
2267
2268 err_free_irq:
2269         free_irq(irq, dc);
2270 err_put_emc_clk:
2271         clk_put(emc_clk);
2272 err_put_clk:
2273         clk_put(clk);
2274 err_iounmap_reg:
2275         iounmap(base);
2276         if (fb_mem)
2277                 release_resource(fb_mem);
2278 err_release_resource_reg:
2279         release_resource(base_res);
2280 err_free:
2281         kfree(dc);
2282
2283         return ret;
2284 }
2285
2286 static int tegra_dc_remove(struct nvhost_device *ndev)
2287 {
2288         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2289
2290         tegra_dc_remove_sysfs(&dc->ndev->dev);
2291         tegra_dc_remove_debugfs(dc);
2292
2293         if (dc->overlay) {
2294                 tegra_overlay_unregister(dc->overlay);
2295         }
2296
2297         if (dc->fb) {
2298                 tegra_fb_unregister(dc->fb);
2299                 if (dc->fb_mem)
2300                         release_resource(dc->fb_mem);
2301         }
2302
2303
2304         if (dc->enabled)
2305                 _tegra_dc_disable(dc);
2306
2307         free_irq(dc->irq, dc);
2308         clk_put(dc->emc_clk);
2309         clk_put(dc->clk);
2310         iounmap(dc->base);
2311         if (dc->fb_mem)
2312                 release_resource(dc->base_res);
2313         kfree(dc);
2314         tegra_dc_set(NULL, ndev->id);
2315         return 0;
2316 }
2317
2318 #ifdef CONFIG_PM
2319 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2320 {
2321         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2322
2323         dev_info(&ndev->dev, "suspend\n");
2324
2325         if (dc->overlay)
2326                 tegra_overlay_disable(dc->overlay);
2327
2328         mutex_lock(&dc->lock);
2329
2330         if (dc->out_ops && dc->out_ops->suspend)
2331                 dc->out_ops->suspend(dc);
2332
2333         if (dc->enabled) {
2334                 tegra_fb_suspend(dc->fb);
2335                 _tegra_dc_disable(dc);
2336
2337                 dc->suspended = true;
2338         }
2339
2340         if (dc->out && dc->out->postsuspend) {
2341                 dc->out->postsuspend();
2342                 msleep(100); /* avoid resume event due to voltage falling */
2343         }
2344
2345         mutex_unlock(&dc->lock);
2346
2347         return 0;
2348 }
2349
2350 static int tegra_dc_resume(struct nvhost_device *ndev)
2351 {
2352         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2353
2354         dev_info(&ndev->dev, "resume\n");
2355
2356         mutex_lock(&dc->lock);
2357         dc->suspended = false;
2358
2359         if (dc->enabled)
2360                 _tegra_dc_enable(dc);
2361
2362         if (dc->out && dc->out->hotplug_init)
2363                 dc->out->hotplug_init();
2364
2365         if (dc->out_ops && dc->out_ops->resume)
2366                 dc->out_ops->resume(dc);
2367         mutex_unlock(&dc->lock);
2368
2369         return 0;
2370 }
2371
2372 #endif /* CONFIG_PM */
2373
2374 extern int suspend_set(const char *val, struct kernel_param *kp)
2375 {
2376         if (!strcmp(val, "dump"))
2377                 dump_regs(tegra_dcs[0]);
2378 #ifdef CONFIG_PM
2379         else if (!strcmp(val, "suspend"))
2380                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2381         else if (!strcmp(val, "resume"))
2382                 tegra_dc_resume(tegra_dcs[0]->ndev);
2383 #endif
2384
2385         return 0;
2386 }
2387
2388 extern int suspend_get(char *buffer, struct kernel_param *kp)
2389 {
2390         return 0;
2391 }
2392
2393 int suspend;
2394
2395 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2396
2397 struct nvhost_driver tegra_dc_driver = {
2398         .driver = {
2399                 .name = "tegradc",
2400                 .owner = THIS_MODULE,
2401         },
2402         .probe = tegra_dc_probe,
2403         .remove = tegra_dc_remove,
2404 #ifdef CONFIG_PM
2405         .suspend = tegra_dc_suspend,
2406         .resume = tegra_dc_resume,
2407 #endif
2408 };
2409
2410 static int __init tegra_dc_module_init(void)
2411 {
2412         return nvhost_driver_register(&tegra_dc_driver);
2413 }
2414
2415 static void __exit tegra_dc_module_exit(void)
2416 {
2417         nvhost_driver_unregister(&tegra_dc_driver);
2418 }
2419
2420 module_exit(tegra_dc_module_exit);
2421 module_init(tegra_dc_module_init);