Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "nvsd.h"
56
57 #define TEGRA_CRC_LATCHED_DELAY         34
58
59 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
60 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
61
62 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
63         .refresh = 60,
64         .xres = 640,
65         .yres = 480,
66         .pixclock = KHZ2PICOS(25200),
67         .hsync_len = 96,        /* h_sync_width */
68         .vsync_len = 2,         /* v_sync_width */
69         .left_margin = 48,      /* h_back_porch */
70         .upper_margin = 33,     /* v_back_porch */
71         .right_margin = 16,     /* h_front_porch */
72         .lower_margin = 10,     /* v_front_porch */
73         .vmode = 0,
74         .sync = 0,
75 };
76
77 static struct tegra_dc_mode override_disp_mode[3];
78
79 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
80
81 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
82
83 DEFINE_MUTEX(tegra_dc_lock);
84 DEFINE_MUTEX(shared_lock);
85
86 static const struct {
87         bool h;
88         bool v;
89 } can_filter[] = {
90         /* Window A has no filtering */
91         { false, false },
92         /* Window B has both H and V filtering */
93         { true,  true  },
94         /* Window C has only H filtering */
95         { false, true  },
96 };
97
98 #ifdef CONFIG_TEGRA_DC_CMU
99 static struct tegra_dc_cmu default_cmu = {
100         /* lut1 maps sRGB to linear space. */
101         {
102                 0,    1,    2,    4,    5,    6,    7,    9,
103                 10,   11,   12,   14,   15,   16,   18,   20,
104                 21,   23,   25,   27,   29,   31,   33,   35,
105                 37,   40,   42,   45,   48,   50,   53,   56,
106                 59,   62,   66,   69,   72,   76,   79,   83,
107                 87,   91,   95,   99,   103,  107,  112,  116,
108                 121,  126,  131,  136,  141,  146,  151,  156,
109                 162,  168,  173,  179,  185,  191,  197,  204,
110                 210,  216,  223,  230,  237,  244,  251,  258,
111                 265,  273,  280,  288,  296,  304,  312,  320,
112                 329,  337,  346,  354,  363,  372,  381,  390,
113                 400,  409,  419,  428,  438,  448,  458,  469,
114                 479,  490,  500,  511,  522,  533,  544,  555,
115                 567,  578,  590,  602,  614,  626,  639,  651,
116                 664,  676,  689,  702,  715,  728,  742,  755,
117                 769,  783,  797,  811,  825,  840,  854,  869,
118                 884,  899,  914,  929,  945,  960,  976,  992,
119                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
120                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
121                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
122                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
123                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
124                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
125                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
126                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
127                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
128                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
129                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
130                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
131                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
132                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
133                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
134         },
135         /* csc */
136         {
137                 0x100, 0x0,   0x0,
138                 0x0,   0x100, 0x0,
139                 0x0,   0x0,   0x100,
140         },
141         /* lut2 maps linear space to sRGB*/
142         {
143                 0,    1,    2,    2,    3,    4,    5,    6,
144                 6,    7,    8,    9,    10,   10,   11,   12,
145                 13,   13,   14,   15,   15,   16,   16,   17,
146                 18,   18,   19,   19,   20,   20,   21,   21,
147                 22,   22,   23,   23,   23,   24,   24,   25,
148                 25,   25,   26,   26,   27,   27,   27,   28,
149                 28,   29,   29,   29,   30,   30,   30,   31,
150                 31,   31,   32,   32,   32,   33,   33,   33,
151                 34,   34,   34,   34,   35,   35,   35,   36,
152                 36,   36,   37,   37,   37,   37,   38,   38,
153                 38,   38,   39,   39,   39,   40,   40,   40,
154                 40,   41,   41,   41,   41,   42,   42,   42,
155                 42,   43,   43,   43,   43,   43,   44,   44,
156                 44,   44,   45,   45,   45,   45,   46,   46,
157                 46,   46,   46,   47,   47,   47,   47,   48,
158                 48,   48,   48,   48,   49,   49,   49,   49,
159                 49,   50,   50,   50,   50,   50,   51,   51,
160                 51,   51,   51,   52,   52,   52,   52,   52,
161                 53,   53,   53,   53,   53,   54,   54,   54,
162                 54,   54,   55,   55,   55,   55,   55,   55,
163                 56,   56,   56,   56,   56,   57,   57,   57,
164                 57,   57,   57,   58,   58,   58,   58,   58,
165                 58,   59,   59,   59,   59,   59,   59,   60,
166                 60,   60,   60,   60,   60,   61,   61,   61,
167                 61,   61,   61,   62,   62,   62,   62,   62,
168                 62,   63,   63,   63,   63,   63,   63,   64,
169                 64,   64,   64,   64,   64,   64,   65,   65,
170                 65,   65,   65,   65,   66,   66,   66,   66,
171                 66,   66,   66,   67,   67,   67,   67,   67,
172                 67,   67,   68,   68,   68,   68,   68,   68,
173                 68,   69,   69,   69,   69,   69,   69,   69,
174                 70,   70,   70,   70,   70,   70,   70,   71,
175                 71,   71,   71,   71,   71,   71,   72,   72,
176                 72,   72,   72,   72,   72,   72,   73,   73,
177                 73,   73,   73,   73,   73,   74,   74,   74,
178                 74,   74,   74,   74,   74,   75,   75,   75,
179                 75,   75,   75,   75,   75,   76,   76,   76,
180                 76,   76,   76,   76,   77,   77,   77,   77,
181                 77,   77,   77,   77,   78,   78,   78,   78,
182                 78,   78,   78,   78,   78,   79,   79,   79,
183                 79,   79,   79,   79,   79,   80,   80,   80,
184                 80,   80,   80,   80,   80,   81,   81,   81,
185                 81,   81,   81,   81,   81,   81,   82,   82,
186                 82,   82,   82,   82,   82,   82,   83,   83,
187                 83,   83,   83,   83,   83,   83,   83,   84,
188                 84,   84,   84,   84,   84,   84,   84,   84,
189                 85,   85,   85,   85,   85,   85,   85,   85,
190                 85,   86,   86,   86,   86,   86,   86,   86,
191                 86,   86,   87,   87,   87,   87,   87,   87,
192                 87,   87,   87,   88,   88,   88,   88,   88,
193                 88,   88,   88,   88,   88,   89,   89,   89,
194                 89,   89,   89,   89,   89,   89,   90,   90,
195                 90,   90,   90,   90,   90,   90,   90,   90,
196                 91,   91,   91,   91,   91,   91,   91,   91,
197                 91,   91,   92,   92,   92,   92,   92,   92,
198                 92,   92,   92,   92,   93,   93,   93,   93,
199                 93,   93,   93,   93,   93,   93,   94,   94,
200                 94,   94,   94,   94,   94,   94,   94,   94,
201                 95,   95,   95,   95,   95,   95,   95,   95,
202                 95,   95,   96,   96,   96,   96,   96,   96,
203                 96,   96,   96,   96,   96,   97,   97,   97,
204                 97,   97,   97,   97,   97,   97,   97,   98,
205                 98,   98,   98,   98,   98,   98,   98,   98,
206                 98,   98,   99,   99,   99,   99,   99,   99,
207                 99,   100,  101,  101,  102,  103,  103,  104,
208                 105,  105,  106,  107,  107,  108,  109,  109,
209                 110,  111,  111,  112,  113,  113,  114,  115,
210                 115,  116,  116,  117,  118,  118,  119,  119,
211                 120,  120,  121,  122,  122,  123,  123,  124,
212                 124,  125,  126,  126,  127,  127,  128,  128,
213                 129,  129,  130,  130,  131,  131,  132,  132,
214                 133,  133,  134,  134,  135,  135,  136,  136,
215                 137,  137,  138,  138,  139,  139,  140,  140,
216                 141,  141,  142,  142,  143,  143,  144,  144,
217                 145,  145,  145,  146,  146,  147,  147,  148,
218                 148,  149,  149,  150,  150,  150,  151,  151,
219                 152,  152,  153,  153,  153,  154,  154,  155,
220                 155,  156,  156,  156,  157,  157,  158,  158,
221                 158,  159,  159,  160,  160,  160,  161,  161,
222                 162,  162,  162,  163,  163,  164,  164,  164,
223                 165,  165,  166,  166,  166,  167,  167,  167,
224                 168,  168,  169,  169,  169,  170,  170,  170,
225                 171,  171,  172,  172,  172,  173,  173,  173,
226                 174,  174,  174,  175,  175,  176,  176,  176,
227                 177,  177,  177,  178,  178,  178,  179,  179,
228                 179,  180,  180,  180,  181,  181,  182,  182,
229                 182,  183,  183,  183,  184,  184,  184,  185,
230                 185,  185,  186,  186,  186,  187,  187,  187,
231                 188,  188,  188,  189,  189,  189,  189,  190,
232                 190,  190,  191,  191,  191,  192,  192,  192,
233                 193,  193,  193,  194,  194,  194,  195,  195,
234                 195,  196,  196,  196,  196,  197,  197,  197,
235                 198,  198,  198,  199,  199,  199,  200,  200,
236                 200,  200,  201,  201,  201,  202,  202,  202,
237                 202,  203,  203,  203,  204,  204,  204,  205,
238                 205,  205,  205,  206,  206,  206,  207,  207,
239                 207,  207,  208,  208,  208,  209,  209,  209,
240                 209,  210,  210,  210,  211,  211,  211,  211,
241                 212,  212,  212,  213,  213,  213,  213,  214,
242                 214,  214,  214,  215,  215,  215,  216,  216,
243                 216,  216,  217,  217,  217,  217,  218,  218,
244                 218,  219,  219,  219,  219,  220,  220,  220,
245                 220,  221,  221,  221,  221,  222,  222,  222,
246                 223,  223,  223,  223,  224,  224,  224,  224,
247                 225,  225,  225,  225,  226,  226,  226,  226,
248                 227,  227,  227,  227,  228,  228,  228,  228,
249                 229,  229,  229,  229,  230,  230,  230,  230,
250                 231,  231,  231,  231,  232,  232,  232,  232,
251                 233,  233,  233,  233,  234,  234,  234,  234,
252                 235,  235,  235,  235,  236,  236,  236,  236,
253                 237,  237,  237,  237,  238,  238,  238,  238,
254                 239,  239,  239,  239,  240,  240,  240,  240,
255                 240,  241,  241,  241,  241,  242,  242,  242,
256                 242,  243,  243,  243,  243,  244,  244,  244,
257                 244,  244,  245,  245,  245,  245,  246,  246,
258                 246,  246,  247,  247,  247,  247,  247,  248,
259                 248,  248,  248,  249,  249,  249,  249,  249,
260                 250,  250,  250,  250,  251,  251,  251,  251,
261                 251,  252,  252,  252,  252,  253,  253,  253,
262                 253,  253,  254,  254,  254,  254,  255,  255,
263         },
264 };
265 #endif
266
267 void tegra_dc_clk_enable(struct tegra_dc *dc)
268 {
269         if (!tegra_is_clk_enabled(dc->clk)) {
270                 clk_enable(dc->clk);
271                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
272         }
273 }
274
275 void tegra_dc_clk_disable(struct tegra_dc *dc)
276 {
277         if (tegra_is_clk_enabled(dc->clk)) {
278                 clk_disable(dc->clk);
279                 tegra_dvfs_set_rate(dc->clk, 0);
280         }
281 }
282
283 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
284 {
285         if (dc->out_ops->hold)
286                 dc->out_ops->hold(dc);
287 }
288
289 void tegra_dc_release_dc_out(struct tegra_dc *dc)
290 {
291         if (dc->out_ops->release)
292                 dc->out_ops->release(dc);
293 }
294
295 #define DUMP_REG(a) do {                        \
296         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
297                  #a, a, tegra_dc_readl(dc, a));               \
298         print(data, buff);                                    \
299         } while (0)
300
301 #define print_underflow_info(dc) do {                 \
302         trace_printk("%s:Underflow stats: underflows : %llu, "      \
303                         "undeflows_a : %llu, "                          \
304                         "underflows_b : %llu, "                         \
305                         "underflows_c : %llu\n",                        \
306                         dc->ndev->name,                                 \
307                         dc->stats.underflows,                           \
308                         dc->stats.underflows_a, dc->stats.underflows_b, \
309                         dc->stats.underflows_c);                        \
310         } while (0)
311
312 static void _dump_regs(struct tegra_dc *dc, void *data,
313                        void (* print)(void *data, const char *str))
314 {
315         int i;
316         char buff[256];
317
318         mutex_lock(&dc->lock);
319         tegra_dc_hold_dc_out(dc);
320         tegra_dc_io_start(dc);
321
322         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
323         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE);
325         DUMP_REG(DC_CMD_INT_STATUS);
326         DUMP_REG(DC_CMD_INT_MASK);
327         DUMP_REG(DC_CMD_INT_ENABLE);
328         DUMP_REG(DC_CMD_INT_TYPE);
329         DUMP_REG(DC_CMD_INT_POLARITY);
330         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
331         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
332         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
333         DUMP_REG(DC_CMD_STATE_ACCESS);
334         DUMP_REG(DC_CMD_STATE_CONTROL);
335         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
336         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
337
338         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
339         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
340         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
341         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
342         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
343         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
344         DUMP_REG(DC_DISP_REF_TO_SYNC);
345         DUMP_REG(DC_DISP_SYNC_WIDTH);
346         DUMP_REG(DC_DISP_BACK_PORCH);
347         DUMP_REG(DC_DISP_DISP_ACTIVE);
348         DUMP_REG(DC_DISP_FRONT_PORCH);
349         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
350         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
351         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
352         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
353         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
354         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
355         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
356         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
357         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
358         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
359         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
360         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
361         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
362         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
363         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
364         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
367         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
368         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
369         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
370         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
371         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
372         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
373         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
374         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
375         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
376         DUMP_REG(DC_DISP_M0_CONTROL);
377         DUMP_REG(DC_DISP_M1_CONTROL);
378         DUMP_REG(DC_DISP_DI_CONTROL);
379         DUMP_REG(DC_DISP_PP_CONTROL);
380         DUMP_REG(DC_DISP_PP_SELECT_A);
381         DUMP_REG(DC_DISP_PP_SELECT_B);
382         DUMP_REG(DC_DISP_PP_SELECT_C);
383         DUMP_REG(DC_DISP_PP_SELECT_D);
384         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
385         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
386         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
387         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
388         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
389         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
390         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
391         DUMP_REG(DC_DISP_BORDER_COLOR);
392         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
393         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
394         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
395         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
396         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
397         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
398         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
399         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
400         DUMP_REG(DC_DISP_CURSOR_POSITION);
401         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
402         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
403         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
404         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
405         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
406         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
407         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
408         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
409         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
410         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
411         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
412         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
413         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
414
415
416         for (i = 0; i < 3; i++) {
417                 print(data, "\n");
418                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
419                 print(data, buff);
420
421                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
422                                 DC_CMD_DISPLAY_WINDOW_HEADER);
423                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
424                 DUMP_REG(DC_WIN_WIN_OPTIONS);
425                 DUMP_REG(DC_WIN_BYTE_SWAP);
426                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
427                 DUMP_REG(DC_WIN_COLOR_DEPTH);
428                 DUMP_REG(DC_WIN_POSITION);
429                 DUMP_REG(DC_WIN_SIZE);
430                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
431                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
432                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
433                 DUMP_REG(DC_WIN_DDA_INCREMENT);
434                 DUMP_REG(DC_WIN_LINE_STRIDE);
435 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
436                 DUMP_REG(DC_WIN_BUF_STRIDE);
437                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
438 #endif
439                 DUMP_REG(DC_WIN_BLEND_NOKEY);
440                 DUMP_REG(DC_WIN_BLEND_1WIN);
441                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
442                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
443                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
444                 DUMP_REG(DC_WINBUF_START_ADDR);
445                 DUMP_REG(DC_WINBUF_START_ADDR_U);
446                 DUMP_REG(DC_WINBUF_START_ADDR_V);
447                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
448                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
449                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
450                 DUMP_REG(DC_WIN_CSC_YOF);
451                 DUMP_REG(DC_WIN_CSC_KYRGB);
452                 DUMP_REG(DC_WIN_CSC_KUR);
453                 DUMP_REG(DC_WIN_CSC_KVR);
454                 DUMP_REG(DC_WIN_CSC_KUG);
455                 DUMP_REG(DC_WIN_CSC_KVG);
456                 DUMP_REG(DC_WIN_CSC_KUB);
457                 DUMP_REG(DC_WIN_CSC_KVB);
458         }
459
460         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
461         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
462         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
463         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
464         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
465         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
466         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
467         DUMP_REG(DC_DISP_M1_CONTROL);
468         DUMP_REG(DC_COM_PM1_CONTROL);
469         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
470         DUMP_REG(DC_DISP_SD_CONTROL);
471
472         tegra_dc_io_end(dc);
473         tegra_dc_release_dc_out(dc);
474         mutex_unlock(&dc->lock);
475 }
476
477 #undef DUMP_REG
478
479 #ifdef DEBUG
480 static void dump_regs_print(void *data, const char *str)
481 {
482         struct tegra_dc *dc = data;
483         dev_dbg(&dc->ndev->dev, "%s", str);
484 }
485
486 static void dump_regs(struct tegra_dc *dc)
487 {
488         _dump_regs(dc, dc, dump_regs_print);
489 }
490 #else /* !DEBUG */
491
492 static void dump_regs(struct tegra_dc *dc) {}
493
494 #endif /* DEBUG */
495
496 #ifdef CONFIG_DEBUG_FS
497
498 static void dbg_regs_print(void *data, const char *str)
499 {
500         struct seq_file *s = data;
501
502         seq_printf(s, "%s", str);
503 }
504
505 #undef DUMP_REG
506
507 static int dbg_dc_show(struct seq_file *s, void *unused)
508 {
509         struct tegra_dc *dc = s->private;
510
511         _dump_regs(dc, s, dbg_regs_print);
512
513         return 0;
514 }
515
516
517 static int dbg_dc_open(struct inode *inode, struct file *file)
518 {
519         return single_open(file, dbg_dc_show, inode->i_private);
520 }
521
522 static const struct file_operations regs_fops = {
523         .open           = dbg_dc_open,
524         .read           = seq_read,
525         .llseek         = seq_lseek,
526         .release        = single_release,
527 };
528
529 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
530 {
531         struct tegra_dc *dc = s->private;
532         struct tegra_dc_mode *m;
533
534         mutex_lock(&dc->lock);
535         m = &dc->mode;
536         seq_printf(s,
537                 "pclk: %d\n"
538                 "h_ref_to_sync: %d\n"
539                 "v_ref_to_sync: %d\n"
540                 "h_sync_width: %d\n"
541                 "v_sync_width: %d\n"
542                 "h_back_porch: %d\n"
543                 "v_back_porch: %d\n"
544                 "h_active: %d\n"
545                 "v_active: %d\n"
546                 "h_front_porch: %d\n"
547                 "v_front_porch: %d\n"
548                 "stereo_mode: %d\n",
549                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
550                 m->h_sync_width, m->v_sync_width,
551                 m->h_back_porch, m->v_back_porch,
552                 m->h_active, m->v_active,
553                 m->h_front_porch, m->v_front_porch,
554                 m->stereo_mode);
555         mutex_unlock(&dc->lock);
556         return 0;
557 }
558
559 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
560 {
561         return single_open(file, dbg_dc_mode_show, inode->i_private);
562 }
563
564 static const struct file_operations mode_fops = {
565         .open           = dbg_dc_mode_open,
566         .read           = seq_read,
567         .llseek         = seq_lseek,
568         .release        = single_release,
569 };
570
571 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
572 {
573         struct tegra_dc *dc = s->private;
574
575         mutex_lock(&dc->lock);
576         seq_printf(s,
577                 "underflows: %llu\n"
578                 "underflows_a: %llu\n"
579                 "underflows_b: %llu\n"
580                 "underflows_c: %llu\n",
581                 dc->stats.underflows,
582                 dc->stats.underflows_a,
583                 dc->stats.underflows_b,
584                 dc->stats.underflows_c);
585         mutex_unlock(&dc->lock);
586
587         return 0;
588 }
589
590 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
591 {
592         return single_open(file, dbg_dc_stats_show, inode->i_private);
593 }
594
595 static const struct file_operations stats_fops = {
596         .open           = dbg_dc_stats_open,
597         .read           = seq_read,
598         .llseek         = seq_lseek,
599         .release        = single_release,
600 };
601
602 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
603 {
604         if (dc->debugdir)
605                 debugfs_remove_recursive(dc->debugdir);
606         dc->debugdir = NULL;
607 }
608
609 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
610 {
611         struct dentry *retval;
612
613         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
614         if (!dc->debugdir)
615                 goto remove_out;
616
617         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
618                 &regs_fops);
619         if (!retval)
620                 goto remove_out;
621
622         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
623                 &mode_fops);
624         if (!retval)
625                 goto remove_out;
626
627         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
628                 &stats_fops);
629         if (!retval)
630                 goto remove_out;
631
632         return;
633 remove_out:
634         dev_err(&dc->ndev->dev, "could not create debugfs\n");
635         tegra_dc_remove_debugfs(dc);
636 }
637
638 #else /* !CONFIG_DEBUGFS */
639 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
640 static inline void __devexit tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
641 #endif /* CONFIG_DEBUGFS */
642
643 static int tegra_dc_set(struct tegra_dc *dc, int index)
644 {
645         int ret = 0;
646
647         mutex_lock(&tegra_dc_lock);
648         if (index >= TEGRA_MAX_DC) {
649                 ret = -EINVAL;
650                 goto out;
651         }
652
653         if (dc != NULL && tegra_dcs[index] != NULL) {
654                 ret = -EBUSY;
655                 goto out;
656         }
657
658         tegra_dcs[index] = dc;
659
660 out:
661         mutex_unlock(&tegra_dc_lock);
662
663         return ret;
664 }
665
666 unsigned int tegra_dc_has_multiple_dc(void)
667 {
668         unsigned int idx;
669         unsigned int cnt = 0;
670         struct tegra_dc *dc;
671
672         mutex_lock(&tegra_dc_lock);
673         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
674                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
675         mutex_unlock(&tegra_dc_lock);
676
677         return (cnt > 1);
678 }
679
680 /* get the stride size of a window.
681  * return: stride size in bytes for window win. or 0 if unavailble. */
682 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
683 {
684         u32 stride;
685
686         if (!dc->enabled)
687                 return 0;
688         BUG_ON(win > DC_N_WINDOWS);
689         mutex_lock(&dc->lock);
690         tegra_dc_hold_dc_out(dc);
691         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
692                 DC_CMD_DISPLAY_WINDOW_HEADER);
693         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
694         tegra_dc_release_dc_out(dc);
695         mutex_unlock(&dc->lock);
696         return GET_LINE_STRIDE(stride);
697 }
698 EXPORT_SYMBOL(tegra_dc_get_stride);
699
700 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
701 {
702         if (idx < TEGRA_MAX_DC)
703                 return tegra_dcs[idx];
704         else
705                 return NULL;
706 }
707 EXPORT_SYMBOL(tegra_dc_get_dc);
708
709 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
710 {
711         if (win >= dc->n_windows)
712                 return NULL;
713
714         return &dc->windows[win];
715 }
716 EXPORT_SYMBOL(tegra_dc_get_window);
717
718 bool tegra_dc_get_connected(struct tegra_dc *dc)
719 {
720         return dc->connected;
721 }
722 EXPORT_SYMBOL(tegra_dc_get_connected);
723
724 bool tegra_dc_hpd(struct tegra_dc *dc)
725 {
726         int sense;
727         int level;
728
729         level = gpio_get_value(dc->out->hotplug_gpio);
730
731         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
732
733         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
734                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
735 }
736 EXPORT_SYMBOL(tegra_dc_hpd);
737
738 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
739 {
740         unsigned i;
741         unsigned v0 = 128;
742         unsigned v1 = 0;
743         /* linear horizontal and vertical filters */
744         for (i = 0; i < 16; i++) {
745                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
746                                 DC_WIN_H_FILTER_P(i));
747
748                 tegra_dc_writel(dc, v0,
749                                 DC_WIN_V_FILTER_P(i));
750                 v0 -= 8;
751                 v1 += 8;
752         }
753 }
754
755 #ifdef CONFIG_TEGRA_DC_CMU
756 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
757                                                 struct tegra_dc_cmu *src_cmu)
758 {
759         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
760 }
761
762 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
763 {
764         u32 val;
765         u32 i;
766
767         for (i = 0; i < 256; i++) {
768                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
769                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
770         }
771
772         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
773         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
774         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
775         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
776         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
777         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
778         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
779         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
780         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
781
782         for (i = 0; i < 960; i++) {
783                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
784                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
785         }
786 }
787
788 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
789 {
790         u32 val;
791         u32 i;
792         bool flags;
793
794         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
795         if (val & CMU_ENABLE)
796                 flags = true;
797
798         val &= ~CMU_ENABLE;
799         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
800         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
801         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
802
803         /*TODO: Sync up with frame end */
804         mdelay(20);
805
806         for (i = 0; i < 256; i++) {
807                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
808                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
809                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
810                 cmu->lut1[i] = LUT1_READ_DATA(val);
811         }
812
813         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
814         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
815         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
816         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
817         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
818         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
819         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
820         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
821         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
822
823         for (i = 0; i < 960; i++) {
824                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
825                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
826                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
827                 cmu->lut2[i] = LUT2_READ_DATA(val);
828         }
829 }
830 EXPORT_SYMBOL(tegra_dc_get_cmu);
831
832 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
833 {
834         mutex_lock(&dc->lock);
835
836         if (!dc->enabled) {
837                 mutex_unlock(&dc->lock);
838                 return -EFAULT;
839         }
840
841         if (cmu_enable) {
842                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
843         } else {
844                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
845                 return 0;
846         }
847
848         tegra_dc_set_cmu(dc, &dc->cmu);
849
850         mutex_unlock(&dc->lock);
851
852         return 0;
853 }
854 EXPORT_SYMBOL(tegra_dc_update_cmu);
855 #else
856 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
857 #define tegra_dc_set_cmu(dc, cmu)
858 #endif
859
860 static inline void disable_dc_irq(unsigned int irq)
861 {
862         disable_irq(irq);
863 }
864
865 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
866 {
867         return dc->syncpt[i].id;
868 }
869 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
870
871 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
872 {
873         u32 max;
874
875         mutex_lock(&dc->lock);
876         tegra_dc_hold_dc_out(dc);
877         max = nvhost_syncpt_incr_max_ext(dc->ndev,
878                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
879         dc->syncpt[i].max = max;
880         tegra_dc_release_dc_out(dc);
881         mutex_unlock(&dc->lock);
882
883         return max;
884 }
885
886 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
887 {
888         mutex_lock(&dc->lock);
889         if (dc->enabled) {
890                 tegra_dc_hold_dc_out(dc);
891                 while (dc->syncpt[i].min < val) {
892                         dc->syncpt[i].min++;
893                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
894                 }
895                 tegra_dc_release_dc_out(dc);
896         }
897         mutex_unlock(&dc->lock);
898 }
899
900 void
901 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
902 {
903         unsigned int ctrl;
904         unsigned long out_sel;
905         unsigned long cmd_state;
906
907         mutex_lock(&dc->lock);
908         if (!dc->enabled) {
909                 mutex_unlock(&dc->lock);
910                 return;
911         }
912
913         tegra_dc_hold_dc_out(dc);
914
915         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
916                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
917                 cfg->clk_select);
918
919         /* The new value should be effected immediately */
920         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
921         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
922
923         switch (cfg->which_pwm) {
924         case TEGRA_PWM_PM0:
925                 /* Select the LM0 on PM0 */
926                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
927                 out_sel &= ~(7 << 0);
928                 out_sel |= (3 << 0);
929                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
930                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
931                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
932                 break;
933         case TEGRA_PWM_PM1:
934                 /* Select the LM1 on PM1 */
935                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
936                 out_sel &= ~(7 << 4);
937                 out_sel |= (3 << 4);
938                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
939                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
940                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
941                 break;
942         default:
943                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
944                 break;
945         }
946         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
947         tegra_dc_release_dc_out(dc);
948         mutex_unlock(&dc->lock);
949 }
950 EXPORT_SYMBOL(tegra_dc_config_pwm);
951
952 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
953                                 const struct tegra_dc_out_pin *pins,
954                                 const unsigned int n_pins)
955 {
956         unsigned int i;
957
958         int name;
959         int pol;
960
961         u32 pol1, pol3;
962
963         u32 set1, unset1;
964         u32 set3, unset3;
965
966         set1 = set3 = unset1 = unset3 = 0;
967
968         for (i = 0; i < n_pins; i++) {
969                 name = (pins + i)->name;
970                 pol  = (pins + i)->pol;
971
972                 /* set polarity by name */
973                 switch (name) {
974                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
975                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
976                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
977                         else
978                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
979                         break;
980                 case TEGRA_DC_OUT_PIN_H_SYNC:
981                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
982                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
983                         else
984                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
985                         break;
986                 case TEGRA_DC_OUT_PIN_V_SYNC:
987                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
988                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
989                         else
990                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
991                         break;
992                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
993                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
994                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
995                         else
996                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
997                         break;
998                 default:
999                         printk("Invalid argument in function %s\n",
1000                                __FUNCTION__);
1001                         break;
1002                 }
1003         }
1004
1005         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1006         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1007
1008         pol1 |= set1;
1009         pol1 &= ~unset1;
1010
1011         pol3 |= set3;
1012         pol3 &= ~unset3;
1013
1014         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1015         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1016 }
1017
1018 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1019 {
1020         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1021                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1022                 dc->out->type == TEGRA_DC_OUT_DSI)
1023                 return override_disp_mode[dc->out->type].pclk ?
1024                         &override_disp_mode[dc->out->type] : NULL;
1025         else
1026                 return NULL;
1027 }
1028
1029 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1030 {
1031         struct tegra_dc_mode *mode;
1032
1033         dc->out = out;
1034         mode = tegra_dc_get_override_mode(dc);
1035
1036         if (mode)
1037                 tegra_dc_set_mode(dc, mode);
1038         else if (out->n_modes > 0)
1039                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1040
1041         switch (out->type) {
1042         case TEGRA_DC_OUT_RGB:
1043                 dc->out_ops = &tegra_dc_rgb_ops;
1044                 break;
1045
1046         case TEGRA_DC_OUT_HDMI:
1047                 dc->out_ops = &tegra_dc_hdmi_ops;
1048                 break;
1049
1050         case TEGRA_DC_OUT_DSI:
1051                 dc->out_ops = &tegra_dc_dsi_ops;
1052                 break;
1053
1054         default:
1055                 dc->out_ops = NULL;
1056                 break;
1057         }
1058
1059         if (dc->out_ops && dc->out_ops->init)
1060                 dc->out_ops->init(dc);
1061
1062 }
1063
1064 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1065 {
1066         if (dc->out)
1067                 return dc->out->height;
1068         else
1069                 return 0;
1070 }
1071 EXPORT_SYMBOL(tegra_dc_get_out_height);
1072
1073 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1074 {
1075         if (dc->out)
1076                 return dc->out->width;
1077         else
1078                 return 0;
1079 }
1080 EXPORT_SYMBOL(tegra_dc_get_out_width);
1081
1082 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1083 {
1084         if (dc->out && dc->out->max_pixclock)
1085                 return dc->out->max_pixclock;
1086         else
1087                 return 0;
1088 }
1089 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1090
1091 void tegra_dc_enable_crc(struct tegra_dc *dc)
1092 {
1093         u32 val;
1094
1095         mutex_lock(&dc->lock);
1096         tegra_dc_hold_dc_out(dc);
1097         tegra_dc_io_start(dc);
1098
1099         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1100                 CRC_ENABLE_ENABLE;
1101         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1102         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1103         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1104         tegra_dc_release_dc_out(dc);
1105         mutex_unlock(&dc->lock);
1106 }
1107
1108 void tegra_dc_disable_crc(struct tegra_dc *dc)
1109 {
1110         mutex_lock(&dc->lock);
1111         tegra_dc_hold_dc_out(dc);
1112         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1113         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1114         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1115
1116         tegra_dc_io_end(dc);
1117         tegra_dc_release_dc_out(dc);
1118         mutex_unlock(&dc->lock);
1119 }
1120
1121 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1122 {
1123         int crc = 0;
1124
1125         if (!dc) {
1126                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1127                 goto crc_error;
1128         }
1129
1130 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1131         /* TODO: Replace mdelay with code to sync VBlANK, since
1132          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1133         mdelay(TEGRA_CRC_LATCHED_DELAY);
1134 #endif
1135
1136         mutex_lock(&dc->lock);
1137         tegra_dc_hold_dc_out(dc);
1138         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1139         tegra_dc_release_dc_out(dc);
1140         mutex_unlock(&dc->lock);
1141 crc_error:
1142         return crc;
1143 }
1144
1145 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1146 {
1147 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1148         u32 val;
1149
1150         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1151         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1152             return true;
1153 #endif
1154         return false;
1155 }
1156
1157 static inline void enable_dc_irq(unsigned int irq)
1158 {
1159 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1160         enable_irq(irq);
1161 #else
1162         /* Always disable DC interrupts on FPGA. */
1163         disable_irq(irq);
1164 #endif
1165 }
1166
1167 static void tegra_dc_vblank(struct work_struct *work)
1168 {
1169         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1170         bool nvsd_updated = false;
1171
1172         mutex_lock(&dc->lock);
1173
1174         if (!dc->enabled) {
1175                 mutex_unlock(&dc->lock);
1176                 return;
1177         }
1178
1179         tegra_dc_hold_dc_out(dc);
1180         /* use the new frame's bandwidth setting instead of max(current, new),
1181          * skip this if we're using tegra_dc_one_shot_worker() */
1182         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1183                 tegra_dc_program_bandwidth(dc, true);
1184
1185         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1186         if (!tegra_dc_windows_are_dirty(dc))
1187                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1188
1189         /* Update the SD brightness */
1190         if (dc->enabled && dc->out->sd_settings) {
1191                 nvsd_updated = nvsd_update_brightness(dc);
1192                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1193                  * V_BLANK_NVSD bit of vblank ref-count. */
1194                 if (nvsd_updated) {
1195                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1196                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1197                 } else {
1198                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1199                 }
1200         }
1201
1202         /* Mask vblank interrupt if ref-count is zero. */
1203         if (!dc->vblank_ref_count)
1204                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1205
1206         tegra_dc_release_dc_out(dc);
1207         mutex_unlock(&dc->lock);
1208
1209         /* Do the actual brightness update outside of the mutex */
1210         if (nvsd_updated && dc->out->sd_settings &&
1211             dc->out->sd_settings->bl_device) {
1212
1213                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1214                 struct backlight_device *bl = platform_get_drvdata(pdev);
1215                 if (bl)
1216                         backlight_update_status(bl);
1217         }
1218 }
1219
1220 static void tegra_dc_one_shot_worker(struct work_struct *work)
1221 {
1222         struct tegra_dc *dc = container_of(
1223                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1224         mutex_lock(&dc->lock);
1225
1226         /* memory client has gone idle */
1227         tegra_dc_clear_bandwidth(dc);
1228
1229         if (dc->out_ops->idle)
1230                 dc->out_ops->idle(dc);
1231
1232         mutex_unlock(&dc->lock);
1233 }
1234
1235 /* return an arbitrarily large number if count overflow occurs.
1236  * make it a nice base-10 number to show up in stats output */
1237 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1238 {
1239         unsigned count = tegra_dc_readl(dc, reg);
1240         tegra_dc_writel(dc, 0, reg);
1241         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1242 }
1243
1244 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1245 {
1246         u32 val;
1247         int i;
1248
1249         dc->stats.underflows++;
1250         if (dc->underflow_mask & WIN_A_UF_INT) {
1251                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1252                         DC_WINBUF_AD_UFLOW_STATUS);
1253                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1254         }
1255         if (dc->underflow_mask & WIN_B_UF_INT) {
1256                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1257                         DC_WINBUF_BD_UFLOW_STATUS);
1258                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1259         }
1260         if (dc->underflow_mask & WIN_C_UF_INT) {
1261                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1262                         DC_WINBUF_CD_UFLOW_STATUS);
1263                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1264         }
1265
1266         /* Check for any underflow reset conditions */
1267         for (i = 0; i < DC_N_WINDOWS; i++) {
1268                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1269                         dc->windows[i].underflows++;
1270
1271 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1272                         if (dc->windows[i].underflows > 4) {
1273                                 schedule_work(&dc->reset_work);
1274                                 /* reset counter */
1275                                 dc->windows[i].underflows = 0;
1276                                 trace_printk("%s:Reset work scheduled for "
1277                                                 "window %c\n",
1278                                                 dc->ndev->name, (65 + i));
1279                         }
1280 #endif
1281 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1282                         if (dc->windows[i].underflows > 4) {
1283                                 printk("%s:dc in underflow state."
1284                                         " enable UF_LINE_FLUSH to clear up\n",
1285                                         __func__);
1286                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1287                                                 DC_DISP_DISP_MISC_CONTROL);
1288                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1289                                                 DC_CMD_STATE_CONTROL);
1290                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1291                                                 DC_CMD_STATE_CONTROL);
1292
1293                                 tegra_dc_writel(dc, 0,
1294                                                 DC_DISP_DISP_MISC_CONTROL);
1295                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1296                                                 DC_CMD_STATE_CONTROL);
1297                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1298                                                 DC_CMD_STATE_CONTROL);
1299                         }
1300 #endif
1301                 } else {
1302                         dc->windows[i].underflows = 0;
1303                 }
1304         }
1305
1306         /* Clear the underflow mask now that we've checked it. */
1307         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1308         dc->underflow_mask = 0;
1309         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1310         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1311         print_underflow_info(dc);
1312 }
1313
1314 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1315 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1316 {
1317         if (status & V_BLANK_INT) {
1318                 /* Sync up windows. */
1319                 tegra_dc_trigger_windows(dc);
1320
1321                 /* Schedule any additional bottom-half vblank actvities. */
1322                 queue_work(system_freezable_wq, &dc->vblank_work);
1323         }
1324
1325         if (status & FRAME_END_INT) {
1326                 /* Mark the frame_end as complete. */
1327                 if (!completion_done(&dc->frame_end_complete))
1328                         complete(&dc->frame_end_complete);
1329         }
1330 }
1331
1332 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1333 {
1334         /* Schedule any additional bottom-half vblank actvities. */
1335         if (status & V_BLANK_INT)
1336                 queue_work(system_freezable_wq, &dc->vblank_work);
1337
1338         if (status & FRAME_END_INT) {
1339                 /* Mark the frame_end as complete. */
1340                 if (!completion_done(&dc->frame_end_complete))
1341                         complete(&dc->frame_end_complete);
1342
1343                 tegra_dc_trigger_windows(dc);
1344         }
1345 }
1346 #endif
1347
1348 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1349 {
1350 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1351         struct tegra_dc *dc = ptr;
1352         unsigned long status;
1353         unsigned long underflow_mask;
1354         u32 val;
1355
1356         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1357                 WARN(1, "IRQ when DC not powered!\n");
1358                 tegra_dc_io_start(dc);
1359                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1360                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1361                 tegra_dc_io_end(dc);
1362                 return IRQ_HANDLED;
1363         }
1364
1365         /* clear all status flags except underflow, save those for the worker */
1366         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1367         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1368         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1369         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1370
1371         /*
1372          * Overlays can get thier internal state corrupted during and underflow
1373          * condition.  The only way to fix this state is to reset the DC.
1374          * if we get 4 consecutive frames with underflows, assume we're
1375          * hosed and reset.
1376          */
1377         underflow_mask = status & ALL_UF_INT;
1378
1379         /* Check underflow */
1380         if (underflow_mask) {
1381                 dc->underflow_mask |= underflow_mask;
1382                 schedule_delayed_work(&dc->underflow_work,
1383                         msecs_to_jiffies(1));
1384         }
1385
1386         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1387                 tegra_dc_one_shot_irq(dc, status);
1388         else
1389                 tegra_dc_continuous_irq(dc, status);
1390
1391         return IRQ_HANDLED;
1392 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1393         return IRQ_NONE;
1394 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1395 }
1396
1397 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1398 {
1399         u32 color_control;
1400
1401         switch (dc->out->depth) {
1402         case 3:
1403                 color_control = BASE_COLOR_SIZE111;
1404                 break;
1405
1406         case 6:
1407                 color_control = BASE_COLOR_SIZE222;
1408                 break;
1409
1410         case 8:
1411                 color_control = BASE_COLOR_SIZE332;
1412                 break;
1413
1414         case 9:
1415                 color_control = BASE_COLOR_SIZE333;
1416                 break;
1417
1418         case 12:
1419                 color_control = BASE_COLOR_SIZE444;
1420                 break;
1421
1422         case 15:
1423                 color_control = BASE_COLOR_SIZE555;
1424                 break;
1425
1426         case 16:
1427                 color_control = BASE_COLOR_SIZE565;
1428                 break;
1429
1430         case 18:
1431                 color_control = BASE_COLOR_SIZE666;
1432                 break;
1433
1434         default:
1435                 color_control = BASE_COLOR_SIZE888;
1436                 break;
1437         }
1438
1439         switch (dc->out->dither) {
1440         case TEGRA_DC_DISABLE_DITHER:
1441                 color_control |= DITHER_CONTROL_DISABLE;
1442                 break;
1443         case TEGRA_DC_ORDERED_DITHER:
1444                 color_control |= DITHER_CONTROL_ORDERED;
1445                 break;
1446         case TEGRA_DC_ERRDIFF_DITHER:
1447                 /* The line buffer for error-diffusion dither is limited
1448                  * to 1280 pixels per line. This limits the maximum
1449                  * horizontal active area size to 1280 pixels when error
1450                  * diffusion is enabled.
1451                  */
1452                 BUG_ON(dc->mode.h_active > 1280);
1453                 color_control |= DITHER_CONTROL_ERRDIFF;
1454                 break;
1455         }
1456
1457 #ifdef CONFIG_TEGRA_DC_CMU
1458         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
1459                 color_control |= CMU_ENABLE;
1460 #endif
1461
1462         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1463 }
1464
1465 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1466 {
1467         u32 syncpt_id;
1468
1469         switch (dc->ndev->id) {
1470         case 0:
1471                 switch (idx) {
1472                 case 0:
1473                         syncpt_id = NVSYNCPT_DISP0_A;
1474                         break;
1475                 case 1:
1476                         syncpt_id = NVSYNCPT_DISP0_B;
1477                         break;
1478                 case 2:
1479                         syncpt_id = NVSYNCPT_DISP0_C;
1480                         break;
1481                 default:
1482                         BUG();
1483                         break;
1484                 }
1485                 break;
1486         case 1:
1487                 switch (idx) {
1488                 case 0:
1489                         syncpt_id = NVSYNCPT_DISP1_A;
1490                         break;
1491                 case 1:
1492                         syncpt_id = NVSYNCPT_DISP1_B;
1493                         break;
1494                 case 2:
1495                         syncpt_id = NVSYNCPT_DISP1_C;
1496                         break;
1497                 default:
1498                         BUG();
1499                         break;
1500                 }
1501                 break;
1502         default:
1503                 BUG();
1504                 break;
1505         }
1506
1507         return syncpt_id;
1508 }
1509
1510 static int tegra_dc_init(struct tegra_dc *dc)
1511 {
1512         int i;
1513
1514         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1515         if (dc->ndev->id == 0) {
1516                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1517                                       TEGRA_MC_PRIO_MED);
1518                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1519                                       TEGRA_MC_PRIO_MED);
1520                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1521                                       TEGRA_MC_PRIO_MED);
1522                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1523                                       TEGRA_MC_PRIO_MED);
1524                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1525                                       TEGRA_MC_PRIO_HIGH);
1526         } else if (dc->ndev->id == 1) {
1527                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1528                                       TEGRA_MC_PRIO_MED);
1529                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1530                                       TEGRA_MC_PRIO_MED);
1531                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1532                                       TEGRA_MC_PRIO_MED);
1533                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1534                                       TEGRA_MC_PRIO_MED);
1535                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1536                                       TEGRA_MC_PRIO_HIGH);
1537         }
1538         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1539                         DC_CMD_CONT_SYNCPT_VSYNC);
1540         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1541         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1542         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1543         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1544 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1545         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1546 #endif
1547         /* enable interrupts for vblank, frame_end and underflows */
1548         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1549                 DC_CMD_INT_ENABLE);
1550         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1551
1552         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1553
1554         tegra_dc_set_color_control(dc);
1555         for (i = 0; i < DC_N_WINDOWS; i++) {
1556                 struct tegra_dc_win *win = &dc->windows[i];
1557                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1558                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1559                 tegra_dc_set_csc(dc, &win->csc);
1560                 tegra_dc_set_lut(dc, win);
1561                 tegra_dc_set_scaling_filter(dc);
1562         }
1563
1564         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
1565         tegra_dc_set_cmu(dc, &dc->cmu);
1566
1567         for (i = 0; i < dc->n_windows; i++) {
1568                 u32 syncpt = get_syncpt(dc, i);
1569
1570                 dc->syncpt[i].id = syncpt;
1571
1572                 dc->syncpt[i].min = dc->syncpt[i].max =
1573                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1574         }
1575
1576         print_mode_info(dc, dc->mode);
1577
1578         if (dc->mode.pclk)
1579                 if (tegra_dc_program_mode(dc, &dc->mode))
1580                         return -EINVAL;
1581
1582         /* Initialize SD AFTER the modeset.
1583            nvsd_init handles the sd_settings = NULL case. */
1584         nvsd_init(dc, dc->out->sd_settings);
1585
1586         return 0;
1587 }
1588
1589 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1590 {
1591         int failed_init = 0;
1592
1593         if (dc->out->enable)
1594                 dc->out->enable();
1595
1596         tegra_dc_setup_clk(dc, dc->clk);
1597         tegra_dc_clk_enable(dc);
1598
1599         /* do not accept interrupts during initialization */
1600         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1601         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1602
1603         enable_dc_irq(dc->irq);
1604
1605         failed_init = tegra_dc_init(dc);
1606         if (failed_init) {
1607                 _tegra_dc_controller_disable(dc);
1608                 return false;
1609         }
1610
1611         if (dc->out_ops && dc->out_ops->enable)
1612                 dc->out_ops->enable(dc);
1613
1614         /* force a full blending update */
1615         dc->blend.z[0] = -1;
1616
1617         tegra_dc_ext_enable(dc->ext);
1618
1619         trace_printk("%s:enable\n", dc->ndev->name);
1620
1621         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1622         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1623
1624         if (dc->out->postpoweron)
1625                 dc->out->postpoweron();
1626
1627         return true;
1628 }
1629
1630 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1631 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1632 {
1633         bool ret = true;
1634
1635         if (dc->out->enable)
1636                 dc->out->enable();
1637
1638         tegra_dc_setup_clk(dc, dc->clk);
1639         tegra_dc_clk_enable(dc);
1640
1641         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1642                 mutex_lock(&tegra_dcs[1]->lock);
1643                 disable_irq(tegra_dcs[1]->irq);
1644         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1645                 mutex_lock(&tegra_dcs[0]->lock);
1646                 disable_irq(tegra_dcs[0]->irq);
1647         }
1648
1649         msleep(5);
1650         tegra_periph_reset_assert(dc->clk);
1651         msleep(2);
1652 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1653         tegra_periph_reset_deassert(dc->clk);
1654         msleep(1);
1655 #endif
1656
1657         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1658                 enable_dc_irq(tegra_dcs[1]->irq);
1659                 mutex_unlock(&tegra_dcs[1]->lock);
1660         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1661                 enable_dc_irq(tegra_dcs[0]->irq);
1662                 mutex_unlock(&tegra_dcs[0]->lock);
1663         }
1664
1665         enable_dc_irq(dc->irq);
1666
1667         if (tegra_dc_init(dc)) {
1668                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1669                 ret = false;
1670         }
1671
1672         if (dc->out_ops && dc->out_ops->enable)
1673                 dc->out_ops->enable(dc);
1674
1675         if (dc->out->postpoweron)
1676                 dc->out->postpoweron();
1677
1678         /* force a full blending update */
1679         dc->blend.z[0] = -1;
1680
1681         tegra_dc_ext_enable(dc->ext);
1682
1683         if (!ret) {
1684                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1685                 _tegra_dc_controller_disable(dc);
1686         }
1687
1688         trace_printk("%s:reset enable\n", dc->ndev->name);
1689         return ret;
1690 }
1691 #endif
1692
1693 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1694 {
1695         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1696 }
1697
1698 static bool _tegra_dc_enable(struct tegra_dc *dc)
1699 {
1700         if (dc->mode.pclk == 0) {
1701                 switch (dc->out->type) {
1702                 case TEGRA_DC_OUT_HDMI:
1703                 /* DC enable called but no videomode is loaded.
1704                      Check if HDMI is connected, then set fallback mdoe */
1705                 if (tegra_dc_hpd(dc)) {
1706                         if (_tegra_dc_set_default_videomode(dc))
1707                                 return false;
1708                 } else
1709                         return false;
1710
1711                 break;
1712
1713                 /* Do nothing for other outputs for now */
1714                 case TEGRA_DC_OUT_RGB:
1715
1716                 case TEGRA_DC_OUT_DSI:
1717
1718                 default:
1719                         return false;
1720                 }
1721         }
1722
1723         if (!dc->out)
1724                 return false;
1725
1726         tegra_dc_io_start(dc);
1727
1728         return _tegra_dc_controller_enable(dc);
1729 }
1730
1731 void tegra_dc_enable(struct tegra_dc *dc)
1732 {
1733         mutex_lock(&dc->lock);
1734
1735         if (!dc->enabled)
1736                 dc->enabled = _tegra_dc_enable(dc);
1737
1738         mutex_unlock(&dc->lock);
1739         print_mode_info(dc, dc->mode);
1740 }
1741
1742 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1743 {
1744         unsigned i;
1745
1746         if (dc->out && dc->out->prepoweroff)
1747                 dc->out->prepoweroff();
1748
1749         if (dc->out_ops && dc->out_ops->disable)
1750                 dc->out_ops->disable(dc);
1751
1752         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1753         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1754         disable_irq(dc->irq);
1755
1756         tegra_dc_clear_bandwidth(dc);
1757         tegra_dc_clk_disable(dc);
1758
1759         if (dc->out && dc->out->disable)
1760                 dc->out->disable();
1761
1762         for (i = 0; i < dc->n_windows; i++) {
1763                 struct tegra_dc_win *w = &dc->windows[i];
1764
1765                 /* reset window bandwidth */
1766                 w->bandwidth = 0;
1767                 w->new_bandwidth = 0;
1768
1769                 /* disable windows */
1770                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1771
1772                 /* flush any pending syncpt waits */
1773                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1774                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1775                                 dc->syncpt[i].id);
1776                         dc->syncpt[i].min++;
1777                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1778                 }
1779         }
1780         trace_printk("%s:disabled\n", dc->ndev->name);
1781 }
1782
1783 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1784 {
1785 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1786         u32 val;
1787         if (dc->enabled)  {
1788                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1789                 if (enable)
1790                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1791                 else
1792                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1793                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1794         }
1795 #endif
1796 }
1797
1798 bool tegra_dc_stats_get(struct tegra_dc *dc)
1799 {
1800 #if 0 /* right now it is always enabled */
1801         u32 val;
1802         bool res;
1803
1804         if (dc->enabled)  {
1805                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1806                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1807         } else {
1808                 res = false;
1809         }
1810
1811         return res;
1812 #endif
1813         return true;
1814 }
1815
1816 /* make the screen blank by disabling all windows */
1817 void tegra_dc_blank(struct tegra_dc *dc)
1818 {
1819         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1820         unsigned i;
1821
1822         for (i = 0; i < DC_N_WINDOWS; i++) {
1823                 dcwins[i] = tegra_dc_get_window(dc, i);
1824                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1825         }
1826
1827         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1828         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1829 }
1830
1831 static void _tegra_dc_disable(struct tegra_dc *dc)
1832 {
1833         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1834                 mutex_lock(&dc->one_shot_lock);
1835                 cancel_delayed_work_sync(&dc->one_shot_work);
1836         }
1837
1838         tegra_dc_hold_dc_out(dc);
1839
1840         _tegra_dc_controller_disable(dc);
1841         tegra_dc_io_end(dc);
1842
1843         tegra_dc_release_dc_out(dc);
1844
1845         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1846                 mutex_unlock(&dc->one_shot_lock);
1847 }
1848
1849 void tegra_dc_disable(struct tegra_dc *dc)
1850 {
1851         tegra_dc_ext_disable(dc->ext);
1852
1853         /* it's important that new underflow work isn't scheduled before the
1854          * lock is acquired. */
1855         cancel_delayed_work_sync(&dc->underflow_work);
1856
1857         mutex_lock(&dc->lock);
1858
1859         if (dc->enabled) {
1860                 dc->enabled = false;
1861
1862                 if (!dc->suspended)
1863                         _tegra_dc_disable(dc);
1864         }
1865
1866 #ifdef CONFIG_SWITCH
1867         switch_set_state(&dc->modeset_switch, 0);
1868 #endif
1869
1870         mutex_unlock(&dc->lock);
1871         print_mode_info(dc, dc->mode);
1872 }
1873
1874 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1875 static void tegra_dc_reset_worker(struct work_struct *work)
1876 {
1877         struct tegra_dc *dc =
1878                 container_of(work, struct tegra_dc, reset_work);
1879
1880         unsigned long val = 0;
1881
1882         mutex_lock(&shared_lock);
1883
1884         dev_warn(&dc->ndev->dev,
1885                 "overlay stuck in underflow state.  resetting.\n");
1886
1887         tegra_dc_ext_disable(dc->ext);
1888
1889         mutex_lock(&dc->lock);
1890
1891         if (dc->enabled == false)
1892                 goto unlock;
1893
1894         dc->enabled = false;
1895
1896         /*
1897          * off host read bus
1898          */
1899         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1900         val &= ~(0x00000100);
1901         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1902
1903         /*
1904          * set DC to STOP mode
1905          */
1906         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1907
1908         msleep(10);
1909
1910         _tegra_dc_controller_disable(dc);
1911
1912         /* _tegra_dc_controller_reset_enable deasserts reset */
1913         _tegra_dc_controller_reset_enable(dc);
1914
1915         dc->enabled = true;
1916
1917         /* reopen host read bus */
1918         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1919         val &= ~(0x00000100);
1920         val |= 0x100;
1921         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1922
1923 unlock:
1924         mutex_unlock(&dc->lock);
1925         mutex_unlock(&shared_lock);
1926         trace_printk("%s:reset complete\n", dc->ndev->name);
1927 }
1928 #endif
1929
1930 static void tegra_dc_underflow_worker(struct work_struct *work)
1931 {
1932         struct tegra_dc *dc = container_of(
1933                 to_delayed_work(work), struct tegra_dc, underflow_work);
1934
1935         mutex_lock(&dc->lock);
1936         tegra_dc_hold_dc_out(dc);
1937
1938         if (dc->enabled) {
1939                 tegra_dc_underflow_handler(dc);
1940         }
1941         tegra_dc_release_dc_out(dc);
1942         mutex_unlock(&dc->lock);
1943 }
1944
1945 #ifdef CONFIG_SWITCH
1946 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1947 {
1948         struct tegra_dc *dc =
1949                 container_of(sdev, struct tegra_dc, modeset_switch);
1950
1951         if (!sdev->state)
1952                 return sprintf(buf, "offline\n");
1953
1954         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1955 }
1956 #endif
1957
1958 static int tegra_dc_probe(struct nvhost_device *ndev,
1959         struct nvhost_device_id *id_table)
1960 {
1961         struct tegra_dc *dc;
1962         struct tegra_dc_mode *mode;
1963         struct clk *clk;
1964         struct clk *emc_clk;
1965         struct resource *res;
1966         struct resource *base_res;
1967         struct resource *fb_mem = NULL;
1968         int ret = 0;
1969         void __iomem *base;
1970         int irq;
1971         int i;
1972
1973         if (!ndev->dev.platform_data) {
1974                 dev_err(&ndev->dev, "no platform data\n");
1975                 return -ENOENT;
1976         }
1977
1978         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1979         if (!dc) {
1980                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1981                 return -ENOMEM;
1982         }
1983
1984         irq = nvhost_get_irq_byname(ndev, "irq");
1985         if (irq <= 0) {
1986                 dev_err(&ndev->dev, "no irq\n");
1987                 ret = -ENOENT;
1988                 goto err_free;
1989         }
1990
1991         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1992         if (!res) {
1993                 dev_err(&ndev->dev, "no mem resource\n");
1994                 ret = -ENOENT;
1995                 goto err_free;
1996         }
1997
1998         base_res = request_mem_region(res->start, resource_size(res),
1999                 ndev->name);
2000         if (!base_res) {
2001                 dev_err(&ndev->dev, "request_mem_region failed\n");
2002                 ret = -EBUSY;
2003                 goto err_free;
2004         }
2005
2006         base = ioremap(res->start, resource_size(res));
2007         if (!base) {
2008                 dev_err(&ndev->dev, "registers can't be mapped\n");
2009                 ret = -EBUSY;
2010                 goto err_release_resource_reg;
2011         }
2012
2013         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2014
2015         clk = clk_get(&ndev->dev, NULL);
2016         if (IS_ERR_OR_NULL(clk)) {
2017                 dev_err(&ndev->dev, "can't get clock\n");
2018                 ret = -ENOENT;
2019                 goto err_iounmap_reg;
2020         }
2021
2022         emc_clk = clk_get(&ndev->dev, "emc");
2023         if (IS_ERR_OR_NULL(emc_clk)) {
2024                 dev_err(&ndev->dev, "can't get emc clock\n");
2025                 ret = -ENOENT;
2026                 goto err_put_clk;
2027         }
2028
2029         dc->clk = clk;
2030         dc->emc_clk = emc_clk;
2031         dc->shift_clk_div = 1;
2032         /* Initialize one shot work delay, it will be assigned by dsi
2033          * according to refresh rate later. */
2034         dc->one_shot_delay_ms = 40;
2035
2036         dc->base_res = base_res;
2037         dc->base = base;
2038         dc->irq = irq;
2039         dc->ndev = ndev;
2040         dc->pdata = ndev->dev.platform_data;
2041
2042         /*
2043          * The emc is a shared clock, it will be set based on
2044          * the requirements for each user on the bus.
2045          */
2046         dc->emc_clk_rate = 0;
2047
2048         mutex_init(&dc->lock);
2049         mutex_init(&dc->one_shot_lock);
2050         init_completion(&dc->frame_end_complete);
2051         init_waitqueue_head(&dc->wq);
2052 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2053         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2054 #endif
2055         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2056         dc->vblank_ref_count = 0;
2057         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2058         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2059
2060         tegra_dc_init_lut_defaults(&dc->fb_lut);
2061
2062         dc->n_windows = DC_N_WINDOWS;
2063         for (i = 0; i < dc->n_windows; i++) {
2064                 struct tegra_dc_win *win = &dc->windows[i];
2065                 win->idx = i;
2066                 win->dc = dc;
2067                 tegra_dc_init_csc_defaults(&win->csc);
2068                 tegra_dc_init_lut_defaults(&win->lut);
2069         }
2070
2071         ret = tegra_dc_set(dc, ndev->id);
2072         if (ret < 0) {
2073                 dev_err(&ndev->dev, "can't add dc\n");
2074                 goto err_free_irq;
2075         }
2076
2077         nvhost_set_drvdata(ndev, dc);
2078
2079 #ifdef CONFIG_SWITCH
2080         dc->modeset_switch.name = dev_name(&ndev->dev);
2081         dc->modeset_switch.state = 0;
2082         dc->modeset_switch.print_state = switch_modeset_print_mode;
2083         switch_dev_register(&dc->modeset_switch);
2084 #endif
2085
2086         tegra_dc_feature_register(dc);
2087
2088         if (dc->pdata->default_out)
2089                 tegra_dc_set_out(dc, dc->pdata->default_out);
2090         else
2091                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2092
2093         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2094                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2095
2096         dc->ext = tegra_dc_ext_register(ndev, dc);
2097         if (IS_ERR_OR_NULL(dc->ext)) {
2098                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2099                 dc->ext = NULL;
2100         }
2101
2102         mutex_lock(&dc->lock);
2103         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2104                 dc->enabled = _tegra_dc_enable(dc);
2105         mutex_unlock(&dc->lock);
2106
2107         /* interrupt handler must be registered before tegra_fb_register() */
2108         if (request_irq(irq, tegra_dc_irq, 0,
2109                         dev_name(&ndev->dev), dc)) {
2110                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2111                 ret = -EBUSY;
2112                 goto err_put_emc_clk;
2113         }
2114
2115         tegra_dc_create_debugfs(dc);
2116
2117         dev_info(&ndev->dev, "probed\n");
2118
2119         if (dc->pdata->fb) {
2120                 if (dc->pdata->fb->bits_per_pixel == -1) {
2121                         unsigned long fmt;
2122                         tegra_dc_writel(dc,
2123                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2124                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2125
2126                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2127                         dc->pdata->fb->bits_per_pixel =
2128                                 tegra_dc_fmt_bpp(fmt);
2129                 }
2130
2131                 mode = tegra_dc_get_override_mode(dc);
2132                 if (mode) {
2133                         dc->pdata->fb->xres = mode->h_active;
2134                         dc->pdata->fb->yres = mode->v_active;
2135                 }
2136
2137                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2138                 if (IS_ERR_OR_NULL(dc->fb))
2139                         dc->fb = NULL;
2140         }
2141
2142         if (dc->out && dc->out->hotplug_init)
2143                 dc->out->hotplug_init();
2144
2145         if (dc->out_ops && dc->out_ops->detect)
2146                 dc->out_ops->detect(dc);
2147         else
2148                 dc->connected = true;
2149
2150         tegra_dc_create_sysfs(&dc->ndev->dev);
2151
2152         return 0;
2153
2154 err_free_irq:
2155         free_irq(irq, dc);
2156 err_put_emc_clk:
2157         clk_put(emc_clk);
2158 err_put_clk:
2159         clk_put(clk);
2160 err_iounmap_reg:
2161         iounmap(base);
2162         if (fb_mem)
2163                 release_resource(fb_mem);
2164 err_release_resource_reg:
2165         release_resource(base_res);
2166 err_free:
2167         kfree(dc);
2168
2169         return ret;
2170 }
2171
2172 static int __devexit tegra_dc_remove(struct nvhost_device *ndev)
2173 {
2174         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2175
2176         tegra_dc_remove_sysfs(&dc->ndev->dev);
2177         tegra_dc_remove_debugfs(dc);
2178
2179         if (dc->fb) {
2180                 tegra_fb_unregister(dc->fb);
2181                 if (dc->fb_mem)
2182                         release_resource(dc->fb_mem);
2183         }
2184
2185         tegra_dc_ext_disable(dc->ext);
2186
2187         if (dc->ext)
2188                 tegra_dc_ext_unregister(dc->ext);
2189
2190         if (dc->enabled)
2191                 _tegra_dc_disable(dc);
2192
2193 #ifdef CONFIG_SWITCH
2194         switch_dev_unregister(&dc->modeset_switch);
2195 #endif
2196         free_irq(dc->irq, dc);
2197         clk_put(dc->emc_clk);
2198         clk_put(dc->clk);
2199         iounmap(dc->base);
2200         if (dc->fb_mem)
2201                 release_resource(dc->base_res);
2202         kfree(dc);
2203         tegra_dc_set(NULL, ndev->id);
2204         return 0;
2205 }
2206
2207 #ifdef CONFIG_PM
2208 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2209 {
2210         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2211
2212         trace_printk("%s:suspend\n", dc->ndev->name);
2213         dev_info(&ndev->dev, "suspend\n");
2214
2215         tegra_dc_ext_disable(dc->ext);
2216
2217         mutex_lock(&dc->lock);
2218
2219         if (dc->out_ops && dc->out_ops->suspend)
2220                 dc->out_ops->suspend(dc);
2221
2222         if (dc->enabled) {
2223                 _tegra_dc_disable(dc);
2224
2225                 dc->suspended = true;
2226         }
2227
2228         if (dc->out && dc->out->postsuspend) {
2229                 dc->out->postsuspend();
2230                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2231                         /*
2232                          * avoid resume event due to voltage falling
2233                          */
2234                         msleep(100);
2235         }
2236
2237         mutex_unlock(&dc->lock);
2238
2239         return 0;
2240 }
2241
2242 static int tegra_dc_resume(struct nvhost_device *ndev)
2243 {
2244         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2245
2246         trace_printk("%s:resume\n", dc->ndev->name);
2247         dev_info(&ndev->dev, "resume\n");
2248
2249         mutex_lock(&dc->lock);
2250         dc->suspended = false;
2251
2252         if (dc->enabled)
2253                 _tegra_dc_enable(dc);
2254
2255         if (dc->out && dc->out->hotplug_init)
2256                 dc->out->hotplug_init();
2257
2258         if (dc->out_ops && dc->out_ops->resume)
2259                 dc->out_ops->resume(dc);
2260         mutex_unlock(&dc->lock);
2261
2262         return 0;
2263 }
2264
2265 #endif /* CONFIG_PM */
2266
2267 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2268 {
2269         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2270
2271         if (!dc || !dc->enabled)
2272                 return;
2273
2274         tegra_dc_blank(dc);
2275         tegra_dc_disable(dc);
2276 }
2277
2278 extern int suspend_set(const char *val, struct kernel_param *kp)
2279 {
2280         if (!strcmp(val, "dump"))
2281                 dump_regs(tegra_dcs[0]);
2282 #ifdef CONFIG_PM
2283         else if (!strcmp(val, "suspend"))
2284                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2285         else if (!strcmp(val, "resume"))
2286                 tegra_dc_resume(tegra_dcs[0]->ndev);
2287 #endif
2288
2289         return 0;
2290 }
2291
2292 extern int suspend_get(char *buffer, struct kernel_param *kp)
2293 {
2294         return 0;
2295 }
2296
2297 int suspend;
2298
2299 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2300
2301 struct nvhost_driver tegra_dc_driver = {
2302         .driver = {
2303                 .name = "tegradc",
2304                 .owner = THIS_MODULE,
2305         },
2306         .probe = tegra_dc_probe,
2307         .remove = tegra_dc_remove,
2308 #ifdef CONFIG_PM
2309         .suspend = tegra_dc_suspend,
2310         .resume = tegra_dc_resume,
2311 #endif
2312         .shutdown = tegra_dc_shutdown,
2313 };
2314
2315 #ifndef MODULE
2316 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2317 {
2318         int i, params[11];
2319         char *p;
2320
2321         for (i = 0; i < ARRAY_SIZE(params); i++) {
2322                 if ((p = strsep(&options, ",")) != NULL) {
2323                         if (*p)
2324                                 params[i] = simple_strtoul(p, &p, 10);
2325                 } else
2326                         return -EINVAL;
2327         }
2328
2329         if ((mode->pclk = params[0]) == 0)
2330                 return -EINVAL;
2331
2332         mode->h_active      = params[1];
2333         mode->v_active      = params[2];
2334         mode->h_ref_to_sync = params[3];
2335         mode->v_ref_to_sync = params[4];
2336         mode->h_sync_width  = params[5];
2337         mode->v_sync_width  = params[6];
2338         mode->h_back_porch  = params[7];
2339         mode->v_back_porch  = params[8];
2340         mode->h_front_porch = params[9];
2341         mode->v_front_porch = params[10];
2342
2343         return 0;
2344 }
2345
2346 static int __init tegra_dc_mode_override(char *str)
2347 {
2348         char *p = str, *options;
2349
2350         if (!p || !*p)
2351                 return -EINVAL;
2352
2353         p = strstr(str, "hdmi:");
2354         if (p) {
2355                 p += 5;
2356                 options = strsep(&p, ";");
2357                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2358                         return -EINVAL;
2359         }
2360
2361         p = strstr(str, "rgb:");
2362         if (p) {
2363                 p += 4;
2364                 options = strsep(&p, ";");
2365                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2366                         return -EINVAL;
2367         }
2368
2369         p = strstr(str, "dsi:");
2370         if (p) {
2371                 p += 4;
2372                 options = strsep(&p, ";");
2373                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2374                         return -EINVAL;
2375         }
2376
2377         return 0;
2378 }
2379
2380 __setup("disp_params=", tegra_dc_mode_override);
2381 #endif
2382
2383 static int __init tegra_dc_module_init(void)
2384 {
2385         int ret = tegra_dc_ext_module_init();
2386         if (ret)
2387                 return ret;
2388         return nvhost_driver_register(&tegra_dc_driver);
2389 }
2390
2391 static void __exit tegra_dc_module_exit(void)
2392 {
2393         nvhost_driver_unregister(&tegra_dc_driver);
2394         tegra_dc_ext_module_exit();
2395 }
2396
2397 module_exit(tegra_dc_module_exit);
2398 module_init(tegra_dc_module_init);