[PATCH] DRIVER MODEL: Get rid of the obsolete tri-level suspend/resume callbacks
[linux-2.6.git] / drivers / video / pxafb.c
1 /*
2  *  linux/drivers/video/pxafb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas.
5  *  Copyright (C) 2004 Jean-Frederic Clere.
6  *  Copyright (C) 2004 Ian Campbell.
7  *  Copyright (C) 2004 Jeff Lackey.
8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9  *  which in turn is
10  *   Based on acornfb.c Copyright (C) Russell King.
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive for
14  * more details.
15  *
16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
17  *
18  * Please direct your questions and comments on this driver to the following
19  * email address:
20  *
21  *      linux-arm-kernel@lists.arm.linux.org.uk
22  *
23  */
24
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
32 #include <linux/interrupt.h>
33 #include <linux/slab.h>
34 #include <linux/fb.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/device.h>
40 #include <linux/dma-mapping.h>
41
42 #include <asm/hardware.h>
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/uaccess.h>
46 #include <asm/div64.h>
47 #include <asm/arch/pxa-regs.h>
48 #include <asm/arch/bitfield.h>
49 #include <asm/arch/pxafb.h>
50
51 /*
52  * Complain if VAR is out of range.
53  */
54 #define DEBUG_VAR 1
55
56 #include "pxafb.h"
57
58 /* Bits which should not be set in machine configuration structures */
59 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
60 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
61
62 static void (*pxafb_backlight_power)(int);
63 static void (*pxafb_lcd_power)(int);
64
65 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
66 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
67
68 #ifdef CONFIG_FB_PXA_PARAMETERS
69 #define PXAFB_OPTIONS_SIZE 256
70 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
71 #endif
72
73 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
74 {
75         unsigned long flags;
76
77         local_irq_save(flags);
78         /*
79          * We need to handle two requests being made at the same time.
80          * There are two important cases:
81          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
82          *     We must perform the unblanking, which will do our REENABLE for us.
83          *  2. When we are blanking, but immediately unblank before we have
84          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
85          */
86         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
87                 state = (u_int) -1;
88         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
89                 state = C_REENABLE;
90
91         if (state != (u_int)-1) {
92                 fbi->task_state = state;
93                 schedule_work(&fbi->task);
94         }
95         local_irq_restore(flags);
96 }
97
98 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
99 {
100         chan &= 0xffff;
101         chan >>= 16 - bf->length;
102         return chan << bf->offset;
103 }
104
105 static int
106 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
107                        u_int trans, struct fb_info *info)
108 {
109         struct pxafb_info *fbi = (struct pxafb_info *)info;
110         u_int val, ret = 1;
111
112         if (regno < fbi->palette_size) {
113                 if (fbi->fb.var.grayscale) {
114                         val = ((blue >> 8) & 0x00ff);
115                 } else {
116                         val  = ((red   >>  0) & 0xf800);
117                         val |= ((green >>  5) & 0x07e0);
118                         val |= ((blue  >> 11) & 0x001f);
119                 }
120                 fbi->palette_cpu[regno] = val;
121                 ret = 0;
122         }
123         return ret;
124 }
125
126 static int
127 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
128                    u_int trans, struct fb_info *info)
129 {
130         struct pxafb_info *fbi = (struct pxafb_info *)info;
131         unsigned int val;
132         int ret = 1;
133
134         /*
135          * If inverse mode was selected, invert all the colours
136          * rather than the register number.  The register number
137          * is what you poke into the framebuffer to produce the
138          * colour you requested.
139          */
140         if (fbi->cmap_inverse) {
141                 red   = 0xffff - red;
142                 green = 0xffff - green;
143                 blue  = 0xffff - blue;
144         }
145
146         /*
147          * If greyscale is true, then we convert the RGB value
148          * to greyscale no matter what visual we are using.
149          */
150         if (fbi->fb.var.grayscale)
151                 red = green = blue = (19595 * red + 38470 * green +
152                                         7471 * blue) >> 16;
153
154         switch (fbi->fb.fix.visual) {
155         case FB_VISUAL_TRUECOLOR:
156                 /*
157                  * 16-bit True Colour.  We encode the RGB value
158                  * according to the RGB bitfield information.
159                  */
160                 if (regno < 16) {
161                         u32 *pal = fbi->fb.pseudo_palette;
162
163                         val  = chan_to_field(red, &fbi->fb.var.red);
164                         val |= chan_to_field(green, &fbi->fb.var.green);
165                         val |= chan_to_field(blue, &fbi->fb.var.blue);
166
167                         pal[regno] = val;
168                         ret = 0;
169                 }
170                 break;
171
172         case FB_VISUAL_STATIC_PSEUDOCOLOR:
173         case FB_VISUAL_PSEUDOCOLOR:
174                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
175                 break;
176         }
177
178         return ret;
179 }
180
181 /*
182  *  pxafb_bpp_to_lccr3():
183  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
184  */
185 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
186 {
187         int ret = 0;
188         switch (var->bits_per_pixel) {
189         case 1:  ret = LCCR3_1BPP; break;
190         case 2:  ret = LCCR3_2BPP; break;
191         case 4:  ret = LCCR3_4BPP; break;
192         case 8:  ret = LCCR3_8BPP; break;
193         case 16: ret = LCCR3_16BPP; break;
194         }
195         return ret;
196 }
197
198 #ifdef CONFIG_CPU_FREQ
199 /*
200  *  pxafb_display_dma_period()
201  *    Calculate the minimum period (in picoseconds) between two DMA
202  *    requests for the LCD controller.  If we hit this, it means we're
203  *    doing nothing but LCD DMA.
204  */
205 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
206 {
207        /*
208         * Period = pixclock * bits_per_byte * bytes_per_transfer
209         *              / memory_bits_per_pixel;
210         */
211        return var->pixclock * 8 * 16 / var->bits_per_pixel;
212 }
213
214 extern unsigned int get_clk_frequency_khz(int info);
215 #endif
216
217 /*
218  *  pxafb_check_var():
219  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
220  *    if it's too big, return -EINVAL.
221  *
222  *    Round up in the following order: bits_per_pixel, xres,
223  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
224  *    bitfields, horizontal timing, vertical timing.
225  */
226 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
227 {
228         struct pxafb_info *fbi = (struct pxafb_info *)info;
229
230         if (var->xres < MIN_XRES)
231                 var->xres = MIN_XRES;
232         if (var->yres < MIN_YRES)
233                 var->yres = MIN_YRES;
234         if (var->xres > fbi->max_xres)
235                 var->xres = fbi->max_xres;
236         if (var->yres > fbi->max_yres)
237                 var->yres = fbi->max_yres;
238         var->xres_virtual =
239                 max(var->xres_virtual, var->xres);
240         var->yres_virtual =
241                 max(var->yres_virtual, var->yres);
242
243         /*
244          * Setup the RGB parameters for this display.
245          *
246          * The pixel packing format is described on page 7-11 of the
247          * PXA2XX Developer's Manual.
248          */
249         if (var->bits_per_pixel == 16) {
250                 var->red.offset   = 11; var->red.length   = 5;
251                 var->green.offset = 5;  var->green.length = 6;
252                 var->blue.offset  = 0;  var->blue.length  = 5;
253                 var->transp.offset = var->transp.length = 0;
254         } else {
255                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
256                 var->red.length   = 8;
257                 var->green.length = 8;
258                 var->blue.length  = 8;
259                 var->transp.length = 0;
260         }
261
262 #ifdef CONFIG_CPU_FREQ
263         pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
264                  pxafb_display_dma_period(var),
265                  get_clk_frequency_khz(0));
266 #endif
267
268         return 0;
269 }
270
271 static inline void pxafb_set_truecolor(u_int is_true_color)
272 {
273         pr_debug("pxafb: true_color = %d\n", is_true_color);
274         // do your machine-specific setup if needed
275 }
276
277 /*
278  * pxafb_set_par():
279  *      Set the user defined part of the display for the specified console
280  */
281 static int pxafb_set_par(struct fb_info *info)
282 {
283         struct pxafb_info *fbi = (struct pxafb_info *)info;
284         struct fb_var_screeninfo *var = &info->var;
285         unsigned long palette_mem_size;
286
287         pr_debug("pxafb: set_par\n");
288
289         if (var->bits_per_pixel == 16)
290                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
291         else if (!fbi->cmap_static)
292                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
293         else {
294                 /*
295                  * Some people have weird ideas about wanting static
296                  * pseudocolor maps.  I suspect their user space
297                  * applications are broken.
298                  */
299                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
300         }
301
302         fbi->fb.fix.line_length = var->xres_virtual *
303                                   var->bits_per_pixel / 8;
304         if (var->bits_per_pixel == 16)
305                 fbi->palette_size = 0;
306         else
307                 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
308
309         palette_mem_size = fbi->palette_size * sizeof(u16);
310
311         pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
312
313         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
314         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
315
316         /*
317          * Set (any) board control register to handle new color depth
318          */
319         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
320
321         if (fbi->fb.var.bits_per_pixel == 16)
322                 fb_dealloc_cmap(&fbi->fb.cmap);
323         else
324                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
325
326         pxafb_activate_var(var, fbi);
327
328         return 0;
329 }
330
331 /*
332  * Formal definition of the VESA spec:
333  *  On
334  *      This refers to the state of the display when it is in full operation
335  *  Stand-By
336  *      This defines an optional operating state of minimal power reduction with
337  *      the shortest recovery time
338  *  Suspend
339  *      This refers to a level of power management in which substantial power
340  *      reduction is achieved by the display.  The display can have a longer
341  *      recovery time from this state than from the Stand-by state
342  *  Off
343  *      This indicates that the display is consuming the lowest level of power
344  *      and is non-operational. Recovery from this state may optionally require
345  *      the user to manually power on the monitor
346  *
347  *  Now, the fbdev driver adds an additional state, (blank), where they
348  *  turn off the video (maybe by colormap tricks), but don't mess with the
349  *  video itself: think of it semantically between on and Stand-By.
350  *
351  *  So here's what we should do in our fbdev blank routine:
352  *
353  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
354  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
355  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
356  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
357  *
358  *  This will match the matrox implementation.
359  */
360
361 /*
362  * pxafb_blank():
363  *      Blank the display by setting all palette values to zero.  Note, the
364  *      16 bpp mode does not really use the palette, so this will not
365  *      blank the display in all modes.
366  */
367 static int pxafb_blank(int blank, struct fb_info *info)
368 {
369         struct pxafb_info *fbi = (struct pxafb_info *)info;
370         int i;
371
372         pr_debug("pxafb: blank=%d\n", blank);
373
374         switch (blank) {
375         case FB_BLANK_POWERDOWN:
376         case FB_BLANK_VSYNC_SUSPEND:
377         case FB_BLANK_HSYNC_SUSPEND:
378         case FB_BLANK_NORMAL:
379                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
380                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
381                         for (i = 0; i < fbi->palette_size; i++)
382                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
383
384                 pxafb_schedule_work(fbi, C_DISABLE);
385                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
386                 break;
387
388         case FB_BLANK_UNBLANK:
389                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
390                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
391                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
392                         fb_set_cmap(&fbi->fb.cmap, info);
393                 pxafb_schedule_work(fbi, C_ENABLE);
394         }
395         return 0;
396 }
397
398 static int pxafb_mmap(struct fb_info *info, struct file *file,
399                       struct vm_area_struct *vma)
400 {
401         struct pxafb_info *fbi = (struct pxafb_info *)info;
402         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
403
404         if (off < info->fix.smem_len) {
405                 vma->vm_pgoff += 1;
406                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
407                                              fbi->map_dma, fbi->map_size);
408         }
409         return -EINVAL;
410 }
411
412 static struct fb_ops pxafb_ops = {
413         .owner          = THIS_MODULE,
414         .fb_check_var   = pxafb_check_var,
415         .fb_set_par     = pxafb_set_par,
416         .fb_setcolreg   = pxafb_setcolreg,
417         .fb_fillrect    = cfb_fillrect,
418         .fb_copyarea    = cfb_copyarea,
419         .fb_imageblit   = cfb_imageblit,
420         .fb_blank       = pxafb_blank,
421         .fb_cursor      = soft_cursor,
422         .fb_mmap        = pxafb_mmap,
423 };
424
425 /*
426  * Calculate the PCD value from the clock rate (in picoseconds).
427  * We take account of the PPCR clock setting.
428  * From PXA Developer's Manual:
429  *
430  *   PixelClock =      LCLK
431  *                -------------
432  *                2 ( PCD + 1 )
433  *
434  *   PCD =      LCLK
435  *         ------------- - 1
436  *         2(PixelClock)
437  *
438  * Where:
439  *   LCLK = LCD/Memory Clock
440  *   PCD = LCCR3[7:0]
441  *
442  * PixelClock here is in Hz while the pixclock argument given is the
443  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
444  *
445  * The function get_lclk_frequency_10khz returns LCLK in units of
446  * 10khz. Calling the result of this function lclk gives us the
447  * following
448  *
449  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
450  *          -------------------------------------- - 1
451  *                          2
452  *
453  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
454  */
455 static inline unsigned int get_pcd(unsigned int pixclock)
456 {
457         unsigned long long pcd;
458
459         /* FIXME: Need to take into account Double Pixel Clock mode
460          * (DPC) bit? or perhaps set it based on the various clock
461          * speeds */
462
463         pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
464         do_div(pcd, 100000000 * 2);
465         /* no need for this, since we should subtract 1 anyway. they cancel */
466         /* pcd += 1; */ /* make up for integer math truncations */
467         return (unsigned int)pcd;
468 }
469
470 /*
471  * Some touchscreens need hsync information from the video driver to
472  * function correctly. We export it here.
473  */
474 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
475 {
476         unsigned long long htime;
477
478         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
479                 fbi->hsync_time=0;
480                 return;
481         }
482
483         htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
484         do_div(htime, pcd * fbi->fb.var.hsync_len);
485         fbi->hsync_time = htime;
486 }
487
488 unsigned long pxafb_get_hsync_time(struct device *dev)
489 {
490         struct pxafb_info *fbi = dev_get_drvdata(dev);
491
492         /* If display is blanked/suspended, hsync isn't active */
493         if (!fbi || (fbi->state != C_ENABLE))
494                 return 0;
495
496         return fbi->hsync_time;
497 }
498 EXPORT_SYMBOL(pxafb_get_hsync_time);
499
500 /*
501  * pxafb_activate_var():
502  *      Configures LCD Controller based on entries in var parameter.  Settings are
503  *      only written to the controller if changes were made.
504  */
505 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
506 {
507         struct pxafb_lcd_reg new_regs;
508         u_long flags;
509         u_int lines_per_panel, pcd = get_pcd(var->pixclock);
510
511         pr_debug("pxafb: Configuring PXA LCD\n");
512
513         pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
514                  var->xres, var->hsync_len,
515                  var->left_margin, var->right_margin);
516         pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
517                  var->yres, var->vsync_len,
518                  var->upper_margin, var->lower_margin);
519         pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
520
521 #if DEBUG_VAR
522         if (var->xres < 16        || var->xres > 1024)
523                 printk(KERN_ERR "%s: invalid xres %d\n",
524                         fbi->fb.fix.id, var->xres);
525         switch(var->bits_per_pixel) {
526         case 1:
527         case 2:
528         case 4:
529         case 8:
530         case 16:
531                 break;
532         default:
533                 printk(KERN_ERR "%s: invalid bit depth %d\n",
534                        fbi->fb.fix.id, var->bits_per_pixel);
535                 break;
536         }
537         if (var->hsync_len < 1    || var->hsync_len > 64)
538                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
539                         fbi->fb.fix.id, var->hsync_len);
540         if (var->left_margin < 1  || var->left_margin > 255)
541                 printk(KERN_ERR "%s: invalid left_margin %d\n",
542                         fbi->fb.fix.id, var->left_margin);
543         if (var->right_margin < 1 || var->right_margin > 255)
544                 printk(KERN_ERR "%s: invalid right_margin %d\n",
545                         fbi->fb.fix.id, var->right_margin);
546         if (var->yres < 1         || var->yres > 1024)
547                 printk(KERN_ERR "%s: invalid yres %d\n",
548                         fbi->fb.fix.id, var->yres);
549         if (var->vsync_len < 1    || var->vsync_len > 64)
550                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
551                         fbi->fb.fix.id, var->vsync_len);
552         if (var->upper_margin < 0 || var->upper_margin > 255)
553                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
554                         fbi->fb.fix.id, var->upper_margin);
555         if (var->lower_margin < 0 || var->lower_margin > 255)
556                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
557                         fbi->fb.fix.id, var->lower_margin);
558 #endif
559
560         new_regs.lccr0 = fbi->lccr0 |
561                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
562                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
563
564         new_regs.lccr1 =
565                 LCCR1_DisWdth(var->xres) +
566                 LCCR1_HorSnchWdth(var->hsync_len) +
567                 LCCR1_BegLnDel(var->left_margin) +
568                 LCCR1_EndLnDel(var->right_margin);
569
570         /*
571          * If we have a dual scan LCD, we need to halve
572          * the YRES parameter.
573          */
574         lines_per_panel = var->yres;
575         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
576                 lines_per_panel /= 2;
577
578         new_regs.lccr2 =
579                 LCCR2_DisHght(lines_per_panel) +
580                 LCCR2_VrtSnchWdth(var->vsync_len) +
581                 LCCR2_BegFrmDel(var->upper_margin) +
582                 LCCR2_EndFrmDel(var->lower_margin);
583
584         new_regs.lccr3 = fbi->lccr3 |
585                 pxafb_bpp_to_lccr3(var) |
586                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
587                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
588
589         if (pcd)
590                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
591
592         pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
593         pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
594         pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
595         pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
596
597         /* Update shadow copy atomically */
598         local_irq_save(flags);
599
600         /* setup dma descriptors */
601         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
602         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
603         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
604
605         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
606         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
607         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
608
609 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
610
611         /* populate descriptors */
612         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
613         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
614         fbi->dmadesc_fblow_cpu->fidr  = 0;
615         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
616
617         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
618
619         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
620         fbi->dmadesc_fbhigh_cpu->fidr = 0;
621         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
622
623         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
624         fbi->dmadesc_palette_cpu->fidr  = 0;
625         fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
626
627         if (var->bits_per_pixel == 16) {
628                 /* palette shouldn't be loaded in true-color mode */
629                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
630                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
631                 /* init it to something, even though we won't be using it */
632                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
633         } else {
634                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
635                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
636                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
637         }
638
639 #if 0
640         pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
641         pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
642         pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
643         pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
644         pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
645         pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
646
647         pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
648         pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
649         pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
650
651         pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
652         pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
653         pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
654
655         pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
656         pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
657         pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
658 #endif
659
660         fbi->reg_lccr0 = new_regs.lccr0;
661         fbi->reg_lccr1 = new_regs.lccr1;
662         fbi->reg_lccr2 = new_regs.lccr2;
663         fbi->reg_lccr3 = new_regs.lccr3;
664         set_hsync_time(fbi, pcd);
665         local_irq_restore(flags);
666
667         /*
668          * Only update the registers if the controller is enabled
669          * and something has changed.
670          */
671         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
672             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
673             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
674                 pxafb_schedule_work(fbi, C_REENABLE);
675
676         return 0;
677 }
678
679 /*
680  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
681  * Do not call them directly; set_ctrlr_state does the correct serialisation
682  * to ensure that things happen in the right way 100% of time time.
683  *      -- rmk
684  */
685 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
686 {
687         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
688
689         if (pxafb_backlight_power)
690                 pxafb_backlight_power(on);
691 }
692
693 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
694 {
695         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
696
697         if (pxafb_lcd_power)
698                 pxafb_lcd_power(on);
699 }
700
701 static void pxafb_setup_gpio(struct pxafb_info *fbi)
702 {
703         int gpio, ldd_bits;
704         unsigned int lccr0 = fbi->lccr0;
705
706         /*
707          * setup is based on type of panel supported
708         */
709
710         /* 4 bit interface */
711         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
712             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
713             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
714                 ldd_bits = 4;
715
716         /* 8 bit interface */
717         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
718                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
719                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
720                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
721                 ldd_bits = 8;
722
723         /* 16 bit interface */
724         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
725                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
726                 ldd_bits = 16;
727
728         else {
729                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
730                 return;
731         }
732
733         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
734                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
735         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
736         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
737         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
738         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
739 }
740
741 static void pxafb_enable_controller(struct pxafb_info *fbi)
742 {
743         pr_debug("pxafb: Enabling LCD controller\n");
744         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
745         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
746         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
747         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
748         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
749         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
750
751         /* enable LCD controller clock */
752         pxa_set_cken(CKEN16_LCD, 1);
753
754         /* Sequence from 11.7.10 */
755         LCCR3 = fbi->reg_lccr3;
756         LCCR2 = fbi->reg_lccr2;
757         LCCR1 = fbi->reg_lccr1;
758         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
759
760         FDADR0 = fbi->fdadr0;
761         FDADR1 = fbi->fdadr1;
762         LCCR0 |= LCCR0_ENB;
763
764         pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
765         pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
766         pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
767         pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
768         pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
769         pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
770 }
771
772 static void pxafb_disable_controller(struct pxafb_info *fbi)
773 {
774         DECLARE_WAITQUEUE(wait, current);
775
776         pr_debug("pxafb: disabling LCD controller\n");
777
778         set_current_state(TASK_UNINTERRUPTIBLE);
779         add_wait_queue(&fbi->ctrlr_wait, &wait);
780
781         LCSR = 0xffffffff;      /* Clear LCD Status Register */
782         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
783         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
784
785         schedule_timeout(20 * HZ / 1000);
786         remove_wait_queue(&fbi->ctrlr_wait, &wait);
787
788         /* disable LCD controller clock */
789         pxa_set_cken(CKEN16_LCD, 0);
790 }
791
792 /*
793  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
794  */
795 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
796 {
797         struct pxafb_info *fbi = dev_id;
798         unsigned int lcsr = LCSR;
799
800         if (lcsr & LCSR_LDD) {
801                 LCCR0 |= LCCR0_LDM;
802                 wake_up(&fbi->ctrlr_wait);
803         }
804
805         LCSR = lcsr;
806         return IRQ_HANDLED;
807 }
808
809 /*
810  * This function must be called from task context only, since it will
811  * sleep when disabling the LCD controller, or if we get two contending
812  * processes trying to alter state.
813  */
814 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
815 {
816         u_int old_state;
817
818         down(&fbi->ctrlr_sem);
819
820         old_state = fbi->state;
821
822         /*
823          * Hack around fbcon initialisation.
824          */
825         if (old_state == C_STARTUP && state == C_REENABLE)
826                 state = C_ENABLE;
827
828         switch (state) {
829         case C_DISABLE_CLKCHANGE:
830                 /*
831                  * Disable controller for clock change.  If the
832                  * controller is already disabled, then do nothing.
833                  */
834                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
835                         fbi->state = state;
836                         //TODO __pxafb_lcd_power(fbi, 0);
837                         pxafb_disable_controller(fbi);
838                 }
839                 break;
840
841         case C_DISABLE_PM:
842         case C_DISABLE:
843                 /*
844                  * Disable controller
845                  */
846                 if (old_state != C_DISABLE) {
847                         fbi->state = state;
848                         __pxafb_backlight_power(fbi, 0);
849                         __pxafb_lcd_power(fbi, 0);
850                         if (old_state != C_DISABLE_CLKCHANGE)
851                                 pxafb_disable_controller(fbi);
852                 }
853                 break;
854
855         case C_ENABLE_CLKCHANGE:
856                 /*
857                  * Enable the controller after clock change.  Only
858                  * do this if we were disabled for the clock change.
859                  */
860                 if (old_state == C_DISABLE_CLKCHANGE) {
861                         fbi->state = C_ENABLE;
862                         pxafb_enable_controller(fbi);
863                         //TODO __pxafb_lcd_power(fbi, 1);
864                 }
865                 break;
866
867         case C_REENABLE:
868                 /*
869                  * Re-enable the controller only if it was already
870                  * enabled.  This is so we reprogram the control
871                  * registers.
872                  */
873                 if (old_state == C_ENABLE) {
874                         pxafb_disable_controller(fbi);
875                         pxafb_setup_gpio(fbi);
876                         pxafb_enable_controller(fbi);
877                 }
878                 break;
879
880         case C_ENABLE_PM:
881                 /*
882                  * Re-enable the controller after PM.  This is not
883                  * perfect - think about the case where we were doing
884                  * a clock change, and we suspended half-way through.
885                  */
886                 if (old_state != C_DISABLE_PM)
887                         break;
888                 /* fall through */
889
890         case C_ENABLE:
891                 /*
892                  * Power up the LCD screen, enable controller, and
893                  * turn on the backlight.
894                  */
895                 if (old_state != C_ENABLE) {
896                         fbi->state = C_ENABLE;
897                         pxafb_setup_gpio(fbi);
898                         pxafb_enable_controller(fbi);
899                         __pxafb_lcd_power(fbi, 1);
900                         __pxafb_backlight_power(fbi, 1);
901                 }
902                 break;
903         }
904         up(&fbi->ctrlr_sem);
905 }
906
907 /*
908  * Our LCD controller task (which is called when we blank or unblank)
909  * via keventd.
910  */
911 static void pxafb_task(void *dummy)
912 {
913         struct pxafb_info *fbi = dummy;
914         u_int state = xchg(&fbi->task_state, -1);
915
916         set_ctrlr_state(fbi, state);
917 }
918
919 #ifdef CONFIG_CPU_FREQ
920 /*
921  * CPU clock speed change handler.  We need to adjust the LCD timing
922  * parameters when the CPU clock is adjusted by the power management
923  * subsystem.
924  *
925  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
926  */
927 static int
928 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
929 {
930         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
931         //TODO struct cpufreq_freqs *f = data;
932         u_int pcd;
933
934         switch (val) {
935         case CPUFREQ_PRECHANGE:
936                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
937                 break;
938
939         case CPUFREQ_POSTCHANGE:
940                 pcd = get_pcd(fbi->fb.var.pixclock);
941                 set_hsync_time(fbi, pcd);
942                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
943                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
944                 break;
945         }
946         return 0;
947 }
948
949 static int
950 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
951 {
952         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
953         struct fb_var_screeninfo *var = &fbi->fb.var;
954         struct cpufreq_policy *policy = data;
955
956         switch (val) {
957         case CPUFREQ_ADJUST:
958         case CPUFREQ_INCOMPATIBLE:
959                 printk(KERN_DEBUG "min dma period: %d ps, "
960                         "new clock %d kHz\n", pxafb_display_dma_period(var),
961                         policy->max);
962                 // TODO: fill in min/max values
963                 break;
964 #if 0
965         case CPUFREQ_NOTIFY:
966                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
967                 do {} while(0);
968                 /* todo: panic if min/max values aren't fulfilled
969                  * [can't really happen unless there's a bug in the
970                  * CPU policy verification process *
971                  */
972                 break;
973 #endif
974         }
975         return 0;
976 }
977 #endif
978
979 #ifdef CONFIG_PM
980 /*
981  * Power management hooks.  Note that we won't be called from IRQ context,
982  * unlike the blank functions above, so we may sleep.
983  */
984 static int pxafb_suspend(struct device *dev, pm_message_t state)
985 {
986         struct pxafb_info *fbi = dev_get_drvdata(dev);
987
988         set_ctrlr_state(fbi, C_DISABLE_PM);
989         return 0;
990 }
991
992 static int pxafb_resume(struct device *dev)
993 {
994         struct pxafb_info *fbi = dev_get_drvdata(dev);
995
996         set_ctrlr_state(fbi, C_ENABLE_PM);
997         return 0;
998 }
999 #else
1000 #define pxafb_suspend   NULL
1001 #define pxafb_resume    NULL
1002 #endif
1003
1004 /*
1005  * pxafb_map_video_memory():
1006  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1007  *      remapped into a non-cached, non-buffered, memory region to
1008  *      allow palette and pixel writes to occur without flushing the
1009  *      cache.  Once this area is remapped, all virtual memory
1010  *      access to the video memory should occur at the new region.
1011  */
1012 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1013 {
1014         u_long palette_mem_size;
1015
1016         /*
1017          * We reserve one page for the palette, plus the size
1018          * of the framebuffer.
1019          */
1020         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1021         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1022                                               &fbi->map_dma, GFP_KERNEL);
1023
1024         if (fbi->map_cpu) {
1025                 /* prevent initial garbage on screen */
1026                 memset(fbi->map_cpu, 0, fbi->map_size);
1027                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1028                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1029                 /*
1030                  * FIXME: this is actually the wrong thing to place in
1031                  * smem_start.  But fbdev suffers from the problem that
1032                  * it needs an API which doesn't exist (in this case,
1033                  * dma_writecombine_mmap)
1034                  */
1035                 fbi->fb.fix.smem_start = fbi->screen_dma;
1036
1037                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1038
1039                 palette_mem_size = fbi->palette_size * sizeof(u16);
1040                 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1041
1042                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1043                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1044         }
1045
1046         return fbi->map_cpu ? 0 : -ENOMEM;
1047 }
1048
1049 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1050 {
1051         struct pxafb_info *fbi;
1052         void *addr;
1053         struct pxafb_mach_info *inf = dev->platform_data;
1054
1055         /* Alloc the pxafb_info and pseudo_palette in one step */
1056         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1057         if (!fbi)
1058                 return NULL;
1059
1060         memset(fbi, 0, sizeof(struct pxafb_info));
1061         fbi->dev = dev;
1062
1063         strcpy(fbi->fb.fix.id, PXA_NAME);
1064
1065         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1066         fbi->fb.fix.type_aux    = 0;
1067         fbi->fb.fix.xpanstep    = 0;
1068         fbi->fb.fix.ypanstep    = 0;
1069         fbi->fb.fix.ywrapstep   = 0;
1070         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1071
1072         fbi->fb.var.nonstd      = 0;
1073         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1074         fbi->fb.var.height      = -1;
1075         fbi->fb.var.width       = -1;
1076         fbi->fb.var.accel_flags = 0;
1077         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1078
1079         fbi->fb.fbops           = &pxafb_ops;
1080         fbi->fb.flags           = FBINFO_DEFAULT;
1081         fbi->fb.node            = -1;
1082
1083         addr = fbi;
1084         addr = addr + sizeof(struct pxafb_info);
1085         fbi->fb.pseudo_palette  = addr;
1086
1087         fbi->max_xres                   = inf->xres;
1088         fbi->fb.var.xres                = inf->xres;
1089         fbi->fb.var.xres_virtual        = inf->xres;
1090         fbi->max_yres                   = inf->yres;
1091         fbi->fb.var.yres                = inf->yres;
1092         fbi->fb.var.yres_virtual        = inf->yres;
1093         fbi->max_bpp                    = inf->bpp;
1094         fbi->fb.var.bits_per_pixel      = inf->bpp;
1095         fbi->fb.var.pixclock            = inf->pixclock;
1096         fbi->fb.var.hsync_len           = inf->hsync_len;
1097         fbi->fb.var.left_margin         = inf->left_margin;
1098         fbi->fb.var.right_margin        = inf->right_margin;
1099         fbi->fb.var.vsync_len           = inf->vsync_len;
1100         fbi->fb.var.upper_margin        = inf->upper_margin;
1101         fbi->fb.var.lower_margin        = inf->lower_margin;
1102         fbi->fb.var.sync                = inf->sync;
1103         fbi->fb.var.grayscale           = inf->cmap_greyscale;
1104         fbi->cmap_inverse               = inf->cmap_inverse;
1105         fbi->cmap_static                = inf->cmap_static;
1106         fbi->lccr0                      = inf->lccr0;
1107         fbi->lccr3                      = inf->lccr3;
1108         fbi->state                      = C_STARTUP;
1109         fbi->task_state                 = (u_char)-1;
1110         fbi->fb.fix.smem_len            = fbi->max_xres * fbi->max_yres *
1111                                           fbi->max_bpp / 8;
1112
1113         init_waitqueue_head(&fbi->ctrlr_wait);
1114         INIT_WORK(&fbi->task, pxafb_task, fbi);
1115         init_MUTEX(&fbi->ctrlr_sem);
1116
1117         return fbi;
1118 }
1119
1120 #ifdef CONFIG_FB_PXA_PARAMETERS
1121 static int __init pxafb_parse_options(struct device *dev, char *options)
1122 {
1123         struct pxafb_mach_info *inf = dev->platform_data;
1124         char *this_opt;
1125
1126         if (!options || !*options)
1127                 return 0;
1128
1129         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1130
1131         /* could be made table driven or similar?... */
1132         while ((this_opt = strsep(&options, ",")) != NULL) {
1133                 if (!strncmp(this_opt, "mode:", 5)) {
1134                         const char *name = this_opt+5;
1135                         unsigned int namelen = strlen(name);
1136                         int res_specified = 0, bpp_specified = 0;
1137                         unsigned int xres = 0, yres = 0, bpp = 0;
1138                         int yres_specified = 0;
1139                         int i;
1140                         for (i = namelen-1; i >= 0; i--) {
1141                                 switch (name[i]) {
1142                                 case '-':
1143                                         namelen = i;
1144                                         if (!bpp_specified && !yres_specified) {
1145                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1146                                                 bpp_specified = 1;
1147                                         } else
1148                                                 goto done;
1149                                         break;
1150                                 case 'x':
1151                                         if (!yres_specified) {
1152                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1153                                                 yres_specified = 1;
1154                                         } else
1155                                                 goto done;
1156                                         break;
1157                                 case '0'...'9':
1158                                         break;
1159                                 default:
1160                                         goto done;
1161                                 }
1162                         }
1163                         if (i < 0 && yres_specified) {
1164                                 xres = simple_strtoul(name, NULL, 0);
1165                                 res_specified = 1;
1166                         }
1167                 done:
1168                         if (res_specified) {
1169                                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1170                                 inf->xres = xres; inf->yres = yres;
1171                         }
1172                         if (bpp_specified)
1173                                 switch (bpp) {
1174                                 case 1:
1175                                 case 2:
1176                                 case 4:
1177                                 case 8:
1178                                 case 16:
1179                                         inf->bpp = bpp;
1180                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1181                                         break;
1182                                 default:
1183                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1184                                 }
1185                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1186                         inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1187                         dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1188                 } else if (!strncmp(this_opt, "left:", 5)) {
1189                         inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1190                         dev_info(dev, "override left: %u\n", inf->left_margin);
1191                 } else if (!strncmp(this_opt, "right:", 6)) {
1192                         inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1193                         dev_info(dev, "override right: %u\n", inf->right_margin);
1194                 } else if (!strncmp(this_opt, "upper:", 6)) {
1195                         inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1196                         dev_info(dev, "override upper: %u\n", inf->upper_margin);
1197                 } else if (!strncmp(this_opt, "lower:", 6)) {
1198                         inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1199                         dev_info(dev, "override lower: %u\n", inf->lower_margin);
1200                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1201                         inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1202                         dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1203                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1204                         inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1205                         dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1206                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1207                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1208                                 dev_info(dev, "override hsync: Active Low\n");
1209                                 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1210                         } else {
1211                                 dev_info(dev, "override hsync: Active High\n");
1212                                 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1213                         }
1214                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1215                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1216                                 dev_info(dev, "override vsync: Active Low\n");
1217                                 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1218                         } else {
1219                                 dev_info(dev, "override vsync: Active High\n");
1220                                 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1221                         }
1222                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1223                         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1224                                 dev_info(dev, "override double pixel clock: false\n");
1225                                 inf->lccr3 &= ~LCCR3_DPC;
1226                         } else {
1227                                 dev_info(dev, "override double pixel clock: true\n");
1228                                 inf->lccr3 |= LCCR3_DPC;
1229                         }
1230                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1231                         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1232                                 dev_info(dev, "override output enable: active low\n");
1233                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1234                         } else {
1235                                 dev_info(dev, "override output enable: active high\n");
1236                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1237                         }
1238                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1239                         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1240                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1241                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1242                         } else {
1243                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1244                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1245                         }
1246                 } else if (!strncmp(this_opt, "color", 5)) {
1247                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1248                 } else if (!strncmp(this_opt, "mono", 4)) {
1249                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1250                 } else if (!strncmp(this_opt, "active", 6)) {
1251                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1252                 } else if (!strncmp(this_opt, "passive", 7)) {
1253                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1254                 } else if (!strncmp(this_opt, "single", 6)) {
1255                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1256                 } else if (!strncmp(this_opt, "dual", 4)) {
1257                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1258                 } else if (!strncmp(this_opt, "4pix", 4)) {
1259                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1260                 } else if (!strncmp(this_opt, "8pix", 4)) {
1261                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1262                 } else {
1263                         dev_err(dev, "unknown option: %s\n", this_opt);
1264                         return -EINVAL;
1265                 }
1266         }
1267         return 0;
1268
1269 }
1270 #endif
1271
1272 int __init pxafb_probe(struct device *dev)
1273 {
1274         struct pxafb_info *fbi;
1275         struct pxafb_mach_info *inf;
1276         int ret;
1277
1278         dev_dbg(dev, "pxafb_probe\n");
1279
1280         inf = dev->platform_data;
1281         ret = -ENOMEM;
1282         fbi = NULL;
1283         if (!inf)
1284                 goto failed;
1285
1286 #ifdef CONFIG_FB_PXA_PARAMETERS
1287         ret = pxafb_parse_options(dev, g_options);
1288         if (ret < 0)
1289                 goto failed;
1290 #endif
1291
1292 #ifdef DEBUG_VAR
1293         /* Check for various illegal bit-combinations. Currently only
1294          * a warning is given. */
1295
1296         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1297                 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1298                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1299         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1300                 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1301                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1302         if (inf->lccr0 & LCCR0_DPD &&
1303             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1304              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1305              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1306                 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1307                          " single panel mode\n");
1308         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1309             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1310                 dev_warn(dev, "Dual panel only valid in passive mode\n");
1311         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1312              (inf->upper_margin || inf->lower_margin))
1313                 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1314 #endif
1315
1316         dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1317         if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1318                 dev_err(dev, "Invalid resolution or bit depth\n");
1319                 ret = -EINVAL;
1320                 goto failed;
1321         }
1322         pxafb_backlight_power = inf->pxafb_backlight_power;
1323         pxafb_lcd_power = inf->pxafb_lcd_power;
1324         fbi = pxafb_init_fbinfo(dev);
1325         if (!fbi) {
1326                 dev_err(dev, "Failed to initialize framebuffer device\n");
1327                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1328                 goto failed;
1329         }
1330
1331         /* Initialize video memory */
1332         ret = pxafb_map_video_memory(fbi);
1333         if (ret) {
1334                 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1335                 ret = -ENOMEM;
1336                 goto failed;
1337         }
1338
1339         ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1340         if (ret) {
1341                 dev_err(dev, "request_irq failed: %d\n", ret);
1342                 ret = -EBUSY;
1343                 goto failed;
1344         }
1345
1346         /*
1347          * This makes sure that our colour bitfield
1348          * descriptors are correctly initialised.
1349          */
1350         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1351         pxafb_set_par(&fbi->fb);
1352
1353         dev_set_drvdata(dev, fbi);
1354
1355         ret = register_framebuffer(&fbi->fb);
1356         if (ret < 0) {
1357                 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1358                 goto failed;
1359         }
1360
1361 #ifdef CONFIG_PM
1362         // TODO
1363 #endif
1364
1365 #ifdef CONFIG_CPU_FREQ
1366         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1367         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1368         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1369         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1370 #endif
1371
1372         /*
1373          * Ok, now enable the LCD controller
1374          */
1375         set_ctrlr_state(fbi, C_ENABLE);
1376
1377         return 0;
1378
1379 failed:
1380         dev_set_drvdata(dev, NULL);
1381         kfree(fbi);
1382         return ret;
1383 }
1384
1385 static struct device_driver pxafb_driver = {
1386         .name           = "pxa2xx-fb",
1387         .bus            = &platform_bus_type,
1388         .probe          = pxafb_probe,
1389 #ifdef CONFIG_PM
1390         .suspend        = pxafb_suspend,
1391         .resume         = pxafb_resume,
1392 #endif
1393 };
1394
1395 #ifndef MODULE
1396 int __devinit pxafb_setup(char *options)
1397 {
1398 # ifdef CONFIG_FB_PXA_PARAMETERS
1399         strlcpy(g_options, options, sizeof(g_options));
1400 # endif
1401         return 0;
1402 }
1403 #else
1404 # ifdef CONFIG_FB_PXA_PARAMETERS
1405 module_param_string(options, g_options, sizeof(g_options), 0);
1406 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1407 # endif
1408 #endif
1409
1410 int __devinit pxafb_init(void)
1411 {
1412 #ifndef MODULE
1413         char *option = NULL;
1414
1415         if (fb_get_options("pxafb", &option))
1416                 return -ENODEV;
1417         pxafb_setup(option);
1418 #endif
1419         return driver_register(&pxafb_driver);
1420 }
1421
1422 module_init(pxafb_init);
1423
1424 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1425 MODULE_LICENSE("GPL");