Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa...
[linux-2.6.git] / drivers / video / pxafb.c
1 /*
2  *  linux/drivers/video/pxafb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas.
5  *  Copyright (C) 2004 Jean-Frederic Clere.
6  *  Copyright (C) 2004 Ian Campbell.
7  *  Copyright (C) 2004 Jeff Lackey.
8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9  *  which in turn is
10  *   Based on acornfb.c Copyright (C) Russell King.
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive for
14  * more details.
15  *
16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
17  *
18  * Please direct your questions and comments on this driver to the following
19  * email address:
20  *
21  *      linux-arm-kernel@lists.arm.linux.org.uk
22  *
23  * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24  *
25  *   Copyright (C) 2004, Intel Corporation
26  *
27  *     2003/08/27: <yu.tang@intel.com>
28  *     2004/03/10: <stanley.cai@intel.com>
29  *     2004/10/28: <yan.yin@intel.com>
30  *
31  *   Copyright (C) 2006-2008 Marvell International Ltd.
32  *   All Rights Reserved
33  */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
41 #include <linux/interrupt.h>
42 #include <linux/slab.h>
43 #include <linux/mm.h>
44 #include <linux/fb.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/cpufreq.h>
49 #include <linux/platform_device.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/clk.h>
52 #include <linux/err.h>
53 #include <linux/completion.h>
54 #include <linux/mutex.h>
55 #include <linux/kthread.h>
56 #include <linux/freezer.h>
57
58 #include <mach/hardware.h>
59 #include <asm/io.h>
60 #include <asm/irq.h>
61 #include <asm/div64.h>
62 #include <mach/pxa-regs.h>
63 #include <mach/bitfield.h>
64 #include <mach/pxafb.h>
65
66 /*
67  * Complain if VAR is out of range.
68  */
69 #define DEBUG_VAR 1
70
71 #include "pxafb.h"
72
73 /* Bits which should not be set in machine configuration structures */
74 #define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
75                                          LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
76                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
77
78 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
79                                          LCCR3_PCD | LCCR3_BPP(0xf))
80
81 static int pxafb_activate_var(struct fb_var_screeninfo *var,
82                                 struct pxafb_info *);
83 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
84 static void setup_base_frame(struct pxafb_info *fbi, int branch);
85 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
86                            unsigned long offset, size_t size);
87
88 static unsigned long video_mem_size = 0;
89
90 static inline unsigned long
91 lcd_readl(struct pxafb_info *fbi, unsigned int off)
92 {
93         return __raw_readl(fbi->mmio_base + off);
94 }
95
96 static inline void
97 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
98 {
99         __raw_writel(val, fbi->mmio_base + off);
100 }
101
102 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
103 {
104         unsigned long flags;
105
106         local_irq_save(flags);
107         /*
108          * We need to handle two requests being made at the same time.
109          * There are two important cases:
110          *  1. When we are changing VT (C_REENABLE) while unblanking
111          *     (C_ENABLE) We must perform the unblanking, which will
112          *     do our REENABLE for us.
113          *  2. When we are blanking, but immediately unblank before
114          *     we have blanked.  We do the "REENABLE" thing here as
115          *     well, just to be sure.
116          */
117         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
118                 state = (u_int) -1;
119         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
120                 state = C_REENABLE;
121
122         if (state != (u_int)-1) {
123                 fbi->task_state = state;
124                 schedule_work(&fbi->task);
125         }
126         local_irq_restore(flags);
127 }
128
129 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
130 {
131         chan &= 0xffff;
132         chan >>= 16 - bf->length;
133         return chan << bf->offset;
134 }
135
136 static int
137 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
138                        u_int trans, struct fb_info *info)
139 {
140         struct pxafb_info *fbi = (struct pxafb_info *)info;
141         u_int val;
142
143         if (regno >= fbi->palette_size)
144                 return 1;
145
146         if (fbi->fb.var.grayscale) {
147                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
148                 return 0;
149         }
150
151         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
152         case LCCR4_PAL_FOR_0:
153                 val  = ((red   >>  0) & 0xf800);
154                 val |= ((green >>  5) & 0x07e0);
155                 val |= ((blue  >> 11) & 0x001f);
156                 fbi->palette_cpu[regno] = val;
157                 break;
158         case LCCR4_PAL_FOR_1:
159                 val  = ((red   << 8) & 0x00f80000);
160                 val |= ((green >> 0) & 0x0000fc00);
161                 val |= ((blue  >> 8) & 0x000000f8);
162                 ((u32 *)(fbi->palette_cpu))[regno] = val;
163                 break;
164         case LCCR4_PAL_FOR_2:
165                 val  = ((red   << 8) & 0x00fc0000);
166                 val |= ((green >> 0) & 0x0000fc00);
167                 val |= ((blue  >> 8) & 0x000000fc);
168                 ((u32 *)(fbi->palette_cpu))[regno] = val;
169                 break;
170         case LCCR4_PAL_FOR_3:
171                 val  = ((red   << 8) & 0x00ff0000);
172                 val |= ((green >> 0) & 0x0000ff00);
173                 val |= ((blue  >> 8) & 0x000000ff);
174                 ((u32 *)(fbi->palette_cpu))[regno] = val;
175                 break;
176         }
177
178         return 0;
179 }
180
181 static int
182 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
183                    u_int trans, struct fb_info *info)
184 {
185         struct pxafb_info *fbi = (struct pxafb_info *)info;
186         unsigned int val;
187         int ret = 1;
188
189         /*
190          * If inverse mode was selected, invert all the colours
191          * rather than the register number.  The register number
192          * is what you poke into the framebuffer to produce the
193          * colour you requested.
194          */
195         if (fbi->cmap_inverse) {
196                 red   = 0xffff - red;
197                 green = 0xffff - green;
198                 blue  = 0xffff - blue;
199         }
200
201         /*
202          * If greyscale is true, then we convert the RGB value
203          * to greyscale no matter what visual we are using.
204          */
205         if (fbi->fb.var.grayscale)
206                 red = green = blue = (19595 * red + 38470 * green +
207                                         7471 * blue) >> 16;
208
209         switch (fbi->fb.fix.visual) {
210         case FB_VISUAL_TRUECOLOR:
211                 /*
212                  * 16-bit True Colour.  We encode the RGB value
213                  * according to the RGB bitfield information.
214                  */
215                 if (regno < 16) {
216                         u32 *pal = fbi->fb.pseudo_palette;
217
218                         val  = chan_to_field(red, &fbi->fb.var.red);
219                         val |= chan_to_field(green, &fbi->fb.var.green);
220                         val |= chan_to_field(blue, &fbi->fb.var.blue);
221
222                         pal[regno] = val;
223                         ret = 0;
224                 }
225                 break;
226
227         case FB_VISUAL_STATIC_PSEUDOCOLOR:
228         case FB_VISUAL_PSEUDOCOLOR:
229                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
230                 break;
231         }
232
233         return ret;
234 }
235
236 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
237 static inline int var_to_depth(struct fb_var_screeninfo *var)
238 {
239         return var->red.length + var->green.length +
240                 var->blue.length + var->transp.length;
241 }
242
243 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
244 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
245 {
246         int bpp = -EINVAL;
247
248         switch (var->bits_per_pixel) {
249         case 1:  bpp = 0; break;
250         case 2:  bpp = 1; break;
251         case 4:  bpp = 2; break;
252         case 8:  bpp = 3; break;
253         case 16: bpp = 4; break;
254         case 24:
255                 switch (var_to_depth(var)) {
256                 case 18: bpp = 6; break; /* 18-bits/pixel packed */
257                 case 19: bpp = 8; break; /* 19-bits/pixel packed */
258                 case 24: bpp = 9; break;
259                 }
260                 break;
261         case 32:
262                 switch (var_to_depth(var)) {
263                 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
264                 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
265                 case 25: bpp = 10; break;
266                 }
267                 break;
268         }
269         return bpp;
270 }
271
272 /*
273  *  pxafb_var_to_lccr3():
274  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
275  *
276  *  NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
277  *  implication of the acutal use of transparency bit,  which we handle it
278  *  here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
279  *  Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280  *
281  *  Transparency for palette pixel formats is not supported at the moment.
282  */
283 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284 {
285         int bpp = pxafb_var_to_bpp(var);
286         uint32_t lccr3;
287
288         if (bpp < 0)
289                 return 0;
290
291         lccr3 = LCCR3_BPP(bpp);
292
293         switch (var_to_depth(var)) {
294         case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
295         case 18: lccr3 |= LCCR3_PDFOR_3; break;
296         case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
297                  break;
298         case 19:
299         case 25: lccr3 |= LCCR3_PDFOR_0; break;
300         }
301         return lccr3;
302 }
303
304 #define SET_PIXFMT(v, r, g, b, t)                               \
305 ({                                                              \
306         (v)->transp.offset = (t) ? (r) + (g) + (b) : 0;         \
307         (v)->transp.length = (t) ? (t) : 0;                     \
308         (v)->blue.length   = (b); (v)->blue.offset = 0;         \
309         (v)->green.length  = (g); (v)->green.offset = (b);      \
310         (v)->red.length    = (r); (v)->red.offset = (b) + (g);  \
311 })
312
313 /* set the RGBT bitfields of fb_var_screeninf according to
314  * var->bits_per_pixel and given depth
315  */
316 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
317 {
318         if (depth == 0)
319                 depth = var->bits_per_pixel;
320
321         if (var->bits_per_pixel < 16) {
322                 /* indexed pixel formats */
323                 var->red.offset    = 0; var->red.length    = 8;
324                 var->green.offset  = 0; var->green.length  = 8;
325                 var->blue.offset   = 0; var->blue.length   = 8;
326                 var->transp.offset = 0; var->transp.length = 8;
327         }
328
329         switch (depth) {
330         case 16: var->transp.length ?
331                  SET_PIXFMT(var, 5, 5, 5, 1) :          /* RGBT555 */
332                  SET_PIXFMT(var, 5, 6, 5, 0); break;    /* RGB565 */
333         case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;    /* RGB666 */
334         case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;    /* RGBT666 */
335         case 24: var->transp.length ?
336                  SET_PIXFMT(var, 8, 8, 7, 1) :          /* RGBT887 */
337                  SET_PIXFMT(var, 8, 8, 8, 0); break;    /* RGB888 */
338         case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;    /* RGBT888 */
339         }
340 }
341
342 #ifdef CONFIG_CPU_FREQ
343 /*
344  *  pxafb_display_dma_period()
345  *    Calculate the minimum period (in picoseconds) between two DMA
346  *    requests for the LCD controller.  If we hit this, it means we're
347  *    doing nothing but LCD DMA.
348  */
349 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
350 {
351         /*
352          * Period = pixclock * bits_per_byte * bytes_per_transfer
353          *              / memory_bits_per_pixel;
354          */
355         return var->pixclock * 8 * 16 / var->bits_per_pixel;
356 }
357 #endif
358
359 /*
360  * Select the smallest mode that allows the desired resolution to be
361  * displayed. If desired parameters can be rounded up.
362  */
363 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
364                                              struct fb_var_screeninfo *var)
365 {
366         struct pxafb_mode_info *mode = NULL;
367         struct pxafb_mode_info *modelist = mach->modes;
368         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
369         unsigned int i;
370
371         for (i = 0; i < mach->num_modes; i++) {
372                 if (modelist[i].xres >= var->xres &&
373                     modelist[i].yres >= var->yres &&
374                     modelist[i].xres < best_x &&
375                     modelist[i].yres < best_y &&
376                     modelist[i].bpp >= var->bits_per_pixel) {
377                         best_x = modelist[i].xres;
378                         best_y = modelist[i].yres;
379                         mode = &modelist[i];
380                 }
381         }
382
383         return mode;
384 }
385
386 static void pxafb_setmode(struct fb_var_screeninfo *var,
387                           struct pxafb_mode_info *mode)
388 {
389         var->xres               = mode->xres;
390         var->yres               = mode->yres;
391         var->bits_per_pixel     = mode->bpp;
392         var->pixclock           = mode->pixclock;
393         var->hsync_len          = mode->hsync_len;
394         var->left_margin        = mode->left_margin;
395         var->right_margin       = mode->right_margin;
396         var->vsync_len          = mode->vsync_len;
397         var->upper_margin       = mode->upper_margin;
398         var->lower_margin       = mode->lower_margin;
399         var->sync               = mode->sync;
400         var->grayscale          = mode->cmap_greyscale;
401
402         /* set the initial RGBA bitfields */
403         pxafb_set_pixfmt(var, mode->depth);
404 }
405
406 static int pxafb_adjust_timing(struct pxafb_info *fbi,
407                                struct fb_var_screeninfo *var)
408 {
409         int line_length;
410
411         var->xres = max_t(int, var->xres, MIN_XRES);
412         var->yres = max_t(int, var->yres, MIN_YRES);
413
414         if (!(fbi->lccr0 & LCCR0_LCDT)) {
415                 clamp_val(var->hsync_len, 1, 64);
416                 clamp_val(var->vsync_len, 1, 64);
417                 clamp_val(var->left_margin,  1, 255);
418                 clamp_val(var->right_margin, 1, 255);
419                 clamp_val(var->upper_margin, 1, 255);
420                 clamp_val(var->lower_margin, 1, 255);
421         }
422
423         /* make sure each line is aligned on word boundary */
424         line_length = var->xres * var->bits_per_pixel / 8;
425         line_length = ALIGN(line_length, 4);
426         var->xres = line_length * 8 / var->bits_per_pixel;
427
428         /* we don't support xpan, force xres_virtual to be equal to xres */
429         var->xres_virtual = var->xres;
430
431         if (var->accel_flags & FB_ACCELF_TEXT)
432                 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
433         else
434                 var->yres_virtual = max(var->yres_virtual, var->yres);
435
436         /* check for limits */
437         if (var->xres > MAX_XRES || var->yres > MAX_YRES)
438                 return -EINVAL;
439
440         if (var->yres > var->yres_virtual)
441                 return -EINVAL;
442
443         return 0;
444 }
445
446 /*
447  *  pxafb_check_var():
448  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
449  *    if it's too big, return -EINVAL.
450  *
451  *    Round up in the following order: bits_per_pixel, xres,
452  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
453  *    bitfields, horizontal timing, vertical timing.
454  */
455 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
456 {
457         struct pxafb_info *fbi = (struct pxafb_info *)info;
458         struct pxafb_mach_info *inf = fbi->dev->platform_data;
459         int err;
460
461         if (inf->fixed_modes) {
462                 struct pxafb_mode_info *mode;
463
464                 mode = pxafb_getmode(inf, var);
465                 if (!mode)
466                         return -EINVAL;
467                 pxafb_setmode(var, mode);
468         }
469
470         /* do a test conversion to BPP fields to check the color formats */
471         err = pxafb_var_to_bpp(var);
472         if (err < 0)
473                 return err;
474
475         pxafb_set_pixfmt(var, var_to_depth(var));
476
477         err = pxafb_adjust_timing(fbi, var);
478         if (err)
479                 return err;
480
481 #ifdef CONFIG_CPU_FREQ
482         pr_debug("pxafb: dma period = %d ps\n",
483                  pxafb_display_dma_period(var));
484 #endif
485
486         return 0;
487 }
488
489 /*
490  * pxafb_set_par():
491  *      Set the user defined part of the display for the specified console
492  */
493 static int pxafb_set_par(struct fb_info *info)
494 {
495         struct pxafb_info *fbi = (struct pxafb_info *)info;
496         struct fb_var_screeninfo *var = &info->var;
497
498         if (var->bits_per_pixel >= 16)
499                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
500         else if (!fbi->cmap_static)
501                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
502         else {
503                 /*
504                  * Some people have weird ideas about wanting static
505                  * pseudocolor maps.  I suspect their user space
506                  * applications are broken.
507                  */
508                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
509         }
510
511         fbi->fb.fix.line_length = var->xres_virtual *
512                                   var->bits_per_pixel / 8;
513         if (var->bits_per_pixel >= 16)
514                 fbi->palette_size = 0;
515         else
516                 fbi->palette_size = var->bits_per_pixel == 1 ?
517                                         4 : 1 << var->bits_per_pixel;
518
519         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
520
521         if (fbi->fb.var.bits_per_pixel >= 16)
522                 fb_dealloc_cmap(&fbi->fb.cmap);
523         else
524                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
525
526         pxafb_activate_var(var, fbi);
527
528         return 0;
529 }
530
531 static int pxafb_pan_display(struct fb_var_screeninfo *var,
532                              struct fb_info *info)
533 {
534         struct pxafb_info *fbi = (struct pxafb_info *)info;
535         int dma = DMA_MAX + DMA_BASE;
536
537         if (fbi->state != C_ENABLE)
538                 return 0;
539
540         setup_base_frame(fbi, 1);
541
542         if (fbi->lccr0 & LCCR0_SDS)
543                 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
544
545         lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
546         return 0;
547 }
548
549 /*
550  * pxafb_blank():
551  *      Blank the display by setting all palette values to zero.  Note, the
552  *      16 bpp mode does not really use the palette, so this will not
553  *      blank the display in all modes.
554  */
555 static int pxafb_blank(int blank, struct fb_info *info)
556 {
557         struct pxafb_info *fbi = (struct pxafb_info *)info;
558         int i;
559
560         switch (blank) {
561         case FB_BLANK_POWERDOWN:
562         case FB_BLANK_VSYNC_SUSPEND:
563         case FB_BLANK_HSYNC_SUSPEND:
564         case FB_BLANK_NORMAL:
565                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
566                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
567                         for (i = 0; i < fbi->palette_size; i++)
568                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
569
570                 pxafb_schedule_work(fbi, C_DISABLE);
571                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
572                 break;
573
574         case FB_BLANK_UNBLANK:
575                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
576                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
577                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
578                         fb_set_cmap(&fbi->fb.cmap, info);
579                 pxafb_schedule_work(fbi, C_ENABLE);
580         }
581         return 0;
582 }
583
584 static struct fb_ops pxafb_ops = {
585         .owner          = THIS_MODULE,
586         .fb_check_var   = pxafb_check_var,
587         .fb_set_par     = pxafb_set_par,
588         .fb_pan_display = pxafb_pan_display,
589         .fb_setcolreg   = pxafb_setcolreg,
590         .fb_fillrect    = cfb_fillrect,
591         .fb_copyarea    = cfb_copyarea,
592         .fb_imageblit   = cfb_imageblit,
593         .fb_blank       = pxafb_blank,
594 };
595
596 #ifdef CONFIG_FB_PXA_OVERLAY
597 static void overlay1fb_setup(struct pxafb_layer *ofb)
598 {
599         int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
600         unsigned long start = ofb->video_mem_phys;
601         setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
602 }
603
604 /* Depending on the enable status of overlay1/2, the DMA should be
605  * updated from FDADRx (when disabled) or FBRx (when enabled).
606  */
607 static void overlay1fb_enable(struct pxafb_layer *ofb)
608 {
609         int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
610         uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
611
612         lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
613         lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
614         lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
615 }
616
617 static void overlay1fb_disable(struct pxafb_layer *ofb)
618 {
619         uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
620
621         lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
622
623         lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
624         lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
625         lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
626
627         if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
628                 pr_warning("%s: timeout disabling overlay1\n", __func__);
629
630         lcd_writel(ofb->fbi, LCCR5, lccr5);
631 }
632
633 static void overlay2fb_setup(struct pxafb_layer *ofb)
634 {
635         int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
636         unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
637
638         if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
639                 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
640                 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
641         } else {
642                 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
643                 switch (pfor) {
644                 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
645                 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
646                 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
647                 }
648                 start[1] = start[0] + size;
649                 start[2] = start[1] + size / div;
650                 setup_frame_dma(ofb->fbi, DMA_OV2_Y,  -1, start[0], size);
651                 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
652                 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
653         }
654 }
655
656 static void overlay2fb_enable(struct pxafb_layer *ofb)
657 {
658         int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
659         int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
660         uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y]  | (enabled ? 0x1 : 0);
661         uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
662         uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
663
664         if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
665                 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
666         else {
667                 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
668                 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
669                 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
670         }
671         lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
672         lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
673 }
674
675 static void overlay2fb_disable(struct pxafb_layer *ofb)
676 {
677         uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
678
679         lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
680
681         lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
682         lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
683         lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y]  | 0x3);
684         lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
685         lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
686
687         if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
688                 pr_warning("%s: timeout disabling overlay2\n", __func__);
689 }
690
691 static struct pxafb_layer_ops ofb_ops[] = {
692         [0] = {
693                 .enable         = overlay1fb_enable,
694                 .disable        = overlay1fb_disable,
695                 .setup          = overlay1fb_setup,
696         },
697         [1] = {
698                 .enable         = overlay2fb_enable,
699                 .disable        = overlay2fb_disable,
700                 .setup          = overlay2fb_setup,
701         },
702 };
703
704 static int overlayfb_open(struct fb_info *info, int user)
705 {
706         struct pxafb_layer *ofb = (struct pxafb_layer *)info;
707
708         /* no support for framebuffer console on overlay */
709         if (user == 0)
710                 return -ENODEV;
711
712         /* allow only one user at a time */
713         if (atomic_inc_and_test(&ofb->usage))
714                 return -EBUSY;
715
716         /* unblank the base framebuffer */
717         fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
718         return 0;
719 }
720
721 static int overlayfb_release(struct fb_info *info, int user)
722 {
723         struct pxafb_layer *ofb = (struct pxafb_layer*) info;
724
725         atomic_dec(&ofb->usage);
726         ofb->ops->disable(ofb);
727
728         free_pages_exact(ofb->video_mem, ofb->video_mem_size);
729         ofb->video_mem = NULL;
730         ofb->video_mem_size = 0;
731         return 0;
732 }
733
734 static int overlayfb_check_var(struct fb_var_screeninfo *var,
735                                struct fb_info *info)
736 {
737         struct pxafb_layer *ofb = (struct pxafb_layer *)info;
738         struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
739         int xpos, ypos, pfor, bpp;
740
741         xpos = NONSTD_TO_XPOS(var->nonstd);
742         ypos = NONSTD_TO_XPOS(var->nonstd);
743         pfor = NONSTD_TO_PFOR(var->nonstd);
744
745         bpp = pxafb_var_to_bpp(var);
746         if (bpp < 0)
747                 return -EINVAL;
748
749         /* no support for YUV format on overlay1 */
750         if (ofb->id == OVERLAY1 && pfor != 0)
751                 return -EINVAL;
752
753         /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
754         switch (pfor) {
755         case OVERLAY_FORMAT_RGB:
756                 bpp = pxafb_var_to_bpp(var);
757                 if (bpp < 0)
758                         return -EINVAL;
759
760                 pxafb_set_pixfmt(var, var_to_depth(var));
761                 break;
762         case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
763         case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
764         case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
765         case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
766         default:
767                 return -EINVAL;
768         }
769
770         /* each line must start at a 32-bit word boundary */
771         if ((xpos * bpp) % 32)
772                 return -EINVAL;
773
774         /* xres must align on 32-bit word boundary */
775         var->xres = roundup(var->xres * bpp, 32) / bpp;
776
777         if ((xpos + var->xres > base_var->xres) ||
778             (ypos + var->yres > base_var->yres))
779                 return -EINVAL;
780
781         var->xres_virtual = var->xres;
782         var->yres_virtual = max(var->yres, var->yres_virtual);
783         return 0;
784 }
785
786 static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
787 {
788         struct fb_var_screeninfo *var = &ofb->fb.var;
789         int pfor = NONSTD_TO_PFOR(var->nonstd);
790         int size, bpp = 0;
791
792         switch (pfor) {
793         case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
794         case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
795         case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
796         case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
797         case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
798         }
799
800         ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
801
802         size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
803
804         /* don't re-allocate if the original video memory is enough */
805         if (ofb->video_mem) {
806                 if (ofb->video_mem_size >= size)
807                         return 0;
808
809                 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
810         }
811
812         ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
813         if (ofb->video_mem == NULL)
814                 return -ENOMEM;
815
816         ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
817         ofb->video_mem_size = size;
818
819         ofb->fb.fix.smem_start  = ofb->video_mem_phys;
820         ofb->fb.fix.smem_len    = ofb->fb.fix.line_length * var->yres_virtual;
821         ofb->fb.screen_base     = ofb->video_mem;
822         return 0;
823 }
824
825 static int overlayfb_set_par(struct fb_info *info)
826 {
827         struct pxafb_layer *ofb = (struct pxafb_layer *)info;
828         struct fb_var_screeninfo *var = &info->var;
829         int xpos, ypos, pfor, bpp, ret;
830
831         ret = overlayfb_map_video_memory(ofb);
832         if (ret)
833                 return ret;
834
835         bpp  = pxafb_var_to_bpp(var);
836         xpos = NONSTD_TO_XPOS(var->nonstd);
837         ypos = NONSTD_TO_XPOS(var->nonstd);
838         pfor = NONSTD_TO_PFOR(var->nonstd);
839
840         ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
841                           OVLxC1_BPP(bpp);
842         ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
843
844         if (ofb->id == OVERLAY2)
845                 ofb->control[1] |= OVL2C2_PFOR(pfor);
846
847         ofb->ops->setup(ofb);
848         ofb->ops->enable(ofb);
849         return 0;
850 }
851
852 static struct fb_ops overlay_fb_ops = {
853         .owner                  = THIS_MODULE,
854         .fb_open                = overlayfb_open,
855         .fb_release             = overlayfb_release,
856         .fb_check_var           = overlayfb_check_var,
857         .fb_set_par             = overlayfb_set_par,
858 };
859
860 static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
861                                          struct pxafb_layer *ofb, int id)
862 {
863         sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
864
865         ofb->fb.fix.type                = FB_TYPE_PACKED_PIXELS;
866         ofb->fb.fix.xpanstep            = 0;
867         ofb->fb.fix.ypanstep            = 1;
868
869         ofb->fb.var.activate            = FB_ACTIVATE_NOW;
870         ofb->fb.var.height              = -1;
871         ofb->fb.var.width               = -1;
872         ofb->fb.var.vmode               = FB_VMODE_NONINTERLACED;
873
874         ofb->fb.fbops                   = &overlay_fb_ops;
875         ofb->fb.flags                   = FBINFO_FLAG_DEFAULT;
876         ofb->fb.node                    = -1;
877         ofb->fb.pseudo_palette          = NULL;
878
879         ofb->id = id;
880         ofb->ops = &ofb_ops[id];
881         atomic_set(&ofb->usage, 0);
882         ofb->fbi = fbi;
883         init_completion(&ofb->branch_done);
884 }
885
886 static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
887 {
888         int i, ret;
889
890         for (i = 0; i < 2; i++) {
891                 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
892                 ret = register_framebuffer(&fbi->overlay[i].fb);
893                 if (ret) {
894                         dev_err(fbi->dev, "failed to register overlay %d\n", i);
895                         return ret;
896                 }
897         }
898
899         /* mask all IU/BS/EOF/SOF interrupts */
900         lcd_writel(fbi, LCCR5, ~0);
901
902         /* place overlay(s) on top of base */
903         fbi->lccr0 |= LCCR0_OUC;
904         pr_info("PXA Overlay driver loaded successfully!\n");
905         return 0;
906 }
907
908 static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
909 {
910         int i;
911
912         for (i = 0; i < 2; i++)
913                 unregister_framebuffer(&fbi->overlay[i].fb);
914 }
915 #else
916 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
917 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
918 #endif /* CONFIG_FB_PXA_OVERLAY */
919
920 /*
921  * Calculate the PCD value from the clock rate (in picoseconds).
922  * We take account of the PPCR clock setting.
923  * From PXA Developer's Manual:
924  *
925  *   PixelClock =      LCLK
926  *                -------------
927  *                2 ( PCD + 1 )
928  *
929  *   PCD =      LCLK
930  *         ------------- - 1
931  *         2(PixelClock)
932  *
933  * Where:
934  *   LCLK = LCD/Memory Clock
935  *   PCD = LCCR3[7:0]
936  *
937  * PixelClock here is in Hz while the pixclock argument given is the
938  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
939  *
940  * The function get_lclk_frequency_10khz returns LCLK in units of
941  * 10khz. Calling the result of this function lclk gives us the
942  * following
943  *
944  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
945  *          -------------------------------------- - 1
946  *                          2
947  *
948  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
949  */
950 static inline unsigned int get_pcd(struct pxafb_info *fbi,
951                                    unsigned int pixclock)
952 {
953         unsigned long long pcd;
954
955         /* FIXME: Need to take into account Double Pixel Clock mode
956          * (DPC) bit? or perhaps set it based on the various clock
957          * speeds */
958         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
959         pcd *= pixclock;
960         do_div(pcd, 100000000 * 2);
961         /* no need for this, since we should subtract 1 anyway. they cancel */
962         /* pcd += 1; */ /* make up for integer math truncations */
963         return (unsigned int)pcd;
964 }
965
966 /*
967  * Some touchscreens need hsync information from the video driver to
968  * function correctly. We export it here.  Note that 'hsync_time' and
969  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
970  * of the hsync period in seconds.
971  */
972 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
973 {
974         unsigned long htime;
975
976         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
977                 fbi->hsync_time = 0;
978                 return;
979         }
980
981         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
982
983         fbi->hsync_time = htime;
984 }
985
986 unsigned long pxafb_get_hsync_time(struct device *dev)
987 {
988         struct pxafb_info *fbi = dev_get_drvdata(dev);
989
990         /* If display is blanked/suspended, hsync isn't active */
991         if (!fbi || (fbi->state != C_ENABLE))
992                 return 0;
993
994         return fbi->hsync_time;
995 }
996 EXPORT_SYMBOL(pxafb_get_hsync_time);
997
998 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
999                            unsigned long start, size_t size)
1000 {
1001         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1002         unsigned int dma_desc_off, pal_desc_off;
1003
1004         if (dma < 0 || dma >= DMA_MAX * 2)
1005                 return -EINVAL;
1006
1007         dma_desc = &fbi->dma_buff->dma_desc[dma];
1008         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1009
1010         dma_desc->fsadr = start;
1011         dma_desc->fidr  = 0;
1012         dma_desc->ldcmd = size;
1013
1014         if (pal < 0 || pal >= PAL_MAX * 2) {
1015                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1016                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1017         } else {
1018                 pal_desc = &fbi->dma_buff->pal_desc[pal];
1019                 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1020
1021                 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1022                 pal_desc->fidr  = 0;
1023
1024                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1025                         pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1026                 else
1027                         pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1028
1029                 pal_desc->ldcmd |= LDCMD_PAL;
1030
1031                 /* flip back and forth between palette and frame buffer */
1032                 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1033                 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1034                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static void setup_base_frame(struct pxafb_info *fbi, int branch)
1041 {
1042         struct fb_var_screeninfo *var = &fbi->fb.var;
1043         struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1044         int nbytes, dma, pal, bpp = var->bits_per_pixel;
1045         unsigned long offset;
1046
1047         dma = DMA_BASE + (branch ? DMA_MAX : 0);
1048         pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1049
1050         nbytes = fix->line_length * var->yres;
1051         offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1052
1053         if (fbi->lccr0 & LCCR0_SDS) {
1054                 nbytes = nbytes / 2;
1055                 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1056         }
1057
1058         setup_frame_dma(fbi, dma, pal, offset, nbytes);
1059 }
1060
1061 #ifdef CONFIG_FB_PXA_SMARTPANEL
1062 static int setup_smart_dma(struct pxafb_info *fbi)
1063 {
1064         struct pxafb_dma_descriptor *dma_desc;
1065         unsigned long dma_desc_off, cmd_buff_off;
1066
1067         dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1068         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1069         cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1070
1071         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1072         dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1073         dma_desc->fidr  = 0;
1074         dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1075
1076         fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1077         return 0;
1078 }
1079
1080 int pxafb_smart_flush(struct fb_info *info)
1081 {
1082         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1083         uint32_t prsr;
1084         int ret = 0;
1085
1086         /* disable controller until all registers are set up */
1087         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1088
1089         /* 1. make it an even number of commands to align on 32-bit boundary
1090          * 2. add the interrupt command to the end of the chain so we can
1091          *    keep track of the end of the transfer
1092          */
1093
1094         while (fbi->n_smart_cmds & 1)
1095                 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1096
1097         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1098         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1099         setup_smart_dma(fbi);
1100
1101         /* continue to execute next command */
1102         prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1103         lcd_writel(fbi, PRSR, prsr);
1104
1105         /* stop the processor in case it executed "wait for sync" cmd */
1106         lcd_writel(fbi, CMDCR, 0x0001);
1107
1108         /* don't send interrupts for fifo underruns on channel 6 */
1109         lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1110
1111         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1112         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1113         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1114         lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1115         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1116         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1117
1118         /* begin sending */
1119         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1120
1121         if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1122                 pr_warning("%s: timeout waiting for command done\n",
1123                                 __func__);
1124                 ret = -ETIMEDOUT;
1125         }
1126
1127         /* quick disable */
1128         prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1129         lcd_writel(fbi, PRSR, prsr);
1130         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1131         lcd_writel(fbi, FDADR6, 0);
1132         fbi->n_smart_cmds = 0;
1133         return ret;
1134 }
1135
1136 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1137 {
1138         int i;
1139         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1140
1141         for (i = 0; i < n_cmds; i++, cmds++) {
1142                 /* if it is a software delay, flush and delay */
1143                 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1144                         pxafb_smart_flush(info);
1145                         mdelay(*cmds & 0xff);
1146                         continue;
1147                 }
1148
1149                 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1150                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1151                         pxafb_smart_flush(info);
1152
1153                 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1154         }
1155
1156         return 0;
1157 }
1158
1159 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1160 {
1161         unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1162         return (t == 0) ? 1 : t;
1163 }
1164
1165 static void setup_smart_timing(struct pxafb_info *fbi,
1166                                 struct fb_var_screeninfo *var)
1167 {
1168         struct pxafb_mach_info *inf = fbi->dev->platform_data;
1169         struct pxafb_mode_info *mode = &inf->modes[0];
1170         unsigned long lclk = clk_get_rate(fbi->clk);
1171         unsigned t1, t2, t3, t4;
1172
1173         t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1174         t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1175         t3 = mode->op_hold_time;
1176         t4 = mode->cmd_inh_time;
1177
1178         fbi->reg_lccr1 =
1179                 LCCR1_DisWdth(var->xres) |
1180                 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1181                 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1182                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1183
1184         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1185         fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1186         fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1187         fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1188
1189         /* FIXME: make this configurable */
1190         fbi->reg_cmdcr = 1;
1191 }
1192
1193 static int pxafb_smart_thread(void *arg)
1194 {
1195         struct pxafb_info *fbi = arg;
1196         struct pxafb_mach_info *inf = fbi->dev->platform_data;
1197
1198         if (!fbi || !inf->smart_update) {
1199                 pr_err("%s: not properly initialized, thread terminated\n",
1200                                 __func__);
1201                 return -EINVAL;
1202         }
1203
1204         pr_debug("%s(): task starting\n", __func__);
1205
1206         set_freezable();
1207         while (!kthread_should_stop()) {
1208
1209                 if (try_to_freeze())
1210                         continue;
1211
1212                 mutex_lock(&fbi->ctrlr_lock);
1213
1214                 if (fbi->state == C_ENABLE) {
1215                         inf->smart_update(&fbi->fb);
1216                         complete(&fbi->refresh_done);
1217                 }
1218
1219                 mutex_unlock(&fbi->ctrlr_lock);
1220
1221                 set_current_state(TASK_INTERRUPTIBLE);
1222                 schedule_timeout(30 * HZ / 1000);
1223         }
1224
1225         pr_debug("%s(): task ending\n", __func__);
1226         return 0;
1227 }
1228
1229 static int pxafb_smart_init(struct pxafb_info *fbi)
1230 {
1231         if (!(fbi->lccr0 & LCCR0_LCDT))
1232                 return 0;
1233
1234         fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1235         fbi->n_smart_cmds = 0;
1236
1237         init_completion(&fbi->command_done);
1238         init_completion(&fbi->refresh_done);
1239
1240         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1241                                         "lcd_refresh");
1242         if (IS_ERR(fbi->smart_thread)) {
1243                 pr_err("%s: unable to create kernel thread\n", __func__);
1244                 return PTR_ERR(fbi->smart_thread);
1245         }
1246
1247         return 0;
1248 }
1249 #else
1250 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1251 {
1252         return 0;
1253 }
1254
1255 int pxafb_smart_flush(struct fb_info *info)
1256 {
1257         return 0;
1258 }
1259
1260 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1261 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1262
1263 static void setup_parallel_timing(struct pxafb_info *fbi,
1264                                   struct fb_var_screeninfo *var)
1265 {
1266         unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1267
1268         fbi->reg_lccr1 =
1269                 LCCR1_DisWdth(var->xres) +
1270                 LCCR1_HorSnchWdth(var->hsync_len) +
1271                 LCCR1_BegLnDel(var->left_margin) +
1272                 LCCR1_EndLnDel(var->right_margin);
1273
1274         /*
1275          * If we have a dual scan LCD, we need to halve
1276          * the YRES parameter.
1277          */
1278         lines_per_panel = var->yres;
1279         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1280                 lines_per_panel /= 2;
1281
1282         fbi->reg_lccr2 =
1283                 LCCR2_DisHght(lines_per_panel) +
1284                 LCCR2_VrtSnchWdth(var->vsync_len) +
1285                 LCCR2_BegFrmDel(var->upper_margin) +
1286                 LCCR2_EndFrmDel(var->lower_margin);
1287
1288         fbi->reg_lccr3 = fbi->lccr3 |
1289                 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1290                  LCCR3_HorSnchH : LCCR3_HorSnchL) |
1291                 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1292                  LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1293
1294         if (pcd) {
1295                 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1296                 set_hsync_time(fbi, pcd);
1297         }
1298 }
1299
1300 /*
1301  * pxafb_activate_var():
1302  *      Configures LCD Controller based on entries in var parameter.
1303  *      Settings are only written to the controller if changes were made.
1304  */
1305 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1306                               struct pxafb_info *fbi)
1307 {
1308         u_long flags;
1309
1310         /* Update shadow copy atomically */
1311         local_irq_save(flags);
1312
1313 #ifdef CONFIG_FB_PXA_SMARTPANEL
1314         if (fbi->lccr0 & LCCR0_LCDT)
1315                 setup_smart_timing(fbi, var);
1316         else
1317 #endif
1318                 setup_parallel_timing(fbi, var);
1319
1320         setup_base_frame(fbi, 0);
1321
1322         fbi->reg_lccr0 = fbi->lccr0 |
1323                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1324                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
1325
1326         fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1327
1328         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1329         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1330         local_irq_restore(flags);
1331
1332         /*
1333          * Only update the registers if the controller is enabled
1334          * and something has changed.
1335          */
1336         if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1337             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1338             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1339             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1340             (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1341             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1342             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1343                 pxafb_schedule_work(fbi, C_REENABLE);
1344
1345         return 0;
1346 }
1347
1348 /*
1349  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
1350  * Do not call them directly; set_ctrlr_state does the correct serialisation
1351  * to ensure that things happen in the right way 100% of time time.
1352  *      -- rmk
1353  */
1354 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1355 {
1356         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1357
1358         if (fbi->backlight_power)
1359                 fbi->backlight_power(on);
1360 }
1361
1362 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1363 {
1364         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1365
1366         if (fbi->lcd_power)
1367                 fbi->lcd_power(on, &fbi->fb.var);
1368 }
1369
1370 static void pxafb_enable_controller(struct pxafb_info *fbi)
1371 {
1372         pr_debug("pxafb: Enabling LCD controller\n");
1373         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1374         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1375         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1376         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1377         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1378         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1379
1380         /* enable LCD controller clock */
1381         clk_enable(fbi->clk);
1382
1383         if (fbi->lccr0 & LCCR0_LCDT)
1384                 return;
1385
1386         /* Sequence from 11.7.10 */
1387         lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1388         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1389         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1390         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1391         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1392
1393         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1394         lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1395         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1396 }
1397
1398 static void pxafb_disable_controller(struct pxafb_info *fbi)
1399 {
1400         uint32_t lccr0;
1401
1402 #ifdef CONFIG_FB_PXA_SMARTPANEL
1403         if (fbi->lccr0 & LCCR0_LCDT) {
1404                 wait_for_completion_timeout(&fbi->refresh_done,
1405                                 200 * HZ / 1000);
1406                 return;
1407         }
1408 #endif
1409
1410         /* Clear LCD Status Register */
1411         lcd_writel(fbi, LCSR, 0xffffffff);
1412
1413         lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1414         lcd_writel(fbi, LCCR0, lccr0);
1415         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1416
1417         wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1418
1419         /* disable LCD controller clock */
1420         clk_disable(fbi->clk);
1421 }
1422
1423 /*
1424  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1425  */
1426 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1427 {
1428         struct pxafb_info *fbi = dev_id;
1429         unsigned int lccr0, lcsr, lcsr1;
1430
1431         lcsr = lcd_readl(fbi, LCSR);
1432         if (lcsr & LCSR_LDD) {
1433                 lccr0 = lcd_readl(fbi, LCCR0);
1434                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1435                 complete(&fbi->disable_done);
1436         }
1437
1438 #ifdef CONFIG_FB_PXA_SMARTPANEL
1439         if (lcsr & LCSR_CMD_INT)
1440                 complete(&fbi->command_done);
1441 #endif
1442         lcd_writel(fbi, LCSR, lcsr);
1443
1444 #ifdef CONFIG_FB_PXA_OVERLAY
1445         lcsr1 = lcd_readl(fbi, LCSR1);
1446         if (lcsr1 & LCSR1_BS(1))
1447                 complete(&fbi->overlay[0].branch_done);
1448
1449         if (lcsr1 & LCSR1_BS(2))
1450                 complete(&fbi->overlay[1].branch_done);
1451
1452         lcd_writel(fbi, LCSR1, lcsr1);
1453 #endif
1454         return IRQ_HANDLED;
1455 }
1456
1457 /*
1458  * This function must be called from task context only, since it will
1459  * sleep when disabling the LCD controller, or if we get two contending
1460  * processes trying to alter state.
1461  */
1462 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1463 {
1464         u_int old_state;
1465
1466         mutex_lock(&fbi->ctrlr_lock);
1467
1468         old_state = fbi->state;
1469
1470         /*
1471          * Hack around fbcon initialisation.
1472          */
1473         if (old_state == C_STARTUP && state == C_REENABLE)
1474                 state = C_ENABLE;
1475
1476         switch (state) {
1477         case C_DISABLE_CLKCHANGE:
1478                 /*
1479                  * Disable controller for clock change.  If the
1480                  * controller is already disabled, then do nothing.
1481                  */
1482                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1483                         fbi->state = state;
1484                         /* TODO __pxafb_lcd_power(fbi, 0); */
1485                         pxafb_disable_controller(fbi);
1486                 }
1487                 break;
1488
1489         case C_DISABLE_PM:
1490         case C_DISABLE:
1491                 /*
1492                  * Disable controller
1493                  */
1494                 if (old_state != C_DISABLE) {
1495                         fbi->state = state;
1496                         __pxafb_backlight_power(fbi, 0);
1497                         __pxafb_lcd_power(fbi, 0);
1498                         if (old_state != C_DISABLE_CLKCHANGE)
1499                                 pxafb_disable_controller(fbi);
1500                 }
1501                 break;
1502
1503         case C_ENABLE_CLKCHANGE:
1504                 /*
1505                  * Enable the controller after clock change.  Only
1506                  * do this if we were disabled for the clock change.
1507                  */
1508                 if (old_state == C_DISABLE_CLKCHANGE) {
1509                         fbi->state = C_ENABLE;
1510                         pxafb_enable_controller(fbi);
1511                         /* TODO __pxafb_lcd_power(fbi, 1); */
1512                 }
1513                 break;
1514
1515         case C_REENABLE:
1516                 /*
1517                  * Re-enable the controller only if it was already
1518                  * enabled.  This is so we reprogram the control
1519                  * registers.
1520                  */
1521                 if (old_state == C_ENABLE) {
1522                         __pxafb_lcd_power(fbi, 0);
1523                         pxafb_disable_controller(fbi);
1524                         pxafb_enable_controller(fbi);
1525                         __pxafb_lcd_power(fbi, 1);
1526                 }
1527                 break;
1528
1529         case C_ENABLE_PM:
1530                 /*
1531                  * Re-enable the controller after PM.  This is not
1532                  * perfect - think about the case where we were doing
1533                  * a clock change, and we suspended half-way through.
1534                  */
1535                 if (old_state != C_DISABLE_PM)
1536                         break;
1537                 /* fall through */
1538
1539         case C_ENABLE:
1540                 /*
1541                  * Power up the LCD screen, enable controller, and
1542                  * turn on the backlight.
1543                  */
1544                 if (old_state != C_ENABLE) {
1545                         fbi->state = C_ENABLE;
1546                         pxafb_enable_controller(fbi);
1547                         __pxafb_lcd_power(fbi, 1);
1548                         __pxafb_backlight_power(fbi, 1);
1549                 }
1550                 break;
1551         }
1552         mutex_unlock(&fbi->ctrlr_lock);
1553 }
1554
1555 /*
1556  * Our LCD controller task (which is called when we blank or unblank)
1557  * via keventd.
1558  */
1559 static void pxafb_task(struct work_struct *work)
1560 {
1561         struct pxafb_info *fbi =
1562                 container_of(work, struct pxafb_info, task);
1563         u_int state = xchg(&fbi->task_state, -1);
1564
1565         set_ctrlr_state(fbi, state);
1566 }
1567
1568 #ifdef CONFIG_CPU_FREQ
1569 /*
1570  * CPU clock speed change handler.  We need to adjust the LCD timing
1571  * parameters when the CPU clock is adjusted by the power management
1572  * subsystem.
1573  *
1574  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1575  */
1576 static int
1577 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1578 {
1579         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1580         /* TODO struct cpufreq_freqs *f = data; */
1581         u_int pcd;
1582
1583         switch (val) {
1584         case CPUFREQ_PRECHANGE:
1585                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1586                 break;
1587
1588         case CPUFREQ_POSTCHANGE:
1589                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1590                 set_hsync_time(fbi, pcd);
1591                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1592                                   LCCR3_PixClkDiv(pcd);
1593                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1594                 break;
1595         }
1596         return 0;
1597 }
1598
1599 static int
1600 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1601 {
1602         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1603         struct fb_var_screeninfo *var = &fbi->fb.var;
1604         struct cpufreq_policy *policy = data;
1605
1606         switch (val) {
1607         case CPUFREQ_ADJUST:
1608         case CPUFREQ_INCOMPATIBLE:
1609                 pr_debug("min dma period: %d ps, "
1610                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1611                         policy->max);
1612                 /* TODO: fill in min/max values */
1613                 break;
1614         }
1615         return 0;
1616 }
1617 #endif
1618
1619 #ifdef CONFIG_PM
1620 /*
1621  * Power management hooks.  Note that we won't be called from IRQ context,
1622  * unlike the blank functions above, so we may sleep.
1623  */
1624 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1625 {
1626         struct pxafb_info *fbi = platform_get_drvdata(dev);
1627
1628         set_ctrlr_state(fbi, C_DISABLE_PM);
1629         return 0;
1630 }
1631
1632 static int pxafb_resume(struct platform_device *dev)
1633 {
1634         struct pxafb_info *fbi = platform_get_drvdata(dev);
1635
1636         set_ctrlr_state(fbi, C_ENABLE_PM);
1637         return 0;
1638 }
1639 #else
1640 #define pxafb_suspend   NULL
1641 #define pxafb_resume    NULL
1642 #endif
1643
1644 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1645 {
1646         int size = PAGE_ALIGN(fbi->video_mem_size);
1647
1648         fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1649         if (fbi->video_mem == NULL)
1650                 return -ENOMEM;
1651
1652         fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1653         fbi->video_mem_size = size;
1654
1655         fbi->fb.fix.smem_start  = fbi->video_mem_phys;
1656         fbi->fb.fix.smem_len    = fbi->video_mem_size;
1657         fbi->fb.screen_base     = fbi->video_mem;
1658
1659         return fbi->video_mem ? 0 : -ENOMEM;
1660 }
1661
1662 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1663                                    struct pxafb_mach_info *inf)
1664 {
1665         unsigned int lcd_conn = inf->lcd_conn;
1666         struct pxafb_mode_info *m;
1667         int i;
1668
1669         fbi->cmap_inverse       = inf->cmap_inverse;
1670         fbi->cmap_static        = inf->cmap_static;
1671         fbi->lccr4              = inf->lccr4;
1672
1673         switch (lcd_conn & LCD_TYPE_MASK) {
1674         case LCD_TYPE_MONO_STN:
1675                 fbi->lccr0 = LCCR0_CMS;
1676                 break;
1677         case LCD_TYPE_MONO_DSTN:
1678                 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1679                 break;
1680         case LCD_TYPE_COLOR_STN:
1681                 fbi->lccr0 = 0;
1682                 break;
1683         case LCD_TYPE_COLOR_DSTN:
1684                 fbi->lccr0 = LCCR0_SDS;
1685                 break;
1686         case LCD_TYPE_COLOR_TFT:
1687                 fbi->lccr0 = LCCR0_PAS;
1688                 break;
1689         case LCD_TYPE_SMART_PANEL:
1690                 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1691                 break;
1692         default:
1693                 /* fall back to backward compatibility way */
1694                 fbi->lccr0 = inf->lccr0;
1695                 fbi->lccr3 = inf->lccr3;
1696                 goto decode_mode;
1697         }
1698
1699         if (lcd_conn == LCD_MONO_STN_8BPP)
1700                 fbi->lccr0 |= LCCR0_DPD;
1701
1702         fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1703
1704         fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1705         fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1706         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1707
1708 decode_mode:
1709         pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1710
1711         /* decide video memory size as follows:
1712          * 1. default to mode of maximum resolution
1713          * 2. allow platform to override
1714          * 3. allow module parameter to override
1715          */
1716         for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1717                 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1718                                 m->xres * m->yres * m->bpp / 8);
1719
1720         if (inf->video_mem_size > fbi->video_mem_size)
1721                 fbi->video_mem_size = inf->video_mem_size;
1722
1723         if (video_mem_size > fbi->video_mem_size)
1724                 fbi->video_mem_size = video_mem_size;
1725 }
1726
1727 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1728 {
1729         struct pxafb_info *fbi;
1730         void *addr;
1731         struct pxafb_mach_info *inf = dev->platform_data;
1732
1733         /* Alloc the pxafb_info and pseudo_palette in one step */
1734         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1735         if (!fbi)
1736                 return NULL;
1737
1738         memset(fbi, 0, sizeof(struct pxafb_info));
1739         fbi->dev = dev;
1740
1741         fbi->clk = clk_get(dev, NULL);
1742         if (IS_ERR(fbi->clk)) {
1743                 kfree(fbi);
1744                 return NULL;
1745         }
1746
1747         strcpy(fbi->fb.fix.id, PXA_NAME);
1748
1749         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1750         fbi->fb.fix.type_aux    = 0;
1751         fbi->fb.fix.xpanstep    = 0;
1752         fbi->fb.fix.ypanstep    = 1;
1753         fbi->fb.fix.ywrapstep   = 0;
1754         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1755
1756         fbi->fb.var.nonstd      = 0;
1757         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1758         fbi->fb.var.height      = -1;
1759         fbi->fb.var.width       = -1;
1760         fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1761         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1762
1763         fbi->fb.fbops           = &pxafb_ops;
1764         fbi->fb.flags           = FBINFO_DEFAULT;
1765         fbi->fb.node            = -1;
1766
1767         addr = fbi;
1768         addr = addr + sizeof(struct pxafb_info);
1769         fbi->fb.pseudo_palette  = addr;
1770
1771         fbi->state              = C_STARTUP;
1772         fbi->task_state         = (u_char)-1;
1773
1774         pxafb_decode_mach_info(fbi, inf);
1775
1776         init_waitqueue_head(&fbi->ctrlr_wait);
1777         INIT_WORK(&fbi->task, pxafb_task);
1778         mutex_init(&fbi->ctrlr_lock);
1779         init_completion(&fbi->disable_done);
1780
1781         return fbi;
1782 }
1783
1784 #ifdef CONFIG_FB_PXA_PARAMETERS
1785 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1786 {
1787         struct pxafb_mach_info *inf = dev->platform_data;
1788
1789         const char *name = this_opt+5;
1790         unsigned int namelen = strlen(name);
1791         int res_specified = 0, bpp_specified = 0;
1792         unsigned int xres = 0, yres = 0, bpp = 0;
1793         int yres_specified = 0;
1794         int i;
1795         for (i = namelen-1; i >= 0; i--) {
1796                 switch (name[i]) {
1797                 case '-':
1798                         namelen = i;
1799                         if (!bpp_specified && !yres_specified) {
1800                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1801                                 bpp_specified = 1;
1802                         } else
1803                                 goto done;
1804                         break;
1805                 case 'x':
1806                         if (!yres_specified) {
1807                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1808                                 yres_specified = 1;
1809                         } else
1810                                 goto done;
1811                         break;
1812                 case '0' ... '9':
1813                         break;
1814                 default:
1815                         goto done;
1816                 }
1817         }
1818         if (i < 0 && yres_specified) {
1819                 xres = simple_strtoul(name, NULL, 0);
1820                 res_specified = 1;
1821         }
1822 done:
1823         if (res_specified) {
1824                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1825                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1826         }
1827         if (bpp_specified)
1828                 switch (bpp) {
1829                 case 1:
1830                 case 2:
1831                 case 4:
1832                 case 8:
1833                 case 16:
1834                         inf->modes[0].bpp = bpp;
1835                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1836                         break;
1837                 default:
1838                         dev_err(dev, "Depth %d is not valid\n", bpp);
1839                         return -EINVAL;
1840                 }
1841         return 0;
1842 }
1843
1844 static int __devinit parse_opt(struct device *dev, char *this_opt)
1845 {
1846         struct pxafb_mach_info *inf = dev->platform_data;
1847         struct pxafb_mode_info *mode = &inf->modes[0];
1848         char s[64];
1849
1850         s[0] = '\0';
1851
1852         if (!strncmp(this_opt, "vmem:", 5)) {
1853                 video_mem_size = memparse(this_opt + 5, NULL);
1854         } else if (!strncmp(this_opt, "mode:", 5)) {
1855                 return parse_opt_mode(dev, this_opt);
1856         } else if (!strncmp(this_opt, "pixclock:", 9)) {
1857                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1858                 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1859         } else if (!strncmp(this_opt, "left:", 5)) {
1860                 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1861                 sprintf(s, "left: %u\n", mode->left_margin);
1862         } else if (!strncmp(this_opt, "right:", 6)) {
1863                 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1864                 sprintf(s, "right: %u\n", mode->right_margin);
1865         } else if (!strncmp(this_opt, "upper:", 6)) {
1866                 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1867                 sprintf(s, "upper: %u\n", mode->upper_margin);
1868         } else if (!strncmp(this_opt, "lower:", 6)) {
1869                 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1870                 sprintf(s, "lower: %u\n", mode->lower_margin);
1871         } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1872                 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1873                 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1874         } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1875                 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1876                 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1877         } else if (!strncmp(this_opt, "hsync:", 6)) {
1878                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1879                         sprintf(s, "hsync: Active Low\n");
1880                         mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1881                 } else {
1882                         sprintf(s, "hsync: Active High\n");
1883                         mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1884                 }
1885         } else if (!strncmp(this_opt, "vsync:", 6)) {
1886                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1887                         sprintf(s, "vsync: Active Low\n");
1888                         mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1889                 } else {
1890                         sprintf(s, "vsync: Active High\n");
1891                         mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1892                 }
1893         } else if (!strncmp(this_opt, "dpc:", 4)) {
1894                 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1895                         sprintf(s, "double pixel clock: false\n");
1896                         inf->lccr3 &= ~LCCR3_DPC;
1897                 } else {
1898                         sprintf(s, "double pixel clock: true\n");
1899                         inf->lccr3 |= LCCR3_DPC;
1900                 }
1901         } else if (!strncmp(this_opt, "outputen:", 9)) {
1902                 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1903                         sprintf(s, "output enable: active low\n");
1904                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1905                 } else {
1906                         sprintf(s, "output enable: active high\n");
1907                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1908                 }
1909         } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1910                 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1911                         sprintf(s, "pixel clock polarity: falling edge\n");
1912                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1913                 } else {
1914                         sprintf(s, "pixel clock polarity: rising edge\n");
1915                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1916                 }
1917         } else if (!strncmp(this_opt, "color", 5)) {
1918                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1919         } else if (!strncmp(this_opt, "mono", 4)) {
1920                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1921         } else if (!strncmp(this_opt, "active", 6)) {
1922                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1923         } else if (!strncmp(this_opt, "passive", 7)) {
1924                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1925         } else if (!strncmp(this_opt, "single", 6)) {
1926                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1927         } else if (!strncmp(this_opt, "dual", 4)) {
1928                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1929         } else if (!strncmp(this_opt, "4pix", 4)) {
1930                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1931         } else if (!strncmp(this_opt, "8pix", 4)) {
1932                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1933         } else {
1934                 dev_err(dev, "unknown option: %s\n", this_opt);
1935                 return -EINVAL;
1936         }
1937
1938         if (s[0] != '\0')
1939                 dev_info(dev, "override %s", s);
1940
1941         return 0;
1942 }
1943
1944 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1945 {
1946         char *this_opt;
1947         int ret;
1948
1949         if (!options || !*options)
1950                 return 0;
1951
1952         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1953
1954         /* could be made table driven or similar?... */
1955         while ((this_opt = strsep(&options, ",")) != NULL) {
1956                 ret = parse_opt(dev, this_opt);
1957                 if (ret)
1958                         return ret;
1959         }
1960         return 0;
1961 }
1962
1963 static char g_options[256] __devinitdata = "";
1964
1965 #ifndef MODULE
1966 static int __init pxafb_setup_options(void)
1967 {
1968         char *options = NULL;
1969
1970         if (fb_get_options("pxafb", &options))
1971                 return -ENODEV;
1972
1973         if (options)
1974                 strlcpy(g_options, options, sizeof(g_options));
1975
1976         return 0;
1977 }
1978 #else
1979 #define pxafb_setup_options()           (0)
1980
1981 module_param_string(options, g_options, sizeof(g_options), 0);
1982 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1983 #endif
1984
1985 #else
1986 #define pxafb_parse_options(...)        (0)
1987 #define pxafb_setup_options()           (0)
1988 #endif
1989
1990 #ifdef DEBUG_VAR
1991 /* Check for various illegal bit-combinations. Currently only
1992  * a warning is given. */
1993 static void __devinit pxafb_check_options(struct device *dev,
1994                                           struct pxafb_mach_info *inf)
1995 {
1996         if (inf->lcd_conn)
1997                 return;
1998
1999         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2000                 dev_warn(dev, "machine LCCR0 setting contains "
2001                                 "illegal bits: %08x\n",
2002                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2003         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2004                 dev_warn(dev, "machine LCCR3 setting contains "
2005                                 "illegal bits: %08x\n",
2006                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2007         if (inf->lccr0 & LCCR0_DPD &&
2008             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2009              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2010              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2011                 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2012                                 "only valid in passive mono"
2013                                 " single panel mode\n");
2014         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2015             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2016                 dev_warn(dev, "Dual panel only valid in passive mode\n");
2017         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2018              (inf->modes->upper_margin || inf->modes->lower_margin))
2019                 dev_warn(dev, "Upper and lower margins must be 0 in "
2020                                 "passive mode\n");
2021 }
2022 #else
2023 #define pxafb_check_options(...)        do {} while (0)
2024 #endif
2025
2026 static int __devinit pxafb_probe(struct platform_device *dev)
2027 {
2028         struct pxafb_info *fbi;
2029         struct pxafb_mach_info *inf;
2030         struct resource *r;
2031         int irq, ret;
2032
2033         dev_dbg(&dev->dev, "pxafb_probe\n");
2034
2035         inf = dev->dev.platform_data;
2036         ret = -ENOMEM;
2037         fbi = NULL;
2038         if (!inf)
2039                 goto failed;
2040
2041         ret = pxafb_parse_options(&dev->dev, g_options);
2042         if (ret < 0)
2043                 goto failed;
2044
2045         pxafb_check_options(&dev->dev, inf);
2046
2047         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2048                         inf->modes->xres,
2049                         inf->modes->yres,
2050                         inf->modes->bpp);
2051         if (inf->modes->xres == 0 ||
2052             inf->modes->yres == 0 ||
2053             inf->modes->bpp == 0) {
2054                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2055                 ret = -EINVAL;
2056                 goto failed;
2057         }
2058
2059         fbi = pxafb_init_fbinfo(&dev->dev);
2060         if (!fbi) {
2061                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
2062                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2063                 ret = -ENOMEM;
2064                 goto failed;
2065         }
2066
2067         fbi->backlight_power = inf->pxafb_backlight_power;
2068         fbi->lcd_power = inf->pxafb_lcd_power;
2069
2070         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2071         if (r == NULL) {
2072                 dev_err(&dev->dev, "no I/O memory resource defined\n");
2073                 ret = -ENODEV;
2074                 goto failed_fbi;
2075         }
2076
2077         r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
2078         if (r == NULL) {
2079                 dev_err(&dev->dev, "failed to request I/O memory\n");
2080                 ret = -EBUSY;
2081                 goto failed_fbi;
2082         }
2083
2084         fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
2085         if (fbi->mmio_base == NULL) {
2086                 dev_err(&dev->dev, "failed to map I/O memory\n");
2087                 ret = -EBUSY;
2088                 goto failed_free_res;
2089         }
2090
2091         fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2092         fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2093                                 &fbi->dma_buff_phys, GFP_KERNEL);
2094         if (fbi->dma_buff == NULL) {
2095                 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2096                 ret = -ENOMEM;
2097                 goto failed_free_io;
2098         }
2099
2100         ret = pxafb_init_video_memory(fbi);
2101         if (ret) {
2102                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2103                 ret = -ENOMEM;
2104                 goto failed_free_dma;
2105         }
2106
2107         irq = platform_get_irq(dev, 0);
2108         if (irq < 0) {
2109                 dev_err(&dev->dev, "no IRQ defined\n");
2110                 ret = -ENODEV;
2111                 goto failed_free_mem;
2112         }
2113
2114         ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
2115         if (ret) {
2116                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2117                 ret = -EBUSY;
2118                 goto failed_free_mem;
2119         }
2120
2121         ret = pxafb_smart_init(fbi);
2122         if (ret) {
2123                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2124                 goto failed_free_irq;
2125         }
2126
2127         /*
2128          * This makes sure that our colour bitfield
2129          * descriptors are correctly initialised.
2130          */
2131         ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2132         if (ret) {
2133                 dev_err(&dev->dev, "failed to get suitable mode\n");
2134                 goto failed_free_irq;
2135         }
2136
2137         ret = pxafb_set_par(&fbi->fb);
2138         if (ret) {
2139                 dev_err(&dev->dev, "Failed to set parameters\n");
2140                 goto failed_free_irq;
2141         }
2142
2143         platform_set_drvdata(dev, fbi);
2144
2145         ret = register_framebuffer(&fbi->fb);
2146         if (ret < 0) {
2147                 dev_err(&dev->dev,
2148                         "Failed to register framebuffer device: %d\n", ret);
2149                 goto failed_free_cmap;
2150         }
2151
2152         pxafb_overlay_init(fbi);
2153
2154 #ifdef CONFIG_CPU_FREQ
2155         fbi->freq_transition.notifier_call = pxafb_freq_transition;
2156         fbi->freq_policy.notifier_call = pxafb_freq_policy;
2157         cpufreq_register_notifier(&fbi->freq_transition,
2158                                 CPUFREQ_TRANSITION_NOTIFIER);
2159         cpufreq_register_notifier(&fbi->freq_policy,
2160                                 CPUFREQ_POLICY_NOTIFIER);
2161 #endif
2162
2163         /*
2164          * Ok, now enable the LCD controller
2165          */
2166         set_ctrlr_state(fbi, C_ENABLE);
2167
2168         return 0;
2169
2170 failed_free_cmap:
2171         if (fbi->fb.cmap.len)
2172                 fb_dealloc_cmap(&fbi->fb.cmap);
2173 failed_free_irq:
2174         free_irq(irq, fbi);
2175 failed_free_mem:
2176         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2177 failed_free_dma:
2178         dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2179                         fbi->dma_buff, fbi->dma_buff_phys);
2180 failed_free_io:
2181         iounmap(fbi->mmio_base);
2182 failed_free_res:
2183         release_mem_region(r->start, r->end - r->start + 1);
2184 failed_fbi:
2185         clk_put(fbi->clk);
2186         platform_set_drvdata(dev, NULL);
2187         kfree(fbi);
2188 failed:
2189         return ret;
2190 }
2191
2192 static int __devexit pxafb_remove(struct platform_device *dev)
2193 {
2194         struct pxafb_info *fbi = platform_get_drvdata(dev);
2195         struct resource *r;
2196         int irq;
2197         struct fb_info *info;
2198
2199         if (!fbi)
2200                 return 0;
2201
2202         info = &fbi->fb;
2203
2204         pxafb_overlay_exit(fbi);
2205         unregister_framebuffer(info);
2206
2207         pxafb_disable_controller(fbi);
2208
2209         if (fbi->fb.cmap.len)
2210                 fb_dealloc_cmap(&fbi->fb.cmap);
2211
2212         irq = platform_get_irq(dev, 0);
2213         free_irq(irq, fbi);
2214
2215         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2216
2217         dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2218                         fbi->dma_buff, fbi->dma_buff_phys);
2219
2220         iounmap(fbi->mmio_base);
2221
2222         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2223         release_mem_region(r->start, r->end - r->start + 1);
2224
2225         clk_put(fbi->clk);
2226         kfree(fbi);
2227
2228         return 0;
2229 }
2230
2231 static struct platform_driver pxafb_driver = {
2232         .probe          = pxafb_probe,
2233         .remove         = pxafb_remove,
2234         .suspend        = pxafb_suspend,
2235         .resume         = pxafb_resume,
2236         .driver         = {
2237                 .owner  = THIS_MODULE,
2238                 .name   = "pxa2xx-fb",
2239         },
2240 };
2241
2242 static int __init pxafb_init(void)
2243 {
2244         if (pxafb_setup_options())
2245                 return -EINVAL;
2246
2247         return platform_driver_register(&pxafb_driver);
2248 }
2249
2250 static void __exit pxafb_exit(void)
2251 {
2252         platform_driver_unregister(&pxafb_driver);
2253 }
2254
2255 module_init(pxafb_init);
2256 module_exit(pxafb_exit);
2257
2258 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2259 MODULE_LICENSE("GPL");