const: mark struct vm_struct_operations
[linux-2.6.git] / drivers / video / omap / dispc.c
1 /*
2  * OMAP2 display controller support
3  *
4  * Copyright (C) 2005 Nokia Corporation
5  * Author: Imre Deak <imre.deak@nokia.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
20  */
21 #include <linux/kernel.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mm.h>
24 #include <linux/vmalloc.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27
28 #include <mach/sram.h>
29 #include <mach/omapfb.h>
30 #include <mach/board.h>
31
32 #include "dispc.h"
33
34 #define MODULE_NAME                     "dispc"
35
36 #define DSS_BASE                        0x48050000
37 #define DSS_SYSCONFIG                   0x0010
38
39 #define DISPC_BASE                      0x48050400
40
41 /* DISPC common */
42 #define DISPC_REVISION                  0x0000
43 #define DISPC_SYSCONFIG                 0x0010
44 #define DISPC_SYSSTATUS                 0x0014
45 #define DISPC_IRQSTATUS                 0x0018
46 #define DISPC_IRQENABLE                 0x001C
47 #define DISPC_CONTROL                   0x0040
48 #define DISPC_CONFIG                    0x0044
49 #define DISPC_CAPABLE                   0x0048
50 #define DISPC_DEFAULT_COLOR0            0x004C
51 #define DISPC_DEFAULT_COLOR1            0x0050
52 #define DISPC_TRANS_COLOR0              0x0054
53 #define DISPC_TRANS_COLOR1              0x0058
54 #define DISPC_LINE_STATUS               0x005C
55 #define DISPC_LINE_NUMBER               0x0060
56 #define DISPC_TIMING_H                  0x0064
57 #define DISPC_TIMING_V                  0x0068
58 #define DISPC_POL_FREQ                  0x006C
59 #define DISPC_DIVISOR                   0x0070
60 #define DISPC_SIZE_DIG                  0x0078
61 #define DISPC_SIZE_LCD                  0x007C
62
63 #define DISPC_DATA_CYCLE1               0x01D4
64 #define DISPC_DATA_CYCLE2               0x01D8
65 #define DISPC_DATA_CYCLE3               0x01DC
66
67 /* DISPC GFX plane */
68 #define DISPC_GFX_BA0                   0x0080
69 #define DISPC_GFX_BA1                   0x0084
70 #define DISPC_GFX_POSITION              0x0088
71 #define DISPC_GFX_SIZE                  0x008C
72 #define DISPC_GFX_ATTRIBUTES            0x00A0
73 #define DISPC_GFX_FIFO_THRESHOLD        0x00A4
74 #define DISPC_GFX_FIFO_SIZE_STATUS      0x00A8
75 #define DISPC_GFX_ROW_INC               0x00AC
76 #define DISPC_GFX_PIXEL_INC             0x00B0
77 #define DISPC_GFX_WINDOW_SKIP           0x00B4
78 #define DISPC_GFX_TABLE_BA              0x00B8
79
80 /* DISPC Video plane 1/2 */
81 #define DISPC_VID1_BASE                 0x00BC
82 #define DISPC_VID2_BASE                 0x014C
83
84 /* Offsets into DISPC_VID1/2_BASE */
85 #define DISPC_VID_BA0                   0x0000
86 #define DISPC_VID_BA1                   0x0004
87 #define DISPC_VID_POSITION              0x0008
88 #define DISPC_VID_SIZE                  0x000C
89 #define DISPC_VID_ATTRIBUTES            0x0010
90 #define DISPC_VID_FIFO_THRESHOLD        0x0014
91 #define DISPC_VID_FIFO_SIZE_STATUS      0x0018
92 #define DISPC_VID_ROW_INC               0x001C
93 #define DISPC_VID_PIXEL_INC             0x0020
94 #define DISPC_VID_FIR                   0x0024
95 #define DISPC_VID_PICTURE_SIZE          0x0028
96 #define DISPC_VID_ACCU0                 0x002C
97 #define DISPC_VID_ACCU1                 0x0030
98
99 /* 8 elements in 8 byte increments */
100 #define DISPC_VID_FIR_COEF_H0           0x0034
101 /* 8 elements in 8 byte increments */
102 #define DISPC_VID_FIR_COEF_HV0          0x0038
103 /* 5 elements in 4 byte increments */
104 #define DISPC_VID_CONV_COEF0            0x0074
105
106 #define DISPC_IRQ_FRAMEMASK             0x0001
107 #define DISPC_IRQ_VSYNC                 0x0002
108 #define DISPC_IRQ_EVSYNC_EVEN           0x0004
109 #define DISPC_IRQ_EVSYNC_ODD            0x0008
110 #define DISPC_IRQ_ACBIAS_COUNT_STAT     0x0010
111 #define DISPC_IRQ_PROG_LINE_NUM         0x0020
112 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    0x0040
113 #define DISPC_IRQ_GFX_END_WIN           0x0080
114 #define DISPC_IRQ_PAL_GAMMA_MASK        0x0100
115 #define DISPC_IRQ_OCP_ERR               0x0200
116 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   0x0400
117 #define DISPC_IRQ_VID1_END_WIN          0x0800
118 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   0x1000
119 #define DISPC_IRQ_VID2_END_WIN          0x2000
120 #define DISPC_IRQ_SYNC_LOST             0x4000
121
122 #define DISPC_IRQ_MASK_ALL              0x7fff
123
124 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
125                                              DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
126                                              DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
127                                              DISPC_IRQ_SYNC_LOST)
128
129 #define RFBI_CONTROL                    0x48050040
130
131 #define MAX_PALETTE_SIZE                (256 * 16)
132
133 #define FLD_MASK(pos, len)      (((1 << len) - 1) << pos)
134
135 #define MOD_REG_FLD(reg, mask, val) \
136         dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val));
137
138 #define OMAP2_SRAM_START                0x40200000
139 /* Maximum size, in reality this is smaller if SRAM is partially locked. */
140 #define OMAP2_SRAM_SIZE                 0xa0000         /* 640k */
141
142 /* We support the SDRAM / SRAM types. See OMAPFB_PLANE_MEMTYPE_* in omapfb.h */
143 #define DISPC_MEMTYPE_NUM               2
144
145 #define RESMAP_SIZE(_page_cnt)                                          \
146         ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
147 #define RESMAP_PTR(_res_map, _page_nr)                                  \
148         (((_res_map)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
149 #define RESMAP_MASK(_page_nr)                                           \
150         (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
151
152 struct resmap {
153         unsigned long   start;
154         unsigned        page_cnt;
155         unsigned long   *map;
156 };
157
158 #define MAX_IRQ_HANDLERS            4
159
160 static struct {
161         void __iomem    *base;
162
163         struct omapfb_mem_desc  mem_desc;
164         struct resmap           *res_map[DISPC_MEMTYPE_NUM];
165         atomic_t                map_count[OMAPFB_PLANE_NUM];
166
167         dma_addr_t      palette_paddr;
168         void            *palette_vaddr;
169
170         int             ext_mode;
171
172         struct {
173                 u32     irq_mask;
174                 void    (*callback)(void *);
175                 void    *data;
176         } irq_handlers[MAX_IRQ_HANDLERS];
177         struct completion       frame_done;
178
179         int             fir_hinc[OMAPFB_PLANE_NUM];
180         int             fir_vinc[OMAPFB_PLANE_NUM];
181
182         struct clk      *dss_ick, *dss1_fck;
183         struct clk      *dss_54m_fck;
184
185         enum omapfb_update_mode update_mode;
186         struct omapfb_device    *fbdev;
187
188         struct omapfb_color_key color_key;
189 } dispc;
190
191 static void enable_lcd_clocks(int enable);
192
193 static void inline dispc_write_reg(int idx, u32 val)
194 {
195         __raw_writel(val, dispc.base + idx);
196 }
197
198 static u32 inline dispc_read_reg(int idx)
199 {
200         u32 l = __raw_readl(dispc.base + idx);
201         return l;
202 }
203
204 /* Select RFBI or bypass mode */
205 static void enable_rfbi_mode(int enable)
206 {
207         u32 l;
208
209         l = dispc_read_reg(DISPC_CONTROL);
210         /* Enable RFBI, GPIO0/1 */
211         l &= ~((1 << 11) | (1 << 15) | (1 << 16));
212         l |= enable ? (1 << 11) : 0;
213         /* RFBI En: GPIO0/1=10  RFBI Dis: GPIO0/1=11 */
214         l |= 1 << 15;
215         l |= enable ? 0 : (1 << 16);
216         dispc_write_reg(DISPC_CONTROL, l);
217
218         /* Set bypass mode in RFBI module */
219         l = __raw_readl(OMAP2_IO_ADDRESS(RFBI_CONTROL));
220         l |= enable ? 0 : (1 << 1);
221         __raw_writel(l, OMAP2_IO_ADDRESS(RFBI_CONTROL));
222 }
223
224 static void set_lcd_data_lines(int data_lines)
225 {
226         u32 l;
227         int code = 0;
228
229         switch (data_lines) {
230         case 12:
231                 code = 0;
232                 break;
233         case 16:
234                 code = 1;
235                 break;
236         case 18:
237                 code = 2;
238                 break;
239         case 24:
240                 code = 3;
241                 break;
242         default:
243                 BUG();
244         }
245
246         l = dispc_read_reg(DISPC_CONTROL);
247         l &= ~(0x03 << 8);
248         l |= code << 8;
249         dispc_write_reg(DISPC_CONTROL, l);
250 }
251
252 static void set_load_mode(int mode)
253 {
254         BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY |
255                         DISPC_LOAD_CLUT_ONCE_FRAME));
256         MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);
257 }
258
259 void omap_dispc_set_lcd_size(int x, int y)
260 {
261         BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
262         enable_lcd_clocks(1);
263         MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),
264                         ((y - 1) << 16) | (x - 1));
265         enable_lcd_clocks(0);
266 }
267 EXPORT_SYMBOL(omap_dispc_set_lcd_size);
268
269 void omap_dispc_set_digit_size(int x, int y)
270 {
271         BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
272         enable_lcd_clocks(1);
273         MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),
274                         ((y - 1) << 16) | (x - 1));
275         enable_lcd_clocks(0);
276 }
277 EXPORT_SYMBOL(omap_dispc_set_digit_size);
278
279 static void setup_plane_fifo(int plane, int ext_mode)
280 {
281         const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
282                                 DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD,
283                                 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD };
284         const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
285                                 DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS,
286                                 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS };
287         int low, high;
288         u32 l;
289
290         BUG_ON(plane > 2);
291
292         l = dispc_read_reg(fsz_reg[plane]);
293         l &= FLD_MASK(0, 11);
294         if (ext_mode) {
295                 low = l * 3 / 4;
296                 high = l;
297         } else {
298                 low = l / 4;
299                 high = l * 3 / 4;
300         }
301         MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),
302                         (high << 16) | low);
303 }
304
305 void omap_dispc_enable_lcd_out(int enable)
306 {
307         enable_lcd_clocks(1);
308         MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);
309         enable_lcd_clocks(0);
310 }
311 EXPORT_SYMBOL(omap_dispc_enable_lcd_out);
312
313 void omap_dispc_enable_digit_out(int enable)
314 {
315         enable_lcd_clocks(1);
316         MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);
317         enable_lcd_clocks(0);
318 }
319 EXPORT_SYMBOL(omap_dispc_enable_digit_out);
320
321 static inline int _setup_plane(int plane, int channel_out,
322                                   u32 paddr, int screen_width,
323                                   int pos_x, int pos_y, int width, int height,
324                                   int color_mode)
325 {
326         const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
327                                 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
328                                 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
329         const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0,
330                                 DISPC_VID2_BASE + DISPC_VID_BA0 };
331         const u32 ps_reg[] = { DISPC_GFX_POSITION,
332                                 DISPC_VID1_BASE + DISPC_VID_POSITION,
333                                 DISPC_VID2_BASE + DISPC_VID_POSITION };
334         const u32 sz_reg[] = { DISPC_GFX_SIZE,
335                                 DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE,
336                                 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE };
337         const u32 ri_reg[] = { DISPC_GFX_ROW_INC,
338                                 DISPC_VID1_BASE + DISPC_VID_ROW_INC,
339                                 DISPC_VID2_BASE + DISPC_VID_ROW_INC };
340         const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
341                                 DISPC_VID2_BASE + DISPC_VID_SIZE };
342
343         int chout_shift, burst_shift;
344         int chout_val;
345         int color_code;
346         int bpp;
347         int cconv_en;
348         int set_vsize;
349         u32 l;
350
351 #ifdef VERBOSE
352         dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d"
353                     " pos_x %d pos_y %d width %d height %d color_mode %d\n",
354                     plane, channel_out, paddr, screen_width, pos_x, pos_y,
355                     width, height, color_mode);
356 #endif
357
358         set_vsize = 0;
359         switch (plane) {
360         case OMAPFB_PLANE_GFX:
361                 burst_shift = 6;
362                 chout_shift = 8;
363                 break;
364         case OMAPFB_PLANE_VID1:
365         case OMAPFB_PLANE_VID2:
366                 burst_shift = 14;
367                 chout_shift = 16;
368                 set_vsize = 1;
369                 break;
370         default:
371                 return -EINVAL;
372         }
373
374         switch (channel_out) {
375         case OMAPFB_CHANNEL_OUT_LCD:
376                 chout_val = 0;
377                 break;
378         case OMAPFB_CHANNEL_OUT_DIGIT:
379                 chout_val = 1;
380                 break;
381         default:
382                 return -EINVAL;
383         }
384
385         cconv_en = 0;
386         switch (color_mode) {
387         case OMAPFB_COLOR_RGB565:
388                 color_code = DISPC_RGB_16_BPP;
389                 bpp = 16;
390                 break;
391         case OMAPFB_COLOR_YUV422:
392                 if (plane == 0)
393                         return -EINVAL;
394                 color_code = DISPC_UYVY_422;
395                 cconv_en = 1;
396                 bpp = 16;
397                 break;
398         case OMAPFB_COLOR_YUY422:
399                 if (plane == 0)
400                         return -EINVAL;
401                 color_code = DISPC_YUV2_422;
402                 cconv_en = 1;
403                 bpp = 16;
404                 break;
405         default:
406                 return -EINVAL;
407         }
408
409         l = dispc_read_reg(at_reg[plane]);
410
411         l &= ~(0x0f << 1);
412         l |= color_code << 1;
413         l &= ~(1 << 9);
414         l |= cconv_en << 9;
415
416         l &= ~(0x03 << burst_shift);
417         l |= DISPC_BURST_8x32 << burst_shift;
418
419         l &= ~(1 << chout_shift);
420         l |= chout_val << chout_shift;
421
422         dispc_write_reg(at_reg[plane], l);
423
424         dispc_write_reg(ba_reg[plane], paddr);
425         MOD_REG_FLD(ps_reg[plane],
426                     FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x);
427
428         MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),
429                         ((height - 1) << 16) | (width - 1));
430
431         if (set_vsize) {
432                 /* Set video size if set_scale hasn't set it */
433                 if (!dispc.fir_vinc[plane])
434                         MOD_REG_FLD(vs_reg[plane],
435                                 FLD_MASK(16, 11), (height - 1) << 16);
436                 if (!dispc.fir_hinc[plane])
437                         MOD_REG_FLD(vs_reg[plane],
438                                 FLD_MASK(0, 11), width - 1);
439         }
440
441         dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
442
443         return height * screen_width * bpp / 8;
444 }
445
446 static int omap_dispc_setup_plane(int plane, int channel_out,
447                                   unsigned long offset,
448                                   int screen_width,
449                                   int pos_x, int pos_y, int width, int height,
450                                   int color_mode)
451 {
452         u32 paddr;
453         int r;
454
455         if ((unsigned)plane > dispc.mem_desc.region_cnt)
456                 return -EINVAL;
457         paddr = dispc.mem_desc.region[plane].paddr + offset;
458         enable_lcd_clocks(1);
459         r = _setup_plane(plane, channel_out, paddr,
460                         screen_width,
461                         pos_x, pos_y, width, height, color_mode);
462         enable_lcd_clocks(0);
463         return r;
464 }
465
466 static void write_firh_reg(int plane, int reg, u32 value)
467 {
468         u32 base;
469
470         if (plane == 1)
471                 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0;
472         else
473                 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0;
474         dispc_write_reg(base + reg * 8, value);
475 }
476
477 static void write_firhv_reg(int plane, int reg, u32 value)
478 {
479         u32 base;
480
481         if (plane == 1)
482                 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0;
483         else
484                 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0;
485         dispc_write_reg(base + reg * 8, value);
486 }
487
488 static void set_upsampling_coef_table(int plane)
489 {
490         const u32 coef[][2] = {
491                 { 0x00800000, 0x00800000 },
492                 { 0x0D7CF800, 0x037B02FF },
493                 { 0x1E70F5FF, 0x0C6F05FE },
494                 { 0x335FF5FE, 0x205907FB },
495                 { 0xF74949F7, 0x00404000 },
496                 { 0xF55F33FB, 0x075920FE },
497                 { 0xF5701EFE, 0x056F0CFF },
498                 { 0xF87C0DFF, 0x027B0300 },
499         };
500         int i;
501
502         for (i = 0; i < 8; i++) {
503                 write_firh_reg(plane, i, coef[i][0]);
504                 write_firhv_reg(plane, i, coef[i][1]);
505         }
506 }
507
508 static int omap_dispc_set_scale(int plane,
509                                 int orig_width, int orig_height,
510                                 int out_width, int out_height)
511 {
512         const u32 at_reg[]  = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
513                                 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
514         const u32 vs_reg[]  = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
515                                 DISPC_VID2_BASE + DISPC_VID_SIZE };
516         const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR,
517                                 DISPC_VID2_BASE + DISPC_VID_FIR };
518
519         u32 l;
520         int fir_hinc;
521         int fir_vinc;
522
523         if ((unsigned)plane > OMAPFB_PLANE_NUM)
524                 return -ENODEV;
525
526         if (plane == OMAPFB_PLANE_GFX &&
527             (out_width != orig_width || out_height != orig_height))
528                 return -EINVAL;
529
530         enable_lcd_clocks(1);
531         if (orig_width < out_width) {
532                 /*
533                  * Upsampling.
534                  * Currently you can only scale both dimensions in one way.
535                  */
536                 if (orig_height > out_height ||
537                     orig_width * 8 < out_width ||
538                     orig_height * 8 < out_height) {
539                         enable_lcd_clocks(0);
540                         return -EINVAL;
541                 }
542                 set_upsampling_coef_table(plane);
543         } else if (orig_width > out_width) {
544                 /* Downsampling not yet supported
545                 */
546
547                 enable_lcd_clocks(0);
548                 return -EINVAL;
549         }
550         if (!orig_width || orig_width == out_width)
551                 fir_hinc = 0;
552         else
553                 fir_hinc = 1024 * orig_width / out_width;
554         if (!orig_height || orig_height == out_height)
555                 fir_vinc = 0;
556         else
557                 fir_vinc = 1024 * orig_height / out_height;
558         dispc.fir_hinc[plane] = fir_hinc;
559         dispc.fir_vinc[plane] = fir_vinc;
560
561         MOD_REG_FLD(fir_reg[plane],
562                     FLD_MASK(16, 12) | FLD_MASK(0, 12),
563                     ((fir_vinc & 4095) << 16) |
564                     (fir_hinc & 4095));
565
566         dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
567                 "orig_height %d fir_hinc  %d fir_vinc %d\n",
568                 out_width, out_height, orig_width, orig_height,
569                 fir_hinc, fir_vinc);
570
571         MOD_REG_FLD(vs_reg[plane],
572                     FLD_MASK(16, 11) | FLD_MASK(0, 11),
573                     ((out_height - 1) << 16) | (out_width - 1));
574
575         l = dispc_read_reg(at_reg[plane]);
576         l &= ~(0x03 << 5);
577         l |= fir_hinc ? (1 << 5) : 0;
578         l |= fir_vinc ? (1 << 6) : 0;
579         dispc_write_reg(at_reg[plane], l);
580
581         enable_lcd_clocks(0);
582         return 0;
583 }
584
585 static int omap_dispc_enable_plane(int plane, int enable)
586 {
587         const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
588                                 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
589                                 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
590         if ((unsigned int)plane > dispc.mem_desc.region_cnt)
591                 return -EINVAL;
592
593         enable_lcd_clocks(1);
594         MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
595         enable_lcd_clocks(0);
596
597         return 0;
598 }
599
600 static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
601 {
602         u32 df_reg, tr_reg;
603         int shift, val;
604
605         switch (ck->channel_out) {
606         case OMAPFB_CHANNEL_OUT_LCD:
607                 df_reg = DISPC_DEFAULT_COLOR0;
608                 tr_reg = DISPC_TRANS_COLOR0;
609                 shift = 10;
610                 break;
611         case OMAPFB_CHANNEL_OUT_DIGIT:
612                 df_reg = DISPC_DEFAULT_COLOR1;
613                 tr_reg = DISPC_TRANS_COLOR1;
614                 shift = 12;
615                 break;
616         default:
617                 return -EINVAL;
618         }
619         switch (ck->key_type) {
620         case OMAPFB_COLOR_KEY_DISABLED:
621                 val = 0;
622                 break;
623         case OMAPFB_COLOR_KEY_GFX_DST:
624                 val = 1;
625                 break;
626         case OMAPFB_COLOR_KEY_VID_SRC:
627                 val = 3;
628                 break;
629         default:
630                 return -EINVAL;
631         }
632         enable_lcd_clocks(1);
633         MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);
634
635         if (val != 0)
636                 dispc_write_reg(tr_reg, ck->trans_key);
637         dispc_write_reg(df_reg, ck->background);
638         enable_lcd_clocks(0);
639
640         dispc.color_key = *ck;
641
642         return 0;
643 }
644
645 static int omap_dispc_get_color_key(struct omapfb_color_key *ck)
646 {
647         *ck = dispc.color_key;
648         return 0;
649 }
650
651 static void load_palette(void)
652 {
653 }
654
655 static int omap_dispc_set_update_mode(enum omapfb_update_mode mode)
656 {
657         int r = 0;
658
659         if (mode != dispc.update_mode) {
660                 switch (mode) {
661                 case OMAPFB_AUTO_UPDATE:
662                 case OMAPFB_MANUAL_UPDATE:
663                         enable_lcd_clocks(1);
664                         omap_dispc_enable_lcd_out(1);
665                         dispc.update_mode = mode;
666                         break;
667                 case OMAPFB_UPDATE_DISABLED:
668                         init_completion(&dispc.frame_done);
669                         omap_dispc_enable_lcd_out(0);
670                         if (!wait_for_completion_timeout(&dispc.frame_done,
671                                         msecs_to_jiffies(500))) {
672                                 dev_err(dispc.fbdev->dev,
673                                          "timeout waiting for FRAME DONE\n");
674                         }
675                         dispc.update_mode = mode;
676                         enable_lcd_clocks(0);
677                         break;
678                 default:
679                         r = -EINVAL;
680                 }
681         }
682
683         return r;
684 }
685
686 static void omap_dispc_get_caps(int plane, struct omapfb_caps *caps)
687 {
688         caps->ctrl |= OMAPFB_CAPS_PLANE_RELOCATE_MEM;
689         if (plane > 0)
690                 caps->ctrl |= OMAPFB_CAPS_PLANE_SCALE;
691         caps->plane_color |= (1 << OMAPFB_COLOR_RGB565) |
692                              (1 << OMAPFB_COLOR_YUV422) |
693                              (1 << OMAPFB_COLOR_YUY422);
694         if (plane == 0)
695                 caps->plane_color |= (1 << OMAPFB_COLOR_CLUT_8BPP) |
696                                      (1 << OMAPFB_COLOR_CLUT_4BPP) |
697                                      (1 << OMAPFB_COLOR_CLUT_2BPP) |
698                                      (1 << OMAPFB_COLOR_CLUT_1BPP) |
699                                      (1 << OMAPFB_COLOR_RGB444);
700 }
701
702 static enum omapfb_update_mode omap_dispc_get_update_mode(void)
703 {
704         return dispc.update_mode;
705 }
706
707 static void setup_color_conv_coef(void)
708 {
709         u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11);
710         int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0;
711         int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0;
712         int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES;
713         int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES;
714         const struct color_conv_coef {
715                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
716                 int  full_range;
717         }  ctbl_bt601_5 = {
718                     298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
719         };
720         const struct color_conv_coef *ct;
721 #define CVAL(x, y)      (((x & 2047) << 16) | (y & 2047))
722
723         ct = &ctbl_bt601_5;
724
725         MOD_REG_FLD(cf1_reg,            mask,   CVAL(ct->rcr, ct->ry));
726         MOD_REG_FLD(cf1_reg + 4,        mask,   CVAL(ct->gy,  ct->rcb));
727         MOD_REG_FLD(cf1_reg + 8,        mask,   CVAL(ct->gcb, ct->gcr));
728         MOD_REG_FLD(cf1_reg + 12,       mask,   CVAL(ct->bcr, ct->by));
729         MOD_REG_FLD(cf1_reg + 16,       mask,   CVAL(0,       ct->bcb));
730
731         MOD_REG_FLD(cf2_reg,            mask,   CVAL(ct->rcr, ct->ry));
732         MOD_REG_FLD(cf2_reg + 4,        mask,   CVAL(ct->gy,  ct->rcb));
733         MOD_REG_FLD(cf2_reg + 8,        mask,   CVAL(ct->gcb, ct->gcr));
734         MOD_REG_FLD(cf2_reg + 12,       mask,   CVAL(ct->bcr, ct->by));
735         MOD_REG_FLD(cf2_reg + 16,       mask,   CVAL(0,       ct->bcb));
736 #undef CVAL
737
738         MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);
739         MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
740 }
741
742 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
743 {
744         unsigned long fck, lck;
745
746         *lck_div = 1;
747         pck = max(1, pck);
748         fck = clk_get_rate(dispc.dss1_fck);
749         lck = fck;
750         *pck_div = (lck + pck - 1) / pck;
751         if (is_tft)
752                 *pck_div = max(2, *pck_div);
753         else
754                 *pck_div = max(3, *pck_div);
755         if (*pck_div > 255) {
756                 *pck_div = 255;
757                 lck = pck * *pck_div;
758                 *lck_div = fck / lck;
759                 BUG_ON(*lck_div < 1);
760                 if (*lck_div > 255) {
761                         *lck_div = 255;
762                         dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n",
763                                  pck / 1000);
764                 }
765         }
766 }
767
768 static void set_lcd_tft_mode(int enable)
769 {
770         u32 mask;
771
772         mask = 1 << 3;
773         MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);
774 }
775
776 static void set_lcd_timings(void)
777 {
778         u32 l;
779         int lck_div, pck_div;
780         struct lcd_panel *panel = dispc.fbdev->panel;
781         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
782         unsigned long fck;
783
784         l = dispc_read_reg(DISPC_TIMING_H);
785         l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
786         l |= ( max(1, (min(64,  panel->hsw))) - 1 ) << 0;
787         l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8;
788         l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20;
789         dispc_write_reg(DISPC_TIMING_H, l);
790
791         l = dispc_read_reg(DISPC_TIMING_V);
792         l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
793         l |= ( max(1, (min(64,  panel->vsw))) - 1 ) << 0;
794         l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8;
795         l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20;
796         dispc_write_reg(DISPC_TIMING_V, l);
797
798         l = dispc_read_reg(DISPC_POL_FREQ);
799         l &= ~FLD_MASK(12, 6);
800         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12;
801         l |= panel->acb & 0xff;
802         dispc_write_reg(DISPC_POL_FREQ, l);
803
804         calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
805
806         l = dispc_read_reg(DISPC_DIVISOR);
807         l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
808         l |= (lck_div << 16) | (pck_div << 0);
809         dispc_write_reg(DISPC_DIVISOR, l);
810
811         /* update panel info with the exact clock */
812         fck = clk_get_rate(dispc.dss1_fck);
813         panel->pixel_clock = fck / lck_div / pck_div / 1000;
814 }
815
816 static void recalc_irq_mask(void)
817 {
818         int i;
819         unsigned long irq_mask = DISPC_IRQ_MASK_ERROR;
820
821         for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
822                 if (!dispc.irq_handlers[i].callback)
823                         continue;
824
825                 irq_mask |= dispc.irq_handlers[i].irq_mask;
826         }
827
828         enable_lcd_clocks(1);
829         MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
830         enable_lcd_clocks(0);
831 }
832
833 int omap_dispc_request_irq(unsigned long irq_mask, void (*callback)(void *data),
834                            void *data)
835 {
836         int i;
837
838         BUG_ON(callback == NULL);
839
840         for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
841                 if (dispc.irq_handlers[i].callback)
842                         continue;
843
844                 dispc.irq_handlers[i].irq_mask = irq_mask;
845                 dispc.irq_handlers[i].callback = callback;
846                 dispc.irq_handlers[i].data = data;
847                 recalc_irq_mask();
848
849                 return 0;
850         }
851
852         return -EBUSY;
853 }
854 EXPORT_SYMBOL(omap_dispc_request_irq);
855
856 void omap_dispc_free_irq(unsigned long irq_mask, void (*callback)(void *data),
857                          void *data)
858 {
859         int i;
860
861         for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
862                 if (dispc.irq_handlers[i].callback == callback &&
863                     dispc.irq_handlers[i].data == data) {
864                         dispc.irq_handlers[i].irq_mask = 0;
865                         dispc.irq_handlers[i].callback = NULL;
866                         dispc.irq_handlers[i].data = NULL;
867                         recalc_irq_mask();
868                         return;
869                 }
870         }
871
872         BUG();
873 }
874 EXPORT_SYMBOL(omap_dispc_free_irq);
875
876 static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
877 {
878         u32 stat;
879         int i = 0;
880
881         enable_lcd_clocks(1);
882
883         stat = dispc_read_reg(DISPC_IRQSTATUS);
884         if (stat & DISPC_IRQ_FRAMEMASK)
885                 complete(&dispc.frame_done);
886
887         if (stat & DISPC_IRQ_MASK_ERROR) {
888                 if (printk_ratelimit()) {
889                         dev_err(dispc.fbdev->dev, "irq error status %04x\n",
890                                 stat & 0x7fff);
891                 }
892         }
893
894         for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
895                 if (unlikely(dispc.irq_handlers[i].callback &&
896                              (stat & dispc.irq_handlers[i].irq_mask)))
897                         dispc.irq_handlers[i].callback(
898                                                 dispc.irq_handlers[i].data);
899         }
900
901         dispc_write_reg(DISPC_IRQSTATUS, stat);
902
903         enable_lcd_clocks(0);
904
905         return IRQ_HANDLED;
906 }
907
908 static int get_dss_clocks(void)
909 {
910         dispc.dss_ick = clk_get(dispc.fbdev->dev, "ick");
911         if (IS_ERR(dispc.dss_ick)) {
912                 dev_err(dispc.fbdev->dev, "can't get ick\n");
913                 return PTR_ERR(dispc.dss_ick);
914         }
915
916         dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck");
917         if (IS_ERR(dispc.dss1_fck)) {
918                 dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
919                 clk_put(dispc.dss_ick);
920                 return PTR_ERR(dispc.dss1_fck);
921         }
922
923         dispc.dss_54m_fck = clk_get(dispc.fbdev->dev, "tv_fck");
924         if (IS_ERR(dispc.dss_54m_fck)) {
925                 dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
926                 clk_put(dispc.dss_ick);
927                 clk_put(dispc.dss1_fck);
928                 return PTR_ERR(dispc.dss_54m_fck);
929         }
930
931         return 0;
932 }
933
934 static void put_dss_clocks(void)
935 {
936         clk_put(dispc.dss_54m_fck);
937         clk_put(dispc.dss1_fck);
938         clk_put(dispc.dss_ick);
939 }
940
941 static void enable_lcd_clocks(int enable)
942 {
943         if (enable) {
944                 clk_enable(dispc.dss_ick);
945                 clk_enable(dispc.dss1_fck);
946         } else {
947                 clk_disable(dispc.dss1_fck);
948                 clk_disable(dispc.dss_ick);
949         }
950 }
951
952 static void enable_digit_clocks(int enable)
953 {
954         if (enable)
955                 clk_enable(dispc.dss_54m_fck);
956         else
957                 clk_disable(dispc.dss_54m_fck);
958 }
959
960 static void omap_dispc_suspend(void)
961 {
962         if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
963                 init_completion(&dispc.frame_done);
964                 omap_dispc_enable_lcd_out(0);
965                 if (!wait_for_completion_timeout(&dispc.frame_done,
966                                 msecs_to_jiffies(500))) {
967                         dev_err(dispc.fbdev->dev,
968                                 "timeout waiting for FRAME DONE\n");
969                 }
970                 enable_lcd_clocks(0);
971         }
972 }
973
974 static void omap_dispc_resume(void)
975 {
976         if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
977                 enable_lcd_clocks(1);
978                 if (!dispc.ext_mode) {
979                         set_lcd_timings();
980                         load_palette();
981                 }
982                 omap_dispc_enable_lcd_out(1);
983         }
984 }
985
986
987 static int omap_dispc_update_window(struct fb_info *fbi,
988                                  struct omapfb_update_window *win,
989                                  void (*complete_callback)(void *arg),
990                                  void *complete_callback_data)
991 {
992         return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0;
993 }
994
995 static int mmap_kern(struct omapfb_mem_region *region)
996 {
997         struct vm_struct        *kvma;
998         struct vm_area_struct   vma;
999         pgprot_t                pgprot;
1000         unsigned long           vaddr;
1001
1002         kvma = get_vm_area(region->size, VM_IOREMAP);
1003         if (kvma == NULL) {
1004                 dev_err(dispc.fbdev->dev, "can't get kernel vm area\n");
1005                 return -ENOMEM;
1006         }
1007         vma.vm_mm = &init_mm;
1008
1009         vaddr = (unsigned long)kvma->addr;
1010
1011         pgprot = pgprot_writecombine(pgprot_kernel);
1012         vma.vm_start = vaddr;
1013         vma.vm_end = vaddr + region->size;
1014         if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT,
1015                            region->size, pgprot) < 0) {
1016                 dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n");
1017                 return -EAGAIN;
1018         }
1019         region->vaddr = (void *)vaddr;
1020
1021         return 0;
1022 }
1023
1024 static void mmap_user_open(struct vm_area_struct *vma)
1025 {
1026         int plane = (int)vma->vm_private_data;
1027
1028         atomic_inc(&dispc.map_count[plane]);
1029 }
1030
1031 static void mmap_user_close(struct vm_area_struct *vma)
1032 {
1033         int plane = (int)vma->vm_private_data;
1034
1035         atomic_dec(&dispc.map_count[plane]);
1036 }
1037
1038 static const struct vm_operations_struct mmap_user_ops = {
1039         .open = mmap_user_open,
1040         .close = mmap_user_close,
1041 };
1042
1043 static int omap_dispc_mmap_user(struct fb_info *info,
1044                                 struct vm_area_struct *vma)
1045 {
1046         struct omapfb_plane_struct *plane = info->par;
1047         unsigned long off;
1048         unsigned long start;
1049         u32 len;
1050
1051         if (vma->vm_end - vma->vm_start == 0)
1052                 return 0;
1053         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1054                 return -EINVAL;
1055         off = vma->vm_pgoff << PAGE_SHIFT;
1056
1057         start = info->fix.smem_start;
1058         len = info->fix.smem_len;
1059         if (off >= len)
1060                 return -EINVAL;
1061         if ((vma->vm_end - vma->vm_start + off) > len)
1062                 return -EINVAL;
1063         off += start;
1064         vma->vm_pgoff = off >> PAGE_SHIFT;
1065         vma->vm_flags |= VM_IO | VM_RESERVED;
1066         vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1067         vma->vm_ops = &mmap_user_ops;
1068         vma->vm_private_data = (void *)plane->idx;
1069         if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1070                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
1071                 return -EAGAIN;
1072         /* vm_ops.open won't be called for mmap itself. */
1073         atomic_inc(&dispc.map_count[plane->idx]);
1074         return 0;
1075 }
1076
1077 static void unmap_kern(struct omapfb_mem_region *region)
1078 {
1079         vunmap(region->vaddr);
1080 }
1081
1082 static int alloc_palette_ram(void)
1083 {
1084         dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1085                 MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL);
1086         if (dispc.palette_vaddr == NULL) {
1087                 dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n");
1088                 return -ENOMEM;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static void free_palette_ram(void)
1095 {
1096         dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE,
1097                         dispc.palette_vaddr, dispc.palette_paddr);
1098 }
1099
1100 static int alloc_fbmem(struct omapfb_mem_region *region)
1101 {
1102         region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1103                         region->size, &region->paddr, GFP_KERNEL);
1104
1105         if (region->vaddr == NULL) {
1106                 dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n");
1107                 return -ENOMEM;
1108         }
1109
1110         return 0;
1111 }
1112
1113 static void free_fbmem(struct omapfb_mem_region *region)
1114 {
1115         dma_free_writecombine(dispc.fbdev->dev, region->size,
1116                               region->vaddr, region->paddr);
1117 }
1118
1119 static struct resmap *init_resmap(unsigned long start, size_t size)
1120 {
1121         unsigned page_cnt;
1122         struct resmap *res_map;
1123
1124         page_cnt = PAGE_ALIGN(size) / PAGE_SIZE;
1125         res_map =
1126             kzalloc(sizeof(struct resmap) + RESMAP_SIZE(page_cnt), GFP_KERNEL);
1127         if (res_map == NULL)
1128                 return NULL;
1129         res_map->start = start;
1130         res_map->page_cnt = page_cnt;
1131         res_map->map = (unsigned long *)(res_map + 1);
1132         return res_map;
1133 }
1134
1135 static void cleanup_resmap(struct resmap *res_map)
1136 {
1137         kfree(res_map);
1138 }
1139
1140 static inline int resmap_mem_type(unsigned long start)
1141 {
1142         if (start >= OMAP2_SRAM_START &&
1143             start < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
1144                 return OMAPFB_MEMTYPE_SRAM;
1145         else
1146                 return OMAPFB_MEMTYPE_SDRAM;
1147 }
1148
1149 static inline int resmap_page_reserved(struct resmap *res_map, unsigned page_nr)
1150 {
1151         return *RESMAP_PTR(res_map, page_nr) & RESMAP_MASK(page_nr) ? 1 : 0;
1152 }
1153
1154 static inline void resmap_reserve_page(struct resmap *res_map, unsigned page_nr)
1155 {
1156         BUG_ON(resmap_page_reserved(res_map, page_nr));
1157         *RESMAP_PTR(res_map, page_nr) |= RESMAP_MASK(page_nr);
1158 }
1159
1160 static inline void resmap_free_page(struct resmap *res_map, unsigned page_nr)
1161 {
1162         BUG_ON(!resmap_page_reserved(res_map, page_nr));
1163         *RESMAP_PTR(res_map, page_nr) &= ~RESMAP_MASK(page_nr);
1164 }
1165
1166 static void resmap_reserve_region(unsigned long start, size_t size)
1167 {
1168
1169         struct resmap   *res_map;
1170         unsigned        start_page;
1171         unsigned        end_page;
1172         int             mtype;
1173         unsigned        i;
1174
1175         mtype = resmap_mem_type(start);
1176         res_map = dispc.res_map[mtype];
1177         dev_dbg(dispc.fbdev->dev, "reserve mem type %d start %08lx size %d\n",
1178                 mtype, start, size);
1179         start_page = (start - res_map->start) / PAGE_SIZE;
1180         end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1181         for (i = start_page; i < end_page; i++)
1182                 resmap_reserve_page(res_map, i);
1183 }
1184
1185 static void resmap_free_region(unsigned long start, size_t size)
1186 {
1187         struct resmap   *res_map;
1188         unsigned        start_page;
1189         unsigned        end_page;
1190         unsigned        i;
1191         int             mtype;
1192
1193         mtype = resmap_mem_type(start);
1194         res_map = dispc.res_map[mtype];
1195         dev_dbg(dispc.fbdev->dev, "free mem type %d start %08lx size %d\n",
1196                 mtype, start, size);
1197         start_page = (start - res_map->start) / PAGE_SIZE;
1198         end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1199         for (i = start_page; i < end_page; i++)
1200                 resmap_free_page(res_map, i);
1201 }
1202
1203 static unsigned long resmap_alloc_region(int mtype, size_t size)
1204 {
1205         unsigned i;
1206         unsigned total;
1207         unsigned start_page;
1208         unsigned long start;
1209         struct resmap *res_map = dispc.res_map[mtype];
1210
1211         BUG_ON(mtype >= DISPC_MEMTYPE_NUM || res_map == NULL || !size);
1212
1213         size = PAGE_ALIGN(size) / PAGE_SIZE;
1214         start_page = 0;
1215         total = 0;
1216         for (i = 0; i < res_map->page_cnt; i++) {
1217                 if (resmap_page_reserved(res_map, i)) {
1218                         start_page = i + 1;
1219                         total = 0;
1220                 } else if (++total == size)
1221                         break;
1222         }
1223         if (total < size)
1224                 return 0;
1225
1226         start = res_map->start + start_page * PAGE_SIZE;
1227         resmap_reserve_region(start, size * PAGE_SIZE);
1228
1229         return start;
1230 }
1231
1232 /* Note that this will only work for user mappings, we don't deal with
1233  * kernel mappings here, so fbcon will keep using the old region.
1234  */
1235 static int omap_dispc_setup_mem(int plane, size_t size, int mem_type,
1236                                 unsigned long *paddr)
1237 {
1238         struct omapfb_mem_region *rg;
1239         unsigned long new_addr = 0;
1240
1241         if ((unsigned)plane > dispc.mem_desc.region_cnt)
1242                 return -EINVAL;
1243         if (mem_type >= DISPC_MEMTYPE_NUM)
1244                 return -EINVAL;
1245         if (dispc.res_map[mem_type] == NULL)
1246                 return -ENOMEM;
1247         rg = &dispc.mem_desc.region[plane];
1248         if (size == rg->size && mem_type == rg->type)
1249                 return 0;
1250         if (atomic_read(&dispc.map_count[plane]))
1251                 return -EBUSY;
1252         if (rg->size != 0)
1253                 resmap_free_region(rg->paddr, rg->size);
1254         if (size != 0) {
1255                 new_addr = resmap_alloc_region(mem_type, size);
1256                 if (!new_addr) {
1257                         /* Reallocate old region. */
1258                         resmap_reserve_region(rg->paddr, rg->size);
1259                         return -ENOMEM;
1260                 }
1261         }
1262         rg->paddr = new_addr;
1263         rg->size = size;
1264         rg->type = mem_type;
1265
1266         *paddr = new_addr;
1267
1268         return 0;
1269 }
1270
1271 static int setup_fbmem(struct omapfb_mem_desc *req_md)
1272 {
1273         struct omapfb_mem_region        *rg;
1274         int i;
1275         int r;
1276         unsigned long                   mem_start[DISPC_MEMTYPE_NUM];
1277         unsigned long                   mem_end[DISPC_MEMTYPE_NUM];
1278
1279         if (!req_md->region_cnt) {
1280                 dev_err(dispc.fbdev->dev, "no memory regions defined\n");
1281                 return -ENOENT;
1282         }
1283
1284         rg = &req_md->region[0];
1285         memset(mem_start, 0xff, sizeof(mem_start));
1286         memset(mem_end, 0, sizeof(mem_end));
1287
1288         for (i = 0; i < req_md->region_cnt; i++, rg++) {
1289                 int mtype;
1290                 if (rg->paddr) {
1291                         rg->alloc = 0;
1292                         if (rg->vaddr == NULL) {
1293                                 rg->map = 1;
1294                                 if ((r = mmap_kern(rg)) < 0)
1295                                         return r;
1296                         }
1297                 } else {
1298                         if (rg->type != OMAPFB_MEMTYPE_SDRAM) {
1299                                 dev_err(dispc.fbdev->dev,
1300                                         "unsupported memory type\n");
1301                                 return -EINVAL;
1302                         }
1303                         rg->alloc = rg->map = 1;
1304                         if ((r = alloc_fbmem(rg)) < 0)
1305                                 return r;
1306                 }
1307                 mtype = rg->type;
1308
1309                 if (rg->paddr < mem_start[mtype])
1310                         mem_start[mtype] = rg->paddr;
1311                 if (rg->paddr + rg->size > mem_end[mtype])
1312                         mem_end[mtype] = rg->paddr + rg->size;
1313         }
1314
1315         for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1316                 unsigned long start;
1317                 size_t size;
1318                 if (mem_end[i] == 0)
1319                         continue;
1320                 start = mem_start[i];
1321                 size = mem_end[i] - start;
1322                 dispc.res_map[i] = init_resmap(start, size);
1323                 r = -ENOMEM;
1324                 if (dispc.res_map[i] == NULL)
1325                         goto fail;
1326                 /* Initial state is that everything is reserved. This
1327                  * includes possible holes as well, which will never be
1328                  * freed.
1329                  */
1330                 resmap_reserve_region(start, size);
1331         }
1332
1333         dispc.mem_desc = *req_md;
1334
1335         return 0;
1336 fail:
1337         for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1338                 if (dispc.res_map[i] != NULL)
1339                         cleanup_resmap(dispc.res_map[i]);
1340         }
1341         return r;
1342 }
1343
1344 static void cleanup_fbmem(void)
1345 {
1346         struct omapfb_mem_region *rg;
1347         int i;
1348
1349         for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1350                 if (dispc.res_map[i] != NULL)
1351                         cleanup_resmap(dispc.res_map[i]);
1352         }
1353         rg = &dispc.mem_desc.region[0];
1354         for (i = 0; i < dispc.mem_desc.region_cnt; i++, rg++) {
1355                 if (rg->alloc)
1356                         free_fbmem(rg);
1357                 else {
1358                         if (rg->map)
1359                                 unmap_kern(rg);
1360                 }
1361         }
1362 }
1363
1364 static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1365                            struct omapfb_mem_desc *req_vram)
1366 {
1367         int r;
1368         u32 l;
1369         struct lcd_panel *panel = fbdev->panel;
1370         int tmo = 10000;
1371         int skip_init = 0;
1372         int i;
1373
1374         memset(&dispc, 0, sizeof(dispc));
1375
1376         dispc.base = ioremap(DISPC_BASE, SZ_1K);
1377         if (!dispc.base) {
1378                 dev_err(fbdev->dev, "can't ioremap DISPC\n");
1379                 return -ENOMEM;
1380         }
1381
1382         dispc.fbdev = fbdev;
1383         dispc.ext_mode = ext_mode;
1384
1385         init_completion(&dispc.frame_done);
1386
1387         if ((r = get_dss_clocks()) < 0)
1388                 goto fail0;
1389
1390         enable_lcd_clocks(1);
1391
1392 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
1393         l = dispc_read_reg(DISPC_CONTROL);
1394         /* LCD enabled ? */
1395         if (l & 1) {
1396                 pr_info("omapfb: skipping hardware initialization\n");
1397                 skip_init = 1;
1398         }
1399 #endif
1400
1401         if (!skip_init) {
1402                 /* Reset monitoring works only w/ the 54M clk */
1403                 enable_digit_clocks(1);
1404
1405                 /* Soft reset */
1406                 MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);
1407
1408                 while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) {
1409                         if (!--tmo) {
1410                                 dev_err(dispc.fbdev->dev, "soft reset failed\n");
1411                                 r = -ENODEV;
1412                                 enable_digit_clocks(0);
1413                                 goto fail1;
1414                         }
1415                 }
1416
1417                 enable_digit_clocks(0);
1418         }
1419
1420         /* Enable smart standby/idle, autoidle and wakeup */
1421         l = dispc_read_reg(DISPC_SYSCONFIG);
1422         l &= ~((3 << 12) | (3 << 3));
1423         l |= (2 << 12) | (2 << 3) | (1 << 2) | (1 << 0);
1424         dispc_write_reg(DISPC_SYSCONFIG, l);
1425         omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
1426
1427         /* Set functional clock autogating */
1428         l = dispc_read_reg(DISPC_CONFIG);
1429         l |= 1 << 9;
1430         dispc_write_reg(DISPC_CONFIG, l);
1431
1432         l = dispc_read_reg(DISPC_IRQSTATUS);
1433         dispc_write_reg(DISPC_IRQSTATUS, l);
1434
1435         recalc_irq_mask();
1436
1437         if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
1438                            0, MODULE_NAME, fbdev)) < 0) {
1439                 dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n");
1440                 goto fail1;
1441         }
1442
1443         /* L3 firewall setting: enable access to OCM RAM */
1444         __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0));
1445
1446         if ((r = alloc_palette_ram()) < 0)
1447                 goto fail2;
1448
1449         if ((r = setup_fbmem(req_vram)) < 0)
1450                 goto fail3;
1451
1452         if (!skip_init) {
1453                 for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1454                         memset(dispc.mem_desc.region[i].vaddr, 0,
1455                                 dispc.mem_desc.region[i].size);
1456                 }
1457
1458                 /* Set logic clock to fck, pixel clock to fck/2 for now */
1459                 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);
1460                 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);
1461
1462                 setup_plane_fifo(0, ext_mode);
1463                 setup_plane_fifo(1, ext_mode);
1464                 setup_plane_fifo(2, ext_mode);
1465
1466                 setup_color_conv_coef();
1467
1468                 set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT);
1469                 set_load_mode(DISPC_LOAD_FRAME_ONLY);
1470
1471                 if (!ext_mode) {
1472                         set_lcd_data_lines(panel->data_lines);
1473                         omap_dispc_set_lcd_size(panel->x_res, panel->y_res);
1474                         set_lcd_timings();
1475                 } else
1476                         set_lcd_data_lines(panel->bpp);
1477                 enable_rfbi_mode(ext_mode);
1478         }
1479
1480         l = dispc_read_reg(DISPC_REVISION);
1481         pr_info("omapfb: DISPC version %d.%d initialized\n",
1482                  l >> 4 & 0x0f, l & 0x0f);
1483         enable_lcd_clocks(0);
1484
1485         return 0;
1486 fail3:
1487         free_palette_ram();
1488 fail2:
1489         free_irq(INT_24XX_DSS_IRQ, fbdev);
1490 fail1:
1491         enable_lcd_clocks(0);
1492         put_dss_clocks();
1493 fail0:
1494         iounmap(dispc.base);
1495         return r;
1496 }
1497
1498 static void omap_dispc_cleanup(void)
1499 {
1500         int i;
1501
1502         omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED);
1503         /* This will also disable clocks that are on */
1504         for (i = 0; i < dispc.mem_desc.region_cnt; i++)
1505                 omap_dispc_enable_plane(i, 0);
1506         cleanup_fbmem();
1507         free_palette_ram();
1508         free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1509         put_dss_clocks();
1510         iounmap(dispc.base);
1511 }
1512
1513 const struct lcd_ctrl omap2_int_ctrl = {
1514         .name                   = "internal",
1515         .init                   = omap_dispc_init,
1516         .cleanup                = omap_dispc_cleanup,
1517         .get_caps               = omap_dispc_get_caps,
1518         .set_update_mode        = omap_dispc_set_update_mode,
1519         .get_update_mode        = omap_dispc_get_update_mode,
1520         .update_window          = omap_dispc_update_window,
1521         .suspend                = omap_dispc_suspend,
1522         .resume                 = omap_dispc_resume,
1523         .setup_plane            = omap_dispc_setup_plane,
1524         .setup_mem              = omap_dispc_setup_mem,
1525         .set_scale              = omap_dispc_set_scale,
1526         .enable_plane           = omap_dispc_enable_plane,
1527         .set_color_key          = omap_dispc_set_color_key,
1528         .get_color_key          = omap_dispc_get_color_key,
1529         .mmap                   = omap_dispc_mmap_user,
1530 };