cyber2000fb, rename BIT macro
[linux-2.6.git] / drivers / video / cyber2000fb.c
1 /*
2  *  linux/drivers/video/cyber2000fb.c
3  *
4  *  Copyright (C) 1998-2002 Russell King
5  *
6  *  MIPS and 50xx clock support
7  *  Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
8  *
9  *  32 bit support, text color and panning fixes for modes != 8 bit
10  *  Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
17  *
18  * Based on cyberfb.c.
19  *
20  * Note that we now use the new fbcon fix, var and cmap scheme.  We do
21  * still have to check which console is the currently displayed one
22  * however, especially for the colourmap stuff.
23  *
24  * We also use the new hotplug PCI subsystem.  I'm not sure if there
25  * are any such cards, but I'm erring on the side of caution.  We don't
26  * want to go pop just because someone does have one.
27  *
28  * Note that this doesn't work fully in the case of multiple CyberPro
29  * cards with grabbers.  We currently can only attach to the first
30  * CyberPro card found.
31  *
32  * When we're in truecolour mode, we power down the LUT RAM as a power
33  * saving feature.  Also, when we enter any of the powersaving modes
34  * (except soft blanking) we power down the RAMDACs.  This saves about
35  * 1W, which is roughly 8% of the power consumption of a NetWinder
36  * (which, incidentally, is about the same saving as a 2.5in hard disk
37  * entering standby mode.)
38  */
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
43 #include <linux/mm.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
46 #include <linux/fb.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
49
50 #include <asm/io.h>
51 #include <asm/pgtable.h>
52 #include <asm/system.h>
53
54 #ifdef __arm__
55 #include <asm/mach-types.h>
56 #endif
57
58 #include "cyber2000fb.h"
59
60 struct cfb_info {
61         struct fb_info          fb;
62         struct display_switch   *dispsw;
63         struct display          *display;
64         struct pci_dev          *dev;
65         unsigned char           __iomem *region;
66         unsigned char           __iomem *regs;
67         u_int                   id;
68         int                     func_use_count;
69         u_long                  ref_ps;
70
71         /*
72          * Clock divisors
73          */
74         u_int                   divisors[4];
75
76         struct {
77                 u8 red, green, blue;
78         } palette[NR_PALETTE];
79
80         u_char                  mem_ctl1;
81         u_char                  mem_ctl2;
82         u_char                  mclk_mult;
83         u_char                  mclk_div;
84         /*
85          * RAMDAC control register is both of these or'ed together
86          */
87         u_char                  ramdac_ctrl;
88         u_char                  ramdac_powerdown;
89
90         u32                     pseudo_palette[16];
91 };
92
93 static char *default_font = "Acorn8x8";
94 module_param(default_font, charp, 0);
95 MODULE_PARM_DESC(default_font, "Default font name");
96
97 /*
98  * Our access methods.
99  */
100 #define cyber2000fb_writel(val,reg,cfb) writel(val, (cfb)->regs + (reg))
101 #define cyber2000fb_writew(val,reg,cfb) writew(val, (cfb)->regs + (reg))
102 #define cyber2000fb_writeb(val,reg,cfb) writeb(val, (cfb)->regs + (reg))
103
104 #define cyber2000fb_readb(reg,cfb)      readb((cfb)->regs + (reg))
105
106 static inline void
107 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
108 {
109         cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
110 }
111
112 static inline void
113 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
114 {
115         cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
116 }
117
118 static inline unsigned int
119 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
120 {
121         cyber2000fb_writeb(reg, 0x3ce, cfb);
122         return cyber2000fb_readb(0x3cf, cfb);
123 }
124
125 static inline void
126 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
127 {
128         cyber2000fb_readb(0x3da, cfb);
129         cyber2000fb_writeb(reg, 0x3c0, cfb);
130         cyber2000fb_readb(0x3c1, cfb);
131         cyber2000fb_writeb(val, 0x3c0, cfb);
132 }
133
134 static inline void
135 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
136 {
137         cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
138 }
139
140 /* -------------------- Hardware specific routines ------------------------- */
141
142 /*
143  * Hardware Cyber2000 Acceleration
144  */
145 static void
146 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
147 {
148         struct cfb_info *cfb = (struct cfb_info *)info;
149         unsigned long dst, col;
150
151         if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
152                 cfb_fillrect(info, rect);
153                 return;
154         }
155
156         cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
157         cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
158         cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
159
160         col = rect->color;
161         if (cfb->fb.var.bits_per_pixel > 8)
162                 col = ((u32 *)cfb->fb.pseudo_palette)[col];
163         cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
164
165         dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
166         if (cfb->fb.var.bits_per_pixel == 24) {
167                 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
168                 dst *= 3;
169         }
170
171         cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
172         cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
173         cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
174         cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
175 }
176
177 static void
178 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
179 {
180         struct cfb_info *cfb = (struct cfb_info *)info;
181         unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
182         unsigned long src, dst;
183
184         if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
185                 cfb_copyarea(info, region);
186                 return;
187         }
188
189         cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
190         cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
191         cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
192
193         src = region->sx + region->sy * cfb->fb.var.xres_virtual;
194         dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
195
196         if (region->sx < region->dx) {
197                 src += region->width - 1;
198                 dst += region->width - 1;
199                 cmd |= CO_CMD_L_INC_LEFT;
200         }
201
202         if (region->sy < region->dy) {
203                 src += (region->height - 1) * cfb->fb.var.xres_virtual;
204                 dst += (region->height - 1) * cfb->fb.var.xres_virtual;
205                 cmd |= CO_CMD_L_INC_UP;
206         }
207
208         if (cfb->fb.var.bits_per_pixel == 24) {
209                 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
210                 src *= 3;
211                 dst *= 3;
212         }
213         cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
214         cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
215         cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
216         cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
217         cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
218                            CO_REG_CMD_H, cfb);
219 }
220
221 static void
222 cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image)
223 {
224 //      struct cfb_info *cfb = (struct cfb_info *)info;
225
226 //      if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
227                 cfb_imageblit(info, image);
228                 return;
229 //      }
230 }
231
232 static int cyber2000fb_sync(struct fb_info *info)
233 {
234         struct cfb_info *cfb = (struct cfb_info *)info;
235         int count = 100000;
236
237         if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
238                 return 0;
239
240         while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
241                 if (!count--) {
242                         debug_printf("accel_wait timed out\n");
243                         cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
244                         break;
245                 }
246                 udelay(1);
247         }
248         return 0;
249 }
250
251 /*
252  * ===========================================================================
253  */
254
255 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
256 {
257         u_int mask = (1 << bf->length) - 1;
258
259         return (val >> (16 - bf->length) & mask) << bf->offset;
260 }
261
262 /*
263  *    Set a single color register. Return != 0 for invalid regno.
264  */
265 static int
266 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
267                       u_int transp, struct fb_info *info)
268 {
269         struct cfb_info *cfb = (struct cfb_info *)info;
270         struct fb_var_screeninfo *var = &cfb->fb.var;
271         u32 pseudo_val;
272         int ret = 1;
273
274         switch (cfb->fb.fix.visual) {
275         default:
276                 return 1;
277
278         /*
279          * Pseudocolour:
280          *         8     8
281          * pixel --/--+--/-->  red lut  --> red dac
282          *            |  8
283          *            +--/--> green lut --> green dac
284          *            |  8
285          *            +--/-->  blue lut --> blue dac
286          */
287         case FB_VISUAL_PSEUDOCOLOR:
288                 if (regno >= NR_PALETTE)
289                         return 1;
290
291                 red >>= 8;
292                 green >>= 8;
293                 blue >>= 8;
294
295                 cfb->palette[regno].red   = red;
296                 cfb->palette[regno].green = green;
297                 cfb->palette[regno].blue  = blue;
298
299                 cyber2000fb_writeb(regno, 0x3c8, cfb);
300                 cyber2000fb_writeb(red, 0x3c9, cfb);
301                 cyber2000fb_writeb(green, 0x3c9, cfb);
302                 cyber2000fb_writeb(blue, 0x3c9, cfb);
303                 return 0;
304
305         /*
306          * Direct colour:
307          *          n     rl
308          *  pixel --/--+--/-->  red lut  --> red dac
309          *             |  gl
310          *             +--/--> green lut --> green dac
311          *             |  bl
312          *             +--/-->  blue lut --> blue dac
313          * n = bpp, rl = red length, gl = green length, bl = blue length
314          */
315         case FB_VISUAL_DIRECTCOLOR:
316                 red >>= 8;
317                 green >>= 8;
318                 blue >>= 8;
319
320                 if (var->green.length == 6 && regno < 64) {
321                         cfb->palette[regno << 2].green = green;
322
323                         /*
324                          * The 6 bits of the green component are applied
325                          * to the high 6 bits of the LUT.
326                          */
327                         cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
328                         cyber2000fb_writeb(cfb->palette[regno >> 1].red, 0x3c9, cfb);
329                         cyber2000fb_writeb(green, 0x3c9, cfb);
330                         cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 0x3c9, cfb);
331
332                         green = cfb->palette[regno << 3].green;
333
334                         ret = 0;
335                 }
336
337                 if (var->green.length >= 5 && regno < 32) {
338                         cfb->palette[regno << 3].red   = red;
339                         cfb->palette[regno << 3].green = green;
340                         cfb->palette[regno << 3].blue  = blue;
341
342                         /*
343                          * The 5 bits of each colour component are
344                          * applied to the high 5 bits of the LUT.
345                          */
346                         cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
347                         cyber2000fb_writeb(red, 0x3c9, cfb);
348                         cyber2000fb_writeb(green, 0x3c9, cfb);
349                         cyber2000fb_writeb(blue, 0x3c9, cfb);
350                         ret = 0;
351                 }
352
353                 if (var->green.length == 4 && regno < 16) {
354                         cfb->palette[regno << 4].red   = red;
355                         cfb->palette[regno << 4].green = green;
356                         cfb->palette[regno << 4].blue  = blue;
357
358                         /*
359                          * The 5 bits of each colour component are
360                          * applied to the high 5 bits of the LUT.
361                          */
362                         cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
363                         cyber2000fb_writeb(red, 0x3c9, cfb);
364                         cyber2000fb_writeb(green, 0x3c9, cfb);
365                         cyber2000fb_writeb(blue, 0x3c9, cfb);
366                         ret = 0;
367                 }
368
369                 /*
370                  * Since this is only used for the first 16 colours, we
371                  * don't have to care about overflowing for regno >= 32
372                  */
373                 pseudo_val = regno << var->red.offset |
374                              regno << var->green.offset |
375                              regno << var->blue.offset;
376                 break;
377
378         /*
379          * True colour:
380          *          n     rl
381          *  pixel --/--+--/--> red dac
382          *             |  gl
383          *             +--/--> green dac
384          *             |  bl
385          *             +--/--> blue dac
386          * n = bpp, rl = red length, gl = green length, bl = blue length
387          */
388         case FB_VISUAL_TRUECOLOR:
389                 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
390                 pseudo_val |= convert_bitfield(red, &var->red);
391                 pseudo_val |= convert_bitfield(green, &var->green);
392                 pseudo_val |= convert_bitfield(blue, &var->blue);
393                 break;
394         }
395
396         /*
397          * Now set our pseudo palette for the CFB16/24/32 drivers.
398          */
399         if (regno < 16)
400                 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
401
402         return ret;
403 }
404
405 struct par_info {
406         /*
407          * Hardware
408          */
409         u_char  clock_mult;
410         u_char  clock_div;
411         u_char  extseqmisc;
412         u_char  co_pixfmt;
413         u_char  crtc_ofl;
414         u_char  crtc[19];
415         u_int   width;
416         u_int   pitch;
417         u_int   fetch;
418
419         /*
420          * Other
421          */
422         u_char  ramdac;
423 };
424
425 static const u_char crtc_idx[] = {
426         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
427         0x08, 0x09,
428         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
429 };
430
431 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
432 {
433         unsigned int i;
434         unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
435
436         cyber2000fb_writeb(0x56, 0x3ce, cfb);
437         i = cyber2000fb_readb(0x3cf, cfb);
438         cyber2000fb_writeb(i | 4, 0x3cf, cfb);
439         cyber2000fb_writeb(val, 0x3c6, cfb);
440         cyber2000fb_writeb(i, 0x3cf, cfb);
441 }
442
443 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
444 {
445         u_int i;
446
447         /*
448          * Blank palette
449          */
450         for (i = 0; i < NR_PALETTE; i++) {
451                 cyber2000fb_writeb(i, 0x3c8, cfb);
452                 cyber2000fb_writeb(0, 0x3c9, cfb);
453                 cyber2000fb_writeb(0, 0x3c9, cfb);
454                 cyber2000fb_writeb(0, 0x3c9, cfb);
455         }
456
457         cyber2000fb_writeb(0xef, 0x3c2, cfb);
458         cyber2000_crtcw(0x11, 0x0b, cfb);
459         cyber2000_attrw(0x11, 0x00, cfb);
460
461         cyber2000_seqw(0x00, 0x01, cfb);
462         cyber2000_seqw(0x01, 0x01, cfb);
463         cyber2000_seqw(0x02, 0x0f, cfb);
464         cyber2000_seqw(0x03, 0x00, cfb);
465         cyber2000_seqw(0x04, 0x0e, cfb);
466         cyber2000_seqw(0x00, 0x03, cfb);
467
468         for (i = 0; i < sizeof(crtc_idx); i++)
469                 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
470
471         for (i = 0x0a; i < 0x10; i++)
472                 cyber2000_crtcw(i, 0, cfb);
473
474         cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
475         cyber2000_grphw(0x00, 0x00, cfb);
476         cyber2000_grphw(0x01, 0x00, cfb);
477         cyber2000_grphw(0x02, 0x00, cfb);
478         cyber2000_grphw(0x03, 0x00, cfb);
479         cyber2000_grphw(0x04, 0x00, cfb);
480         cyber2000_grphw(0x05, 0x60, cfb);
481         cyber2000_grphw(0x06, 0x05, cfb);
482         cyber2000_grphw(0x07, 0x0f, cfb);
483         cyber2000_grphw(0x08, 0xff, cfb);
484
485         /* Attribute controller registers */
486         for (i = 0; i < 16; i++)
487                 cyber2000_attrw(i, i, cfb);
488
489         cyber2000_attrw(0x10, 0x01, cfb);
490         cyber2000_attrw(0x11, 0x00, cfb);
491         cyber2000_attrw(0x12, 0x0f, cfb);
492         cyber2000_attrw(0x13, 0x00, cfb);
493         cyber2000_attrw(0x14, 0x00, cfb);
494
495         /* PLL registers */
496         cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
497         cyber2000_grphw(EXT_DCLK_DIV,  hw->clock_div, cfb);
498         cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
499         cyber2000_grphw(EXT_MCLK_DIV,  cfb->mclk_div, cfb);
500         cyber2000_grphw(0x90, 0x01, cfb);
501         cyber2000_grphw(0xb9, 0x80, cfb);
502         cyber2000_grphw(0xb9, 0x00, cfb);
503
504         cfb->ramdac_ctrl = hw->ramdac;
505         cyber2000fb_write_ramdac_ctrl(cfb);
506
507         cyber2000fb_writeb(0x20, 0x3c0, cfb);
508         cyber2000fb_writeb(0xff, 0x3c6, cfb);
509
510         cyber2000_grphw(0x14, hw->fetch, cfb);
511         cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
512                               ((hw->pitch >> 4) & 0x30), cfb);
513         cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
514
515         /*
516          * Set up accelerator registers
517          */
518         cyber2000fb_writew(hw->width,     CO_REG_SRC_WIDTH,  cfb);
519         cyber2000fb_writew(hw->width,     CO_REG_DEST_WIDTH, cfb);
520         cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
521 }
522
523 static inline int
524 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
525 {
526         u_int base = var->yoffset * var->xres_virtual + var->xoffset;
527
528         base *= var->bits_per_pixel;
529
530         /*
531          * Convert to bytes and shift two extra bits because DAC
532          * can only start on 4 byte aligned data.
533          */
534         base >>= 5;
535
536         if (base >= 1 << 20)
537                 return -EINVAL;
538
539         cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
540         cyber2000_crtcw(0x0c, base >> 8, cfb);
541         cyber2000_crtcw(0x0d, base, cfb);
542
543         return 0;
544 }
545
546 static int
547 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
548                         struct fb_var_screeninfo *var)
549 {
550         u_int Htotal, Hblankend, Hsyncend;
551         u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
552 #define ENCODE_BIT(v,b1,m,b2) (((v >> b1) & m) << b2)
553
554         hw->crtc[13] = hw->pitch;
555         hw->crtc[17] = 0xe3;
556         hw->crtc[14] = 0;
557         hw->crtc[8]  = 0;
558
559         Htotal      = var->xres + var->right_margin +
560                       var->hsync_len + var->left_margin;
561
562         if (Htotal > 2080)
563                 return -EINVAL;
564
565         hw->crtc[0] = (Htotal >> 3) - 5;
566         hw->crtc[1] = (var->xres >> 3) - 1;
567         hw->crtc[2] = var->xres >> 3;
568         hw->crtc[4] = (var->xres + var->right_margin) >> 3;
569
570         Hblankend   = (Htotal - 4*8) >> 3;
571
572         hw->crtc[3] = ENCODE_BIT(Hblankend,  0, 0x1f,  0) |
573                       ENCODE_BIT(1,          0, 0x01,  7);
574
575         Hsyncend    = (var->xres + var->right_margin + var->hsync_len) >> 3;
576
577         hw->crtc[5] = ENCODE_BIT(Hsyncend,   0, 0x1f,  0) |
578                       ENCODE_BIT(Hblankend,  5, 0x01,  7);
579
580         Vdispend    = var->yres - 1;
581         Vsyncstart  = var->yres + var->lower_margin;
582         Vsyncend    = var->yres + var->lower_margin + var->vsync_len;
583         Vtotal      = var->yres + var->lower_margin + var->vsync_len +
584                       var->upper_margin - 2;
585
586         if (Vtotal > 2047)
587                 return -EINVAL;
588
589         Vblankstart = var->yres + 6;
590         Vblankend   = Vtotal - 10;
591
592         hw->crtc[6]  = Vtotal;
593         hw->crtc[7]  = ENCODE_BIT(Vtotal,     8, 0x01,  0) |
594                         ENCODE_BIT(Vdispend,   8, 0x01,  1) |
595                         ENCODE_BIT(Vsyncstart, 8, 0x01,  2) |
596                         ENCODE_BIT(Vblankstart,8, 0x01,  3) |
597                         ENCODE_BIT(1,          0, 0x01,  4) |
598                         ENCODE_BIT(Vtotal,     9, 0x01,  5) |
599                         ENCODE_BIT(Vdispend,   9, 0x01,  6) |
600                         ENCODE_BIT(Vsyncstart, 9, 0x01,  7);
601         hw->crtc[9]  = ENCODE_BIT(0,          0, 0x1f,  0) |
602                         ENCODE_BIT(Vblankstart,9, 0x01,  5) |
603                         ENCODE_BIT(1,          0, 0x01,  6);
604         hw->crtc[10] = Vsyncstart;
605         hw->crtc[11] = ENCODE_BIT(Vsyncend,   0, 0x0f,  0) |
606                        ENCODE_BIT(1,          0, 0x01,  7);
607         hw->crtc[12] = Vdispend;
608         hw->crtc[15] = Vblankstart;
609         hw->crtc[16] = Vblankend;
610         hw->crtc[18] = 0xff;
611
612         /*
613          * overflow - graphics reg 0x11
614          * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
615          * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
616          */
617         hw->crtc_ofl =
618                 ENCODE_BIT(Vtotal,     10, 0x01,  0) |
619                 ENCODE_BIT(Vdispend,   10, 0x01,  1) |
620                 ENCODE_BIT(Vsyncstart, 10, 0x01,  2) |
621                 ENCODE_BIT(Vblankstart,10, 0x01,  3) |
622                 EXT_CRT_VRTOFL_LINECOMP10;
623
624         /* woody: set the interlaced bit... */
625         /* FIXME: what about doublescan? */
626         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
627                 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
628
629         return 0;
630 }
631
632 /*
633  * The following was discovered by a good monitor, bit twiddling, theorising
634  * and but mostly luck.  Strangely, it looks like everyone elses' PLL!
635  *
636  * Clock registers:
637  *   fclock = fpll / div2
638  *   fpll   = fref * mult / div1
639  * where:
640  *   fref = 14.318MHz (69842ps)
641  *   mult = reg0xb0.7:0
642  *   div1 = (reg0xb1.5:0 + 1)
643  *   div2 =  2^(reg0xb1.7:6)
644  *   fpll should be between 115 and 260 MHz
645  *  (8696ps and 3846ps)
646  */
647 static int
648 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
649                          struct fb_var_screeninfo *var)
650 {
651         u_long pll_ps = var->pixclock;
652         const u_long ref_ps = cfb->ref_ps;
653         u_int div2, t_div1, best_div1, best_mult;
654         int best_diff;
655         int vco;
656
657         /*
658          * Step 1:
659          *   find div2 such that 115MHz < fpll < 260MHz
660          *   and 0 <= div2 < 4
661          */
662         for (div2 = 0; div2 < 4; div2++) {
663                 u_long new_pll;
664
665                 new_pll = pll_ps / cfb->divisors[div2];
666                 if (8696 > new_pll && new_pll > 3846) {
667                         pll_ps = new_pll;
668                         break;
669                 }
670         }
671
672         if (div2 == 4)
673                 return -EINVAL;
674
675         /*
676          * Step 2:
677          *  Given pll_ps and ref_ps, find:
678          *    pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
679          *  where { 1 < best_div1 < 32, 1 < best_mult < 256 }
680          *    pll_ps_calc = best_div1 / (ref_ps * best_mult)
681          */
682         best_diff = 0x7fffffff;
683         best_mult = 32;
684         best_div1 = 255;
685         for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) {
686                 u_int rr, t_mult, t_pll_ps;
687                 int diff;
688
689                 /*
690                  * Find the multiplier for this divisor
691                  */
692                 rr = ref_ps * t_div1;
693                 t_mult = (rr + pll_ps / 2) / pll_ps;
694
695                 /*
696                  * Is the multiplier within the correct range?
697                  */
698                 if (t_mult > 256 || t_mult < 2)
699                         continue;
700
701                 /*
702                  * Calculate the actual clock period from this multiplier
703                  * and divisor, and estimate the error.
704                  */
705                 t_pll_ps = (rr + t_mult / 2) / t_mult;
706                 diff = pll_ps - t_pll_ps;
707                 if (diff < 0)
708                         diff = -diff;
709
710                 if (diff < best_diff) {
711                         best_diff = diff;
712                         best_mult = t_mult;
713                         best_div1 = t_div1;
714                 }
715
716                 /*
717                  * If we hit an exact value, there is no point in continuing.
718                  */
719                 if (diff == 0)
720                         break;
721         }
722
723         /*
724          * Step 3:
725          *  combine values
726          */
727         hw->clock_mult = best_mult - 1;
728         hw->clock_div  = div2 << 6 | (best_div1 - 1);
729
730         vco = ref_ps * best_div1 / best_mult;
731         if ((ref_ps == 40690) && (vco < 5556))
732                 /* Set VFSEL when VCO > 180MHz (5.556 ps). */
733                 hw->clock_div |= EXT_DCLK_DIV_VFSEL;
734
735         return 0;
736 }
737
738 /*
739  *    Set the User Defined Part of the Display
740  */
741 static int
742 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
743 {
744         struct cfb_info *cfb = (struct cfb_info *)info;
745         struct par_info hw;
746         unsigned int mem;
747         int err;
748
749         var->transp.msb_right   = 0;
750         var->red.msb_right      = 0;
751         var->green.msb_right    = 0;
752         var->blue.msb_right     = 0;
753
754         switch (var->bits_per_pixel) {
755         case 8: /* PSEUDOCOLOUR, 256 */
756                 var->transp.offset      = 0;
757                 var->transp.length      = 0;
758                 var->red.offset         = 0;
759                 var->red.length         = 8;
760                 var->green.offset       = 0;
761                 var->green.length       = 8;
762                 var->blue.offset        = 0;
763                 var->blue.length        = 8;
764                 break;
765
766         case 16:/* DIRECTCOLOUR, 64k or 32k */
767                 switch (var->green.length) {
768                 case 6: /* RGB565, 64k */
769                         var->transp.offset      = 0;
770                         var->transp.length      = 0;
771                         var->red.offset         = 11;
772                         var->red.length         = 5;
773                         var->green.offset       = 5;
774                         var->green.length       = 6;
775                         var->blue.offset        = 0;
776                         var->blue.length        = 5;
777                         break;
778
779                 default:
780                 case 5: /* RGB555, 32k */
781                         var->transp.offset      = 0;
782                         var->transp.length      = 0;
783                         var->red.offset         = 10;
784                         var->red.length         = 5;
785                         var->green.offset       = 5;
786                         var->green.length       = 5;
787                         var->blue.offset        = 0;
788                         var->blue.length        = 5;
789                         break;
790
791                 case 4: /* RGB444, 4k + transparency? */
792                         var->transp.offset      = 12;
793                         var->transp.length      = 4;
794                         var->red.offset         = 8;
795                         var->red.length         = 4;
796                         var->green.offset       = 4;
797                         var->green.length       = 4;
798                         var->blue.offset        = 0;
799                         var->blue.length        = 4;
800                         break;
801                 }
802                 break;
803
804         case 24:/* TRUECOLOUR, 16m */
805                 var->transp.offset      = 0;
806                 var->transp.length      = 0;
807                 var->red.offset         = 16;
808                 var->red.length         = 8;
809                 var->green.offset       = 8;
810                 var->green.length       = 8;
811                 var->blue.offset        = 0;
812                 var->blue.length        = 8;
813                 break;
814
815         case 32:/* TRUECOLOUR, 16m */
816                 var->transp.offset      = 24;
817                 var->transp.length      = 8;
818                 var->red.offset         = 16;
819                 var->red.length         = 8;
820                 var->green.offset       = 8;
821                 var->green.length       = 8;
822                 var->blue.offset        = 0;
823                 var->blue.length        = 8;
824                 break;
825
826         default:
827                 return -EINVAL;
828         }
829
830         mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
831         if (mem > cfb->fb.fix.smem_len)
832                 var->yres_virtual = cfb->fb.fix.smem_len * 8 /
833                         (var->bits_per_pixel * var->xres_virtual);
834
835         if (var->yres > var->yres_virtual)
836                 var->yres = var->yres_virtual;
837         if (var->xres > var->xres_virtual)
838                 var->xres = var->xres_virtual;
839
840         err = cyber2000fb_decode_clock(&hw, cfb, var);
841         if (err)
842                 return err;
843
844         err = cyber2000fb_decode_crtc(&hw, cfb, var);
845         if (err)
846                 return err;
847
848         return 0;
849 }
850
851 static int cyber2000fb_set_par(struct fb_info *info)
852 {
853         struct cfb_info *cfb = (struct cfb_info *)info;
854         struct fb_var_screeninfo *var = &cfb->fb.var;
855         struct par_info hw;
856         unsigned int mem;
857
858         hw.width = var->xres_virtual;
859         hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
860
861         switch (var->bits_per_pixel) {
862         case 8:
863                 hw.co_pixfmt            = CO_PIXFMT_8BPP;
864                 hw.pitch                = hw.width >> 3;
865                 hw.extseqmisc           = EXT_SEQ_MISC_8;
866                 break;
867
868         case 16:
869                 hw.co_pixfmt            = CO_PIXFMT_16BPP;
870                 hw.pitch                = hw.width >> 2;
871
872                 switch (var->green.length) {
873                 case 6: /* RGB565, 64k */
874                         hw.extseqmisc   = EXT_SEQ_MISC_16_RGB565;
875                         break;
876                 case 5: /* RGB555, 32k */
877                         hw.extseqmisc   = EXT_SEQ_MISC_16_RGB555;
878                         break;
879                 case 4: /* RGB444, 4k + transparency? */
880                         hw.extseqmisc   = EXT_SEQ_MISC_16_RGB444;
881                         break;
882                 default:
883                         BUG();
884                 }
885         case 24:/* TRUECOLOUR, 16m */
886                 hw.co_pixfmt            = CO_PIXFMT_24BPP;
887                 hw.width                *= 3;
888                 hw.pitch                = hw.width >> 3;
889                 hw.ramdac               |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
890                 hw.extseqmisc           = EXT_SEQ_MISC_24_RGB888;
891                 break;
892
893         case 32:/* TRUECOLOUR, 16m */
894                 hw.co_pixfmt            = CO_PIXFMT_32BPP;
895                 hw.pitch                = hw.width >> 1;
896                 hw.ramdac               |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
897                 hw.extseqmisc           = EXT_SEQ_MISC_32;
898                 break;
899
900         default:
901                 BUG();
902         }
903
904         /*
905          * Sigh, this is absolutely disgusting, but caused by
906          * the way the fbcon developers want to separate out
907          * the "checking" and the "setting" of the video mode.
908          *
909          * If the mode is not suitable for the hardware here,
910          * we can't prevent it being set by returning an error.
911          *
912          * In theory, since NetWinders contain just one VGA card,
913          * we should never end up hitting this problem.
914          */
915         BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
916         BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
917
918         hw.width -= 1;
919         hw.fetch = hw.pitch;
920         if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
921                 hw.fetch <<= 1;
922         hw.fetch += 1;
923
924         cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
925
926         /*
927          * Same here - if the size of the video mode exceeds the
928          * available RAM, we can't prevent this mode being set.
929          *
930          * In theory, since NetWinders contain just one VGA card,
931          * we should never end up hitting this problem.
932          */
933         mem = cfb->fb.fix.line_length * var->yres_virtual;
934         BUG_ON(mem > cfb->fb.fix.smem_len);
935
936         /*
937          * 8bpp displays are always pseudo colour.  16bpp and above
938          * are direct colour or true colour, depending on whether
939          * the RAMDAC palettes are bypassed.  (Direct colour has
940          * palettes, true colour does not.)
941          */
942         if (var->bits_per_pixel == 8)
943                 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
944         else if (hw.ramdac & RAMDAC_BYPASS)
945                 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
946         else
947                 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
948
949         cyber2000fb_set_timing(cfb, &hw);
950         cyber2000fb_update_start(cfb, var);
951
952         return 0;
953 }
954
955
956 /*
957  *    Pan or Wrap the Display
958  */
959 static int
960 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
961 {
962         struct cfb_info *cfb = (struct cfb_info *)info;
963
964         if (cyber2000fb_update_start(cfb, var))
965                 return -EINVAL;
966
967         cfb->fb.var.xoffset = var->xoffset;
968         cfb->fb.var.yoffset = var->yoffset;
969
970         if (var->vmode & FB_VMODE_YWRAP) {
971                 cfb->fb.var.vmode |= FB_VMODE_YWRAP;
972         } else {
973                 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
974         }
975
976         return 0;
977 }
978
979 /*
980  *    (Un)Blank the display.
981  *
982  *  Blank the screen if blank_mode != 0, else unblank. If
983  *  blank == NULL then the caller blanks by setting the CLUT
984  *  (Color Look Up Table) to all black. Return 0 if blanking
985  *  succeeded, != 0 if un-/blanking failed due to e.g. a
986  *  video mode which doesn't support it. Implements VESA
987  *  suspend and powerdown modes on hardware that supports
988  *  disabling hsync/vsync:
989  *    blank_mode == 2: suspend vsync
990  *    blank_mode == 3: suspend hsync
991  *    blank_mode == 4: powerdown
992  *
993  *  wms...Enable VESA DMPS compatible powerdown mode
994  *  run "setterm -powersave powerdown" to take advantage
995  */
996 static int cyber2000fb_blank(int blank, struct fb_info *info)
997 {
998         struct cfb_info *cfb = (struct cfb_info *)info;
999         unsigned int sync = 0;
1000         int i;
1001
1002         switch (blank) {
1003         case FB_BLANK_POWERDOWN:        /* powerdown - both sync lines down */
1004                 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
1005                 break;  
1006         case FB_BLANK_HSYNC_SUSPEND:    /* hsync off */
1007                 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
1008                 break;  
1009         case FB_BLANK_VSYNC_SUSPEND:    /* vsync off */
1010                 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
1011                 break;
1012         case FB_BLANK_NORMAL:           /* soft blank */
1013         default: /* unblank */
1014                 break;
1015         }
1016
1017         cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
1018
1019         if (blank <= 1) {
1020                 /* turn on ramdacs */
1021                 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
1022                 cyber2000fb_write_ramdac_ctrl(cfb);
1023         }
1024
1025         /*
1026          * Soft blank/unblank the display.
1027          */
1028         if (blank) {    /* soft blank */
1029                 for (i = 0; i < NR_PALETTE; i++) {
1030                         cyber2000fb_writeb(i, 0x3c8, cfb);
1031                         cyber2000fb_writeb(0, 0x3c9, cfb);
1032                         cyber2000fb_writeb(0, 0x3c9, cfb);
1033                         cyber2000fb_writeb(0, 0x3c9, cfb);
1034                 }
1035         } else {        /* unblank */
1036                 for (i = 0; i < NR_PALETTE; i++) {
1037                         cyber2000fb_writeb(i, 0x3c8, cfb);
1038                         cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
1039                         cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
1040                         cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
1041                 }
1042         }
1043
1044         if (blank >= 2) {
1045                 /* turn off ramdacs */
1046                 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN;
1047                 cyber2000fb_write_ramdac_ctrl(cfb);
1048         }
1049
1050         return 0;
1051 }
1052
1053 static struct fb_ops cyber2000fb_ops = {
1054         .owner          = THIS_MODULE,
1055         .fb_check_var   = cyber2000fb_check_var,
1056         .fb_set_par     = cyber2000fb_set_par,
1057         .fb_setcolreg   = cyber2000fb_setcolreg,
1058         .fb_blank       = cyber2000fb_blank,
1059         .fb_pan_display = cyber2000fb_pan_display,
1060         .fb_fillrect    = cyber2000fb_fillrect,
1061         .fb_copyarea    = cyber2000fb_copyarea,
1062         .fb_imageblit   = cyber2000fb_imageblit,
1063         .fb_sync        = cyber2000fb_sync,
1064 };
1065
1066 /*
1067  * This is the only "static" reference to the internal data structures
1068  * of this driver.  It is here solely at the moment to support the other
1069  * CyberPro modules external to this driver.
1070  */
1071 static struct cfb_info          *int_cfb_info;
1072
1073 /*
1074  * Enable access to the extended registers
1075  */
1076 void cyber2000fb_enable_extregs(struct cfb_info *cfb)
1077 {
1078         cfb->func_use_count += 1;
1079
1080         if (cfb->func_use_count == 1) {
1081                 int old;
1082
1083                 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1084                 old |= EXT_FUNC_CTL_EXTREGENBL;
1085                 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1086         }
1087 }
1088
1089 /*
1090  * Disable access to the extended registers
1091  */
1092 void cyber2000fb_disable_extregs(struct cfb_info *cfb)
1093 {
1094         if (cfb->func_use_count == 1) {
1095                 int old;
1096
1097                 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1098                 old &= ~EXT_FUNC_CTL_EXTREGENBL;
1099                 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1100         }
1101
1102         if (cfb->func_use_count == 0)
1103                 printk(KERN_ERR "disable_extregs: count = 0\n");
1104         else
1105                 cfb->func_use_count -= 1;
1106 }
1107
1108 void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var)
1109 {
1110         memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo));
1111 }
1112
1113 /*
1114  * Attach a capture/tv driver to the core CyberX0X0 driver.
1115  */
1116 int cyber2000fb_attach(struct cyberpro_info *info, int idx)
1117 {
1118         if (int_cfb_info != NULL) {
1119                 info->dev             = int_cfb_info->dev;
1120                 info->regs            = int_cfb_info->regs;
1121                 info->fb              = int_cfb_info->fb.screen_base;
1122                 info->fb_size         = int_cfb_info->fb.fix.smem_len;
1123                 info->enable_extregs  = cyber2000fb_enable_extregs;
1124                 info->disable_extregs = cyber2000fb_disable_extregs;
1125                 info->info            = int_cfb_info;
1126
1127                 strlcpy(info->dev_name, int_cfb_info->fb.fix.id, sizeof(info->dev_name));
1128         }
1129
1130         return int_cfb_info != NULL;
1131 }
1132
1133 /*
1134  * Detach a capture/tv driver from the core CyberX0X0 driver.
1135  */
1136 void cyber2000fb_detach(int idx)
1137 {
1138 }
1139
1140 EXPORT_SYMBOL(cyber2000fb_attach);
1141 EXPORT_SYMBOL(cyber2000fb_detach);
1142 EXPORT_SYMBOL(cyber2000fb_enable_extregs);
1143 EXPORT_SYMBOL(cyber2000fb_disable_extregs);
1144 EXPORT_SYMBOL(cyber2000fb_get_fb_var);
1145
1146 /*
1147  * These parameters give
1148  * 640x480, hsync 31.5kHz, vsync 60Hz
1149  */
1150 static struct fb_videomode __devinitdata cyber2000fb_default_mode = {
1151         .refresh        = 60,
1152         .xres           = 640,
1153         .yres           = 480,
1154         .pixclock       = 39722,
1155         .left_margin    = 56,
1156         .right_margin   = 16,
1157         .upper_margin   = 34,
1158         .lower_margin   = 9,
1159         .hsync_len      = 88,
1160         .vsync_len      = 2,
1161         .sync           = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1162         .vmode          = FB_VMODE_NONINTERLACED
1163 };
1164
1165 static char igs_regs[] = {
1166         EXT_CRT_IRQ,            0,
1167         EXT_CRT_TEST,           0,
1168         EXT_SYNC_CTL,           0,
1169         EXT_SEG_WRITE_PTR,      0,
1170         EXT_SEG_READ_PTR,       0,
1171         EXT_BIU_MISC,           EXT_BIU_MISC_LIN_ENABLE |
1172                                 EXT_BIU_MISC_COP_ENABLE |
1173                                 EXT_BIU_MISC_COP_BFC,
1174         EXT_FUNC_CTL,           0,
1175         CURS_H_START,           0,
1176         CURS_H_START + 1,       0,
1177         CURS_H_PRESET,          0,
1178         CURS_V_START,           0,
1179         CURS_V_START + 1,       0,
1180         CURS_V_PRESET,          0,
1181         CURS_CTL,               0,
1182         EXT_ATTRIB_CTL,         EXT_ATTRIB_CTL_EXT,
1183         EXT_OVERSCAN_RED,       0,
1184         EXT_OVERSCAN_GREEN,     0,
1185         EXT_OVERSCAN_BLUE,      0,
1186
1187         /* some of these are questionable when we have a BIOS */
1188         EXT_MEM_CTL0,           EXT_MEM_CTL0_7CLK |
1189                                 EXT_MEM_CTL0_RAS_1 |
1190                                 EXT_MEM_CTL0_MULTCAS,
1191         EXT_HIDDEN_CTL1,        0x30,
1192         EXT_FIFO_CTL,           0x0b,
1193         EXT_FIFO_CTL + 1,       0x17,
1194         0x76,                   0x00,
1195         EXT_HIDDEN_CTL4,        0xc8
1196 };
1197
1198 /*
1199  * Initialise the CyberPro hardware.  On the CyberPro5XXXX,
1200  * ensure that we're using the correct PLL (5XXX's may be
1201  * programmed to use an additional set of PLLs.)
1202  */
1203 static void cyberpro_init_hw(struct cfb_info *cfb)
1204 {
1205         int i;
1206
1207         for (i = 0; i < sizeof(igs_regs); i += 2)
1208                 cyber2000_grphw(igs_regs[i], igs_regs[i+1], cfb);
1209
1210         if (cfb->id == ID_CYBERPRO_5000) {
1211                 unsigned char val;
1212                 cyber2000fb_writeb(0xba, 0x3ce, cfb);
1213                 val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
1214                 cyber2000fb_writeb(val, 0x3cf, cfb);
1215         }
1216 }
1217
1218 static struct cfb_info * __devinit
1219 cyberpro_alloc_fb_info(unsigned int id, char *name)
1220 {
1221         struct cfb_info *cfb;
1222
1223         cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL);
1224         if (!cfb)
1225                 return NULL;
1226
1227
1228         cfb->id                 = id;
1229
1230         if (id == ID_CYBERPRO_5000)
1231                 cfb->ref_ps     = 40690; // 24.576 MHz
1232         else
1233                 cfb->ref_ps     = 69842; // 14.31818 MHz (69841?)
1234
1235         cfb->divisors[0]        = 1;
1236         cfb->divisors[1]        = 2;
1237         cfb->divisors[2]        = 4;
1238
1239         if (id == ID_CYBERPRO_2000)
1240                 cfb->divisors[3] = 8;
1241         else
1242                 cfb->divisors[3] = 6;
1243
1244         strcpy(cfb->fb.fix.id, name);
1245
1246         cfb->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1247         cfb->fb.fix.type_aux    = 0;
1248         cfb->fb.fix.xpanstep    = 0;
1249         cfb->fb.fix.ypanstep    = 1;
1250         cfb->fb.fix.ywrapstep   = 0;
1251
1252         switch (id) {
1253         case ID_IGA_1682:
1254                 cfb->fb.fix.accel = 0;
1255                 break;
1256
1257         case ID_CYBERPRO_2000:
1258                 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
1259                 break;
1260
1261         case ID_CYBERPRO_2010:
1262                 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
1263                 break;
1264
1265         case ID_CYBERPRO_5000:
1266                 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
1267                 break;
1268         }
1269
1270         cfb->fb.var.nonstd      = 0;
1271         cfb->fb.var.activate    = FB_ACTIVATE_NOW;
1272         cfb->fb.var.height      = -1;
1273         cfb->fb.var.width       = -1;
1274         cfb->fb.var.accel_flags = FB_ACCELF_TEXT;
1275
1276         cfb->fb.fbops           = &cyber2000fb_ops;
1277         cfb->fb.flags           = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1278         cfb->fb.pseudo_palette  = cfb->pseudo_palette;
1279
1280         fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
1281
1282         return cfb;
1283 }
1284
1285 static void
1286 cyberpro_free_fb_info(struct cfb_info *cfb)
1287 {
1288         if (cfb) {
1289                 /*
1290                  * Free the colourmap
1291                  */
1292                 fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
1293
1294                 kfree(cfb);
1295         }
1296 }
1297
1298 /*
1299  * Parse Cyber2000fb options.  Usage:
1300  *  video=cyber2000:font:fontname
1301  */
1302 #ifndef MODULE
1303 static int
1304 cyber2000fb_setup(char *options)
1305 {
1306         char *opt;
1307
1308         if (!options || !*options)
1309                 return 0;
1310
1311         while ((opt = strsep(&options, ",")) != NULL) {
1312                 if (!*opt)
1313                         continue;
1314
1315                 if (strncmp(opt, "font:", 5) == 0) {
1316                         static char default_font_storage[40];
1317
1318                         strlcpy(default_font_storage, opt + 5, sizeof(default_font_storage));
1319                         default_font = default_font_storage;
1320                         continue;
1321                 }
1322
1323                 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
1324         }
1325         return 0;
1326 }
1327 #endif  /*  MODULE  */
1328
1329 /*
1330  * The CyberPro chips can be placed on many different bus types.
1331  * This probe function is common to all bus types.  The bus-specific
1332  * probe function is expected to have:
1333  *  - enabled access to the linear memory region
1334  *  - memory mapped access to the registers
1335  *  - initialised mem_ctl1 and mem_ctl2 appropriately.
1336  */
1337 static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
1338 {
1339         u_long smem_size;
1340         u_int h_sync, v_sync;
1341         int err;
1342
1343         cyberpro_init_hw(cfb);
1344
1345         /*
1346          * Get the video RAM size and width from the VGA register.
1347          * This should have been already initialised by the BIOS,
1348          * but if it's garbage, claim default 1MB VRAM (woody)
1349          */
1350         cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
1351         cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
1352
1353         /*
1354          * Determine the size of the memory.
1355          */
1356         switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
1357         case MEM_CTL2_SIZE_4MB: smem_size = 0x00400000; break;
1358         case MEM_CTL2_SIZE_2MB: smem_size = 0x00200000; break;
1359         case MEM_CTL2_SIZE_1MB: smem_size = 0x00100000; break;
1360         default:                smem_size = 0x00100000; break;
1361         }
1362
1363         cfb->fb.fix.smem_len   = smem_size;
1364         cfb->fb.fix.mmio_len   = MMIO_SIZE;
1365         cfb->fb.screen_base    = cfb->region;
1366
1367         err = -EINVAL;
1368         if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
1369                           &cyber2000fb_default_mode, 8)) {
1370                 printk("%s: no valid mode found\n", cfb->fb.fix.id);
1371                 goto failed;
1372         }
1373
1374         cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
1375                         (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
1376
1377         if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
1378                 cfb->fb.var.yres_virtual = cfb->fb.var.yres;
1379
1380 //      fb_set_var(&cfb->fb.var, -1, &cfb->fb);
1381
1382         /*
1383          * Calculate the hsync and vsync frequencies.  Note that
1384          * we split the 1e12 constant up so that we can preserve
1385          * the precision and fit the results into 32-bit registers.
1386          *  (1953125000 * 512 = 1e12)
1387          */
1388         h_sync = 1953125000 / cfb->fb.var.pixclock;
1389         h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
1390                  cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
1391         v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
1392                  cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
1393
1394         printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
1395                 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
1396                 cfb->fb.var.xres, cfb->fb.var.yres,
1397                 h_sync / 1000, h_sync % 1000, v_sync);
1398
1399         if (cfb->dev)
1400                 cfb->fb.device = &cfb->dev->dev;
1401         err = register_framebuffer(&cfb->fb);
1402
1403 failed:
1404         return err;
1405 }
1406
1407 static void cyberpro_common_resume(struct cfb_info *cfb)
1408 {
1409         cyberpro_init_hw(cfb);
1410
1411         /*
1412          * Reprogram the MEM_CTL1 and MEM_CTL2 registers
1413          */
1414         cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
1415         cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
1416
1417         /*
1418          * Restore the old video mode and the palette.
1419          * We also need to tell fbcon to redraw the console.
1420          */
1421         cyber2000fb_set_par(&cfb->fb);
1422 }
1423
1424 #ifdef CONFIG_ARCH_SHARK
1425
1426 #include <asm/arch/hardware.h>
1427
1428 static int __devinit
1429 cyberpro_vl_probe(void)
1430 {
1431         struct cfb_info *cfb;
1432         int err = -ENOMEM;
1433
1434         if (!request_mem_region(FB_START,FB_SIZE,"CyberPro2010")) return err;
1435
1436         cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010");
1437         if (!cfb)
1438                 goto failed_release;
1439
1440         cfb->dev = NULL;
1441         cfb->region = ioremap(FB_START,FB_SIZE);
1442         if (!cfb->region)
1443                 goto failed_ioremap;
1444
1445         cfb->regs = cfb->region + MMIO_OFFSET;
1446         cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET;
1447         cfb->fb.fix.smem_start = FB_START;
1448
1449         /*
1450          * Bring up the hardware.  This is expected to enable access
1451          * to the linear memory region, and allow access to the memory
1452          * mapped registers.  Also, mem_ctl1 and mem_ctl2 must be
1453          * initialised.
1454          */
1455         cyber2000fb_writeb(0x18, 0x46e8, cfb);
1456         cyber2000fb_writeb(0x01, 0x102, cfb);
1457         cyber2000fb_writeb(0x08, 0x46e8, cfb);
1458         cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb);
1459         cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb);
1460
1461         cfb->mclk_mult = 0xdb;
1462         cfb->mclk_div  = 0x54;
1463
1464         err = cyberpro_common_probe(cfb);
1465         if (err)
1466                 goto failed;
1467
1468         if (int_cfb_info == NULL)
1469                 int_cfb_info = cfb;
1470
1471         return 0;
1472
1473 failed:
1474         iounmap(cfb->region);
1475 failed_ioremap:
1476         cyberpro_free_fb_info(cfb);
1477 failed_release:
1478         release_mem_region(FB_START,FB_SIZE);
1479
1480         return err;
1481 }
1482 #endif /* CONFIG_ARCH_SHARK */
1483
1484 /*
1485  * PCI specific support.
1486  */
1487 #ifdef CONFIG_PCI
1488 /*
1489  * We need to wake up the CyberPro, and make sure its in linear memory
1490  * mode.  Unfortunately, this is specific to the platform and card that
1491  * we are running on.
1492  *
1493  * On x86 and ARM, should we be initialising the CyberPro first via the
1494  * IO registers, and then the MMIO registers to catch all cases?  Can we
1495  * end up in the situation where the chip is in MMIO mode, but not awake
1496  * on an x86 system?
1497  */
1498 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
1499 {
1500         unsigned char val;
1501
1502 #if defined(__sparc_v9__)
1503 #error "You lose, consult DaveM."
1504 #elif defined(__sparc__)
1505         /*
1506          * SPARC does not have an "outb" instruction, so we generate
1507          * I/O cycles storing into a reserved memory space at
1508          * physical address 0x3000000
1509          */
1510         unsigned char __iomem *iop;
1511
1512         iop = ioremap(0x3000000, 0x5000);
1513         if (iop == NULL) {
1514                 prom_printf("iga5000: cannot map I/O\n");
1515                 return -ENOMEM;
1516         }
1517
1518         writeb(0x18, iop + 0x46e8);
1519         writeb(0x01, iop + 0x102);
1520         writeb(0x08, iop + 0x46e8);
1521         writeb(EXT_BIU_MISC, iop + 0x3ce);
1522         writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
1523
1524         iounmap(iop);
1525 #else
1526         /*
1527          * Most other machine types are "normal", so
1528          * we use the standard IO-based wakeup.
1529          */
1530         outb(0x18, 0x46e8);
1531         outb(0x01, 0x102);
1532         outb(0x08, 0x46e8);
1533         outb(EXT_BIU_MISC, 0x3ce);
1534         outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
1535 #endif
1536
1537         /*
1538          * Allow the CyberPro to accept PCI burst accesses
1539          */
1540         if (cfb->id == ID_CYBERPRO_2010) {
1541                 printk(KERN_INFO "%s: NOT enabling PCI bursts\n", cfb->fb.fix.id);
1542         } else {
1543                 val = cyber2000_grphr(EXT_BUS_CTL, cfb);
1544                 if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
1545                         printk(KERN_INFO "%s: enabling PCI bursts\n",
1546                                 cfb->fb.fix.id);
1547
1548                         val |= EXT_BUS_CTL_PCIBURST_WRITE;
1549
1550                         if (cfb->id == ID_CYBERPRO_5000)
1551                                 val |= EXT_BUS_CTL_PCIBURST_READ;
1552
1553                         cyber2000_grphw(EXT_BUS_CTL, val, cfb);
1554                 }
1555         }
1556
1557         return 0;
1558 }
1559
1560 static int __devinit
1561 cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1562 {
1563         struct cfb_info *cfb;
1564         char name[16];
1565         int err;
1566
1567         sprintf(name, "CyberPro%4X", id->device);
1568
1569         err = pci_enable_device(dev);
1570         if (err)
1571                 return err;
1572
1573         err = pci_request_regions(dev, name);
1574         if (err)
1575                 return err;
1576
1577         err = -ENOMEM;
1578         cfb = cyberpro_alloc_fb_info(id->driver_data, name);
1579         if (!cfb)
1580                 goto failed_release;
1581
1582         cfb->dev = dev;
1583         cfb->region = ioremap(pci_resource_start(dev, 0),
1584                               pci_resource_len(dev, 0));
1585         if (!cfb->region)
1586                 goto failed_ioremap;
1587
1588         cfb->regs = cfb->region + MMIO_OFFSET;
1589         cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
1590         cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
1591
1592         /*
1593          * Bring up the hardware.  This is expected to enable access
1594          * to the linear memory region, and allow access to the memory
1595          * mapped registers.  Also, mem_ctl1 and mem_ctl2 must be
1596          * initialised.
1597          */
1598         err = cyberpro_pci_enable_mmio(cfb);
1599         if (err)
1600                 goto failed;
1601
1602         /*
1603          * Use MCLK from BIOS. FIXME: what about hotplug?
1604          */
1605         cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
1606         cfb->mclk_div  = cyber2000_grphr(EXT_MCLK_DIV, cfb);
1607
1608 #ifdef __arm__
1609         /*
1610          * MCLK on the NetWinder and the Shark is fixed at 75MHz
1611          */
1612         if (machine_is_netwinder()) {
1613                 cfb->mclk_mult = 0xdb;
1614                 cfb->mclk_div  = 0x54;
1615         }
1616 #endif
1617
1618         err = cyberpro_common_probe(cfb);
1619         if (err)
1620                 goto failed;
1621
1622         /*
1623          * Our driver data
1624          */
1625         pci_set_drvdata(dev, cfb);
1626         if (int_cfb_info == NULL)
1627                 int_cfb_info = cfb;
1628
1629         return 0;
1630
1631 failed:
1632         iounmap(cfb->region);
1633 failed_ioremap:
1634         cyberpro_free_fb_info(cfb);
1635 failed_release:
1636         pci_release_regions(dev);
1637
1638         return err;
1639 }
1640
1641 static void __devexit cyberpro_pci_remove(struct pci_dev *dev)
1642 {
1643         struct cfb_info *cfb = pci_get_drvdata(dev);
1644
1645         if (cfb) {
1646                 /*
1647                  * If unregister_framebuffer fails, then
1648                  * we will be leaving hooks that could cause
1649                  * oopsen laying around.
1650                  */
1651                 if (unregister_framebuffer(&cfb->fb))
1652                         printk(KERN_WARNING "%s: danger Will Robinson, "
1653                                 "danger danger!  Oopsen imminent!\n",
1654                                 cfb->fb.fix.id);
1655                 iounmap(cfb->region);
1656                 cyberpro_free_fb_info(cfb);
1657
1658                 /*
1659                  * Ensure that the driver data is no longer
1660                  * valid.
1661                  */
1662                 pci_set_drvdata(dev, NULL);
1663                 if (cfb == int_cfb_info)
1664                         int_cfb_info = NULL;
1665
1666                 pci_release_regions(dev);
1667         }
1668 }
1669
1670 static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state)
1671 {
1672         return 0;
1673 }
1674
1675 /*
1676  * Re-initialise the CyberPro hardware
1677  */
1678 static int cyberpro_pci_resume(struct pci_dev *dev)
1679 {
1680         struct cfb_info *cfb = pci_get_drvdata(dev);
1681
1682         if (cfb) {
1683                 cyberpro_pci_enable_mmio(cfb);
1684                 cyberpro_common_resume(cfb);
1685         }
1686
1687         return 0;
1688 }
1689
1690 static struct pci_device_id cyberpro_pci_table[] = {
1691 //      Not yet
1692 //      { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
1693 //              PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
1694         { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
1695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
1696         { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
1697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
1698         { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
1699                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
1700         { 0, }
1701 };
1702
1703 MODULE_DEVICE_TABLE(pci,cyberpro_pci_table);
1704
1705 static struct pci_driver cyberpro_driver = {
1706         .name           = "CyberPro",
1707         .probe          = cyberpro_pci_probe,
1708         .remove         = __devexit_p(cyberpro_pci_remove),
1709         .suspend        = cyberpro_pci_suspend,
1710         .resume         = cyberpro_pci_resume,
1711         .id_table       = cyberpro_pci_table
1712 };
1713 #endif
1714
1715 /*
1716  * I don't think we can use the "module_init" stuff here because
1717  * the fbcon stuff may not be initialised yet.  Hence the #ifdef
1718  * around module_init.
1719  *
1720  * Tony: "module_init" is now required
1721  */
1722 static int __init cyber2000fb_init(void)
1723 {
1724         int ret = -1, err;
1725
1726 #ifndef MODULE
1727         char *option = NULL;
1728
1729         if (fb_get_options("cyber2000fb", &option))
1730                 return -ENODEV;
1731         cyber2000fb_setup(option);
1732 #endif
1733
1734 #ifdef CONFIG_ARCH_SHARK
1735         err = cyberpro_vl_probe();
1736         if (!err) {
1737                 ret = 0;
1738                 __module_get(THIS_MODULE);
1739         }
1740 #endif
1741 #ifdef CONFIG_PCI
1742         err = pci_register_driver(&cyberpro_driver);
1743         if (!err)
1744                 ret = 0;
1745 #endif
1746
1747         return ret ? err : 0;
1748 }
1749
1750 static void __exit cyberpro_exit(void)
1751 {
1752         pci_unregister_driver(&cyberpro_driver);
1753 }
1754
1755 module_init(cyber2000fb_init);
1756 module_exit(cyberpro_exit);
1757
1758 MODULE_AUTHOR("Russell King");
1759 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
1760 MODULE_LICENSE("GPL");