drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/kernel.h>
  55 #include <linux/errno.h>
  56 #include <linux/string.h>
  57 #include <linux/mm.h>
  58 #include <linux/slab.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/delay.h>
  61 #include <linux/console.h>
  62 #include <linux/fb.h>
  63 #include <linux/init.h>
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/wait.h>
  68 #include <linux/backlight.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/machdep.h>
  79 #include <asm/prom.h>
  80 #include "../macmodes.h"
  81 #endif
  82 #ifdef __sparc__
  83 #include <asm/pbm.h>
  84 #include <asm/fbio.h>
  85 #endif
  86
  87 #ifdef CONFIG_ADB_PMU
  88 #include <linux/adb.h>
  89 #include <linux/pmu.h>
  90 #endif
  91 #ifdef CONFIG_BOOTX_TEXT
  92 #include <asm/btext.h>
  93 #endif
  94 #ifdef CONFIG_PMAC_BACKLIGHT
  95 #include <asm/backlight.h>
  96 #endif
  97 #ifdef CONFIG_MTRR
  98 #include <asm/mtrr.h>
  99 #endif
 100
 101 /*
 102  * Debug flags.
 103  */
 104 #undef DEBUG
 105 /*#define DEBUG*/
 106
 107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 108 /*  - must be large enough to catch all GUI-Regs   */
 109 /*  - must be aligned to a PAGE boundary           */
 110 #define GUI_RESERVE     (1 * PAGE_SIZE)
 111
 112 /* FIXME: remove the FAIL definition */
 113 #define FAIL(msg) do { \
 114         if (!(var->activate & FB_ACTIVATE_TEST)) \
 115                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 116         return -EINVAL; \
 117 } while (0)
 118 #define FAIL_MAX(msg, x, _max_) do { \
 119         if (x > _max_) { \
 120                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 121                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 122                 return -EINVAL; \
 123         } \
 124 } while (0)
 125 #ifdef DEBUG
 126 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 127 #else
 128 #define DPRINTK(fmt, args...)
 129 #endif
 130
 131 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 132 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 133
 134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 135 static const u32 lt_lcd_regs[] = {
 136         CONFIG_PANEL_LG,
 137         LCD_GEN_CNTL_LG,
 138         DSTN_CONTROL_LG,
 139         HFB_PITCH_ADDR_LG,
 140         HORZ_STRETCHING_LG,
 141         VERT_STRETCHING_LG,
 142         0, /* EXT_VERT_STRETCH */
 143         LT_GIO_LG,
 144         POWER_MANAGEMENT_LG
 145 };
 146
 147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 148 {
 149         if (M64_HAS(LT_LCD_REGS)) {
 150                 aty_st_le32(lt_lcd_regs[index], val, par);
 151         } else {
 152                 unsigned long temp;
 153
 154                 /* write addr byte */
 155                 temp = aty_ld_le32(LCD_INDEX, par);
 156                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 157                 /* write the register value */
 158                 aty_st_le32(LCD_DATA, val, par);
 159         }
 160 }
 161
 162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 163 {
 164         if (M64_HAS(LT_LCD_REGS)) {
 165                 return aty_ld_le32(lt_lcd_regs[index], par);
 166         } else {
 167                 unsigned long temp;
 168
 169                 /* write addr byte */
 170                 temp = aty_ld_le32(LCD_INDEX, par);
 171                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 172                 /* read the register value */
 173                 return aty_ld_le32(LCD_DATA, par);
 174         }
 175 }
 176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 177
 178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 179 /*
 180  * ATIReduceRatio --
 181  *
 182  * Reduce a fraction by factoring out the largest common divider of the
 183  * fraction's numerator and denominator.
 184  */
 185 static void ATIReduceRatio(int *Numerator, int *Denominator)
 186 {
 187     int Multiplier, Divider, Remainder;
 188
 189     Multiplier = *Numerator;
 190     Divider = *Denominator;
 191
 192     while ((Remainder = Multiplier % Divider))
 193     {
 194         Multiplier = Divider;
 195         Divider = Remainder;
 196     }
 197
 198     *Numerator /= Divider;
 199     *Denominator /= Divider;
 200 }
 201 #endif
 202     /*
 203      *  The Hardware parameters for each card
 204      */
 205
 206 struct aty_cmap_regs {
 207         u8 windex;
 208         u8 lut;
 209         u8 mask;
 210         u8 rindex;
 211         u8 cntl;
 212 };
 213
 214 struct pci_mmap_map {
 215         unsigned long voff;
 216         unsigned long poff;
 217         unsigned long size;
 218         unsigned long prot_flag;
 219         unsigned long prot_mask;
 220 };
 221
 222 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 223         .id             = "ATY Mach64",
 224         .type           = FB_TYPE_PACKED_PIXELS,
 225         .visual         = FB_VISUAL_PSEUDOCOLOR,
 226         .xpanstep       = 8,
 227         .ypanstep       = 1,
 228 };
 229
 230     /*
 231      *  Frame buffer device API
 232      */
 233
 234 static int atyfb_open(struct fb_info *info, int user);
 235 static int atyfb_release(struct fb_info *info, int user);
 236 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 237 static int atyfb_set_par(struct fb_info *info);
 238 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 239         u_int transp, struct fb_info *info);
 240 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 241 static int atyfb_blank(int blank, struct fb_info *info);
 242 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 243 #ifdef __sparc__
 244 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 245 #endif
 246 static int atyfb_sync(struct fb_info *info);
 247
 248     /*
 249      *  Internal routines
 250      */
 251
 252 static int aty_init(struct fb_info *info, const char *name);
 253 #ifdef CONFIG_ATARI
 254 static int store_video_par(char *videopar, unsigned char m64_num);
 255 #endif
 256
 257 static struct crtc saved_crtc;
 258 static union aty_pll saved_pll;
 259 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 260
 261 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 262 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 263 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 264 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 265 #ifdef CONFIG_PPC
 266 static int read_aty_sense(const struct atyfb_par *par);
 267 #endif
 268
 269
 270     /*
 271      *  Interface used by the world
 272      */
 273
 274 static struct fb_var_screeninfo default_var = {
 275         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 276         640, 480, 640, 480, 0, 0, 8, 0,
 277         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 278         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 279         0, FB_VMODE_NONINTERLACED
 280 };
 281
 282 static struct fb_videomode defmode = {
 283         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 284         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 285         0, FB_VMODE_NONINTERLACED
 286 };
 287
 288 static struct fb_ops atyfb_ops = {
 289         .owner          = THIS_MODULE,
 290         .fb_open        = atyfb_open,
 291         .fb_release     = atyfb_release,
 292         .fb_check_var   = atyfb_check_var,
 293         .fb_set_par     = atyfb_set_par,
 294         .fb_setcolreg   = atyfb_setcolreg,
 295         .fb_pan_display = atyfb_pan_display,
 296         .fb_blank       = atyfb_blank,
 297         .fb_ioctl       = atyfb_ioctl,
 298         .fb_fillrect    = atyfb_fillrect,
 299         .fb_copyarea    = atyfb_copyarea,
 300         .fb_imageblit   = atyfb_imageblit,
 301 #ifdef __sparc__
 302         .fb_mmap        = atyfb_mmap,
 303 #endif
 304         .fb_sync        = atyfb_sync,
 305 };
 306
 307 static int noaccel;
 308 #ifdef CONFIG_MTRR
 309 static int nomtrr;
 310 #endif
 311 static int vram;
 312 static int pll;
 313 static int mclk;
 314 static int xclk;
 315 static int comp_sync __devinitdata = -1;
 316 static char *mode;
 317
 318 #ifdef CONFIG_PPC
 319 static int default_vmode __devinitdata = VMODE_CHOOSE;
 320 static int default_cmode __devinitdata = CMODE_CHOOSE;
 321
 322 module_param_named(vmode, default_vmode, int, 0);
 323 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 324 module_param_named(cmode, default_cmode, int, 0);
 325 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 326 #endif
 327
 328 #ifdef CONFIG_ATARI
 329 static unsigned int mach64_count __devinitdata = 0;
 330 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
 331 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
 332 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
 333 #endif
 334
 335 /* top -> down is an evolution of mach64 chipset, any corrections? */
 336 #define ATI_CHIP_88800GX   (M64F_GX)
 337 #define ATI_CHIP_88800CX   (M64F_GX)
 338
 339 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 340 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 341
 342 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 343 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 344
 345 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 346 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 347 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 348
 349 /* FIXME what is this chip? */
 350 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 351
 352 /* make sets shorter */
 353 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 354
 355 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 356 /*#define ATI_CHIP_264GTDVD  ?*/
 357 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 358
 359 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 360 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 361 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 362
 363 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 364 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 365
 366 static struct {
 367         u16 pci_id;
 368         const char *name;
 369         int pll, mclk, xclk, ecp_max;
 370         u32 features;
 371 } aty_chips[] __devinitdata = {
 372 #ifdef CONFIG_FB_ATY_GX
 373         /* Mach64 GX */
 374         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 375         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 376 #endif /* CONFIG_FB_ATY_GX */
 377
 378 #ifdef CONFIG_FB_ATY_CT
 379         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 380         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 381
 382         /* FIXME what is this chip? */
 383         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 384
 385         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 386         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 387
 388         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 389         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 390
 391         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 392
 393         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 394
 395         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 396         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 397         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 398         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 399
 400         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 401         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 402         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 403         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 404         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 405
 406         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 407         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 408         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 409         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
 410         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 411
 412         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 413         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 414         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 415         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 416         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 417         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 418
 419         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 420         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 421         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 422         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 423 #endif /* CONFIG_FB_ATY_CT */
 424 };
 425
 426 /* can not fail */
 427 static int __devinit correct_chipset(struct atyfb_par *par)
 428 {
 429         u8 rev;
 430         u16 type;
 431         u32 chip_id;
 432         const char *name;
 433         int i;
 434
 435         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
 436                 if (par->pci_id == aty_chips[i].pci_id)
 437                         break;
 438
 439         name = aty_chips[i].name;
 440         par->pll_limits.pll_max = aty_chips[i].pll;
 441         par->pll_limits.mclk = aty_chips[i].mclk;
 442         par->pll_limits.xclk = aty_chips[i].xclk;
 443         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 444         par->features = aty_chips[i].features;
 445
 446         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 447         type = chip_id & CFG_CHIP_TYPE;
 448         rev = (chip_id & CFG_CHIP_REV) >> 24;
 449
 450         switch(par->pci_id) {
 451 #ifdef CONFIG_FB_ATY_GX
 452         case PCI_CHIP_MACH64GX:
 453                 if(type != 0x00d7)
 454                         return -ENODEV;
 455                 break;
 456         case PCI_CHIP_MACH64CX:
 457                 if(type != 0x0057)
 458                         return -ENODEV;
 459                 break;
 460 #endif
 461 #ifdef CONFIG_FB_ATY_CT
 462         case PCI_CHIP_MACH64VT:
 463                 switch (rev & 0x07) {
 464                 case 0x00:
 465                         switch (rev & 0xc0) {
 466                         case 0x00:
 467                                 name = "ATI264VT (A3) (Mach64 VT)";
 468                                 par->pll_limits.pll_max = 170;
 469                                 par->pll_limits.mclk = 67;
 470                                 par->pll_limits.xclk = 67;
 471                                 par->pll_limits.ecp_max = 80;
 472                                 par->features = ATI_CHIP_264VT;
 473                                 break;
 474                         case 0x40:
 475                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 476                                 par->pll_limits.pll_max = 200;
 477                                 par->pll_limits.mclk = 67;
 478                                 par->pll_limits.xclk = 67;
 479                                 par->pll_limits.ecp_max = 80;
 480                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 481                                 break;
 482                         }
 483                         break;
 484                 case 0x01:
 485                         name = "ATI264VT3 (B1) (Mach64 VT)";
 486                         par->pll_limits.pll_max = 200;
 487                         par->pll_limits.mclk = 67;
 488                         par->pll_limits.xclk = 67;
 489                         par->pll_limits.ecp_max = 80;
 490                         par->features = ATI_CHIP_264VTB;
 491                         break;
 492                 case 0x02:
 493                         name = "ATI264VT3 (B2) (Mach64 VT)";
 494                         par->pll_limits.pll_max = 200;
 495                         par->pll_limits.mclk = 67;
 496                         par->pll_limits.xclk = 67;
 497                         par->pll_limits.ecp_max = 80;
 498                         par->features = ATI_CHIP_264VT3;
 499                         break;
 500                 }
 501                 break;
 502         case PCI_CHIP_MACH64GT:
 503                 switch (rev & 0x07) {
 504                 case 0x01:
 505                         name = "3D RAGE II (Mach64 GT)";
 506                         par->pll_limits.pll_max = 170;
 507                         par->pll_limits.mclk = 67;
 508                         par->pll_limits.xclk = 67;
 509                         par->pll_limits.ecp_max = 80;
 510                         par->features = ATI_CHIP_264GTB;
 511                         break;
 512                 case 0x02:
 513                         name = "3D RAGE II+ (Mach64 GT)";
 514                         par->pll_limits.pll_max = 200;
 515                         par->pll_limits.mclk = 67;
 516                         par->pll_limits.xclk = 67;
 517                         par->pll_limits.ecp_max = 100;
 518                         par->features = ATI_CHIP_264GTB;
 519                         break;
 520                 }
 521                 break;
 522 #endif
 523         }
 524
 525         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 526         return 0;
 527 }
 528
 529 static char ram_dram[] __devinitdata = "DRAM";
 530 static char ram_resv[] __devinitdata = "RESV";
 531 #ifdef CONFIG_FB_ATY_GX
 532 static char ram_vram[] __devinitdata = "VRAM";
 533 #endif /* CONFIG_FB_ATY_GX */
 534 #ifdef CONFIG_FB_ATY_CT
 535 static char ram_edo[] __devinitdata = "EDO";
 536 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 537 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 538 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 539 static char ram_off[] __devinitdata = "OFF";
 540 #endif /* CONFIG_FB_ATY_CT */
 541
 542
 543 static u32 pseudo_palette[17];
 544
 545 #ifdef CONFIG_FB_ATY_GX
 546 static char *aty_gx_ram[8] __devinitdata = {
 547         ram_dram, ram_vram, ram_vram, ram_dram,
 548         ram_dram, ram_vram, ram_vram, ram_resv
 549 };
 550 #endif /* CONFIG_FB_ATY_GX */
 551
 552 #ifdef CONFIG_FB_ATY_CT
 553 static char *aty_ct_ram[8] __devinitdata = {
 554         ram_off, ram_dram, ram_edo, ram_edo,
 555         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 556 };
 557 #endif /* CONFIG_FB_ATY_CT */
 558
 559 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 560 {
 561         u32 pixclock = var->pixclock;
 562 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 563         u32 lcd_on_off;
 564         par->pll.ct.xres = 0;
 565         if (par->lcd_table != 0) {
 566                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 567                 if(lcd_on_off & LCD_ON) {
 568                         par->pll.ct.xres = var->xres;
 569                         pixclock = par->lcd_pixclock;
 570                 }
 571         }
 572 #endif
 573         return pixclock;
 574 }
 575
 576 #if defined(CONFIG_PPC)
 577
 578 /*
 579  *  Apple monitor sense
 580  */
 581
 582 static int __devinit read_aty_sense(const struct atyfb_par *par)
 583 {
 584         int sense, i;
 585
 586         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 587         __delay(200);
 588         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 589         __delay(2000);
 590         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 591         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 592
 593         /* drive each sense line low in turn and collect the other 2 */
 594         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 595         __delay(2000);
 596         i = aty_ld_le32(GP_IO, par);
 597         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 598         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 599         __delay(200);
 600
 601         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 602         __delay(2000);
 603         i = aty_ld_le32(GP_IO, par);
 604         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 605         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 606         __delay(200);
 607
 608         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 609         __delay(2000);
 610         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 611         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 612         return sense;
 613 }
 614
 615 #endif /* defined(CONFIG_PPC) */
 616
 617 /* ------------------------------------------------------------------------- */
 618
 619 /*
 620  *  CRTC programming
 621  */
 622
 623 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 624 {
 625 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 626         if (par->lcd_table != 0) {
 627                 if(!M64_HAS(LT_LCD_REGS)) {
 628                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 629                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 630                 }
 631                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 632                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 633
 634
 635                 /* switch to non shadow registers */
 636                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 637                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 638
 639                 /* save stretching */
 640                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 641                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 642                 if (!M64_HAS(LT_LCD_REGS))
 643                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 644         }
 645 #endif
 646         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 647         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 648         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 649         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 650         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 651         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 652         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 653
 654 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 655         if (par->lcd_table != 0) {
 656                 /* switch to shadow registers */
 657                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 658                         SHADOW_EN | SHADOW_RW_EN, par);
 659
 660                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 661                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 662                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 663                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 664
 665                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 666         }
 667 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 668 }
 669
 670 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 671 {
 672 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 673         if (par->lcd_table != 0) {
 674                 /* stop CRTC */
 675                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 676
 677                 /* update non-shadow registers first */
 678                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 679                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 680                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 681
 682                 /* temporarily disable stretching */
 683                 aty_st_lcd(HORZ_STRETCHING,
 684                         crtc->horz_stretching &
 685                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 686                 aty_st_lcd(VERT_STRETCHING,
 687                         crtc->vert_stretching &
 688                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 689                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 690         }
 691 #endif
 692         /* turn off CRT */
 693         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 694
 695         DPRINTK("setting up CRTC\n");
 696         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 697             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 698             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 699             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 700
 701         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 702         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 703         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 704         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 705         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 706         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 707         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 708
 709         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 710         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 711         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 712         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 713         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 714         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 715
 716         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 717 #if 0
 718         FIXME
 719         if (par->accel_flags & FB_ACCELF_TEXT)
 720                 aty_init_engine(par, info);
 721 #endif
 722 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 723         /* after setting the CRTC registers we should set the LCD registers. */
 724         if (par->lcd_table != 0) {
 725                 /* switch to shadow registers */
 726                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 727                         (SHADOW_EN | SHADOW_RW_EN), par);
 728
 729                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 730                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 731                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 732
 733                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 734                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 735                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 736                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 737
 738                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 739                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 740                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 741                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 742
 743                 /* restore CRTC selection & shadow state and enable stretching */
 744                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 745                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 746                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 747                 if(!M64_HAS(LT_LCD_REGS))
 748                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 749
 750                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 751                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 752                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 753                 if(!M64_HAS(LT_LCD_REGS)) {
 754                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 755                     aty_ld_le32(LCD_INDEX, par);
 756                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 757                 }
 758         }
 759 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 760 }
 761
 762 static int aty_var_to_crtc(const struct fb_info *info,
 763         const struct fb_var_screeninfo *var, struct crtc *crtc)
 764 {
 765         struct atyfb_par *par = (struct atyfb_par *) info->par;
 766         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 767         u32 sync, vmode, vdisplay;
 768         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 769         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 770         u32 pix_width, dp_pix_width, dp_chain_mask;
 771
 772         /* input */
 773         xres = var->xres;
 774         yres = var->yres;
 775         vxres = var->xres_virtual;
 776         vyres = var->yres_virtual;
 777         xoffset = var->xoffset;
 778         yoffset = var->yoffset;
 779         bpp = var->bits_per_pixel;
 780         if (bpp == 16)
 781                 bpp = (var->green.length == 5) ? 15 : 16;
 782         sync = var->sync;
 783         vmode = var->vmode;
 784
 785         /* convert (and round up) and validate */
 786         if (vxres < xres + xoffset)
 787                 vxres = xres + xoffset;
 788         h_disp = xres;
 789
 790         if (vyres < yres + yoffset)
 791                 vyres = yres + yoffset;
 792         v_disp = yres;
 793
 794         if (bpp <= 8) {
 795                 bpp = 8;
 796                 pix_width = CRTC_PIX_WIDTH_8BPP;
 797                 dp_pix_width =
 798                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 799                     BYTE_ORDER_LSB_TO_MSB;
 800                 dp_chain_mask = DP_CHAIN_8BPP;
 801         } else if (bpp <= 15) {
 802                 bpp = 16;
 803                 pix_width = CRTC_PIX_WIDTH_15BPP;
 804                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 805                     BYTE_ORDER_LSB_TO_MSB;
 806                 dp_chain_mask = DP_CHAIN_15BPP;
 807         } else if (bpp <= 16) {
 808                 bpp = 16;
 809                 pix_width = CRTC_PIX_WIDTH_16BPP;
 810                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 811                     BYTE_ORDER_LSB_TO_MSB;
 812                 dp_chain_mask = DP_CHAIN_16BPP;
 813         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 814                 bpp = 24;
 815                 pix_width = CRTC_PIX_WIDTH_24BPP;
 816                 dp_pix_width =
 817                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 818                     BYTE_ORDER_LSB_TO_MSB;
 819                 dp_chain_mask = DP_CHAIN_24BPP;
 820         } else if (bpp <= 32) {
 821                 bpp = 32;
 822                 pix_width = CRTC_PIX_WIDTH_32BPP;
 823                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 824                     BYTE_ORDER_LSB_TO_MSB;
 825                 dp_chain_mask = DP_CHAIN_32BPP;
 826         } else
 827                 FAIL("invalid bpp");
 828
 829         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 830                 FAIL("not enough video RAM");
 831
 832         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 833         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 834
 835         if((xres > 1600) || (yres > 1200)) {
 836                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 837                 "select anoter resolution.");
 838         }
 839         h_sync_strt = h_disp + var->right_margin;
 840         h_sync_end = h_sync_strt + var->hsync_len;
 841         h_sync_dly  = var->right_margin & 7;
 842         h_total = h_sync_end + h_sync_dly + var->left_margin;
 843
 844         v_sync_strt = v_disp + var->lower_margin;
 845         v_sync_end = v_sync_strt + var->vsync_len;
 846         v_total = v_sync_end + var->upper_margin;
 847
 848 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 849         if (par->lcd_table != 0) {
 850                 if(!M64_HAS(LT_LCD_REGS)) {
 851                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 852                     crtc->lcd_index = lcd_index &
 853                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 854                     aty_st_le32(LCD_INDEX, lcd_index, par);
 855                 }
 856
 857                 if (!M64_HAS(MOBIL_BUS))
 858                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 859
 860                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 861                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 862
 863                 crtc->lcd_gen_cntl &=
 864                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 865                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 866                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 867                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 868
 869                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 870                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 871                         /* We cannot display the mode on the LCD. If the CRT is enabled
 872                            we can turn off the LCD.
 873                            If the CRT is off, it isn't a good idea to switch it on; we don't
 874                            know if one is connected. So it's better to fail then.
 875                          */
 876                         if (crtc->lcd_gen_cntl & CRT_ON) {
 877                                 if (!(var->activate & FB_ACTIVATE_TEST))
 878                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 879                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 880                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 881                         } else {
 882                                 if (!(var->activate & FB_ACTIVATE_TEST))
 883                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 884                                 return -EINVAL;
 885                         }
 886                 }
 887         }
 888
 889         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 890                 int VScan = 1;
 891                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 892                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 893                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 894
 895                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 896
 897                 /* This is horror! When we simulate, say 640x480 on an 800x600
 898                    LCD monitor, the CRTC should be programmed 800x600 values for
 899                    the non visible part, but 640x480 for the visible part.
 900                    This code has been tested on a laptop with it's 1400x1050 LCD
 901                    monitor and a conventional monitor both switched on.
 902                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 903                     works with little glitches also with DOUBLESCAN modes
 904                  */
 905                 if (yres < par->lcd_height) {
 906                         VScan = par->lcd_height / yres;
 907                         if(VScan > 1) {
 908                                 VScan = 2;
 909                                 vmode |= FB_VMODE_DOUBLE;
 910                         }
 911                 }
 912
 913                 h_sync_strt = h_disp + par->lcd_right_margin;
 914                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 915                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 916                 h_total = h_disp + par->lcd_hblank_len;
 917
 918                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 919                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 920                 v_total = v_disp + par->lcd_vblank_len / VScan;
 921         }
 922 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 923
 924         h_disp = (h_disp >> 3) - 1;
 925         h_sync_strt = (h_sync_strt >> 3) - 1;
 926         h_sync_end = (h_sync_end >> 3) - 1;
 927         h_total = (h_total >> 3) - 1;
 928         h_sync_wid = h_sync_end - h_sync_strt;
 929
 930         FAIL_MAX("h_disp too large", h_disp, 0xff);
 931         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 932         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 933         if(h_sync_wid > 0x1f)
 934                 h_sync_wid = 0x1f;
 935         FAIL_MAX("h_total too large", h_total, 0x1ff);
 936
 937         if (vmode & FB_VMODE_DOUBLE) {
 938                 v_disp <<= 1;
 939                 v_sync_strt <<= 1;
 940                 v_sync_end <<= 1;
 941                 v_total <<= 1;
 942         }
 943
 944         vdisplay = yres;
 945 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 946         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 947                 vdisplay  = par->lcd_height;
 948 #endif
 949
 950         v_disp--;
 951         v_sync_strt--;
 952         v_sync_end--;
 953         v_total--;
 954         v_sync_wid = v_sync_end - v_sync_strt;
 955
 956         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 957         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 958         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 959         if(v_sync_wid > 0x1f)
 960                 v_sync_wid = 0x1f;
 961         FAIL_MAX("v_total too large", v_total, 0x7ff);
 962
 963         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 964
 965         /* output */
 966         crtc->vxres = vxres;
 967         crtc->vyres = vyres;
 968         crtc->xoffset = xoffset;
 969         crtc->yoffset = yoffset;
 970         crtc->bpp = bpp;
 971         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 972         crtc->vline_crnt_vline = 0;
 973
 974         crtc->h_tot_disp = h_total | (h_disp<<16);
 975         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 976                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 977         crtc->v_tot_disp = v_total | (v_disp<<16);
 978         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 979
 980         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 981         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 982         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 983
 984         /* Enable doublescan mode if requested */
 985         if (vmode & FB_VMODE_DOUBLE)
 986                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 987         /* Enable interlaced mode if requested */
 988         if (vmode & FB_VMODE_INTERLACED)
 989                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 990 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 991         if (par->lcd_table != 0) {
 992                 vdisplay = yres;
 993                 if(vmode & FB_VMODE_DOUBLE)
 994                         vdisplay <<= 1;
 995                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 996                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 997                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 998                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 999                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1000
1001                 /* MOBILITY M1 tested, FIXME: LT */
1002                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1003                 if (!M64_HAS(LT_LCD_REGS))
1004                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1005                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1006
1007                 crtc->horz_stretching &=
1008                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1009                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1010                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1011                         do {
1012                                 /*
1013                                 * The horizontal blender misbehaves when HDisplay is less than a
1014                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1015                                 * stretch such modes enough.  Use pixel replication instead of
1016                                 * blending to stretch modes that can be made to exactly fit the
1017                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1018                                 * pixel-replicated mode to be slightly wider or narrower than the
1019                                 * panel width.  It also causes a mode that is exactly half as wide
1020                                 * as the panel to be pixel-replicated, rather than blended.
1021                                 */
1022                                 int HDisplay  = xres & ~7;
1023                                 int nStretch  = par->lcd_width / HDisplay;
1024                                 int Remainder = par->lcd_width % HDisplay;
1025
1026                                 if ((!Remainder && ((nStretch > 2))) ||
1027                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1028                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1029                                         int horz_stretch_loop = -1, BestRemainder;
1030                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1031                                         int Index = 5;
1032                                         ATIReduceRatio(&Numerator, &Denominator);
1033
1034                                         BestRemainder = (Numerator * 16) / Denominator;
1035                                         while (--Index >= 0) {
1036                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1037                                                         Denominator;
1038                                                 if (Remainder < BestRemainder) {
1039                                                         horz_stretch_loop = Index;
1040                                                         if (!(BestRemainder = Remainder))
1041                                                                 break;
1042                                                 }
1043                                         }
1044
1045                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1046                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1047                                                 int reuse_previous = 1;
1048
1049                                                 Index = StretchLoops[horz_stretch_loop];
1050
1051                                                 while (--Index >= 0) {
1052                                                         if (Accumulator > 0)
1053                                                                 horz_stretch_ratio |= reuse_previous;
1054                                                         else
1055                                                                 Accumulator += Denominator;
1056                                                         Accumulator -= Numerator;
1057                                                         reuse_previous <<= 1;
1058                                                 }
1059
1060                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1061                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1062                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1063                                                 break;      /* Out of the do { ... } while (0) */
1064                                         }
1065                                 }
1066
1067                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1068                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1069                         } while (0);
1070                 }
1071
1072                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1073                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1074                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1075
1076                         if (!M64_HAS(LT_LCD_REGS) &&
1077                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1078                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1079                 } else {
1080                         /*
1081                          * Don't use vertical blending if the mode is too wide or not
1082                          * vertically stretched.
1083                          */
1084                         crtc->vert_stretching = 0;
1085                 }
1086                 /* copy to shadow crtc */
1087                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1088                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1089                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1090                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1091         }
1092 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1093
1094         if (M64_HAS(MAGIC_FIFO)) {
1095                 /* FIXME: display FIFO low watermark values */
1096                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1097         }
1098         crtc->dp_pix_width = dp_pix_width;
1099         crtc->dp_chain_mask = dp_chain_mask;
1100
1101         return 0;
1102 }
1103
1104 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1105 {
1106         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1107         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1108             h_sync_pol;
1109         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1110         u32 pix_width;
1111         u32 double_scan, interlace;
1112
1113         /* input */
1114         h_total = crtc->h_tot_disp & 0x1ff;
1115         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1116         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1117         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1118         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1119         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1120         v_total = crtc->v_tot_disp & 0x7ff;
1121         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1122         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1123         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1124         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1125         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1126         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1127         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1128         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1129
1130         /* convert */
1131         xres = (h_disp + 1) * 8;
1132         yres = v_disp + 1;
1133         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1134         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1135         hslen = h_sync_wid * 8;
1136         upper = v_total - v_sync_strt - v_sync_wid;
1137         lower = v_sync_strt - v_disp;
1138         vslen = v_sync_wid;
1139         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1140             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1141             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1142
1143         switch (pix_width) {
1144 #if 0
1145         case CRTC_PIX_WIDTH_4BPP:
1146                 bpp = 4;
1147                 var->red.offset = 0;
1148                 var->red.length = 8;
1149                 var->green.offset = 0;
1150                 var->green.length = 8;
1151                 var->blue.offset = 0;
1152                 var->blue.length = 8;
1153                 var->transp.offset = 0;
1154                 var->transp.length = 0;
1155                 break;
1156 #endif
1157         case CRTC_PIX_WIDTH_8BPP:
1158                 bpp = 8;
1159                 var->red.offset = 0;
1160                 var->red.length = 8;
1161                 var->green.offset = 0;
1162                 var->green.length = 8;
1163                 var->blue.offset = 0;
1164                 var->blue.length = 8;
1165                 var->transp.offset = 0;
1166                 var->transp.length = 0;
1167                 break;
1168         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1169                 bpp = 16;
1170                 var->red.offset = 10;
1171                 var->red.length = 5;
1172                 var->green.offset = 5;
1173                 var->green.length = 5;
1174                 var->blue.offset = 0;
1175                 var->blue.length = 5;
1176                 var->transp.offset = 0;
1177                 var->transp.length = 0;
1178                 break;
1179         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1180                 bpp = 16;
1181                 var->red.offset = 11;
1182                 var->red.length = 5;
1183                 var->green.offset = 5;
1184                 var->green.length = 6;
1185                 var->blue.offset = 0;
1186                 var->blue.length = 5;
1187                 var->transp.offset = 0;
1188                 var->transp.length = 0;
1189                 break;
1190         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1191                 bpp = 24;
1192                 var->red.offset = 16;
1193                 var->red.length = 8;
1194                 var->green.offset = 8;
1195                 var->green.length = 8;
1196                 var->blue.offset = 0;
1197                 var->blue.length = 8;
1198                 var->transp.offset = 0;
1199                 var->transp.length = 0;
1200                 break;
1201         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1202                 bpp = 32;
1203                 var->red.offset = 16;
1204                 var->red.length = 8;
1205                 var->green.offset = 8;
1206                 var->green.length = 8;
1207                 var->blue.offset = 0;
1208                 var->blue.length = 8;
1209                 var->transp.offset = 24;
1210                 var->transp.length = 8;
1211                 break;
1212         default:
1213                 PRINTKE("Invalid pixel width\n");
1214                 return -EINVAL;
1215         }
1216
1217         /* output */
1218         var->xres = xres;
1219         var->yres = yres;
1220         var->xres_virtual = crtc->vxres;
1221         var->yres_virtual = crtc->vyres;
1222         var->bits_per_pixel = bpp;
1223         var->left_margin = left;
1224         var->right_margin = right;
1225         var->upper_margin = upper;
1226         var->lower_margin = lower;
1227         var->hsync_len = hslen;
1228         var->vsync_len = vslen;
1229         var->sync = sync;
1230         var->vmode = FB_VMODE_NONINTERLACED;
1231         /* In double scan mode, the vertical parameters are doubled, so we need to
1232            half them to get the right values.
1233            In interlaced mode the values are already correct, so no correction is
1234            necessary.
1235          */
1236         if (interlace)
1237                 var->vmode = FB_VMODE_INTERLACED;
1238
1239         if (double_scan) {
1240                 var->vmode = FB_VMODE_DOUBLE;
1241                 var->yres>>=1;
1242                 var->upper_margin>>=1;
1243                 var->lower_margin>>=1;
1244                 var->vsync_len>>=1;
1245         }
1246
1247         return 0;
1248 }
1249
1250 /* ------------------------------------------------------------------------- */
1251
1252 static int atyfb_set_par(struct fb_info *info)
1253 {
1254         struct atyfb_par *par = (struct atyfb_par *) info->par;
1255         struct fb_var_screeninfo *var = &info->var;
1256         u32 tmp, pixclock;
1257         int err;
1258 #ifdef DEBUG
1259         struct fb_var_screeninfo debug;
1260         u32 pixclock_in_ps;
1261 #endif
1262         if (par->asleep)
1263                 return 0;
1264
1265         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1266                 return err;
1267
1268         pixclock = atyfb_get_pixclock(var, par);
1269
1270         if (pixclock == 0) {
1271                 PRINTKE("Invalid pixclock\n");
1272                 return -EINVAL;
1273         } else {
1274                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1275                         return err;
1276         }
1277
1278         par->accel_flags = var->accel_flags; /* hack */
1279
1280         if (var->accel_flags) {
1281                 info->fbops->fb_sync = atyfb_sync;
1282                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1283         } else {
1284                 info->fbops->fb_sync = NULL;
1285                 info->flags |= FBINFO_HWACCEL_DISABLED;
1286         }
1287
1288         if (par->blitter_may_be_busy)
1289                 wait_for_idle(par);
1290
1291         aty_set_crtc(par, &par->crtc);
1292         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1293         par->pll_ops->set_pll(info, &par->pll);
1294
1295 #ifdef DEBUG
1296         if(par->pll_ops && par->pll_ops->pll_to_var)
1297                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1298         else
1299                 pixclock_in_ps = 0;
1300
1301         if(0 == pixclock_in_ps) {
1302                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1303                 pixclock_in_ps = pixclock;
1304         }
1305
1306         memset(&debug, 0, sizeof(debug));
1307         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1308                 u32 hSync, vRefresh;
1309                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1310                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1311
1312                 h_disp = debug.xres;
1313                 h_sync_strt = h_disp + debug.right_margin;
1314                 h_sync_end = h_sync_strt + debug.hsync_len;
1315                 h_total = h_sync_end + debug.left_margin;
1316                 v_disp = debug.yres;
1317                 v_sync_strt = v_disp + debug.lower_margin;
1318                 v_sync_end = v_sync_strt + debug.vsync_len;
1319                 v_total = v_sync_end + debug.upper_margin;
1320
1321                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1322                 vRefresh = (hSync * 1000) / v_total;
1323                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1324                 vRefresh *= 2;
1325                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1326                 vRefresh /= 2;
1327
1328                 DPRINTK("atyfb_set_par\n");
1329                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1330                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1331                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1332                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1333                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1334                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1335                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1336                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1337                         h_disp, h_sync_strt, h_sync_end, h_total,
1338                         v_disp, v_sync_strt, v_sync_end, v_total);
1339                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1340                         pixclock_in_ps,
1341                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1342                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1343         }
1344 #endif /* DEBUG */
1345
1346         if (!M64_HAS(INTEGRATED)) {
1347                 /* Don't forget MEM_CNTL */
1348                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1349                 switch (var->bits_per_pixel) {
1350                 case 8:
1351                         tmp |= 0x02000000;
1352                         break;
1353                 case 16:
1354                         tmp |= 0x03000000;
1355                         break;
1356                 case 32:
1357                         tmp |= 0x06000000;
1358                         break;
1359                 }
1360                 aty_st_le32(MEM_CNTL, tmp, par);
1361         } else {
1362                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1363                 if (!M64_HAS(MAGIC_POSTDIV))
1364                         tmp |= par->mem_refresh_rate << 20;
1365                 switch (var->bits_per_pixel) {
1366                 case 8:
1367                 case 24:
1368                         tmp |= 0x00000000;
1369                         break;
1370                 case 16:
1371                         tmp |= 0x04000000;
1372                         break;
1373                 case 32:
1374                         tmp |= 0x08000000;
1375                         break;
1376                 }
1377                 if (M64_HAS(CT_BUS)) {
1378                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1379                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1380                 } else if (M64_HAS(VT_BUS)) {
1381                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1382                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1383                 } else if (M64_HAS(MOBIL_BUS)) {
1384                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1385                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1386                 } else {
1387                         /* GT */
1388                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1389                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1390                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1391                 }
1392                 aty_st_le32(MEM_CNTL, tmp, par);
1393         }
1394         aty_st_8(DAC_MASK, 0xff, par);
1395
1396         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1397         info->fix.visual = var->bits_per_pixel <= 8 ?
1398                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1399
1400         /* Initialize the graphics engine */
1401         if (par->accel_flags & FB_ACCELF_TEXT)
1402                 aty_init_engine(par, info);
1403
1404 #ifdef CONFIG_BOOTX_TEXT
1405         btext_update_display(info->fix.smem_start,
1406                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1407                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1408                 var->bits_per_pixel,
1409                 par->crtc.vxres * var->bits_per_pixel / 8);
1410 #endif /* CONFIG_BOOTX_TEXT */
1411 #if 0
1412         /* switch to accelerator mode */
1413         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1414                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1415 #endif
1416 #ifdef DEBUG
1417 {
1418         /* dump non shadow CRTC, pll, LCD registers */
1419         int i; u32 base;
1420
1421         /* CRTC registers */
1422         base = 0x2000;
1423         printk("debug atyfb: Mach64 non-shadow register values:");
1424         for (i = 0; i < 256; i = i+4) {
1425                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1426                 printk(" %08X", aty_ld_le32(i, par));
1427         }
1428         printk("\n\n");
1429
1430 #ifdef CONFIG_FB_ATY_CT
1431         /* PLL registers */
1432         base = 0x00;
1433         printk("debug atyfb: Mach64 PLL register values:");
1434         for (i = 0; i < 64; i++) {
1435                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1436                 if(i%4 == 0)  printk(" ");
1437                 printk("%02X", aty_ld_pll_ct(i, par));
1438         }
1439         printk("\n\n");
1440 #endif  /* CONFIG_FB_ATY_CT */
1441
1442 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1443         if (par->lcd_table != 0) {
1444                 /* LCD registers */
1445                 base = 0x00;
1446                 printk("debug atyfb: LCD register values:");
1447                 if(M64_HAS(LT_LCD_REGS)) {
1448                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1449                         if(i == EXT_VERT_STRETCH)
1450                             continue;
1451                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1452                         printk(" %08X", aty_ld_lcd(i, par));
1453                     }
1454
1455                 } else {
1456                     for (i = 0; i < 64; i++) {
1457                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1458                         printk(" %08X", aty_ld_lcd(i, par));
1459                     }
1460                 }
1461                 printk("\n\n");
1462         }
1463 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1464 }
1465 #endif /* DEBUG */
1466         return 0;
1467 }
1468
1469 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1470 {
1471         struct atyfb_par *par = (struct atyfb_par *) info->par;
1472         int err;
1473         struct crtc crtc;
1474         union aty_pll pll;
1475         u32 pixclock;
1476
1477         memcpy(&pll, &(par->pll), sizeof(pll));
1478
1479         if((err = aty_var_to_crtc(info, var, &crtc)))
1480                 return err;
1481
1482         pixclock = atyfb_get_pixclock(var, par);
1483
1484         if (pixclock == 0) {
1485                 if (!(var->activate & FB_ACTIVATE_TEST))
1486                         PRINTKE("Invalid pixclock\n");
1487                 return -EINVAL;
1488         } else {
1489                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1490                         return err;
1491         }
1492
1493         if (var->accel_flags & FB_ACCELF_TEXT)
1494                 info->var.accel_flags = FB_ACCELF_TEXT;
1495         else
1496                 info->var.accel_flags = 0;
1497
1498 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1499         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1500                 return -EINVAL;
1501 #endif
1502         aty_crtc_to_var(&crtc, var);
1503         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1504         return 0;
1505 }
1506
1507 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1508 {
1509         u32 xoffset = info->var.xoffset;
1510         u32 yoffset = info->var.yoffset;
1511         u32 vxres = par->crtc.vxres;
1512         u32 bpp = info->var.bits_per_pixel;
1513
1514         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1515 }
1516
1517
1518     /*
1519      *  Open/Release the frame buffer device
1520      */
1521
1522 static int atyfb_open(struct fb_info *info, int user)
1523 {
1524         struct atyfb_par *par = (struct atyfb_par *) info->par;
1525
1526         if (user) {
1527                 par->open++;
1528 #ifdef __sparc__
1529                 par->mmaped = 0;
1530 #endif
1531         }
1532         return (0);
1533 }
1534
1535 static irqreturn_t aty_irq(int irq, void *dev_id)
1536 {
1537         struct atyfb_par *par = dev_id;
1538         int handled = 0;
1539         u32 int_cntl;
1540
1541         spin_lock(&par->int_lock);
1542
1543         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1544
1545         if (int_cntl & CRTC_VBLANK_INT) {
1546                 /* clear interrupt */
1547                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1548                 par->vblank.count++;
1549                 if (par->vblank.pan_display) {
1550                         par->vblank.pan_display = 0;
1551                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1552                 }
1553                 wake_up_interruptible(&par->vblank.wait);
1554                 handled = 1;
1555         }
1556
1557         spin_unlock(&par->int_lock);
1558
1559         return IRQ_RETVAL(handled);
1560 }
1561
1562 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1563 {
1564         u32 int_cntl;
1565
1566         if (!test_and_set_bit(0, &par->irq_flags)) {
1567                 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1568                         clear_bit(0, &par->irq_flags);
1569                         return -EINVAL;
1570                 }
1571                 spin_lock_irq(&par->int_lock);
1572                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1573                 /* clear interrupt */
1574                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1575                 /* enable interrupt */
1576                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1577                 spin_unlock_irq(&par->int_lock);
1578         } else if (reenable) {
1579                 spin_lock_irq(&par->int_lock);
1580                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1581                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1582                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1583                         /* re-enable interrupt */
1584                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1585                 }
1586                 spin_unlock_irq(&par->int_lock);
1587         }
1588
1589         return 0;
1590 }
1591
1592 static int aty_disable_irq(struct atyfb_par *par)
1593 {
1594         u32 int_cntl;
1595
1596         if (test_and_clear_bit(0, &par->irq_flags)) {
1597                 if (par->vblank.pan_display) {
1598                         par->vblank.pan_display = 0;
1599                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1600                 }
1601                 spin_lock_irq(&par->int_lock);
1602                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1603                 /* disable interrupt */
1604                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1605                 spin_unlock_irq(&par->int_lock);
1606                 free_irq(par->irq, par);
1607         }
1608
1609         return 0;
1610 }
1611
1612 static int atyfb_release(struct fb_info *info, int user)
1613 {
1614         struct atyfb_par *par = (struct atyfb_par *) info->par;
1615         if (user) {
1616                 par->open--;
1617                 mdelay(1);
1618                 wait_for_idle(par);
1619                 if (!par->open) {
1620 #ifdef __sparc__
1621                         int was_mmaped = par->mmaped;
1622
1623                         par->mmaped = 0;
1624
1625                         if (was_mmaped) {
1626                                 struct fb_var_screeninfo var;
1627
1628                                 /* Now reset the default display config, we have no
1629                                  * idea what the program(s) which mmap'd the chip did
1630                                  * to the configuration, nor whether it restored it
1631                                  * correctly.
1632                                  */
1633                                 var = default_var;
1634                                 if (noaccel)
1635                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1636                                 else
1637                                         var.accel_flags |= FB_ACCELF_TEXT;
1638                                 if (var.yres == var.yres_virtual) {
1639                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1640                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1641                                         if (var.yres_virtual < var.yres)
1642                                                 var.yres_virtual = var.yres;
1643                                 }
1644                         }
1645 #endif
1646                         aty_disable_irq(par);
1647                 }
1648         }
1649         return (0);
1650 }
1651
1652     /*
1653      *  Pan or Wrap the Display
1654      *
1655      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1656      */
1657
1658 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1659 {
1660         struct atyfb_par *par = (struct atyfb_par *) info->par;
1661         u32 xres, yres, xoffset, yoffset;
1662
1663         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1664         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1665         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1666                 yres >>= 1;
1667         xoffset = (var->xoffset + 7) & ~7;
1668         yoffset = var->yoffset;
1669         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1670                 return -EINVAL;
1671         info->var.xoffset = xoffset;
1672         info->var.yoffset = yoffset;
1673         if (par->asleep)
1674                 return 0;
1675
1676         set_off_pitch(par, info);
1677         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1678                 par->vblank.pan_display = 1;
1679         } else {
1680                 par->vblank.pan_display = 0;
1681                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1688 {
1689         struct aty_interrupt *vbl;
1690         unsigned int count;
1691         int ret;
1692
1693         switch (crtc) {
1694         case 0:
1695                 vbl = &par->vblank;
1696                 break;
1697         default:
1698                 return -ENODEV;
1699         }
1700
1701         ret = aty_enable_irq(par, 0);
1702         if (ret)
1703                 return ret;
1704
1705         count = vbl->count;
1706         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1707         if (ret < 0) {
1708                 return ret;
1709         }
1710         if (ret == 0) {
1711                 aty_enable_irq(par, 1);
1712                 return -ETIMEDOUT;
1713         }
1714
1715         return 0;
1716 }
1717
1718
1719 #ifdef DEBUG
1720 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1721 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1722
1723 struct atyclk {
1724         u32 ref_clk_per;
1725         u8 pll_ref_div;
1726         u8 mclk_fb_div;
1727         u8 mclk_post_div;       /* 1,2,3,4,8 */
1728         u8 mclk_fb_mult;        /* 2 or 4 */
1729         u8 xclk_post_div;       /* 1,2,3,4,8 */
1730         u8 vclk_fb_div;
1731         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1732         u32 dsp_xclks_per_row;  /* 0-16383 */
1733         u32 dsp_loop_latency;   /* 0-15 */
1734         u32 dsp_precision;      /* 0-7 */
1735         u32 dsp_on;             /* 0-2047 */
1736         u32 dsp_off;            /* 0-2047 */
1737 };
1738
1739 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1740 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1741 #endif
1742
1743 #ifndef FBIO_WAITFORVSYNC
1744 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1745 #endif
1746
1747 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1748 {
1749         struct atyfb_par *par = (struct atyfb_par *) info->par;
1750 #ifdef __sparc__
1751         struct fbtype fbtyp;
1752 #endif
1753
1754         switch (cmd) {
1755 #ifdef __sparc__
1756         case FBIOGTYPE:
1757                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1758                 fbtyp.fb_width = par->crtc.vxres;
1759                 fbtyp.fb_height = par->crtc.vyres;
1760                 fbtyp.fb_depth = info->var.bits_per_pixel;
1761                 fbtyp.fb_cmsize = info->cmap.len;
1762                 fbtyp.fb_size = info->fix.smem_len;
1763                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1764                         return -EFAULT;
1765                 break;
1766 #endif /* __sparc__ */
1767
1768         case FBIO_WAITFORVSYNC:
1769                 {
1770                         u32 crtc;
1771
1772                         if (get_user(crtc, (__u32 __user *) arg))
1773                                 return -EFAULT;
1774
1775                         return aty_waitforvblank(par, crtc);
1776                 }
1777                 break;
1778
1779 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1780         case ATYIO_CLKR:
1781                 if (M64_HAS(INTEGRATED)) {
1782                         struct atyclk clk;
1783                         union aty_pll *pll = &(par->pll);
1784                         u32 dsp_config = pll->ct.dsp_config;
1785                         u32 dsp_on_off = pll->ct.dsp_on_off;
1786                         clk.ref_clk_per = par->ref_clk_per;
1787                         clk.pll_ref_div = pll->ct.pll_ref_div;
1788                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1789                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1790                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1791                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1792                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1793                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1794                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1795                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1796                         clk.dsp_precision = (dsp_config >> 20) & 7;
1797                         clk.dsp_off = dsp_on_off & 0x7ff;
1798                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1799                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1800                                          sizeof(clk)))
1801                                 return -EFAULT;
1802                 } else
1803                         return -EINVAL;
1804                 break;
1805         case ATYIO_CLKW:
1806                 if (M64_HAS(INTEGRATED)) {
1807                         struct atyclk clk;
1808                         union aty_pll *pll = &(par->pll);
1809                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1810                                 return -EFAULT;
1811                         par->ref_clk_per = clk.ref_clk_per;
1812                         pll->ct.pll_ref_div = clk.pll_ref_div;
1813                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1814                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1815                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1816                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1817                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1818                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1819                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1820                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1821                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1822                         /*aty_calc_pll_ct(info, &pll->ct);*/
1823                         aty_set_pll_ct(info, pll);
1824                 } else
1825                         return -EINVAL;
1826                 break;
1827         case ATYIO_FEATR:
1828                 if (get_user(par->features, (u32 __user *) arg))
1829                         return -EFAULT;
1830                 break;
1831         case ATYIO_FEATW:
1832                 if (put_user(par->features, (u32 __user *) arg))
1833                         return -EFAULT;
1834                 break;
1835 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1836         default:
1837                 return -EINVAL;
1838         }
1839         return 0;
1840 }
1841
1842 static int atyfb_sync(struct fb_info *info)
1843 {
1844         struct atyfb_par *par = (struct atyfb_par *) info->par;
1845
1846         if (par->blitter_may_be_busy)
1847                 wait_for_idle(par);
1848         return 0;
1849 }
1850
1851 #ifdef __sparc__
1852 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1853 {
1854         struct atyfb_par *par = (struct atyfb_par *) info->par;
1855         unsigned int size, page, map_size = 0;
1856         unsigned long map_offset = 0;
1857         unsigned long off;
1858         int i;
1859
1860         if (!par->mmap_map)
1861                 return -ENXIO;
1862
1863         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1864                 return -EINVAL;
1865
1866         off = vma->vm_pgoff << PAGE_SHIFT;
1867         size = vma->vm_end - vma->vm_start;
1868
1869         /* To stop the swapper from even considering these pages. */
1870         vma->vm_flags |= (VM_IO | VM_RESERVED);
1871
1872         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1873             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1874                 off += 0x8000000000000000UL;
1875
1876         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1877
1878         /* Each page, see which map applies */
1879         for (page = 0; page < size;) {
1880                 map_size = 0;
1881                 for (i = 0; par->mmap_map[i].size; i++) {
1882                         unsigned long start = par->mmap_map[i].voff;
1883                         unsigned long end = start + par->mmap_map[i].size;
1884                         unsigned long offset = off + page;
1885
1886                         if (start > offset)
1887                                 continue;
1888                         if (offset >= end)
1889                                 continue;
1890
1891                         map_size = par->mmap_map[i].size - (offset - start);
1892                         map_offset =
1893                             par->mmap_map[i].poff + (offset - start);
1894                         break;
1895                 }
1896                 if (!map_size) {
1897                         page += PAGE_SIZE;
1898                         continue;
1899                 }
1900                 if (page + map_size > size)
1901                         map_size = size - page;
1902
1903                 pgprot_val(vma->vm_page_prot) &=
1904                     ~(par->mmap_map[i].prot_mask);
1905                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1906
1907                 if (remap_pfn_range(vma, vma->vm_start + page,
1908                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1909                         return -EAGAIN;
1910
1911                 page += map_size;
1912         }
1913
1914         if (!map_size)
1915                 return -EINVAL;
1916
1917         if (!par->mmaped)
1918                 par->mmaped = 1;
1919         return 0;
1920 }
1921
1922 static struct {
1923         u32 yoffset;
1924         u8 r[2][256];
1925         u8 g[2][256];
1926         u8 b[2][256];
1927 } atyfb_save;
1928
1929 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1930 {
1931         int i, tmp;
1932
1933         for (i = 0; i < 256; i++) {
1934                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1935                 if (M64_HAS(EXTRA_BRIGHT))
1936                         tmp |= 0x2;
1937                 aty_st_8(DAC_CNTL, tmp, par);
1938                 aty_st_8(DAC_MASK, 0xff, par);
1939
1940                 writeb(i, &par->aty_cmap_regs->rindex);
1941                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1942                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1943                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1944                 writeb(i, &par->aty_cmap_regs->windex);
1945                 writeb(atyfb_save.r[1 - enter][i],
1946                        &par->aty_cmap_regs->lut);
1947                 writeb(atyfb_save.g[1 - enter][i],
1948                        &par->aty_cmap_regs->lut);
1949                 writeb(atyfb_save.b[1 - enter][i],
1950                        &par->aty_cmap_regs->lut);
1951         }
1952 }
1953
1954 static void atyfb_palette(int enter)
1955 {
1956         struct atyfb_par *par;
1957         struct fb_info *info;
1958         int i;
1959
1960         for (i = 0; i < FB_MAX; i++) {
1961                 info = registered_fb[i];
1962                 if (info && info->fbops == &atyfb_ops) {
1963                         par = (struct atyfb_par *) info->par;
1964
1965                         atyfb_save_palette(par, enter);
1966                         if (enter) {
1967                                 atyfb_save.yoffset = info->var.yoffset;
1968                                 info->var.yoffset = 0;
1969                                 set_off_pitch(par, info);
1970                         } else {
1971                                 info->var.yoffset = atyfb_save.yoffset;
1972                                 set_off_pitch(par, info);
1973                         }
1974                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1975                         break;
1976                 }
1977         }
1978 }
1979 #endif /* __sparc__ */
1980
1981
1982
1983 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1984
1985 /* Power management routines. Those are used for PowerBook sleep.
1986  */
1987 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1988 {
1989         u32 pm;
1990         int timeout;
1991
1992         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1993         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1994         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1995         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1996
1997         timeout = 2000;
1998         if (sleep) {
1999                 /* Sleep */
2000                 pm &= ~PWR_MGT_ON;
2001                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2002                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2003                 udelay(10);
2004                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2005                 pm |= SUSPEND_NOW;
2006                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2007                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2008                 udelay(10);
2009                 pm |= PWR_MGT_ON;
2010                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2011                 do {
2012                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2013                         mdelay(1);
2014                         if ((--timeout) == 0)
2015                                 break;
2016                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2017         } else {
2018                 /* Wakeup */
2019                 pm &= ~PWR_MGT_ON;
2020                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2021                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2022                 udelay(10);
2023                 pm &= ~SUSPEND_NOW;
2024                 pm |= (PWR_BLON | AUTO_PWR_UP);
2025                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2026                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2027                 udelay(10);
2028                 pm |= PWR_MGT_ON;
2029                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2030                 do {
2031                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2032                         mdelay(1);
2033                         if ((--timeout) == 0)
2034                                 break;
2035                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2036         }
2037         mdelay(500);
2038
2039         return timeout ? 0 : -EIO;
2040 }
2041
2042 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2043 {
2044         struct fb_info *info = pci_get_drvdata(pdev);
2045         struct atyfb_par *par = (struct atyfb_par *) info->par;
2046
2047 #ifndef CONFIG_PPC_PMAC
2048         /* HACK ALERT ! Once I find a proper way to say to each driver
2049          * individually what will happen with it's PCI slot, I'll change
2050          * that. On laptops, the AGP slot is just unclocked, so D2 is
2051          * expected, while on desktops, the card is powered off
2052          */
2053         return 0;
2054 #endif /* CONFIG_PPC_PMAC */
2055
2056         if (state.event == pdev->dev.power.power_state.event)
2057                 return 0;
2058
2059         acquire_console_sem();
2060
2061         fb_set_suspend(info, 1);
2062
2063         /* Idle & reset engine */
2064         wait_for_idle(par);
2065         aty_reset_engine(par);
2066
2067         /* Blank display and LCD */
2068         atyfb_blank(FB_BLANK_POWERDOWN, info);
2069
2070         par->asleep = 1;
2071         par->lock_blank = 1;
2072
2073         /* Set chip to "suspend" mode */
2074         if (aty_power_mgmt(1, par)) {
2075                 par->asleep = 0;
2076                 par->lock_blank = 0;
2077                 atyfb_blank(FB_BLANK_UNBLANK, info);
2078                 fb_set_suspend(info, 0);
2079                 release_console_sem();
2080                 return -EIO;
2081         }
2082
2083         release_console_sem();
2084
2085         pdev->dev.power.power_state = state;
2086
2087         return 0;
2088 }
2089
2090 static int atyfb_pci_resume(struct pci_dev *pdev)
2091 {
2092         struct fb_info *info = pci_get_drvdata(pdev);
2093         struct atyfb_par *par = (struct atyfb_par *) info->par;
2094
2095         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2096                 return 0;
2097
2098         acquire_console_sem();
2099
2100         if (pdev->dev.power.power_state.event == 2)
2101                 aty_power_mgmt(0, par);
2102         par->asleep = 0;
2103
2104         /* Restore display */
2105         atyfb_set_par(info);
2106
2107         /* Refresh */
2108         fb_set_suspend(info, 0);
2109
2110         /* Unblank */
2111         par->lock_blank = 0;
2112         atyfb_blank(FB_BLANK_UNBLANK, info);
2113
2114         release_console_sem();
2115
2116         pdev->dev.power.power_state = PMSG_ON;
2117
2118         return 0;
2119 }
2120
2121 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2122
2123 /* Backlight */
2124 #ifdef CONFIG_FB_ATY_BACKLIGHT
2125 #define MAX_LEVEL 0xFF
2126
2127 static struct backlight_properties aty_bl_data;
2128
2129 /* Call with fb_info->bl_mutex held */
2130 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2131 {
2132         struct fb_info *info = pci_get_drvdata(par->pdev);
2133         int atylevel;
2134
2135         /* Get and convert the value */
2136         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2137
2138         if (atylevel < 0)
2139                 atylevel = 0;
2140         else if (atylevel > MAX_LEVEL)
2141                 atylevel = MAX_LEVEL;
2142
2143         return atylevel;
2144 }
2145
2146 /* Call with fb_info->bl_mutex held */
2147 static int __aty_bl_update_status(struct backlight_device *bd)
2148 {
2149         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2150         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2151         int level;
2152
2153         if (bd->props->power != FB_BLANK_UNBLANK ||
2154             bd->props->fb_blank != FB_BLANK_UNBLANK)
2155                 level = 0;
2156         else
2157                 level = bd->props->brightness;
2158
2159         reg |= (BLMOD_EN | BIASMOD_EN);
2160         if (level > 0) {
2161                 reg &= ~BIAS_MOD_LEVEL_MASK;
2162                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2163         } else {
2164                 reg &= ~BIAS_MOD_LEVEL_MASK;
2165                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2166         }
2167         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2168
2169         return 0;
2170 }
2171
2172 static int aty_bl_update_status(struct backlight_device *bd)
2173 {
2174         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2175         struct fb_info *info = pci_get_drvdata(par->pdev);
2176         int ret;
2177
2178         mutex_lock(&info->bl_mutex);
2179         ret = __aty_bl_update_status(bd);
2180         mutex_unlock(&info->bl_mutex);
2181
2182         return ret;
2183 }
2184
2185 static int aty_bl_get_brightness(struct backlight_device *bd)
2186 {
2187         return bd->props->brightness;
2188 }
2189
2190 static struct backlight_properties aty_bl_data = {
2191         .owner    = THIS_MODULE,
2192         .get_brightness = aty_bl_get_brightness,
2193         .update_status  = aty_bl_update_status,
2194         .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2195 };
2196
2197 static void aty_bl_set_power(struct fb_info *info, int power)
2198 {
2199         mutex_lock(&info->bl_mutex);
2200
2201         if (info->bl_dev) {
2202                 down(&info->bl_dev->sem);
2203                 info->bl_dev->props->power = power;
2204                 __aty_bl_update_status(info->bl_dev);
2205                 up(&info->bl_dev->sem);
2206         }
2207
2208         mutex_unlock(&info->bl_mutex);
2209 }
2210
2211 static void aty_bl_init(struct atyfb_par *par)
2212 {
2213         struct fb_info *info = pci_get_drvdata(par->pdev);
2214         struct backlight_device *bd;
2215         char name[12];
2216
2217 #ifdef CONFIG_PMAC_BACKLIGHT
2218         if (!pmac_has_backlight_type("ati"))
2219                 return;
2220 #endif
2221
2222         snprintf(name, sizeof(name), "atybl%d", info->node);
2223
2224         bd = backlight_device_register(name, par, &aty_bl_data);
2225         if (IS_ERR(bd)) {
2226                 info->bl_dev = NULL;
2227                 printk(KERN_WARNING "aty: Backlight registration failed\n");
2228                 goto error;
2229         }
2230
2231         mutex_lock(&info->bl_mutex);
2232         info->bl_dev = bd;
2233         fb_bl_default_curve(info, 0,
2234                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2235                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2236         mutex_unlock(&info->bl_mutex);
2237
2238         down(&bd->sem);
2239         bd->props->brightness = aty_bl_data.max_brightness;
2240         bd->props->power = FB_BLANK_UNBLANK;
2241         bd->props->update_status(bd);
2242         up(&bd->sem);
2243
2244 #ifdef CONFIG_PMAC_BACKLIGHT
2245         mutex_lock(&pmac_backlight_mutex);
2246         if (!pmac_backlight)
2247                 pmac_backlight = bd;
2248         mutex_unlock(&pmac_backlight_mutex);
2249 #endif
2250
2251         printk("aty: Backlight initialized (%s)\n", name);
2252
2253         return;
2254
2255 error:
2256         return;
2257 }
2258
2259 static void aty_bl_exit(struct atyfb_par *par)
2260 {
2261         struct fb_info *info = pci_get_drvdata(par->pdev);
2262
2263 #ifdef CONFIG_PMAC_BACKLIGHT
2264         mutex_lock(&pmac_backlight_mutex);
2265 #endif
2266
2267         mutex_lock(&info->bl_mutex);
2268         if (info->bl_dev) {
2269 #ifdef CONFIG_PMAC_BACKLIGHT
2270                 if (pmac_backlight == info->bl_dev)
2271                         pmac_backlight = NULL;
2272 #endif
2273
2274                 backlight_device_unregister(info->bl_dev);
2275
2276                 printk("aty: Backlight unloaded\n");
2277         }
2278         mutex_unlock(&info->bl_mutex);
2279
2280 #ifdef CONFIG_PMAC_BACKLIGHT
2281         mutex_unlock(&pmac_backlight_mutex);
2282 #endif
2283 }
2284
2285 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2286
2287 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2288 {
2289         const int ragepro_tbl[] = {
2290                 44, 50, 55, 66, 75, 80, 100
2291         };
2292         const int ragexl_tbl[] = {
2293                 50, 66, 75, 83, 90, 95, 100, 105,
2294                 110, 115, 120, 125, 133, 143, 166
2295         };
2296         const int *refresh_tbl;
2297         int i, size;
2298
2299         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2300                 refresh_tbl = ragexl_tbl;
2301                 size = ARRAY_SIZE(ragexl_tbl);
2302         } else {
2303                 refresh_tbl = ragepro_tbl;
2304                 size = ARRAY_SIZE(ragepro_tbl);
2305         }
2306
2307         for (i=0; i < size; i++) {
2308                 if (xclk < refresh_tbl[i])
2309                 break;
2310         }
2311         par->mem_refresh_rate = i;
2312 }
2313
2314     /*
2315      *  Initialisation
2316      */
2317
2318 static struct fb_info *fb_list = NULL;
2319
2320 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2321 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2322                                                 struct fb_var_screeninfo *var)
2323 {
2324         int ret = -EINVAL;
2325
2326         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2327                 *var = default_var;
2328                 var->xres = var->xres_virtual = par->lcd_hdisp;
2329                 var->right_margin = par->lcd_right_margin;
2330                 var->left_margin = par->lcd_hblank_len -
2331                         (par->lcd_right_margin + par->lcd_hsync_dly +
2332                          par->lcd_hsync_len);
2333                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2334                 var->yres = var->yres_virtual = par->lcd_vdisp;
2335                 var->lower_margin = par->lcd_lower_margin;
2336                 var->upper_margin = par->lcd_vblank_len -
2337                         (par->lcd_lower_margin + par->lcd_vsync_len);
2338                 var->vsync_len = par->lcd_vsync_len;
2339                 var->pixclock = par->lcd_pixclock;
2340                 ret = 0;
2341         }
2342
2343         return ret;
2344 }
2345 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2346
2347 static int __devinit aty_init(struct fb_info *info, const char *name)
2348 {
2349         struct atyfb_par *par = (struct atyfb_par *) info->par;
2350         const char *ramname = NULL, *xtal;
2351         int gtb_memsize, has_var = 0;
2352         struct fb_var_screeninfo var;
2353         u32 i;
2354
2355         init_waitqueue_head(&par->vblank.wait);
2356         spin_lock_init(&par->int_lock);
2357
2358         par->aty_cmap_regs =
2359             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2360
2361 #ifdef CONFIG_PPC_PMAC
2362         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2363          * and set the frequency manually. */
2364         if (machine_is_compatible("PowerBook2,1")) {
2365                 par->pll_limits.mclk = 70;
2366                 par->pll_limits.xclk = 53;
2367         }
2368 #endif
2369         if (pll)
2370                 par->pll_limits.pll_max = pll;
2371         if (mclk)
2372                 par->pll_limits.mclk = mclk;
2373         if (xclk)
2374                 par->pll_limits.xclk = xclk;
2375
2376         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2377         par->pll_per = 1000000/par->pll_limits.pll_max;
2378         par->mclk_per = 1000000/par->pll_limits.mclk;
2379         par->xclk_per = 1000000/par->pll_limits.xclk;
2380
2381         par->ref_clk_per = 1000000000000ULL / 14318180;
2382         xtal = "14.31818";
2383
2384 #ifdef CONFIG_FB_ATY_GX
2385         if (!M64_HAS(INTEGRATED)) {
2386                 u32 stat0;
2387                 u8 dac_type, dac_subtype, clk_type;
2388                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2389                 par->bus_type = (stat0 >> 0) & 0x07;
2390                 par->ram_type = (stat0 >> 3) & 0x07;
2391                 ramname = aty_gx_ram[par->ram_type];
2392                 /* FIXME: clockchip/RAMDAC probing? */
2393                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2394 #ifdef CONFIG_ATARI
2395                 clk_type = CLK_ATI18818_1;
2396                 dac_type = (stat0 >> 9) & 0x07;
2397                 if (dac_type == 0x07)
2398                         dac_subtype = DAC_ATT20C408;
2399                 else
2400                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2401 #else
2402                 dac_type = DAC_IBMRGB514;
2403                 dac_subtype = DAC_IBMRGB514;
2404                 clk_type = CLK_IBMRGB514;
2405 #endif
2406                 switch (dac_subtype) {
2407                 case DAC_IBMRGB514:
2408                         par->dac_ops = &aty_dac_ibm514;
2409                         break;
2410                 case DAC_ATI68860_B:
2411                 case DAC_ATI68860_C:
2412                         par->dac_ops = &aty_dac_ati68860b;
2413                         break;
2414                 case DAC_ATT20C408:
2415                 case DAC_ATT21C498:
2416                         par->dac_ops = &aty_dac_att21c498;
2417                         break;
2418                 default:
2419                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2420                         par->dac_ops = &aty_dac_unsupported;
2421                         break;
2422                 }
2423                 switch (clk_type) {
2424 #ifdef CONFIG_ATARI
2425                 case CLK_ATI18818_1:
2426                         par->pll_ops = &aty_pll_ati18818_1;
2427                         break;
2428 #else
2429                 case CLK_IBMRGB514:
2430                         par->pll_ops = &aty_pll_ibm514;
2431                         break;
2432 #endif
2433 #if 0 /* dead code */
2434                 case CLK_STG1703:
2435                         par->pll_ops = &aty_pll_stg1703;
2436                         break;
2437                 case CLK_CH8398:
2438                         par->pll_ops = &aty_pll_ch8398;
2439                         break;
2440                 case CLK_ATT20C408:
2441                         par->pll_ops = &aty_pll_att20c408;
2442                         break;
2443 #endif
2444                 default:
2445                         PRINTKI("aty_init: CLK type not implemented yet!");
2446                         par->pll_ops = &aty_pll_unsupported;
2447                         break;
2448                 }
2449         }
2450 #endif /* CONFIG_FB_ATY_GX */
2451 #ifdef CONFIG_FB_ATY_CT
2452         if (M64_HAS(INTEGRATED)) {
2453                 par->dac_ops = &aty_dac_ct;
2454                 par->pll_ops = &aty_pll_ct;
2455                 par->bus_type = PCI;
2456                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2457                 ramname = aty_ct_ram[par->ram_type];
2458                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2459                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2460                         par->pll_limits.mclk = 63;
2461         }
2462
2463         if (M64_HAS(GTB_DSP)) {
2464                 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2465
2466                 if (pll_ref_div) {
2467                         int diff1, diff2;
2468                         diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2469                         diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2470                         if (diff1 < 0)
2471                                 diff1 = -diff1;
2472                         if (diff2 < 0)
2473                                 diff2 = -diff2;
2474                         if (diff2 < diff1) {
2475                                 par->ref_clk_per = 1000000000000ULL / 29498928;
2476                                 xtal = "29.498928";
2477                         }
2478                 }
2479         }
2480 #endif /* CONFIG_FB_ATY_CT */
2481
2482         /* save previous video mode */
2483         aty_get_crtc(par, &saved_crtc);
2484         if(par->pll_ops->get_pll)
2485                 par->pll_ops->get_pll(info, &saved_pll);
2486
2487         i = aty_ld_le32(MEM_CNTL, par);
2488         gtb_memsize = M64_HAS(GTB_DSP);
2489         if (gtb_memsize)
2490                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2491                 case MEM_SIZE_512K:
2492                         info->fix.smem_len = 0x80000;
2493                         break;
2494                 case MEM_SIZE_1M:
2495                         info->fix.smem_len = 0x100000;
2496                         break;
2497                 case MEM_SIZE_2M_GTB:
2498                         info->fix.smem_len = 0x200000;
2499                         break;
2500                 case MEM_SIZE_4M_GTB:
2501                         info->fix.smem_len = 0x400000;
2502                         break;
2503                 case MEM_SIZE_6M_GTB:
2504                         info->fix.smem_len = 0x600000;
2505                         break;
2506                 case MEM_SIZE_8M_GTB:
2507                         info->fix.smem_len = 0x800000;
2508                         break;
2509                 default:
2510                         info->fix.smem_len = 0x80000;
2511         } else
2512                 switch (i & MEM_SIZE_ALIAS) {
2513                 case MEM_SIZE_512K:
2514                         info->fix.smem_len = 0x80000;
2515                         break;
2516                 case MEM_SIZE_1M:
2517                         info->fix.smem_len = 0x100000;
2518                         break;
2519                 case MEM_SIZE_2M:
2520                         info->fix.smem_len = 0x200000;
2521                         break;
2522                 case MEM_SIZE_4M:
2523                         info->fix.smem_len = 0x400000;
2524                         break;
2525                 case MEM_SIZE_6M:
2526                         info->fix.smem_len = 0x600000;
2527                         break;
2528                 case MEM_SIZE_8M:
2529                         info->fix.smem_len = 0x800000;
2530                         break;
2531                 default:
2532                         info->fix.smem_len = 0x80000;
2533                 }
2534
2535         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2536                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2537                         info->fix.smem_len += 0x400000;
2538         }
2539
2540         if (vram) {
2541                 info->fix.smem_len = vram * 1024;
2542                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2543                 if (info->fix.smem_len <= 0x80000)
2544                         i |= MEM_SIZE_512K;
2545                 else if (info->fix.smem_len <= 0x100000)
2546                         i |= MEM_SIZE_1M;
2547                 else if (info->fix.smem_len <= 0x200000)
2548                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2549                 else if (info->fix.smem_len <= 0x400000)
2550                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2551                 else if (info->fix.smem_len <= 0x600000)
2552                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2553                 else
2554                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2555                 aty_st_le32(MEM_CNTL, i, par);
2556         }
2557
2558         /*
2559          *  Reg Block 0 (CT-compatible block) is at mmio_start
2560          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2561          */
2562         if (M64_HAS(GX)) {
2563                 info->fix.mmio_len = 0x400;
2564                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2565         } else if (M64_HAS(CT)) {
2566                 info->fix.mmio_len = 0x400;
2567                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2568         } else if (M64_HAS(VT)) {
2569                 info->fix.mmio_start -= 0x400;
2570                 info->fix.mmio_len = 0x800;
2571                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2572         } else {/* GT */
2573                 info->fix.mmio_start -= 0x400;
2574                 info->fix.mmio_len = 0x800;
2575                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2576         }
2577
2578         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2579                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2580                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2581                par->pll_limits.mclk, par->pll_limits.xclk);
2582
2583 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2584         if (M64_HAS(INTEGRATED)) {
2585                 int i;
2586                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2587                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2588                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2589                        "debug atyfb: PLL",
2590                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2591                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2592                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2593                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2594                 for (i = 0; i < 40; i++)
2595                         printk(" %02x", aty_ld_pll_ct(i, par));
2596                 printk("\n");
2597         }
2598 #endif
2599         if(par->pll_ops->init_pll)
2600                 par->pll_ops->init_pll(info, &par->pll);
2601
2602         /*
2603          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2604          *  unless the auxiliary register aperture is used.
2605          */
2606
2607         if (!par->aux_start &&
2608                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2609                 info->fix.smem_len -= GUI_RESERVE;
2610
2611         /*
2612          *  Disable register access through the linear aperture
2613          *  if the auxiliary aperture is used so we can access
2614          *  the full 8 MB of video RAM on 8 MB boards.
2615          */
2616         if (par->aux_start)
2617                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2618
2619 #ifdef CONFIG_MTRR
2620         par->mtrr_aper = -1;
2621         par->mtrr_reg = -1;
2622         if (!nomtrr) {
2623                 /* Cover the whole resource. */
2624                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2625                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2626                         /* Make a hole for mmio. */
2627                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2628                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2629                         if (par->mtrr_reg < 0) {
2630                                 mtrr_del(par->mtrr_aper, 0, 0);
2631                                 par->mtrr_aper = -1;
2632                         }
2633                  }
2634         }
2635 #endif
2636
2637         info->fbops = &atyfb_ops;
2638         info->pseudo_palette = pseudo_palette;
2639         info->flags = FBINFO_DEFAULT           |
2640                       FBINFO_HWACCEL_IMAGEBLIT |
2641                       FBINFO_HWACCEL_FILLRECT  |
2642                       FBINFO_HWACCEL_COPYAREA  |
2643                       FBINFO_HWACCEL_YPAN;
2644
2645 #ifdef CONFIG_PMAC_BACKLIGHT
2646         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2647                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2648                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2649                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2650         } else
2651 #endif
2652         if (M64_HAS(MOBIL_BUS)) {
2653 #ifdef CONFIG_FB_ATY_BACKLIGHT
2654                 aty_bl_init (par);
2655 #endif
2656         }
2657
2658         memset(&var, 0, sizeof(var));
2659 #ifdef CONFIG_PPC
2660         if (machine_is(powermac)) {
2661                 /*
2662                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2663                  *         applies to all Mac video cards
2664                  */
2665                 if (mode) {
2666                         if (mac_find_mode(&var, info, mode, 8))
2667                                 has_var = 1;
2668                 } else {
2669                         if (default_vmode == VMODE_CHOOSE) {
2670                                 int sense;
2671                                 if (M64_HAS(G3_PB_1024x768))
2672                                         /* G3 PowerBook with 1024x768 LCD */
2673                                         default_vmode = VMODE_1024_768_60;
2674                                 else if (machine_is_compatible("iMac"))
2675                                         default_vmode = VMODE_1024_768_75;
2676                                 else if (machine_is_compatible
2677                                          ("PowerBook2,1"))
2678                                         /* iBook with 800x600 LCD */
2679                                         default_vmode = VMODE_800_600_60;
2680                                 else
2681                                         default_vmode = VMODE_640_480_67;
2682                                 sense = read_aty_sense(par);
2683                                 PRINTKI("monitor sense=%x, mode %d\n",
2684                                         sense,  mac_map_monitor_sense(sense));
2685                         }
2686                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2687                                 default_vmode = VMODE_640_480_60;
2688                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2689                                 default_cmode = CMODE_8;
2690                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2691                                                &var))
2692                                 has_var = 1;
2693                 }
2694         }
2695
2696 #endif /* !CONFIG_PPC */
2697
2698 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2699         if (!atyfb_get_timings_from_lcd(par, &var))
2700                 has_var = 1;
2701 #endif
2702
2703         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2704                 has_var = 1;
2705
2706         if (!has_var)
2707                 var = default_var;
2708
2709         if (noaccel)
2710                 var.accel_flags &= ~FB_ACCELF_TEXT;
2711         else
2712                 var.accel_flags |= FB_ACCELF_TEXT;
2713
2714         if (comp_sync != -1) {
2715                 if (!comp_sync)
2716                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2717                 else
2718                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2719         }
2720
2721         if (var.yres == var.yres_virtual) {
2722                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2723                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2724                 if (var.yres_virtual < var.yres)
2725                         var.yres_virtual = var.yres;
2726         }
2727
2728         if (atyfb_check_var(&var, info)) {
2729                 PRINTKE("can't set default video mode\n");
2730                 goto aty_init_exit;
2731         }
2732
2733 #ifdef __sparc__
2734         atyfb_save_palette(par, 0);
2735 #endif
2736
2737 #ifdef CONFIG_FB_ATY_CT
2738         if (!noaccel && M64_HAS(INTEGRATED))
2739                 aty_init_cursor(info);
2740 #endif /* CONFIG_FB_ATY_CT */
2741         info->var = var;
2742
2743         fb_alloc_cmap(&info->cmap, 256, 0);
2744
2745         if (register_framebuffer(info) < 0)
2746                 goto aty_init_exit;
2747
2748         fb_list = info;
2749
2750         PRINTKI("fb%d: %s frame buffer device on %s\n",
2751                info->node, info->fix.id, name);
2752         return 0;
2753
2754 aty_init_exit:
2755         /* restore video mode */
2756         aty_set_crtc(par, &saved_crtc);
2757         par->pll_ops->set_pll(info, &saved_pll);
2758
2759 #ifdef CONFIG_MTRR
2760         if (par->mtrr_reg >= 0) {
2761             mtrr_del(par->mtrr_reg, 0, 0);
2762             par->mtrr_reg = -1;
2763         }
2764         if (par->mtrr_aper >= 0) {
2765             mtrr_del(par->mtrr_aper, 0, 0);
2766             par->mtrr_aper = -1;
2767         }
2768 #endif
2769         return -1;
2770 }
2771
2772 #ifdef CONFIG_ATARI
2773 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2774 {
2775         char *p;
2776         unsigned long vmembase, size, guiregbase;
2777
2778         PRINTKI("store_video_par() '%s' \n", video_str);
2779
2780         if (!(p = strsep(&video_str, ";")) || !*p)
2781                 goto mach64_invalid;
2782         vmembase = simple_strtoul(p, NULL, 0);
2783         if (!(p = strsep(&video_str, ";")) || !*p)
2784                 goto mach64_invalid;
2785         size = simple_strtoul(p, NULL, 0);
2786         if (!(p = strsep(&video_str, ";")) || !*p)
2787                 goto mach64_invalid;
2788         guiregbase = simple_strtoul(p, NULL, 0);
2789
2790         phys_vmembase[m64_num] = vmembase;
2791         phys_size[m64_num] = size;
2792         phys_guiregbase[m64_num] = guiregbase;
2793         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2794                guiregbase);
2795         return 0;
2796
2797       mach64_invalid:
2798         phys_vmembase[m64_num] = 0;
2799         return -1;
2800 }
2801 #endif /* CONFIG_ATARI */
2802
2803     /*
2804      *  Blank the display.
2805      */
2806
2807 static int atyfb_blank(int blank, struct fb_info *info)
2808 {
2809         struct atyfb_par *par = (struct atyfb_par *) info->par;
2810         u32 gen_cntl;
2811
2812         if (par->lock_blank || par->asleep)
2813                 return 0;
2814
2815 #ifdef CONFIG_FB_ATY_BACKLIGHT
2816         if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2817                 aty_bl_set_power(info, FB_BLANK_POWERDOWN);
2818 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2819         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2820             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2821                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2822                 pm &= ~PWR_BLON;
2823                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2824         }
2825 #endif
2826
2827         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2828         switch (blank) {
2829                 case FB_BLANK_UNBLANK:
2830                         gen_cntl &= ~0x400004c;
2831                         break;
2832                 case FB_BLANK_NORMAL:
2833                         gen_cntl |= 0x4000040;
2834                         break;
2835                 case FB_BLANK_VSYNC_SUSPEND:
2836                         gen_cntl |= 0x4000048;
2837                         break;
2838                 case FB_BLANK_HSYNC_SUSPEND:
2839                         gen_cntl |= 0x4000044;
2840                         break;
2841                 case FB_BLANK_POWERDOWN:
2842                         gen_cntl |= 0x400004c;
2843                         break;
2844         }
2845         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2846
2847 #ifdef CONFIG_FB_ATY_BACKLIGHT
2848         if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2849                 aty_bl_set_power(info, FB_BLANK_UNBLANK);
2850 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2851         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2852             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2853                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2854                 pm |= PWR_BLON;
2855                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2856         }
2857 #endif
2858
2859         return 0;
2860 }
2861
2862 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2863                        const struct atyfb_par *par)
2864 {
2865 #ifdef CONFIG_ATARI
2866         out_8(&par->aty_cmap_regs->windex, regno);
2867         out_8(&par->aty_cmap_regs->lut, red);
2868         out_8(&par->aty_cmap_regs->lut, green);
2869         out_8(&par->aty_cmap_regs->lut, blue);
2870 #else
2871         writeb(regno, &par->aty_cmap_regs->windex);
2872         writeb(red, &par->aty_cmap_regs->lut);
2873         writeb(green, &par->aty_cmap_regs->lut);
2874         writeb(blue, &par->aty_cmap_regs->lut);
2875 #endif
2876 }
2877
2878     /*
2879      *  Set a single color register. The values supplied are already
2880      *  rounded down to the hardware's capabilities (according to the
2881      *  entries in the var structure). Return != 0 for invalid regno.
2882      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2883      */
2884
2885 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2886         u_int transp, struct fb_info *info)
2887 {
2888         struct atyfb_par *par = (struct atyfb_par *) info->par;
2889         int i, depth;
2890         u32 *pal = info->pseudo_palette;
2891
2892         depth = info->var.bits_per_pixel;
2893         if (depth == 16)
2894                 depth = (info->var.green.length == 5) ? 15 : 16;
2895
2896         if (par->asleep)
2897                 return 0;
2898
2899         if (regno > 255 ||
2900             (depth == 16 && regno > 63) ||
2901             (depth == 15 && regno > 31))
2902                 return 1;
2903
2904         red >>= 8;
2905         green >>= 8;
2906         blue >>= 8;
2907
2908         par->palette[regno].red = red;
2909         par->palette[regno].green = green;
2910         par->palette[regno].blue = blue;
2911
2912         if (regno < 16) {
2913                 switch (depth) {
2914                 case 15:
2915                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2916                         break;
2917                 case 16:
2918                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2919                         break;
2920                 case 24:
2921                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2922                         break;
2923                 case 32:
2924                         i = (regno << 8) | regno;
2925                         pal[regno] = (i << 16) | i;
2926                         break;
2927                 }
2928         }
2929
2930         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2931         if (M64_HAS(EXTRA_BRIGHT))
2932                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2933         aty_st_8(DAC_CNTL, i, par);
2934         aty_st_8(DAC_MASK, 0xff, par);
2935
2936         if (M64_HAS(INTEGRATED)) {
2937                 if (depth == 16) {
2938                         if (regno < 32)
2939                                 aty_st_pal(regno << 3, red,
2940                                            par->palette[regno<<1].green,
2941                                            blue, par);
2942                         red = par->palette[regno>>1].red;
2943                         blue = par->palette[regno>>1].blue;
2944                         regno <<= 2;
2945                 } else if (depth == 15) {
2946                         regno <<= 3;
2947                         for(i = 0; i < 8; i++) {
2948                             aty_st_pal(regno + i, red, green, blue, par);
2949                         }
2950                 }
2951         }
2952         aty_st_pal(regno, red, green, blue, par);
2953
2954         return 0;
2955 }
2956
2957 #ifdef CONFIG_PCI
2958
2959 #ifdef __sparc__
2960
2961 extern void (*prom_palette) (int);
2962
2963 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2964                         struct fb_info *info, unsigned long addr)
2965 {
2966         extern int con_is_present(void);
2967
2968         struct atyfb_par *par = info->par;
2969         struct pcidev_cookie *pcp;
2970         char prop[128];
2971         int node, len, i, j, ret;
2972         u32 mem, chip_id;
2973
2974         /* Do not attach when we have a serial console. */
2975         if (!con_is_present())
2976                 return -ENXIO;
2977
2978         /*
2979          * Map memory-mapped registers.
2980          */
2981         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2982         info->fix.mmio_start = addr + 0x7ffc00UL;
2983
2984         /*
2985          * Map in big-endian aperture.
2986          */
2987         info->screen_base = (char *) (addr + 0x800000UL);
2988         info->fix.smem_start = addr + 0x800000UL;
2989
2990         /*
2991          * Figure mmap addresses from PCI config space.
2992          * Split Framebuffer in big- and little-endian halfs.
2993          */
2994         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2995                 /* nothing */ ;
2996         j = i + 4;
2997
2998         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2999         if (!par->mmap_map) {
3000                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
3001                 return -ENOMEM;
3002         }
3003         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
3004
3005         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
3006                 struct resource *rp = &pdev->resource[i];
3007                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
3008                 unsigned long base;
3009                 u32 size, pbase;
3010
3011                 base = rp->start;
3012
3013                 io = (rp->flags & IORESOURCE_IO);
3014
3015                 size = rp->end - base + 1;
3016
3017                 pci_read_config_dword(pdev, breg, &pbase);
3018
3019                 if (io)
3020                         size &= ~1;
3021
3022                 /*
3023                  * Map the framebuffer a second time, this time without
3024                  * the braindead _PAGE_IE setting. This is used by the
3025                  * fixed Xserver, but we need to maintain the old mapping
3026                  * to stay compatible with older ones...
3027                  */
3028                 if (base == addr) {
3029                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3030                         par->mmap_map[j].poff = base & PAGE_MASK;
3031                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3032                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3033                         par->mmap_map[j].prot_flag = _PAGE_E;
3034                         j++;
3035                 }
3036
3037                 /*
3038                  * Here comes the old framebuffer mapping with _PAGE_IE
3039                  * set for the big endian half of the framebuffer...
3040                  */
3041                 if (base == addr) {
3042                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3043                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3044                         par->mmap_map[j].size = 0x800000;
3045                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3046                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3047                         size -= 0x800000;
3048                         j++;
3049                 }
3050
3051                 par->mmap_map[j].voff = pbase & PAGE_MASK;
3052                 par->mmap_map[j].poff = base & PAGE_MASK;
3053                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3054                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3055                 par->mmap_map[j].prot_flag = _PAGE_E;
3056                 j++;
3057         }
3058
3059         if((ret = correct_chipset(par)))
3060                 return ret;
3061
3062         if (IS_XL(pdev->device)) {
3063                 /*
3064                  * Fix PROMs idea of MEM_CNTL settings...
3065                  */
3066                 mem = aty_ld_le32(MEM_CNTL, par);
3067                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3068                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3069                         switch (mem & 0x0f) {
3070                         case 3:
3071                                 mem = (mem & ~(0x0f)) | 2;
3072                                 break;
3073                         case 7:
3074                                 mem = (mem & ~(0x0f)) | 3;
3075                                 break;
3076                         case 9:
3077                                 mem = (mem & ~(0x0f)) | 4;
3078                                 break;
3079                         case 11:
3080                                 mem = (mem & ~(0x0f)) | 5;
3081                                 break;
3082                         default:
3083                                 break;
3084                         }
3085                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3086                                 mem &= ~(0x00700000);
3087                 }
3088                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
3089                 aty_st_le32(MEM_CNTL, mem, par);
3090         }
3091
3092         /*
3093          * If this is the console device, we will set default video
3094          * settings to what the PROM left us with.
3095          */
3096         node = prom_getchild(prom_root_node);
3097         node = prom_searchsiblings(node, "aliases");
3098         if (node) {
3099                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3100                 if (len > 0) {
3101                         prop[len] = '\0';
3102                         node = prom_finddevice(prop);
3103                 } else
3104                         node = 0;
3105         }
3106
3107         pcp = pdev->sysdata;
3108         if (node == pcp->prom_node->node) {
3109                 struct fb_var_screeninfo *var = &default_var;
3110                 unsigned int N, P, Q, M, T, R;
3111                 u32 v_total, h_total;
3112                 struct crtc crtc;
3113                 u8 pll_regs[16];
3114                 u8 clock_cntl;
3115
3116                 crtc.vxres = prom_getintdefault(node, "width", 1024);
3117                 crtc.vyres = prom_getintdefault(node, "height", 768);
3118                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3119                 var->xoffset = var->yoffset = 0;
3120                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3121                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3122                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3123                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3124                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3125                 aty_crtc_to_var(&crtc, var);
3126
3127                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3128                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3129
3130                 /*
3131                  * Read the PLL to figure actual Refresh Rate.
3132                  */
3133                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3134                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3135                 for (i = 0; i < 16; i++)
3136                         pll_regs[i] = aty_ld_pll_ct(i, par);
3137
3138                 /*
3139                  * PLL Reference Divider M:
3140                  */
3141                 M = pll_regs[2];
3142
3143                 /*
3144                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3145                  */
3146                 N = pll_regs[7 + (clock_cntl & 3)];
3147
3148                 /*
3149                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3150                  */
3151                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3152
3153                 /*
3154                  * PLL Divider Q:
3155                  */
3156                 Q = N / P;
3157
3158                 /*
3159                  * Target Frequency:
3160                  *
3161                  *      T * M
3162                  * Q = -------
3163                  *      2 * R
3164                  *
3165                  * where R is XTALIN (= 14318 or 29498 kHz).
3166                  */
3167                 if (IS_XL(pdev->device))
3168                         R = 29498;
3169                 else
3170                         R = 14318;
3171
3172                 T = 2 * Q * R / M;
3173
3174                 default_var.pixclock = 1000000000 / T;
3175         }
3176
3177         return 0;
3178 }
3179
3180 #else /* __sparc__ */
3181
3182 #ifdef __i386__
3183 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3184 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3185 {
3186         u32 driv_inf_tab, sig;
3187         u16 lcd_ofs;
3188
3189         /* To support an LCD panel, we should know it's dimensions and
3190          *  it's desired pixel clock.
3191          * There are two ways to do it:
3192          *  - Check the startup video mode and calculate the panel
3193          *    size from it. This is unreliable.
3194          *  - Read it from the driver information table in the video BIOS.
3195         */
3196         /* Address of driver information table is at offset 0x78. */
3197         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3198
3199         /* Check for the driver information table signature. */
3200         sig = (*(u32 *)driv_inf_tab);
3201         if ((sig == 0x54504c24) || /* Rage LT pro */
3202                 (sig == 0x544d5224) || /* Rage mobility */
3203                 (sig == 0x54435824) || /* Rage XC */
3204                 (sig == 0x544c5824)) { /* Rage XL */
3205                 PRINTKI("BIOS contains driver information table.\n");
3206                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3207                 par->lcd_table = 0;
3208                 if (lcd_ofs != 0) {
3209                         par->lcd_table = bios_base + lcd_ofs;
3210                 }
3211         }
3212
3213         if (par->lcd_table != 0) {
3214                 char model[24];
3215                 char strbuf[16];
3216                 char refresh_rates_buf[100];
3217                 int id, tech, f, i, m, default_refresh_rate;
3218                 char *txtcolour;
3219                 char *txtmonitor;
3220                 char *txtdual;
3221                 char *txtformat;
3222                 u16 width, height, panel_type, refresh_rates;
3223                 u16 *lcdmodeptr;
3224                 u32 format;
3225                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3226                 /* The most important information is the panel size at
3227                  * offset 25 and 27, but there's some other nice information
3228                  * which we print to the screen.
3229                  */
3230                 id = *(u8 *)par->lcd_table;
3231                 strncpy(model,(char *)par->lcd_table+1,24);
3232                 model[23]=0;
3233
3234                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3235                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3236                 panel_type = *(u16 *)(par->lcd_table+29);
3237                 if (panel_type & 1)
3238                         txtcolour = "colour";
3239                 else
3240                         txtcolour = "monochrome";
3241                 if (panel_type & 2)
3242                         txtdual = "dual (split) ";
3243                 else
3244                         txtdual = "";
3245                 tech = (panel_type>>2) & 63;
3246                 switch (tech) {
3247                 case 0:
3248                         txtmonitor = "passive matrix";
3249                         break;
3250                 case 1:
3251                         txtmonitor = "active matrix";
3252                         break;
3253                 case 2:
3254                         txtmonitor = "active addressed STN";
3255                         break;
3256                 case 3:
3257                         txtmonitor = "EL";
3258                         break;
3259                 case 4:
3260                         txtmonitor = "plasma";
3261                         break;
3262                 default:
3263                         txtmonitor = "unknown";
3264                 }
3265                 format = *(u32 *)(par->lcd_table+57);
3266                 if (tech == 0 || tech == 2) {
3267                         switch (format & 7) {
3268                         case 0:
3269                                 txtformat = "12 bit interface";
3270                                 break;
3271                         case 1:
3272                                 txtformat = "16 bit interface";
3273                                 break;
3274                         case 2:
3275                                 txtformat = "24 bit interface";
3276                                 break;
3277                         default:
3278                                 txtformat = "unkown format";
3279                         }
3280                 } else {
3281                         switch (format & 7) {
3282                         case 0:
3283                                 txtformat = "8 colours";
3284                                 break;
3285                         case 1:
3286                                 txtformat = "512 colours";
3287                                 break;
3288                         case 2:
3289                                 txtformat = "4096 colours";
3290                                 break;
3291                         case 4:
3292                                 txtformat = "262144 colours (LT mode)";
3293                                 break;
3294                         case 5:
3295                                 txtformat = "16777216 colours";
3296                                 break;
3297                         case 6:
3298                                 txtformat = "262144 colours (FDPI-2 mode)";
3299                                 break;
3300                         default:
3301                                 txtformat = "unkown format";
3302                         }
3303                 }
3304                 PRINTKI("%s%s %s monitor detected: %s\n",
3305                         txtdual ,txtcolour, txtmonitor, model);
3306                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3307                         id, width, height, txtformat);
3308                 refresh_rates_buf[0] = 0;
3309                 refresh_rates = *(u16 *)(par->lcd_table+62);
3310                 m = 1;
3311                 f = 0;
3312                 for (i=0;i<16;i++) {
3313                         if (refresh_rates & m) {
3314                                 if (f == 0) {
3315                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3316                                         f++;
3317                                 } else {
3318                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3319                                 }
3320                                 strcat(refresh_rates_buf,strbuf);
3321                         }
3322                         m = m << 1;
3323                 }
3324                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3325                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3326                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3327                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3328                 /* We now need to determine the crtc parameters for the
3329                  * LCD monitor. This is tricky, because they are not stored
3330                  * individually in the BIOS. Instead, the BIOS contains a
3331                  * table of display modes that work for this monitor.
3332                  *
3333                  * The idea is that we search for a mode of the same dimensions
3334                  * as the dimensions of the LCD monitor. Say our LCD monitor
3335                  * is 800x600 pixels, we search for a 800x600 monitor.
3336                  * The CRTC parameters we find here are the ones that we need
3337                  * to use to simulate other resolutions on the LCD screen.
3338                  */
3339                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3340                 while (*lcdmodeptr != 0) {
3341                         u32 modeptr;
3342                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3343                         modeptr = bios_base + *lcdmodeptr;
3344
3345                         mwidth = *((u16 *)(modeptr+0));
3346                         mheight = *((u16 *)(modeptr+2));
3347
3348                         if (mwidth == width && mheight == height) {
3349                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3350                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3351                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3352                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3353                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3354                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3355
3356                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3357                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3358                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3359                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3360
3361                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3362                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3363                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3364                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3365
3366                                 par->lcd_vtotal++;
3367                                 par->lcd_vdisp++;
3368                                 lcd_vsync_start++;
3369
3370                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3371                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3372                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3373                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3374                                 break;
3375                         }
3376
3377                         lcdmodeptr++;
3378                 }
3379                 if (*lcdmodeptr == 0) {
3380                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3381                         /* To do: Switch to CRT if possible. */
3382                 } else {
3383                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3384                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3385                                 par->lcd_hdisp,
3386                                 par->lcd_hdisp + par->lcd_right_margin,
3387                                 par->lcd_hdisp + par->lcd_right_margin
3388                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3389                                 par->lcd_htotal,
3390                                 par->lcd_vdisp,
3391                                 par->lcd_vdisp + par->lcd_lower_margin,
3392                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3393                                 par->lcd_vtotal);
3394                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3395                                 par->lcd_pixclock,
3396                                 par->lcd_hblank_len - (par->lcd_right_margin +
3397                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3398                                 par->lcd_hdisp,
3399                                 par->lcd_right_margin,
3400                                 par->lcd_hsync_len,
3401                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3402                                 par->lcd_vdisp,
3403                                 par->lcd_lower_margin,
3404                                 par->lcd_vsync_len);
3405                 }
3406         }
3407 }
3408 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3409
3410 static int __devinit init_from_bios(struct atyfb_par *par)
3411 {
3412         u32 bios_base, rom_addr;
3413         int ret;
3414
3415         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3416         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3417
3418         /* The BIOS starts with 0xaa55. */
3419         if (*((u16 *)bios_base) == 0xaa55) {
3420
3421                 u8 *bios_ptr;
3422                 u16 rom_table_offset, freq_table_offset;
3423                 PLL_BLOCK_MACH64 pll_block;
3424
3425                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3426
3427                 /* check for frequncy table */
3428                 bios_ptr = (u8*)bios_base;
3429                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3430                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3431                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3432
3433                 PRINTKI("BIOS frequency table:\n");
3434                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3435                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3436                         pll_block.ref_freq, pll_block.ref_divider);
3437                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3438                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3439                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3440
3441                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3442                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3443                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3444                 par->pll_limits.ref_div = pll_block.ref_divider;
3445                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3446                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3447                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3448                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3449 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3450                 aty_init_lcd(par, bios_base);
3451 #endif
3452                 ret = 0;
3453         } else {
3454                 PRINTKE("no BIOS frequency table found, use parameters\n");
3455                 ret = -ENXIO;
3456         }
3457         iounmap((void* __iomem )bios_base);
3458
3459         return ret;
3460 }
3461 #endif /* __i386__ */
3462
3463 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3464 {
3465         struct atyfb_par *par = info->par;
3466         u16 tmp;
3467         unsigned long raddr;
3468         struct resource *rrp;
3469         int ret = 0;
3470
3471         raddr = addr + 0x7ff000UL;
3472         rrp = &pdev->resource[2];
3473         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3474                 par->aux_start = rrp->start;
3475                 par->aux_size = rrp->end - rrp->start + 1;
3476                 raddr = rrp->start;
3477                 PRINTKI("using auxiliary register aperture\n");
3478         }
3479
3480         info->fix.mmio_start = raddr;
3481         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3482         if (par->ati_regbase == 0)
3483                 return -ENOMEM;
3484
3485         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3486         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3487
3488         /*
3489          * Enable memory-space accesses using config-space
3490          * command register.
3491          */
3492         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3493         if (!(tmp & PCI_COMMAND_MEMORY)) {
3494                 tmp |= PCI_COMMAND_MEMORY;
3495                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3496         }
3497 #ifdef __BIG_ENDIAN
3498         /* Use the big-endian aperture */
3499         addr += 0x800000;
3500 #endif
3501
3502         /* Map in frame buffer */
3503         info->fix.smem_start = addr;
3504         info->screen_base = ioremap(addr, 0x800000);
3505         if (info->screen_base == NULL) {
3506                 ret = -ENOMEM;
3507                 goto atyfb_setup_generic_fail;
3508         }
3509
3510         if((ret = correct_chipset(par)))
3511                 goto atyfb_setup_generic_fail;
3512 #ifdef __i386__
3513         if((ret = init_from_bios(par)))
3514                 goto atyfb_setup_generic_fail;
3515 #endif
3516         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3517                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3518         else
3519                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3520
3521         /* according to ATI, we should use clock 3 for acelerated mode */
3522         par->clk_wr_offset = 3;
3523
3524         return 0;
3525
3526 atyfb_setup_generic_fail:
3527         iounmap(par->ati_regbase);
3528         par->ati_regbase = NULL;
3529         if (info->screen_base) {
3530                 iounmap(info->screen_base);
3531                 info->screen_base = NULL;
3532         }
3533         return ret;
3534 }
3535
3536 #endif /* !__sparc__ */
3537
3538 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3539 {
3540         unsigned long addr, res_start, res_size;
3541         struct fb_info *info;
3542         struct resource *rp;
3543         struct atyfb_par *par;
3544         int i, rc = -ENOMEM;
3545
3546         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3547                 if (pdev->device == aty_chips[i].pci_id)
3548                         break;
3549
3550         if (i < 0)
3551                 return -ENODEV;
3552
3553         /* Enable device in PCI config */
3554         if (pci_enable_device(pdev)) {
3555                 PRINTKE("Cannot enable PCI device\n");
3556                 return -ENXIO;
3557         }
3558
3559         /* Find which resource to use */
3560         rp = &pdev->resource[0];
3561         if (rp->flags & IORESOURCE_IO)
3562                 rp = &pdev->resource[1];
3563         addr = rp->start;
3564         if (!addr)
3565                 return -ENXIO;
3566
3567         /* Reserve space */
3568         res_start = rp->start;
3569         res_size = rp->end - rp->start + 1;
3570         if (!request_mem_region (res_start, res_size, "atyfb"))
3571                 return -EBUSY;
3572
3573         /* Allocate framebuffer */
3574         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3575         if (!info) {
3576                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3577                 return -ENOMEM;
3578         }
3579         par = info->par;
3580         info->fix = atyfb_fix;
3581         info->device = &pdev->dev;
3582         par->pci_id = aty_chips[i].pci_id;
3583         par->res_start = res_start;
3584         par->res_size = res_size;
3585         par->irq = pdev->irq;
3586         par->pdev = pdev;
3587
3588         /* Setup "info" structure */
3589 #ifdef __sparc__
3590         rc = atyfb_setup_sparc(pdev, info, addr);
3591 #else
3592         rc = atyfb_setup_generic(pdev, info, addr);
3593 #endif
3594         if (rc)
3595                 goto err_release_mem;
3596
3597         pci_set_drvdata(pdev, info);
3598
3599         /* Init chip & register framebuffer */
3600         if (aty_init(info, "PCI"))
3601                 goto err_release_io;
3602
3603 #ifdef __sparc__
3604         if (!prom_palette)
3605                 prom_palette = atyfb_palette;
3606
3607         /*
3608          * Add /dev/fb mmap values.
3609          */
3610         par->mmap_map[0].voff = 0x8000000000000000UL;
3611         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3612         par->mmap_map[0].size = info->fix.smem_len;
3613         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3614         par->mmap_map[0].prot_flag = _PAGE_E;
3615         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3616         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3617         par->mmap_map[1].size = PAGE_SIZE;
3618         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3619         par->mmap_map[1].prot_flag = _PAGE_E;
3620 #endif /* __sparc__ */
3621
3622         return 0;
3623
3624 err_release_io:
3625 #ifdef __sparc__
3626         kfree(par->mmap_map);
3627 #else
3628         if (par->ati_regbase)
3629                 iounmap(par->ati_regbase);
3630         if (info->screen_base)
3631                 iounmap(info->screen_base);
3632 #endif
3633 err_release_mem:
3634         if (par->aux_start)
3635                 release_mem_region(par->aux_start, par->aux_size);
3636
3637         release_mem_region(par->res_start, par->res_size);
3638         framebuffer_release(info);
3639
3640         return rc;
3641 }
3642
3643 #endif /* CONFIG_PCI */
3644
3645 #ifdef CONFIG_ATARI
3646
3647 static int __devinit atyfb_atari_probe(void)
3648 {
3649         struct atyfb_par *par;
3650         struct fb_info *info;
3651         int m64_num;
3652         u32 clock_r;
3653
3654         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3655                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3656                     !phys_guiregbase[m64_num]) {
3657                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3658                         continue;
3659                 }
3660
3661                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3662                 if (!info) {
3663                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3664                         return -ENOMEM;
3665                 }
3666                 par = info->par;
3667
3668                 info->fix = atyfb_fix;
3669
3670                 par->irq = (unsigned int) -1; /* something invalid */
3671
3672                 /*
3673                  *  Map the video memory (physical address given) to somewhere in the
3674                  *  kernel address space.
3675                  */
3676                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3677                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3678                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3679                                                 0xFC00ul;
3680                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3681
3682                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3683                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3684
3685                 switch (clock_r & 0x003F) {
3686                 case 0x12:
3687                         par->clk_wr_offset = 3; /*  */
3688                         break;
3689                 case 0x34:
3690                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3691                         break;
3692                 case 0x16:
3693                         par->clk_wr_offset = 1; /*  */
3694                         break;
3695                 case 0x38:
3696                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3697                         break;
3698                 }
3699
3700                 if (aty_init(info, "ISA bus")) {
3701                         if (info->screen_base)
3702                                 iounmap(info->screen_base);
3703                         if (par->ati_regbase)
3704                                 iounmap(par->ati_regbase);
3705                         framebuffer_release(info);
3706                         /* This is insufficient! kernel_map has added two large chunks!! */
3707                         return -ENXIO;
3708                 }
3709         }
3710 }
3711
3712 #endif /* CONFIG_ATARI */
3713
3714 #ifdef CONFIG_PCI
3715
3716 static void __devexit atyfb_remove(struct fb_info *info)
3717 {
3718         struct atyfb_par *par = (struct atyfb_par *) info->par;
3719
3720         /* restore video mode */
3721         aty_set_crtc(par, &saved_crtc);
3722         par->pll_ops->set_pll(info, &saved_pll);
3723
3724 #ifdef CONFIG_FB_ATY_BACKLIGHT
3725         if (M64_HAS(MOBIL_BUS))
3726                 aty_bl_exit(par);
3727 #endif
3728
3729         unregister_framebuffer(info);
3730
3731 #ifdef CONFIG_MTRR
3732         if (par->mtrr_reg >= 0) {
3733             mtrr_del(par->mtrr_reg, 0, 0);
3734             par->mtrr_reg = -1;
3735         }
3736         if (par->mtrr_aper >= 0) {
3737             mtrr_del(par->mtrr_aper, 0, 0);
3738             par->mtrr_aper = -1;
3739         }
3740 #endif
3741 #ifndef __sparc__
3742         if (par->ati_regbase)
3743                 iounmap(par->ati_regbase);
3744         if (info->screen_base)
3745                 iounmap(info->screen_base);
3746 #ifdef __BIG_ENDIAN
3747         if (info->sprite.addr)
3748                 iounmap(info->sprite.addr);
3749 #endif
3750 #endif
3751 #ifdef __sparc__
3752         kfree(par->mmap_map);
3753 #endif
3754         if (par->aux_start)
3755                 release_mem_region(par->aux_start, par->aux_size);
3756
3757         if (par->res_start)
3758                 release_mem_region(par->res_start, par->res_size);
3759
3760         framebuffer_release(info);
3761 }
3762
3763
3764 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3765 {
3766         struct fb_info *info = pci_get_drvdata(pdev);
3767
3768         atyfb_remove(info);
3769 }
3770
3771 /*
3772  * This driver uses its own matching table. That will be more difficult
3773  * to fix, so for now, we just match against any ATI ID and let the
3774  * probe() function find out what's up. That also mean we don't have
3775  * a module ID table though.
3776  */
3777 static struct pci_device_id atyfb_pci_tbl[] = {
3778         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3779           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3780         { 0, }
3781 };
3782
3783 static struct pci_driver atyfb_driver = {
3784         .name           = "atyfb",
3785         .id_table       = atyfb_pci_tbl,
3786         .probe          = atyfb_pci_probe,
3787         .remove         = __devexit_p(atyfb_pci_remove),
3788 #ifdef CONFIG_PM
3789         .suspend        = atyfb_pci_suspend,
3790         .resume         = atyfb_pci_resume,
3791 #endif /* CONFIG_PM */
3792 };
3793
3794 #endif /* CONFIG_PCI */
3795
3796 #ifndef MODULE
3797 static int __devinit atyfb_setup(char *options)
3798 {
3799         char *this_opt;
3800
3801         if (!options || !*options)
3802                 return 0;
3803
3804         while ((this_opt = strsep(&options, ",")) != NULL) {
3805                 if (!strncmp(this_opt, "noaccel", 7)) {
3806                         noaccel = 1;
3807 #ifdef CONFIG_MTRR
3808                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3809                         nomtrr = 1;
3810 #endif
3811                 } else if (!strncmp(this_opt, "vram:", 5))
3812                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3813                 else if (!strncmp(this_opt, "pll:", 4))
3814                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3815                 else if (!strncmp(this_opt, "mclk:", 5))
3816                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3817                 else if (!strncmp(this_opt, "xclk:", 5))
3818                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3819                 else if (!strncmp(this_opt, "comp_sync:", 10))
3820                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3821 #ifdef CONFIG_PPC
3822                 else if (!strncmp(this_opt, "vmode:", 6)) {
3823                         unsigned int vmode =
3824                             simple_strtoul(this_opt + 6, NULL, 0);
3825                         if (vmode > 0 && vmode <= VMODE_MAX)
3826                                 default_vmode = vmode;
3827                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3828                         unsigned int cmode =
3829                             simple_strtoul(this_opt + 6, NULL, 0);
3830                         switch (cmode) {
3831                         case 0:
3832                         case 8:
3833                                 default_cmode = CMODE_8;
3834                                 break;
3835                         case 15:
3836                         case 16:
3837                                 default_cmode = CMODE_16;
3838                                 break;
3839                         case 24:
3840                         case 32:
3841                                 default_cmode = CMODE_32;
3842                                 break;
3843                         }
3844                 }
3845 #endif
3846 #ifdef CONFIG_ATARI
3847                 /*
3848                  * Why do we need this silly Mach64 argument?
3849                  * We are already here because of mach64= so its redundant.
3850                  */
3851                 else if (MACH_IS_ATARI
3852                          && (!strncmp(this_opt, "Mach64:", 7))) {
3853                         static unsigned char m64_num;
3854                         static char mach64_str[80];
3855                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3856                         if (!store_video_par(mach64_str, m64_num)) {
3857                                 m64_num++;
3858                                 mach64_count = m64_num;
3859                         }
3860                 }
3861 #endif
3862                 else
3863                         mode = this_opt;
3864         }
3865         return 0;
3866 }
3867 #endif  /*  MODULE  */
3868
3869 static int __devinit atyfb_init(void)
3870 {
3871     int err1 = 1, err2 = 1;
3872 #ifndef MODULE
3873     char *option = NULL;
3874
3875     if (fb_get_options("atyfb", &option))
3876         return -ENODEV;
3877     atyfb_setup(option);
3878 #endif
3879
3880 #ifdef CONFIG_PCI
3881     err1 = pci_register_driver(&atyfb_driver);
3882 #endif
3883 #ifdef CONFIG_ATARI
3884     err2 = atyfb_atari_probe();
3885 #endif
3886
3887     return (err1 && err2) ? -ENODEV : 0;
3888 }
3889
3890 static void __exit atyfb_exit(void)
3891 {
3892 #ifdef CONFIG_PCI
3893         pci_unregister_driver(&atyfb_driver);
3894 #endif
3895 }
3896
3897 module_init(atyfb_init);
3898 module_exit(atyfb_exit);
3899
3900 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3901 MODULE_LICENSE("GPL");
3902 module_param(noaccel, bool, 0);
3903 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3904 module_param(vram, int, 0);
3905 MODULE_PARM_DESC(vram, "int: override size of video ram");
3906 module_param(pll, int, 0);
3907 MODULE_PARM_DESC(pll, "int: override video clock");
3908 module_param(mclk, int, 0);
3909 MODULE_PARM_DESC(mclk, "int: override memory clock");
3910 module_param(xclk, int, 0);
3911 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3912 module_param(comp_sync, int, 0);
3913 MODULE_PARM_DESC(comp_sync,
3914                  "Set composite sync signal to low (0) or high (1)");
3915 module_param(mode, charp, 0);
3916 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3917 #ifdef CONFIG_MTRR
3918 module_param(nomtrr, bool, 0);
3919 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3920 #endif