drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/kernel.h>
  55 #include <linux/errno.h>
  56 #include <linux/string.h>
  57 #include <linux/mm.h>
  58 #include <linux/slab.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/delay.h>
  61 #include <linux/console.h>
  62 #include <linux/fb.h>
  63 #include <linux/init.h>
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/wait.h>
  68 #include <linux/backlight.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/machdep.h>
  79 #include <asm/prom.h>
  80 #include "../macmodes.h"
  81 #endif
  82 #ifdef __sparc__
  83 #include <asm/pbm.h>
  84 #include <asm/fbio.h>
  85 #endif
  86
  87 #ifdef CONFIG_ADB_PMU
  88 #include <linux/adb.h>
  89 #include <linux/pmu.h>
  90 #endif
  91 #ifdef CONFIG_BOOTX_TEXT
  92 #include <asm/btext.h>
  93 #endif
  94 #ifdef CONFIG_PMAC_BACKLIGHT
  95 #include <asm/backlight.h>
  96 #endif
  97 #ifdef CONFIG_MTRR
  98 #include <asm/mtrr.h>
  99 #endif
 100
 101 /*
 102  * Debug flags.
 103  */
 104 #undef DEBUG
 105 /*#define DEBUG*/
 106
 107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 108 /*  - must be large enough to catch all GUI-Regs   */
 109 /*  - must be aligned to a PAGE boundary           */
 110 #define GUI_RESERVE     (1 * PAGE_SIZE)
 111
 112 /* FIXME: remove the FAIL definition */
 113 #define FAIL(msg) do { \
 114         if (!(var->activate & FB_ACTIVATE_TEST)) \
 115                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 116         return -EINVAL; \
 117 } while (0)
 118 #define FAIL_MAX(msg, x, _max_) do { \
 119         if (x > _max_) { \
 120                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 121                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 122                 return -EINVAL; \
 123         } \
 124 } while (0)
 125 #ifdef DEBUG
 126 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 127 #else
 128 #define DPRINTK(fmt, args...)
 129 #endif
 130
 131 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 132 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 133
 134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 135 static const u32 lt_lcd_regs[] = {
 136         CONFIG_PANEL_LG,
 137         LCD_GEN_CNTL_LG,
 138         DSTN_CONTROL_LG,
 139         HFB_PITCH_ADDR_LG,
 140         HORZ_STRETCHING_LG,
 141         VERT_STRETCHING_LG,
 142         0, /* EXT_VERT_STRETCH */
 143         LT_GIO_LG,
 144         POWER_MANAGEMENT_LG
 145 };
 146
 147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 148 {
 149         if (M64_HAS(LT_LCD_REGS)) {
 150                 aty_st_le32(lt_lcd_regs[index], val, par);
 151         } else {
 152                 unsigned long temp;
 153
 154                 /* write addr byte */
 155                 temp = aty_ld_le32(LCD_INDEX, par);
 156                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 157                 /* write the register value */
 158                 aty_st_le32(LCD_DATA, val, par);
 159         }
 160 }
 161
 162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 163 {
 164         if (M64_HAS(LT_LCD_REGS)) {
 165                 return aty_ld_le32(lt_lcd_regs[index], par);
 166         } else {
 167                 unsigned long temp;
 168
 169                 /* write addr byte */
 170                 temp = aty_ld_le32(LCD_INDEX, par);
 171                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 172                 /* read the register value */
 173                 return aty_ld_le32(LCD_DATA, par);
 174         }
 175 }
 176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 177
 178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 179 /*
 180  * ATIReduceRatio --
 181  *
 182  * Reduce a fraction by factoring out the largest common divider of the
 183  * fraction's numerator and denominator.
 184  */
 185 static void ATIReduceRatio(int *Numerator, int *Denominator)
 186 {
 187     int Multiplier, Divider, Remainder;
 188
 189     Multiplier = *Numerator;
 190     Divider = *Denominator;
 191
 192     while ((Remainder = Multiplier % Divider))
 193     {
 194         Multiplier = Divider;
 195         Divider = Remainder;
 196     }
 197
 198     *Numerator /= Divider;
 199     *Denominator /= Divider;
 200 }
 201 #endif
 202     /*
 203      *  The Hardware parameters for each card
 204      */
 205
 206 struct pci_mmap_map {
 207         unsigned long voff;
 208         unsigned long poff;
 209         unsigned long size;
 210         unsigned long prot_flag;
 211         unsigned long prot_mask;
 212 };
 213
 214 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 215         .id             = "ATY Mach64",
 216         .type           = FB_TYPE_PACKED_PIXELS,
 217         .visual         = FB_VISUAL_PSEUDOCOLOR,
 218         .xpanstep       = 8,
 219         .ypanstep       = 1,
 220 };
 221
 222     /*
 223      *  Frame buffer device API
 224      */
 225
 226 static int atyfb_open(struct fb_info *info, int user);
 227 static int atyfb_release(struct fb_info *info, int user);
 228 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 229 static int atyfb_set_par(struct fb_info *info);
 230 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 231         u_int transp, struct fb_info *info);
 232 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 233 static int atyfb_blank(int blank, struct fb_info *info);
 234 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 235 #ifdef __sparc__
 236 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 237 #endif
 238 static int atyfb_sync(struct fb_info *info);
 239
 240     /*
 241      *  Internal routines
 242      */
 243
 244 static int aty_init(struct fb_info *info);
 245 static void aty_resume_chip(struct fb_info *info);
 246 #ifdef CONFIG_ATARI
 247 static int store_video_par(char *videopar, unsigned char m64_num);
 248 #endif
 249
 250 static struct crtc saved_crtc;
 251 static union aty_pll saved_pll;
 252 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 253
 254 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 255 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 256 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 257 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 258 #ifdef CONFIG_PPC
 259 static int read_aty_sense(const struct atyfb_par *par);
 260 #endif
 261
 262
 263     /*
 264      *  Interface used by the world
 265      */
 266
 267 static struct fb_var_screeninfo default_var = {
 268         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 269         640, 480, 640, 480, 0, 0, 8, 0,
 270         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 271         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 272         0, FB_VMODE_NONINTERLACED
 273 };
 274
 275 static struct fb_videomode defmode = {
 276         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 277         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 278         0, FB_VMODE_NONINTERLACED
 279 };
 280
 281 static struct fb_ops atyfb_ops = {
 282         .owner          = THIS_MODULE,
 283         .fb_open        = atyfb_open,
 284         .fb_release     = atyfb_release,
 285         .fb_check_var   = atyfb_check_var,
 286         .fb_set_par     = atyfb_set_par,
 287         .fb_setcolreg   = atyfb_setcolreg,
 288         .fb_pan_display = atyfb_pan_display,
 289         .fb_blank       = atyfb_blank,
 290         .fb_ioctl       = atyfb_ioctl,
 291         .fb_fillrect    = atyfb_fillrect,
 292         .fb_copyarea    = atyfb_copyarea,
 293         .fb_imageblit   = atyfb_imageblit,
 294 #ifdef __sparc__
 295         .fb_mmap        = atyfb_mmap,
 296 #endif
 297         .fb_sync        = atyfb_sync,
 298 };
 299
 300 static int noaccel;
 301 #ifdef CONFIG_MTRR
 302 static int nomtrr;
 303 #endif
 304 static int vram;
 305 static int pll;
 306 static int mclk;
 307 static int xclk;
 308 static int comp_sync __devinitdata = -1;
 309 static char *mode;
 310
 311 #ifdef CONFIG_PMAC_BACKLIGHT
 312 static int backlight __devinitdata = 1;
 313 #else
 314 static int backlight __devinitdata = 0;
 315 #endif
 316
 317 #ifdef CONFIG_PPC
 318 static int default_vmode __devinitdata = VMODE_CHOOSE;
 319 static int default_cmode __devinitdata = CMODE_CHOOSE;
 320
 321 module_param_named(vmode, default_vmode, int, 0);
 322 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 323 module_param_named(cmode, default_cmode, int, 0);
 324 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 325 #endif
 326
 327 #ifdef CONFIG_ATARI
 328 static unsigned int mach64_count __devinitdata = 0;
 329 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
 330 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
 331 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
 332 #endif
 333
 334 /* top -> down is an evolution of mach64 chipset, any corrections? */
 335 #define ATI_CHIP_88800GX   (M64F_GX)
 336 #define ATI_CHIP_88800CX   (M64F_GX)
 337
 338 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 339 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 340
 341 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 342 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 343
 344 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 345 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 346 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 347
 348 /* FIXME what is this chip? */
 349 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 350
 351 /* make sets shorter */
 352 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 353
 354 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 355 /*#define ATI_CHIP_264GTDVD  ?*/
 356 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 357
 358 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 359 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 360 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 361
 362 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 363 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 364
 365 static struct {
 366         u16 pci_id;
 367         const char *name;
 368         int pll, mclk, xclk, ecp_max;
 369         u32 features;
 370 } aty_chips[] __devinitdata = {
 371 #ifdef CONFIG_FB_ATY_GX
 372         /* Mach64 GX */
 373         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 374         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 375 #endif /* CONFIG_FB_ATY_GX */
 376
 377 #ifdef CONFIG_FB_ATY_CT
 378         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 379         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 380
 381         /* FIXME what is this chip? */
 382         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 383
 384         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 385         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 386
 387         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 388         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 389
 390         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 391
 392         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 393
 394         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 395         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 396         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 397         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 398
 399         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 400         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 401         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 402         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 403         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 404
 405         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 406         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 407         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 408         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
 409         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 410
 411         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 412         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 413         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 414         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 415         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 416         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 417
 418         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 419         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 420         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 421         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 422 #endif /* CONFIG_FB_ATY_CT */
 423 };
 424
 425 /* can not fail */
 426 static int __devinit correct_chipset(struct atyfb_par *par)
 427 {
 428         u8 rev;
 429         u16 type;
 430         u32 chip_id;
 431         const char *name;
 432         int i;
 433
 434         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
 435                 if (par->pci_id == aty_chips[i].pci_id)
 436                         break;
 437
 438         name = aty_chips[i].name;
 439         par->pll_limits.pll_max = aty_chips[i].pll;
 440         par->pll_limits.mclk = aty_chips[i].mclk;
 441         par->pll_limits.xclk = aty_chips[i].xclk;
 442         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 443         par->features = aty_chips[i].features;
 444
 445         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 446         type = chip_id & CFG_CHIP_TYPE;
 447         rev = (chip_id & CFG_CHIP_REV) >> 24;
 448
 449         switch(par->pci_id) {
 450 #ifdef CONFIG_FB_ATY_GX
 451         case PCI_CHIP_MACH64GX:
 452                 if(type != 0x00d7)
 453                         return -ENODEV;
 454                 break;
 455         case PCI_CHIP_MACH64CX:
 456                 if(type != 0x0057)
 457                         return -ENODEV;
 458                 break;
 459 #endif
 460 #ifdef CONFIG_FB_ATY_CT
 461         case PCI_CHIP_MACH64VT:
 462                 switch (rev & 0x07) {
 463                 case 0x00:
 464                         switch (rev & 0xc0) {
 465                         case 0x00:
 466                                 name = "ATI264VT (A3) (Mach64 VT)";
 467                                 par->pll_limits.pll_max = 170;
 468                                 par->pll_limits.mclk = 67;
 469                                 par->pll_limits.xclk = 67;
 470                                 par->pll_limits.ecp_max = 80;
 471                                 par->features = ATI_CHIP_264VT;
 472                                 break;
 473                         case 0x40:
 474                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 475                                 par->pll_limits.pll_max = 200;
 476                                 par->pll_limits.mclk = 67;
 477                                 par->pll_limits.xclk = 67;
 478                                 par->pll_limits.ecp_max = 80;
 479                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 480                                 break;
 481                         }
 482                         break;
 483                 case 0x01:
 484                         name = "ATI264VT3 (B1) (Mach64 VT)";
 485                         par->pll_limits.pll_max = 200;
 486                         par->pll_limits.mclk = 67;
 487                         par->pll_limits.xclk = 67;
 488                         par->pll_limits.ecp_max = 80;
 489                         par->features = ATI_CHIP_264VTB;
 490                         break;
 491                 case 0x02:
 492                         name = "ATI264VT3 (B2) (Mach64 VT)";
 493                         par->pll_limits.pll_max = 200;
 494                         par->pll_limits.mclk = 67;
 495                         par->pll_limits.xclk = 67;
 496                         par->pll_limits.ecp_max = 80;
 497                         par->features = ATI_CHIP_264VT3;
 498                         break;
 499                 }
 500                 break;
 501         case PCI_CHIP_MACH64GT:
 502                 switch (rev & 0x07) {
 503                 case 0x01:
 504                         name = "3D RAGE II (Mach64 GT)";
 505                         par->pll_limits.pll_max = 170;
 506                         par->pll_limits.mclk = 67;
 507                         par->pll_limits.xclk = 67;
 508                         par->pll_limits.ecp_max = 80;
 509                         par->features = ATI_CHIP_264GTB;
 510                         break;
 511                 case 0x02:
 512                         name = "3D RAGE II+ (Mach64 GT)";
 513                         par->pll_limits.pll_max = 200;
 514                         par->pll_limits.mclk = 67;
 515                         par->pll_limits.xclk = 67;
 516                         par->pll_limits.ecp_max = 100;
 517                         par->features = ATI_CHIP_264GTB;
 518                         break;
 519                 }
 520                 break;
 521 #endif
 522         }
 523
 524         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 525         return 0;
 526 }
 527
 528 static char ram_dram[] __devinitdata = "DRAM";
 529 static char ram_resv[] __devinitdata = "RESV";
 530 #ifdef CONFIG_FB_ATY_GX
 531 static char ram_vram[] __devinitdata = "VRAM";
 532 #endif /* CONFIG_FB_ATY_GX */
 533 #ifdef CONFIG_FB_ATY_CT
 534 static char ram_edo[] __devinitdata = "EDO";
 535 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 536 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 537 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 538 static char ram_off[] __devinitdata = "OFF";
 539 #endif /* CONFIG_FB_ATY_CT */
 540
 541
 542 static u32 pseudo_palette[17];
 543
 544 #ifdef CONFIG_FB_ATY_GX
 545 static char *aty_gx_ram[8] __devinitdata = {
 546         ram_dram, ram_vram, ram_vram, ram_dram,
 547         ram_dram, ram_vram, ram_vram, ram_resv
 548 };
 549 #endif /* CONFIG_FB_ATY_GX */
 550
 551 #ifdef CONFIG_FB_ATY_CT
 552 static char *aty_ct_ram[8] __devinitdata = {
 553         ram_off, ram_dram, ram_edo, ram_edo,
 554         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 555 };
 556 #endif /* CONFIG_FB_ATY_CT */
 557
 558 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 559 {
 560         u32 pixclock = var->pixclock;
 561 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 562         u32 lcd_on_off;
 563         par->pll.ct.xres = 0;
 564         if (par->lcd_table != 0) {
 565                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 566                 if(lcd_on_off & LCD_ON) {
 567                         par->pll.ct.xres = var->xres;
 568                         pixclock = par->lcd_pixclock;
 569                 }
 570         }
 571 #endif
 572         return pixclock;
 573 }
 574
 575 #if defined(CONFIG_PPC)
 576
 577 /*
 578  *  Apple monitor sense
 579  */
 580
 581 static int __devinit read_aty_sense(const struct atyfb_par *par)
 582 {
 583         int sense, i;
 584
 585         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 586         __delay(200);
 587         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 588         __delay(2000);
 589         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 590         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 591
 592         /* drive each sense line low in turn and collect the other 2 */
 593         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 594         __delay(2000);
 595         i = aty_ld_le32(GP_IO, par);
 596         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 597         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 598         __delay(200);
 599
 600         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 601         __delay(2000);
 602         i = aty_ld_le32(GP_IO, par);
 603         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 604         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 605         __delay(200);
 606
 607         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 608         __delay(2000);
 609         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 610         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 611         return sense;
 612 }
 613
 614 #endif /* defined(CONFIG_PPC) */
 615
 616 /* ------------------------------------------------------------------------- */
 617
 618 /*
 619  *  CRTC programming
 620  */
 621
 622 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 623 {
 624 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 625         if (par->lcd_table != 0) {
 626                 if(!M64_HAS(LT_LCD_REGS)) {
 627                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 628                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 629                 }
 630                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 631                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 632
 633
 634                 /* switch to non shadow registers */
 635                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 636                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 637
 638                 /* save stretching */
 639                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 640                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 641                 if (!M64_HAS(LT_LCD_REGS))
 642                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 643         }
 644 #endif
 645         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 646         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 647         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 648         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 649         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 650         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 651         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 652
 653 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 654         if (par->lcd_table != 0) {
 655                 /* switch to shadow registers */
 656                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 657                         SHADOW_EN | SHADOW_RW_EN, par);
 658
 659                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 660                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 661                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 662                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 663
 664                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 665         }
 666 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 667 }
 668
 669 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 670 {
 671 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 672         if (par->lcd_table != 0) {
 673                 /* stop CRTC */
 674                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 675
 676                 /* update non-shadow registers first */
 677                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 678                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 679                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 680
 681                 /* temporarily disable stretching */
 682                 aty_st_lcd(HORZ_STRETCHING,
 683                         crtc->horz_stretching &
 684                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 685                 aty_st_lcd(VERT_STRETCHING,
 686                         crtc->vert_stretching &
 687                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 688                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 689         }
 690 #endif
 691         /* turn off CRT */
 692         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 693
 694         DPRINTK("setting up CRTC\n");
 695         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 696             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 697             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 698             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 699
 700         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 701         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 702         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 703         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 704         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 705         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 706         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 707
 708         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 709         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 710         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 711         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 712         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 713         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 714
 715         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 716 #if 0
 717         FIXME
 718         if (par->accel_flags & FB_ACCELF_TEXT)
 719                 aty_init_engine(par, info);
 720 #endif
 721 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 722         /* after setting the CRTC registers we should set the LCD registers. */
 723         if (par->lcd_table != 0) {
 724                 /* switch to shadow registers */
 725                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 726                         (SHADOW_EN | SHADOW_RW_EN), par);
 727
 728                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 729                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 730                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 731
 732                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 733                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 734                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 735                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 736
 737                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 738                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 739                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 740                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 741
 742                 /* restore CRTC selection & shadow state and enable stretching */
 743                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 744                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 745                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 746                 if(!M64_HAS(LT_LCD_REGS))
 747                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 748
 749                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 750                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 751                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 752                 if(!M64_HAS(LT_LCD_REGS)) {
 753                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 754                     aty_ld_le32(LCD_INDEX, par);
 755                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 756                 }
 757         }
 758 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 759 }
 760
 761 static int aty_var_to_crtc(const struct fb_info *info,
 762         const struct fb_var_screeninfo *var, struct crtc *crtc)
 763 {
 764         struct atyfb_par *par = (struct atyfb_par *) info->par;
 765         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 766         u32 sync, vmode, vdisplay;
 767         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 768         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 769         u32 pix_width, dp_pix_width, dp_chain_mask;
 770
 771         /* input */
 772         xres = var->xres;
 773         yres = var->yres;
 774         vxres = var->xres_virtual;
 775         vyres = var->yres_virtual;
 776         xoffset = var->xoffset;
 777         yoffset = var->yoffset;
 778         bpp = var->bits_per_pixel;
 779         if (bpp == 16)
 780                 bpp = (var->green.length == 5) ? 15 : 16;
 781         sync = var->sync;
 782         vmode = var->vmode;
 783
 784         /* convert (and round up) and validate */
 785         if (vxres < xres + xoffset)
 786                 vxres = xres + xoffset;
 787         h_disp = xres;
 788
 789         if (vyres < yres + yoffset)
 790                 vyres = yres + yoffset;
 791         v_disp = yres;
 792
 793         if (bpp <= 8) {
 794                 bpp = 8;
 795                 pix_width = CRTC_PIX_WIDTH_8BPP;
 796                 dp_pix_width =
 797                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 798                     BYTE_ORDER_LSB_TO_MSB;
 799                 dp_chain_mask = DP_CHAIN_8BPP;
 800         } else if (bpp <= 15) {
 801                 bpp = 16;
 802                 pix_width = CRTC_PIX_WIDTH_15BPP;
 803                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 804                     BYTE_ORDER_LSB_TO_MSB;
 805                 dp_chain_mask = DP_CHAIN_15BPP;
 806         } else if (bpp <= 16) {
 807                 bpp = 16;
 808                 pix_width = CRTC_PIX_WIDTH_16BPP;
 809                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 810                     BYTE_ORDER_LSB_TO_MSB;
 811                 dp_chain_mask = DP_CHAIN_16BPP;
 812         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 813                 bpp = 24;
 814                 pix_width = CRTC_PIX_WIDTH_24BPP;
 815                 dp_pix_width =
 816                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 817                     BYTE_ORDER_LSB_TO_MSB;
 818                 dp_chain_mask = DP_CHAIN_24BPP;
 819         } else if (bpp <= 32) {
 820                 bpp = 32;
 821                 pix_width = CRTC_PIX_WIDTH_32BPP;
 822                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 823                     BYTE_ORDER_LSB_TO_MSB;
 824                 dp_chain_mask = DP_CHAIN_32BPP;
 825         } else
 826                 FAIL("invalid bpp");
 827
 828         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 829                 FAIL("not enough video RAM");
 830
 831         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 832         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 833
 834         if((xres > 1600) || (yres > 1200)) {
 835                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 836                 "select anoter resolution.");
 837         }
 838         h_sync_strt = h_disp + var->right_margin;
 839         h_sync_end = h_sync_strt + var->hsync_len;
 840         h_sync_dly  = var->right_margin & 7;
 841         h_total = h_sync_end + h_sync_dly + var->left_margin;
 842
 843         v_sync_strt = v_disp + var->lower_margin;
 844         v_sync_end = v_sync_strt + var->vsync_len;
 845         v_total = v_sync_end + var->upper_margin;
 846
 847 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 848         if (par->lcd_table != 0) {
 849                 if(!M64_HAS(LT_LCD_REGS)) {
 850                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 851                     crtc->lcd_index = lcd_index &
 852                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 853                     aty_st_le32(LCD_INDEX, lcd_index, par);
 854                 }
 855
 856                 if (!M64_HAS(MOBIL_BUS))
 857                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 858
 859                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 860                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 861
 862                 crtc->lcd_gen_cntl &=
 863                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 864                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 865                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 866                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 867
 868                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 869                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 870                         /* We cannot display the mode on the LCD. If the CRT is enabled
 871                            we can turn off the LCD.
 872                            If the CRT is off, it isn't a good idea to switch it on; we don't
 873                            know if one is connected. So it's better to fail then.
 874                          */
 875                         if (crtc->lcd_gen_cntl & CRT_ON) {
 876                                 if (!(var->activate & FB_ACTIVATE_TEST))
 877                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 878                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 879                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 880                         } else {
 881                                 if (!(var->activate & FB_ACTIVATE_TEST))
 882                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 883                                 return -EINVAL;
 884                         }
 885                 }
 886         }
 887
 888         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 889                 int VScan = 1;
 890                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 891                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 892                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 893
 894                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 895
 896                 /* This is horror! When we simulate, say 640x480 on an 800x600
 897                    LCD monitor, the CRTC should be programmed 800x600 values for
 898                    the non visible part, but 640x480 for the visible part.
 899                    This code has been tested on a laptop with it's 1400x1050 LCD
 900                    monitor and a conventional monitor both switched on.
 901                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 902                     works with little glitches also with DOUBLESCAN modes
 903                  */
 904                 if (yres < par->lcd_height) {
 905                         VScan = par->lcd_height / yres;
 906                         if(VScan > 1) {
 907                                 VScan = 2;
 908                                 vmode |= FB_VMODE_DOUBLE;
 909                         }
 910                 }
 911
 912                 h_sync_strt = h_disp + par->lcd_right_margin;
 913                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 914                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 915                 h_total = h_disp + par->lcd_hblank_len;
 916
 917                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 918                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 919                 v_total = v_disp + par->lcd_vblank_len / VScan;
 920         }
 921 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 922
 923         h_disp = (h_disp >> 3) - 1;
 924         h_sync_strt = (h_sync_strt >> 3) - 1;
 925         h_sync_end = (h_sync_end >> 3) - 1;
 926         h_total = (h_total >> 3) - 1;
 927         h_sync_wid = h_sync_end - h_sync_strt;
 928
 929         FAIL_MAX("h_disp too large", h_disp, 0xff);
 930         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 931         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 932         if(h_sync_wid > 0x1f)
 933                 h_sync_wid = 0x1f;
 934         FAIL_MAX("h_total too large", h_total, 0x1ff);
 935
 936         if (vmode & FB_VMODE_DOUBLE) {
 937                 v_disp <<= 1;
 938                 v_sync_strt <<= 1;
 939                 v_sync_end <<= 1;
 940                 v_total <<= 1;
 941         }
 942
 943         vdisplay = yres;
 944 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 945         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 946                 vdisplay  = par->lcd_height;
 947 #endif
 948
 949         v_disp--;
 950         v_sync_strt--;
 951         v_sync_end--;
 952         v_total--;
 953         v_sync_wid = v_sync_end - v_sync_strt;
 954
 955         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 956         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 957         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 958         if(v_sync_wid > 0x1f)
 959                 v_sync_wid = 0x1f;
 960         FAIL_MAX("v_total too large", v_total, 0x7ff);
 961
 962         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 963
 964         /* output */
 965         crtc->vxres = vxres;
 966         crtc->vyres = vyres;
 967         crtc->xoffset = xoffset;
 968         crtc->yoffset = yoffset;
 969         crtc->bpp = bpp;
 970         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 971         crtc->vline_crnt_vline = 0;
 972
 973         crtc->h_tot_disp = h_total | (h_disp<<16);
 974         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 975                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 976         crtc->v_tot_disp = v_total | (v_disp<<16);
 977         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 978
 979         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 980         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 981         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 982
 983         /* Enable doublescan mode if requested */
 984         if (vmode & FB_VMODE_DOUBLE)
 985                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 986         /* Enable interlaced mode if requested */
 987         if (vmode & FB_VMODE_INTERLACED)
 988                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 989 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 990         if (par->lcd_table != 0) {
 991                 vdisplay = yres;
 992                 if(vmode & FB_VMODE_DOUBLE)
 993                         vdisplay <<= 1;
 994                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 995                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 996                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 997                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 998                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
 999
1000                 /* MOBILITY M1 tested, FIXME: LT */
1001                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1002                 if (!M64_HAS(LT_LCD_REGS))
1003                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1004                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1005
1006                 crtc->horz_stretching &=
1007                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1008                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1009                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1010                         do {
1011                                 /*
1012                                 * The horizontal blender misbehaves when HDisplay is less than a
1013                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1014                                 * stretch such modes enough.  Use pixel replication instead of
1015                                 * blending to stretch modes that can be made to exactly fit the
1016                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1017                                 * pixel-replicated mode to be slightly wider or narrower than the
1018                                 * panel width.  It also causes a mode that is exactly half as wide
1019                                 * as the panel to be pixel-replicated, rather than blended.
1020                                 */
1021                                 int HDisplay  = xres & ~7;
1022                                 int nStretch  = par->lcd_width / HDisplay;
1023                                 int Remainder = par->lcd_width % HDisplay;
1024
1025                                 if ((!Remainder && ((nStretch > 2))) ||
1026                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1027                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1028                                         int horz_stretch_loop = -1, BestRemainder;
1029                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1030                                         int Index = 5;
1031                                         ATIReduceRatio(&Numerator, &Denominator);
1032
1033                                         BestRemainder = (Numerator * 16) / Denominator;
1034                                         while (--Index >= 0) {
1035                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1036                                                         Denominator;
1037                                                 if (Remainder < BestRemainder) {
1038                                                         horz_stretch_loop = Index;
1039                                                         if (!(BestRemainder = Remainder))
1040                                                                 break;
1041                                                 }
1042                                         }
1043
1044                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1045                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1046                                                 int reuse_previous = 1;
1047
1048                                                 Index = StretchLoops[horz_stretch_loop];
1049
1050                                                 while (--Index >= 0) {
1051                                                         if (Accumulator > 0)
1052                                                                 horz_stretch_ratio |= reuse_previous;
1053                                                         else
1054                                                                 Accumulator += Denominator;
1055                                                         Accumulator -= Numerator;
1056                                                         reuse_previous <<= 1;
1057                                                 }
1058
1059                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1060                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1061                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1062                                                 break;      /* Out of the do { ... } while (0) */
1063                                         }
1064                                 }
1065
1066                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1067                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1068                         } while (0);
1069                 }
1070
1071                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1072                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1073                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1074
1075                         if (!M64_HAS(LT_LCD_REGS) &&
1076                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1077                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1078                 } else {
1079                         /*
1080                          * Don't use vertical blending if the mode is too wide or not
1081                          * vertically stretched.
1082                          */
1083                         crtc->vert_stretching = 0;
1084                 }
1085                 /* copy to shadow crtc */
1086                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1087                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1088                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1089                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1090         }
1091 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1092
1093         if (M64_HAS(MAGIC_FIFO)) {
1094                 /* FIXME: display FIFO low watermark values */
1095                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1096         }
1097         crtc->dp_pix_width = dp_pix_width;
1098         crtc->dp_chain_mask = dp_chain_mask;
1099
1100         return 0;
1101 }
1102
1103 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1104 {
1105         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1106         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1107             h_sync_pol;
1108         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1109         u32 pix_width;
1110         u32 double_scan, interlace;
1111
1112         /* input */
1113         h_total = crtc->h_tot_disp & 0x1ff;
1114         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1115         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1116         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1117         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1118         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1119         v_total = crtc->v_tot_disp & 0x7ff;
1120         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1121         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1122         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1123         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1124         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1125         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1126         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1127         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1128
1129         /* convert */
1130         xres = (h_disp + 1) * 8;
1131         yres = v_disp + 1;
1132         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1133         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1134         hslen = h_sync_wid * 8;
1135         upper = v_total - v_sync_strt - v_sync_wid;
1136         lower = v_sync_strt - v_disp;
1137         vslen = v_sync_wid;
1138         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1139             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1140             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1141
1142         switch (pix_width) {
1143 #if 0
1144         case CRTC_PIX_WIDTH_4BPP:
1145                 bpp = 4;
1146                 var->red.offset = 0;
1147                 var->red.length = 8;
1148                 var->green.offset = 0;
1149                 var->green.length = 8;
1150                 var->blue.offset = 0;
1151                 var->blue.length = 8;
1152                 var->transp.offset = 0;
1153                 var->transp.length = 0;
1154                 break;
1155 #endif
1156         case CRTC_PIX_WIDTH_8BPP:
1157                 bpp = 8;
1158                 var->red.offset = 0;
1159                 var->red.length = 8;
1160                 var->green.offset = 0;
1161                 var->green.length = 8;
1162                 var->blue.offset = 0;
1163                 var->blue.length = 8;
1164                 var->transp.offset = 0;
1165                 var->transp.length = 0;
1166                 break;
1167         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1168                 bpp = 16;
1169                 var->red.offset = 10;
1170                 var->red.length = 5;
1171                 var->green.offset = 5;
1172                 var->green.length = 5;
1173                 var->blue.offset = 0;
1174                 var->blue.length = 5;
1175                 var->transp.offset = 0;
1176                 var->transp.length = 0;
1177                 break;
1178         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1179                 bpp = 16;
1180                 var->red.offset = 11;
1181                 var->red.length = 5;
1182                 var->green.offset = 5;
1183                 var->green.length = 6;
1184                 var->blue.offset = 0;
1185                 var->blue.length = 5;
1186                 var->transp.offset = 0;
1187                 var->transp.length = 0;
1188                 break;
1189         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1190                 bpp = 24;
1191                 var->red.offset = 16;
1192                 var->red.length = 8;
1193                 var->green.offset = 8;
1194                 var->green.length = 8;
1195                 var->blue.offset = 0;
1196                 var->blue.length = 8;
1197                 var->transp.offset = 0;
1198                 var->transp.length = 0;
1199                 break;
1200         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1201                 bpp = 32;
1202                 var->red.offset = 16;
1203                 var->red.length = 8;
1204                 var->green.offset = 8;
1205                 var->green.length = 8;
1206                 var->blue.offset = 0;
1207                 var->blue.length = 8;
1208                 var->transp.offset = 24;
1209                 var->transp.length = 8;
1210                 break;
1211         default:
1212                 PRINTKE("Invalid pixel width\n");
1213                 return -EINVAL;
1214         }
1215
1216         /* output */
1217         var->xres = xres;
1218         var->yres = yres;
1219         var->xres_virtual = crtc->vxres;
1220         var->yres_virtual = crtc->vyres;
1221         var->bits_per_pixel = bpp;
1222         var->left_margin = left;
1223         var->right_margin = right;
1224         var->upper_margin = upper;
1225         var->lower_margin = lower;
1226         var->hsync_len = hslen;
1227         var->vsync_len = vslen;
1228         var->sync = sync;
1229         var->vmode = FB_VMODE_NONINTERLACED;
1230         /* In double scan mode, the vertical parameters are doubled, so we need to
1231            half them to get the right values.
1232            In interlaced mode the values are already correct, so no correction is
1233            necessary.
1234          */
1235         if (interlace)
1236                 var->vmode = FB_VMODE_INTERLACED;
1237
1238         if (double_scan) {
1239                 var->vmode = FB_VMODE_DOUBLE;
1240                 var->yres>>=1;
1241                 var->upper_margin>>=1;
1242                 var->lower_margin>>=1;
1243                 var->vsync_len>>=1;
1244         }
1245
1246         return 0;
1247 }
1248
1249 /* ------------------------------------------------------------------------- */
1250
1251 static int atyfb_set_par(struct fb_info *info)
1252 {
1253         struct atyfb_par *par = (struct atyfb_par *) info->par;
1254         struct fb_var_screeninfo *var = &info->var;
1255         u32 tmp, pixclock;
1256         int err;
1257 #ifdef DEBUG
1258         struct fb_var_screeninfo debug;
1259         u32 pixclock_in_ps;
1260 #endif
1261         if (par->asleep)
1262                 return 0;
1263
1264         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1265                 return err;
1266
1267         pixclock = atyfb_get_pixclock(var, par);
1268
1269         if (pixclock == 0) {
1270                 PRINTKE("Invalid pixclock\n");
1271                 return -EINVAL;
1272         } else {
1273                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1274                         return err;
1275         }
1276
1277         par->accel_flags = var->accel_flags; /* hack */
1278
1279         if (var->accel_flags) {
1280                 info->fbops->fb_sync = atyfb_sync;
1281                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1282         } else {
1283                 info->fbops->fb_sync = NULL;
1284                 info->flags |= FBINFO_HWACCEL_DISABLED;
1285         }
1286
1287         if (par->blitter_may_be_busy)
1288                 wait_for_idle(par);
1289
1290         aty_set_crtc(par, &par->crtc);
1291         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1292         par->pll_ops->set_pll(info, &par->pll);
1293
1294 #ifdef DEBUG
1295         if(par->pll_ops && par->pll_ops->pll_to_var)
1296                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1297         else
1298                 pixclock_in_ps = 0;
1299
1300         if(0 == pixclock_in_ps) {
1301                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1302                 pixclock_in_ps = pixclock;
1303         }
1304
1305         memset(&debug, 0, sizeof(debug));
1306         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1307                 u32 hSync, vRefresh;
1308                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1309                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1310
1311                 h_disp = debug.xres;
1312                 h_sync_strt = h_disp + debug.right_margin;
1313                 h_sync_end = h_sync_strt + debug.hsync_len;
1314                 h_total = h_sync_end + debug.left_margin;
1315                 v_disp = debug.yres;
1316                 v_sync_strt = v_disp + debug.lower_margin;
1317                 v_sync_end = v_sync_strt + debug.vsync_len;
1318                 v_total = v_sync_end + debug.upper_margin;
1319
1320                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1321                 vRefresh = (hSync * 1000) / v_total;
1322                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1323                 vRefresh *= 2;
1324                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1325                 vRefresh /= 2;
1326
1327                 DPRINTK("atyfb_set_par\n");
1328                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1329                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1330                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1331                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1332                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1333                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1334                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1335                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1336                         h_disp, h_sync_strt, h_sync_end, h_total,
1337                         v_disp, v_sync_strt, v_sync_end, v_total);
1338                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1339                         pixclock_in_ps,
1340                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1341                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1342         }
1343 #endif /* DEBUG */
1344
1345         if (!M64_HAS(INTEGRATED)) {
1346                 /* Don't forget MEM_CNTL */
1347                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1348                 switch (var->bits_per_pixel) {
1349                 case 8:
1350                         tmp |= 0x02000000;
1351                         break;
1352                 case 16:
1353                         tmp |= 0x03000000;
1354                         break;
1355                 case 32:
1356                         tmp |= 0x06000000;
1357                         break;
1358                 }
1359                 aty_st_le32(MEM_CNTL, tmp, par);
1360         } else {
1361                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1362                 if (!M64_HAS(MAGIC_POSTDIV))
1363                         tmp |= par->mem_refresh_rate << 20;
1364                 switch (var->bits_per_pixel) {
1365                 case 8:
1366                 case 24:
1367                         tmp |= 0x00000000;
1368                         break;
1369                 case 16:
1370                         tmp |= 0x04000000;
1371                         break;
1372                 case 32:
1373                         tmp |= 0x08000000;
1374                         break;
1375                 }
1376                 if (M64_HAS(CT_BUS)) {
1377                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1378                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1379                 } else if (M64_HAS(VT_BUS)) {
1380                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1381                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1382                 } else if (M64_HAS(MOBIL_BUS)) {
1383                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1384                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1385                 } else {
1386                         /* GT */
1387                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1388                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1389                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1390                 }
1391                 aty_st_le32(MEM_CNTL, tmp, par);
1392         }
1393         aty_st_8(DAC_MASK, 0xff, par);
1394
1395         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1396         info->fix.visual = var->bits_per_pixel <= 8 ?
1397                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1398
1399         /* Initialize the graphics engine */
1400         if (par->accel_flags & FB_ACCELF_TEXT)
1401                 aty_init_engine(par, info);
1402
1403 #ifdef CONFIG_BOOTX_TEXT
1404         btext_update_display(info->fix.smem_start,
1405                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1406                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1407                 var->bits_per_pixel,
1408                 par->crtc.vxres * var->bits_per_pixel / 8);
1409 #endif /* CONFIG_BOOTX_TEXT */
1410 #if 0
1411         /* switch to accelerator mode */
1412         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1413                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1414 #endif
1415 #ifdef DEBUG
1416 {
1417         /* dump non shadow CRTC, pll, LCD registers */
1418         int i; u32 base;
1419
1420         /* CRTC registers */
1421         base = 0x2000;
1422         printk("debug atyfb: Mach64 non-shadow register values:");
1423         for (i = 0; i < 256; i = i+4) {
1424                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1425                 printk(" %08X", aty_ld_le32(i, par));
1426         }
1427         printk("\n\n");
1428
1429 #ifdef CONFIG_FB_ATY_CT
1430         /* PLL registers */
1431         base = 0x00;
1432         printk("debug atyfb: Mach64 PLL register values:");
1433         for (i = 0; i < 64; i++) {
1434                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1435                 if(i%4 == 0)  printk(" ");
1436                 printk("%02X", aty_ld_pll_ct(i, par));
1437         }
1438         printk("\n\n");
1439 #endif  /* CONFIG_FB_ATY_CT */
1440
1441 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1442         if (par->lcd_table != 0) {
1443                 /* LCD registers */
1444                 base = 0x00;
1445                 printk("debug atyfb: LCD register values:");
1446                 if(M64_HAS(LT_LCD_REGS)) {
1447                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1448                         if(i == EXT_VERT_STRETCH)
1449                             continue;
1450                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1451                         printk(" %08X", aty_ld_lcd(i, par));
1452                     }
1453
1454                 } else {
1455                     for (i = 0; i < 64; i++) {
1456                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1457                         printk(" %08X", aty_ld_lcd(i, par));
1458                     }
1459                 }
1460                 printk("\n\n");
1461         }
1462 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1463 }
1464 #endif /* DEBUG */
1465         return 0;
1466 }
1467
1468 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1469 {
1470         struct atyfb_par *par = (struct atyfb_par *) info->par;
1471         int err;
1472         struct crtc crtc;
1473         union aty_pll pll;
1474         u32 pixclock;
1475
1476         memcpy(&pll, &(par->pll), sizeof(pll));
1477
1478         if((err = aty_var_to_crtc(info, var, &crtc)))
1479                 return err;
1480
1481         pixclock = atyfb_get_pixclock(var, par);
1482
1483         if (pixclock == 0) {
1484                 if (!(var->activate & FB_ACTIVATE_TEST))
1485                         PRINTKE("Invalid pixclock\n");
1486                 return -EINVAL;
1487         } else {
1488                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1489                         return err;
1490         }
1491
1492         if (var->accel_flags & FB_ACCELF_TEXT)
1493                 info->var.accel_flags = FB_ACCELF_TEXT;
1494         else
1495                 info->var.accel_flags = 0;
1496
1497         aty_crtc_to_var(&crtc, var);
1498         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1499         return 0;
1500 }
1501
1502 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1503 {
1504         u32 xoffset = info->var.xoffset;
1505         u32 yoffset = info->var.yoffset;
1506         u32 vxres = par->crtc.vxres;
1507         u32 bpp = info->var.bits_per_pixel;
1508
1509         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1510 }
1511
1512
1513     /*
1514      *  Open/Release the frame buffer device
1515      */
1516
1517 static int atyfb_open(struct fb_info *info, int user)
1518 {
1519         struct atyfb_par *par = (struct atyfb_par *) info->par;
1520
1521         if (user) {
1522                 par->open++;
1523 #ifdef __sparc__
1524                 par->mmaped = 0;
1525 #endif
1526         }
1527         return (0);
1528 }
1529
1530 static irqreturn_t aty_irq(int irq, void *dev_id)
1531 {
1532         struct atyfb_par *par = dev_id;
1533         int handled = 0;
1534         u32 int_cntl;
1535
1536         spin_lock(&par->int_lock);
1537
1538         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1539
1540         if (int_cntl & CRTC_VBLANK_INT) {
1541                 /* clear interrupt */
1542                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1543                 par->vblank.count++;
1544                 if (par->vblank.pan_display) {
1545                         par->vblank.pan_display = 0;
1546                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1547                 }
1548                 wake_up_interruptible(&par->vblank.wait);
1549                 handled = 1;
1550         }
1551
1552         spin_unlock(&par->int_lock);
1553
1554         return IRQ_RETVAL(handled);
1555 }
1556
1557 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1558 {
1559         u32 int_cntl;
1560
1561         if (!test_and_set_bit(0, &par->irq_flags)) {
1562                 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1563                         clear_bit(0, &par->irq_flags);
1564                         return -EINVAL;
1565                 }
1566                 spin_lock_irq(&par->int_lock);
1567                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1568                 /* clear interrupt */
1569                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1570                 /* enable interrupt */
1571                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1572                 spin_unlock_irq(&par->int_lock);
1573         } else if (reenable) {
1574                 spin_lock_irq(&par->int_lock);
1575                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1577                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1578                         /* re-enable interrupt */
1579                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1580                 }
1581                 spin_unlock_irq(&par->int_lock);
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int aty_disable_irq(struct atyfb_par *par)
1588 {
1589         u32 int_cntl;
1590
1591         if (test_and_clear_bit(0, &par->irq_flags)) {
1592                 if (par->vblank.pan_display) {
1593                         par->vblank.pan_display = 0;
1594                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1595                 }
1596                 spin_lock_irq(&par->int_lock);
1597                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1598                 /* disable interrupt */
1599                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1600                 spin_unlock_irq(&par->int_lock);
1601                 free_irq(par->irq, par);
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int atyfb_release(struct fb_info *info, int user)
1608 {
1609         struct atyfb_par *par = (struct atyfb_par *) info->par;
1610         if (user) {
1611                 par->open--;
1612                 mdelay(1);
1613                 wait_for_idle(par);
1614                 if (!par->open) {
1615 #ifdef __sparc__
1616                         int was_mmaped = par->mmaped;
1617
1618                         par->mmaped = 0;
1619
1620                         if (was_mmaped) {
1621                                 struct fb_var_screeninfo var;
1622
1623                                 /* Now reset the default display config, we have no
1624                                  * idea what the program(s) which mmap'd the chip did
1625                                  * to the configuration, nor whether it restored it
1626                                  * correctly.
1627                                  */
1628                                 var = default_var;
1629                                 if (noaccel)
1630                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1631                                 else
1632                                         var.accel_flags |= FB_ACCELF_TEXT;
1633                                 if (var.yres == var.yres_virtual) {
1634                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1635                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1636                                         if (var.yres_virtual < var.yres)
1637                                                 var.yres_virtual = var.yres;
1638                                 }
1639                         }
1640 #endif
1641                         aty_disable_irq(par);
1642                 }
1643         }
1644         return (0);
1645 }
1646
1647     /*
1648      *  Pan or Wrap the Display
1649      *
1650      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1651      */
1652
1653 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1654 {
1655         struct atyfb_par *par = (struct atyfb_par *) info->par;
1656         u32 xres, yres, xoffset, yoffset;
1657
1658         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1659         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1660         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1661                 yres >>= 1;
1662         xoffset = (var->xoffset + 7) & ~7;
1663         yoffset = var->yoffset;
1664         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1665                 return -EINVAL;
1666         info->var.xoffset = xoffset;
1667         info->var.yoffset = yoffset;
1668         if (par->asleep)
1669                 return 0;
1670
1671         set_off_pitch(par, info);
1672         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1673                 par->vblank.pan_display = 1;
1674         } else {
1675                 par->vblank.pan_display = 0;
1676                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1683 {
1684         struct aty_interrupt *vbl;
1685         unsigned int count;
1686         int ret;
1687
1688         switch (crtc) {
1689         case 0:
1690                 vbl = &par->vblank;
1691                 break;
1692         default:
1693                 return -ENODEV;
1694         }
1695
1696         ret = aty_enable_irq(par, 0);
1697         if (ret)
1698                 return ret;
1699
1700         count = vbl->count;
1701         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1702         if (ret < 0) {
1703                 return ret;
1704         }
1705         if (ret == 0) {
1706                 aty_enable_irq(par, 1);
1707                 return -ETIMEDOUT;
1708         }
1709
1710         return 0;
1711 }
1712
1713
1714 #ifdef DEBUG
1715 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1716 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1717
1718 struct atyclk {
1719         u32 ref_clk_per;
1720         u8 pll_ref_div;
1721         u8 mclk_fb_div;
1722         u8 mclk_post_div;       /* 1,2,3,4,8 */
1723         u8 mclk_fb_mult;        /* 2 or 4 */
1724         u8 xclk_post_div;       /* 1,2,3,4,8 */
1725         u8 vclk_fb_div;
1726         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1727         u32 dsp_xclks_per_row;  /* 0-16383 */
1728         u32 dsp_loop_latency;   /* 0-15 */
1729         u32 dsp_precision;      /* 0-7 */
1730         u32 dsp_on;             /* 0-2047 */
1731         u32 dsp_off;            /* 0-2047 */
1732 };
1733
1734 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1735 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1736 #endif
1737
1738 #ifndef FBIO_WAITFORVSYNC
1739 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1740 #endif
1741
1742 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1743 {
1744         struct atyfb_par *par = (struct atyfb_par *) info->par;
1745 #ifdef __sparc__
1746         struct fbtype fbtyp;
1747 #endif
1748
1749         switch (cmd) {
1750 #ifdef __sparc__
1751         case FBIOGTYPE:
1752                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1753                 fbtyp.fb_width = par->crtc.vxres;
1754                 fbtyp.fb_height = par->crtc.vyres;
1755                 fbtyp.fb_depth = info->var.bits_per_pixel;
1756                 fbtyp.fb_cmsize = info->cmap.len;
1757                 fbtyp.fb_size = info->fix.smem_len;
1758                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1759                         return -EFAULT;
1760                 break;
1761 #endif /* __sparc__ */
1762
1763         case FBIO_WAITFORVSYNC:
1764                 {
1765                         u32 crtc;
1766
1767                         if (get_user(crtc, (__u32 __user *) arg))
1768                                 return -EFAULT;
1769
1770                         return aty_waitforvblank(par, crtc);
1771                 }
1772                 break;
1773
1774 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1775         case ATYIO_CLKR:
1776                 if (M64_HAS(INTEGRATED)) {
1777                         struct atyclk clk;
1778                         union aty_pll *pll = &(par->pll);
1779                         u32 dsp_config = pll->ct.dsp_config;
1780                         u32 dsp_on_off = pll->ct.dsp_on_off;
1781                         clk.ref_clk_per = par->ref_clk_per;
1782                         clk.pll_ref_div = pll->ct.pll_ref_div;
1783                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1784                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1785                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1786                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1787                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1788                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1789                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1790                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1791                         clk.dsp_precision = (dsp_config >> 20) & 7;
1792                         clk.dsp_off = dsp_on_off & 0x7ff;
1793                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1794                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1795                                          sizeof(clk)))
1796                                 return -EFAULT;
1797                 } else
1798                         return -EINVAL;
1799                 break;
1800         case ATYIO_CLKW:
1801                 if (M64_HAS(INTEGRATED)) {
1802                         struct atyclk clk;
1803                         union aty_pll *pll = &(par->pll);
1804                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1805                                 return -EFAULT;
1806                         par->ref_clk_per = clk.ref_clk_per;
1807                         pll->ct.pll_ref_div = clk.pll_ref_div;
1808                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1809                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1810                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1811                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1812                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1813                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1814                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1815                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1816                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1817                         /*aty_calc_pll_ct(info, &pll->ct);*/
1818                         aty_set_pll_ct(info, pll);
1819                 } else
1820                         return -EINVAL;
1821                 break;
1822         case ATYIO_FEATR:
1823                 if (get_user(par->features, (u32 __user *) arg))
1824                         return -EFAULT;
1825                 break;
1826         case ATYIO_FEATW:
1827                 if (put_user(par->features, (u32 __user *) arg))
1828                         return -EFAULT;
1829                 break;
1830 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1831         default:
1832                 return -EINVAL;
1833         }
1834         return 0;
1835 }
1836
1837 static int atyfb_sync(struct fb_info *info)
1838 {
1839         struct atyfb_par *par = (struct atyfb_par *) info->par;
1840
1841         if (par->blitter_may_be_busy)
1842                 wait_for_idle(par);
1843         return 0;
1844 }
1845
1846 #ifdef __sparc__
1847 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1848 {
1849         struct atyfb_par *par = (struct atyfb_par *) info->par;
1850         unsigned int size, page, map_size = 0;
1851         unsigned long map_offset = 0;
1852         unsigned long off;
1853         int i;
1854
1855         if (!par->mmap_map)
1856                 return -ENXIO;
1857
1858         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1859                 return -EINVAL;
1860
1861         off = vma->vm_pgoff << PAGE_SHIFT;
1862         size = vma->vm_end - vma->vm_start;
1863
1864         /* To stop the swapper from even considering these pages. */
1865         vma->vm_flags |= (VM_IO | VM_RESERVED);
1866
1867         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1868             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1869                 off += 0x8000000000000000UL;
1870
1871         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1872
1873         /* Each page, see which map applies */
1874         for (page = 0; page < size;) {
1875                 map_size = 0;
1876                 for (i = 0; par->mmap_map[i].size; i++) {
1877                         unsigned long start = par->mmap_map[i].voff;
1878                         unsigned long end = start + par->mmap_map[i].size;
1879                         unsigned long offset = off + page;
1880
1881                         if (start > offset)
1882                                 continue;
1883                         if (offset >= end)
1884                                 continue;
1885
1886                         map_size = par->mmap_map[i].size - (offset - start);
1887                         map_offset =
1888                             par->mmap_map[i].poff + (offset - start);
1889                         break;
1890                 }
1891                 if (!map_size) {
1892                         page += PAGE_SIZE;
1893                         continue;
1894                 }
1895                 if (page + map_size > size)
1896                         map_size = size - page;
1897
1898                 pgprot_val(vma->vm_page_prot) &=
1899                     ~(par->mmap_map[i].prot_mask);
1900                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1901
1902                 if (remap_pfn_range(vma, vma->vm_start + page,
1903                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1904                         return -EAGAIN;
1905
1906                 page += map_size;
1907         }
1908
1909         if (!map_size)
1910                 return -EINVAL;
1911
1912         if (!par->mmaped)
1913                 par->mmaped = 1;
1914         return 0;
1915 }
1916
1917 static struct {
1918         u32 yoffset;
1919         u8 r[2][256];
1920         u8 g[2][256];
1921         u8 b[2][256];
1922 } atyfb_save;
1923
1924 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1925 {
1926         int i, tmp;
1927
1928         for (i = 0; i < 256; i++) {
1929                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1930                 if (M64_HAS(EXTRA_BRIGHT))
1931                         tmp |= 0x2;
1932                 aty_st_8(DAC_CNTL, tmp, par);
1933                 aty_st_8(DAC_MASK, 0xff, par);
1934
1935                 aty_st_8(DAC_R_INDEX, i, par);
1936                 atyfb_save.r[enter][i] = aty_ld_8(DAC_DATA, par);
1937                 atyfb_save.g[enter][i] = aty_ld_8(DAC_DATA, par);
1938                 atyfb_save.b[enter][i] = aty_ld_8(DAC_DATA, par);
1939                 aty_st_8(DAC_W_INDEX, i, par);
1940                 aty_st_8(DAC_DATA, atyfb_save.r[1 - enter][i], par);
1941                 aty_st_8(DAC_DATA, atyfb_save.g[1 - enter][i], par);
1942                 aty_st_8(DAC_DATA, atyfb_save.b[1 - enter][i], par);
1943         }
1944 }
1945
1946 static void atyfb_palette(int enter)
1947 {
1948         struct atyfb_par *par;
1949         struct fb_info *info;
1950         int i;
1951
1952         for (i = 0; i < FB_MAX; i++) {
1953                 info = registered_fb[i];
1954                 if (info && info->fbops == &atyfb_ops) {
1955                         par = (struct atyfb_par *) info->par;
1956
1957                         atyfb_save_palette(par, enter);
1958                         if (enter) {
1959                                 atyfb_save.yoffset = info->var.yoffset;
1960                                 info->var.yoffset = 0;
1961                                 set_off_pitch(par, info);
1962                         } else {
1963                                 info->var.yoffset = atyfb_save.yoffset;
1964                                 set_off_pitch(par, info);
1965                         }
1966                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1967                         break;
1968                 }
1969         }
1970 }
1971 #endif /* __sparc__ */
1972
1973
1974
1975 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1976
1977 #ifdef CONFIG_PPC_PMAC
1978 /* Power management routines. Those are used for PowerBook sleep.
1979  */
1980 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1981 {
1982         u32 pm;
1983         int timeout;
1984
1985         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1986         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1987         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1988         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1989
1990         timeout = 2000;
1991         if (sleep) {
1992                 /* Sleep */
1993                 pm &= ~PWR_MGT_ON;
1994                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1995                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1996                 udelay(10);
1997                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1998                 pm |= SUSPEND_NOW;
1999                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2000                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2001                 udelay(10);
2002                 pm |= PWR_MGT_ON;
2003                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2004                 do {
2005                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2006                         mdelay(1);
2007                         if ((--timeout) == 0)
2008                                 break;
2009                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2010         } else {
2011                 /* Wakeup */
2012                 pm &= ~PWR_MGT_ON;
2013                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2014                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2015                 udelay(10);
2016                 pm &= ~SUSPEND_NOW;
2017                 pm |= (PWR_BLON | AUTO_PWR_UP);
2018                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2019                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2020                 udelay(10);
2021                 pm |= PWR_MGT_ON;
2022                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2023                 do {
2024                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2025                         mdelay(1);
2026                         if ((--timeout) == 0)
2027                                 break;
2028                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2029         }
2030         mdelay(500);
2031
2032         return timeout ? 0 : -EIO;
2033 }
2034 #endif
2035
2036 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2037 {
2038         struct fb_info *info = pci_get_drvdata(pdev);
2039         struct atyfb_par *par = (struct atyfb_par *) info->par;
2040
2041         if (state.event == pdev->dev.power.power_state.event)
2042                 return 0;
2043
2044         acquire_console_sem();
2045
2046         fb_set_suspend(info, 1);
2047
2048         /* Idle & reset engine */
2049         wait_for_idle(par);
2050         aty_reset_engine(par);
2051
2052         /* Blank display and LCD */
2053         atyfb_blank(FB_BLANK_POWERDOWN, info);
2054
2055         par->asleep = 1;
2056         par->lock_blank = 1;
2057
2058 #ifdef CONFIG_PPC_PMAC
2059         /* Set chip to "suspend" mode */
2060         if (aty_power_mgmt(1, par)) {
2061                 par->asleep = 0;
2062                 par->lock_blank = 0;
2063                 atyfb_blank(FB_BLANK_UNBLANK, info);
2064                 fb_set_suspend(info, 0);
2065                 release_console_sem();
2066                 return -EIO;
2067         }
2068 #else
2069         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2070 #endif
2071
2072         release_console_sem();
2073
2074         pdev->dev.power.power_state = state;
2075
2076         return 0;
2077 }
2078
2079 static int atyfb_pci_resume(struct pci_dev *pdev)
2080 {
2081         struct fb_info *info = pci_get_drvdata(pdev);
2082         struct atyfb_par *par = (struct atyfb_par *) info->par;
2083
2084         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2085                 return 0;
2086
2087         acquire_console_sem();
2088
2089 #ifdef CONFIG_PPC_PMAC
2090         if (pdev->dev.power.power_state.event == 2)
2091                 aty_power_mgmt(0, par);
2092 #else
2093         pci_set_power_state(pdev, PCI_D0);
2094 #endif
2095
2096         aty_resume_chip(info);
2097
2098         par->asleep = 0;
2099
2100         /* Restore display */
2101         atyfb_set_par(info);
2102
2103         /* Refresh */
2104         fb_set_suspend(info, 0);
2105
2106         /* Unblank */
2107         par->lock_blank = 0;
2108         atyfb_blank(FB_BLANK_UNBLANK, info);
2109
2110         release_console_sem();
2111
2112         pdev->dev.power.power_state = PMSG_ON;
2113
2114         return 0;
2115 }
2116
2117 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2118
2119 /* Backlight */
2120 #ifdef CONFIG_FB_ATY_BACKLIGHT
2121 #define MAX_LEVEL 0xFF
2122
2123 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2124 {
2125         struct fb_info *info = pci_get_drvdata(par->pdev);
2126         int atylevel;
2127
2128         /* Get and convert the value */
2129         /* No locking of bl_curve since we read a single value */
2130         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2131
2132         if (atylevel < 0)
2133                 atylevel = 0;
2134         else if (atylevel > MAX_LEVEL)
2135                 atylevel = MAX_LEVEL;
2136
2137         return atylevel;
2138 }
2139
2140 static int aty_bl_update_status(struct backlight_device *bd)
2141 {
2142         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2143         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2144         int level;
2145
2146         if (bd->props.power != FB_BLANK_UNBLANK ||
2147             bd->props.fb_blank != FB_BLANK_UNBLANK)
2148                 level = 0;
2149         else
2150                 level = bd->props.brightness;
2151
2152         reg |= (BLMOD_EN | BIASMOD_EN);
2153         if (level > 0) {
2154                 reg &= ~BIAS_MOD_LEVEL_MASK;
2155                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2156         } else {
2157                 reg &= ~BIAS_MOD_LEVEL_MASK;
2158                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2159         }
2160         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2161
2162         return 0;
2163 }
2164
2165 static int aty_bl_get_brightness(struct backlight_device *bd)
2166 {
2167         return bd->props.brightness;
2168 }
2169
2170 static struct backlight_ops aty_bl_data = {
2171         .get_brightness = aty_bl_get_brightness,
2172         .update_status  = aty_bl_update_status,
2173 };
2174
2175 static void aty_bl_init(struct atyfb_par *par)
2176 {
2177         struct fb_info *info = pci_get_drvdata(par->pdev);
2178         struct backlight_device *bd;
2179         char name[12];
2180
2181 #ifdef CONFIG_PMAC_BACKLIGHT
2182         if (!pmac_has_backlight_type("ati"))
2183                 return;
2184 #endif
2185
2186         snprintf(name, sizeof(name), "atybl%d", info->node);
2187
2188         bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2189         if (IS_ERR(bd)) {
2190                 info->bl_dev = NULL;
2191                 printk(KERN_WARNING "aty: Backlight registration failed\n");
2192                 goto error;
2193         }
2194
2195         info->bl_dev = bd;
2196         fb_bl_default_curve(info, 0,
2197                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2198                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2199
2200         bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2201         bd->props.brightness = bd->props.max_brightness;
2202         bd->props.power = FB_BLANK_UNBLANK;
2203         backlight_update_status(bd);
2204
2205         printk("aty: Backlight initialized (%s)\n", name);
2206
2207         return;
2208
2209 error:
2210         return;
2211 }
2212
2213 static void aty_bl_exit(struct backlight_device *bd)
2214 {
2215         backlight_device_unregister(bd);
2216         printk("aty: Backlight unloaded\n");
2217 }
2218
2219 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2220
2221 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2222 {
2223         const int ragepro_tbl[] = {
2224                 44, 50, 55, 66, 75, 80, 100
2225         };
2226         const int ragexl_tbl[] = {
2227                 50, 66, 75, 83, 90, 95, 100, 105,
2228                 110, 115, 120, 125, 133, 143, 166
2229         };
2230         const int *refresh_tbl;
2231         int i, size;
2232
2233         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2234                 refresh_tbl = ragexl_tbl;
2235                 size = ARRAY_SIZE(ragexl_tbl);
2236         } else {
2237                 refresh_tbl = ragepro_tbl;
2238                 size = ARRAY_SIZE(ragepro_tbl);
2239         }
2240
2241         for (i=0; i < size; i++) {
2242                 if (xclk < refresh_tbl[i])
2243                 break;
2244         }
2245         par->mem_refresh_rate = i;
2246 }
2247
2248     /*
2249      *  Initialisation
2250      */
2251
2252 static struct fb_info *fb_list = NULL;
2253
2254 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2255 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2256                                                 struct fb_var_screeninfo *var)
2257 {
2258         int ret = -EINVAL;
2259
2260         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2261                 *var = default_var;
2262                 var->xres = var->xres_virtual = par->lcd_hdisp;
2263                 var->right_margin = par->lcd_right_margin;
2264                 var->left_margin = par->lcd_hblank_len -
2265                         (par->lcd_right_margin + par->lcd_hsync_dly +
2266                          par->lcd_hsync_len);
2267                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2268                 var->yres = var->yres_virtual = par->lcd_vdisp;
2269                 var->lower_margin = par->lcd_lower_margin;
2270                 var->upper_margin = par->lcd_vblank_len -
2271                         (par->lcd_lower_margin + par->lcd_vsync_len);
2272                 var->vsync_len = par->lcd_vsync_len;
2273                 var->pixclock = par->lcd_pixclock;
2274                 ret = 0;
2275         }
2276
2277         return ret;
2278 }
2279 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2280
2281 static int __devinit aty_init(struct fb_info *info)
2282 {
2283         struct atyfb_par *par = (struct atyfb_par *) info->par;
2284         const char *ramname = NULL, *xtal;
2285         int gtb_memsize, has_var = 0;
2286         struct fb_var_screeninfo var;
2287
2288         init_waitqueue_head(&par->vblank.wait);
2289         spin_lock_init(&par->int_lock);
2290
2291 #ifdef CONFIG_PPC_PMAC
2292         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2293          * and set the frequency manually. */
2294         if (machine_is_compatible("PowerBook2,1")) {
2295                 par->pll_limits.mclk = 70;
2296                 par->pll_limits.xclk = 53;
2297         }
2298 #endif
2299         if (pll)
2300                 par->pll_limits.pll_max = pll;
2301         if (mclk)
2302                 par->pll_limits.mclk = mclk;
2303         if (xclk)
2304                 par->pll_limits.xclk = xclk;
2305
2306         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2307         par->pll_per = 1000000/par->pll_limits.pll_max;
2308         par->mclk_per = 1000000/par->pll_limits.mclk;
2309         par->xclk_per = 1000000/par->pll_limits.xclk;
2310
2311         par->ref_clk_per = 1000000000000ULL / 14318180;
2312         xtal = "14.31818";
2313
2314 #ifdef CONFIG_FB_ATY_GX
2315         if (!M64_HAS(INTEGRATED)) {
2316                 u32 stat0;
2317                 u8 dac_type, dac_subtype, clk_type;
2318                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2319                 par->bus_type = (stat0 >> 0) & 0x07;
2320                 par->ram_type = (stat0 >> 3) & 0x07;
2321                 ramname = aty_gx_ram[par->ram_type];
2322                 /* FIXME: clockchip/RAMDAC probing? */
2323                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2324 #ifdef CONFIG_ATARI
2325                 clk_type = CLK_ATI18818_1;
2326                 dac_type = (stat0 >> 9) & 0x07;
2327                 if (dac_type == 0x07)
2328                         dac_subtype = DAC_ATT20C408;
2329                 else
2330                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2331 #else
2332                 dac_type = DAC_IBMRGB514;
2333                 dac_subtype = DAC_IBMRGB514;
2334                 clk_type = CLK_IBMRGB514;
2335 #endif
2336                 switch (dac_subtype) {
2337                 case DAC_IBMRGB514:
2338                         par->dac_ops = &aty_dac_ibm514;
2339                         break;
2340                 case DAC_ATI68860_B:
2341                 case DAC_ATI68860_C:
2342                         par->dac_ops = &aty_dac_ati68860b;
2343                         break;
2344                 case DAC_ATT20C408:
2345                 case DAC_ATT21C498:
2346                         par->dac_ops = &aty_dac_att21c498;
2347                         break;
2348                 default:
2349                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2350                         par->dac_ops = &aty_dac_unsupported;
2351                         break;
2352                 }
2353                 switch (clk_type) {
2354 #ifdef CONFIG_ATARI
2355                 case CLK_ATI18818_1:
2356                         par->pll_ops = &aty_pll_ati18818_1;
2357                         break;
2358 #else
2359                 case CLK_IBMRGB514:
2360                         par->pll_ops = &aty_pll_ibm514;
2361                         break;
2362 #endif
2363 #if 0 /* dead code */
2364                 case CLK_STG1703:
2365                         par->pll_ops = &aty_pll_stg1703;
2366                         break;
2367                 case CLK_CH8398:
2368                         par->pll_ops = &aty_pll_ch8398;
2369                         break;
2370                 case CLK_ATT20C408:
2371                         par->pll_ops = &aty_pll_att20c408;
2372                         break;
2373 #endif
2374                 default:
2375                         PRINTKI("aty_init: CLK type not implemented yet!");
2376                         par->pll_ops = &aty_pll_unsupported;
2377                         break;
2378                 }
2379         }
2380 #endif /* CONFIG_FB_ATY_GX */
2381 #ifdef CONFIG_FB_ATY_CT
2382         if (M64_HAS(INTEGRATED)) {
2383                 par->dac_ops = &aty_dac_ct;
2384                 par->pll_ops = &aty_pll_ct;
2385                 par->bus_type = PCI;
2386                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2387                 ramname = aty_ct_ram[par->ram_type];
2388                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2389                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2390                         par->pll_limits.mclk = 63;
2391         }
2392
2393         if (M64_HAS(GTB_DSP)) {
2394                 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2395
2396                 if (pll_ref_div) {
2397                         int diff1, diff2;
2398                         diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2399                         diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2400                         if (diff1 < 0)
2401                                 diff1 = -diff1;
2402                         if (diff2 < 0)
2403                                 diff2 = -diff2;
2404                         if (diff2 < diff1) {
2405                                 par->ref_clk_per = 1000000000000ULL / 29498928;
2406                                 xtal = "29.498928";
2407                         }
2408                 }
2409         }
2410 #endif /* CONFIG_FB_ATY_CT */
2411
2412         /* save previous video mode */
2413         aty_get_crtc(par, &saved_crtc);
2414         if(par->pll_ops->get_pll)
2415                 par->pll_ops->get_pll(info, &saved_pll);
2416
2417         par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2418         gtb_memsize = M64_HAS(GTB_DSP);
2419         if (gtb_memsize)
2420                 switch (par->mem_cntl & 0xF) {  /* 0xF used instead of MEM_SIZE_ALIAS */
2421                 case MEM_SIZE_512K:
2422                         info->fix.smem_len = 0x80000;
2423                         break;
2424                 case MEM_SIZE_1M:
2425                         info->fix.smem_len = 0x100000;
2426                         break;
2427                 case MEM_SIZE_2M_GTB:
2428                         info->fix.smem_len = 0x200000;
2429                         break;
2430                 case MEM_SIZE_4M_GTB:
2431                         info->fix.smem_len = 0x400000;
2432                         break;
2433                 case MEM_SIZE_6M_GTB:
2434                         info->fix.smem_len = 0x600000;
2435                         break;
2436                 case MEM_SIZE_8M_GTB:
2437                         info->fix.smem_len = 0x800000;
2438                         break;
2439                 default:
2440                         info->fix.smem_len = 0x80000;
2441         } else
2442                 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2443                 case MEM_SIZE_512K:
2444                         info->fix.smem_len = 0x80000;
2445                         break;
2446                 case MEM_SIZE_1M:
2447                         info->fix.smem_len = 0x100000;
2448                         break;
2449                 case MEM_SIZE_2M:
2450                         info->fix.smem_len = 0x200000;
2451                         break;
2452                 case MEM_SIZE_4M:
2453                         info->fix.smem_len = 0x400000;
2454                         break;
2455                 case MEM_SIZE_6M:
2456                         info->fix.smem_len = 0x600000;
2457                         break;
2458                 case MEM_SIZE_8M:
2459                         info->fix.smem_len = 0x800000;
2460                         break;
2461                 default:
2462                         info->fix.smem_len = 0x80000;
2463                 }
2464
2465         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2466                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2467                         info->fix.smem_len += 0x400000;
2468         }
2469
2470         if (vram) {
2471                 info->fix.smem_len = vram * 1024;
2472                 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2473                 if (info->fix.smem_len <= 0x80000)
2474                         par->mem_cntl |= MEM_SIZE_512K;
2475                 else if (info->fix.smem_len <= 0x100000)
2476                         par->mem_cntl |= MEM_SIZE_1M;
2477                 else if (info->fix.smem_len <= 0x200000)
2478                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2479                 else if (info->fix.smem_len <= 0x400000)
2480                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2481                 else if (info->fix.smem_len <= 0x600000)
2482                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2483                 else
2484                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2485                 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2486         }
2487
2488         /*
2489          *  Reg Block 0 (CT-compatible block) is at mmio_start
2490          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2491          */
2492         if (M64_HAS(GX)) {
2493                 info->fix.mmio_len = 0x400;
2494                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2495         } else if (M64_HAS(CT)) {
2496                 info->fix.mmio_len = 0x400;
2497                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2498         } else if (M64_HAS(VT)) {
2499                 info->fix.mmio_start -= 0x400;
2500                 info->fix.mmio_len = 0x800;
2501                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2502         } else {/* GT */
2503                 info->fix.mmio_start -= 0x400;
2504                 info->fix.mmio_len = 0x800;
2505                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2506         }
2507
2508         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2509                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2510                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2511                par->pll_limits.mclk, par->pll_limits.xclk);
2512
2513 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2514         if (M64_HAS(INTEGRATED)) {
2515                 int i;
2516                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2517                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2518                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2519                        "debug atyfb: PLL",
2520                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2521                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2522                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2523                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2524                 for (i = 0; i < 40; i++)
2525                         printk(" %02x", aty_ld_pll_ct(i, par));
2526                 printk("\n");
2527         }
2528 #endif
2529         if(par->pll_ops->init_pll)
2530                 par->pll_ops->init_pll(info, &par->pll);
2531         if (par->pll_ops->resume_pll)
2532                 par->pll_ops->resume_pll(info, &par->pll);
2533
2534         /*
2535          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2536          *  unless the auxiliary register aperture is used.
2537          */
2538
2539         if (!par->aux_start &&
2540                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2541                 info->fix.smem_len -= GUI_RESERVE;
2542
2543         /*
2544          *  Disable register access through the linear aperture
2545          *  if the auxiliary aperture is used so we can access
2546          *  the full 8 MB of video RAM on 8 MB boards.
2547          */
2548         if (par->aux_start)
2549                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2550
2551 #ifdef CONFIG_MTRR
2552         par->mtrr_aper = -1;
2553         par->mtrr_reg = -1;
2554         if (!nomtrr) {
2555                 /* Cover the whole resource. */
2556                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2557                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2558                         /* Make a hole for mmio. */
2559                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2560                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2561                         if (par->mtrr_reg < 0) {
2562                                 mtrr_del(par->mtrr_aper, 0, 0);
2563                                 par->mtrr_aper = -1;
2564                         }
2565                  }
2566         }
2567 #endif
2568
2569         info->fbops = &atyfb_ops;
2570         info->pseudo_palette = pseudo_palette;
2571         info->flags = FBINFO_DEFAULT           |
2572                       FBINFO_HWACCEL_IMAGEBLIT |
2573                       FBINFO_HWACCEL_FILLRECT  |
2574                       FBINFO_HWACCEL_COPYAREA  |
2575                       FBINFO_HWACCEL_YPAN;
2576
2577 #ifdef CONFIG_PMAC_BACKLIGHT
2578         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2579                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2580                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2581                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2582         } else
2583 #endif
2584         if (M64_HAS(MOBIL_BUS) && backlight) {
2585 #ifdef CONFIG_FB_ATY_BACKLIGHT
2586                 aty_bl_init (par);
2587 #endif
2588         }
2589
2590         memset(&var, 0, sizeof(var));
2591 #ifdef CONFIG_PPC
2592         if (machine_is(powermac)) {
2593                 /*
2594                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2595                  *         applies to all Mac video cards
2596                  */
2597                 if (mode) {
2598                         if (mac_find_mode(&var, info, mode, 8))
2599                                 has_var = 1;
2600                 } else {
2601                         if (default_vmode == VMODE_CHOOSE) {
2602                                 int sense;
2603                                 if (M64_HAS(G3_PB_1024x768))
2604                                         /* G3 PowerBook with 1024x768 LCD */
2605                                         default_vmode = VMODE_1024_768_60;
2606                                 else if (machine_is_compatible("iMac"))
2607                                         default_vmode = VMODE_1024_768_75;
2608                                 else if (machine_is_compatible
2609                                          ("PowerBook2,1"))
2610                                         /* iBook with 800x600 LCD */
2611                                         default_vmode = VMODE_800_600_60;
2612                                 else
2613                                         default_vmode = VMODE_640_480_67;
2614                                 sense = read_aty_sense(par);
2615                                 PRINTKI("monitor sense=%x, mode %d\n",
2616                                         sense,  mac_map_monitor_sense(sense));
2617                         }
2618                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2619                                 default_vmode = VMODE_640_480_60;
2620                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2621                                 default_cmode = CMODE_8;
2622                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2623                                                &var))
2624                                 has_var = 1;
2625                 }
2626         }
2627
2628 #endif /* !CONFIG_PPC */
2629
2630 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2631         if (!atyfb_get_timings_from_lcd(par, &var))
2632                 has_var = 1;
2633 #endif
2634
2635         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2636                 has_var = 1;
2637
2638         if (!has_var)
2639                 var = default_var;
2640
2641         if (noaccel)
2642                 var.accel_flags &= ~FB_ACCELF_TEXT;
2643         else
2644                 var.accel_flags |= FB_ACCELF_TEXT;
2645
2646         if (comp_sync != -1) {
2647                 if (!comp_sync)
2648                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2649                 else
2650                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2651         }
2652
2653         if (var.yres == var.yres_virtual) {
2654                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2655                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2656                 if (var.yres_virtual < var.yres)
2657                         var.yres_virtual = var.yres;
2658         }
2659
2660         if (atyfb_check_var(&var, info)) {
2661                 PRINTKE("can't set default video mode\n");
2662                 goto aty_init_exit;
2663         }
2664
2665 #ifdef __sparc__
2666         atyfb_save_palette(par, 0);
2667 #endif
2668
2669 #ifdef CONFIG_FB_ATY_CT
2670         if (!noaccel && M64_HAS(INTEGRATED))
2671                 aty_init_cursor(info);
2672 #endif /* CONFIG_FB_ATY_CT */
2673         info->var = var;
2674
2675         fb_alloc_cmap(&info->cmap, 256, 0);
2676
2677         if (register_framebuffer(info) < 0)
2678                 goto aty_init_exit;
2679
2680         fb_list = info;
2681
2682         PRINTKI("fb%d: %s frame buffer device on %s\n",
2683                 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2684         return 0;
2685
2686 aty_init_exit:
2687         /* restore video mode */
2688         aty_set_crtc(par, &saved_crtc);
2689         par->pll_ops->set_pll(info, &saved_pll);
2690
2691 #ifdef CONFIG_MTRR
2692         if (par->mtrr_reg >= 0) {
2693             mtrr_del(par->mtrr_reg, 0, 0);
2694             par->mtrr_reg = -1;
2695         }
2696         if (par->mtrr_aper >= 0) {
2697             mtrr_del(par->mtrr_aper, 0, 0);
2698             par->mtrr_aper = -1;
2699         }
2700 #endif
2701         return -1;
2702 }
2703
2704 static void aty_resume_chip(struct fb_info *info)
2705 {
2706         struct atyfb_par *par = info->par;
2707
2708         aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2709
2710         if (par->pll_ops->resume_pll)
2711                 par->pll_ops->resume_pll(info, &par->pll);
2712
2713         if (par->aux_start)
2714                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2715 }
2716
2717 #ifdef CONFIG_ATARI
2718 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2719 {
2720         char *p;
2721         unsigned long vmembase, size, guiregbase;
2722
2723         PRINTKI("store_video_par() '%s' \n", video_str);
2724
2725         if (!(p = strsep(&video_str, ";")) || !*p)
2726                 goto mach64_invalid;
2727         vmembase = simple_strtoul(p, NULL, 0);
2728         if (!(p = strsep(&video_str, ";")) || !*p)
2729                 goto mach64_invalid;
2730         size = simple_strtoul(p, NULL, 0);
2731         if (!(p = strsep(&video_str, ";")) || !*p)
2732                 goto mach64_invalid;
2733         guiregbase = simple_strtoul(p, NULL, 0);
2734
2735         phys_vmembase[m64_num] = vmembase;
2736         phys_size[m64_num] = size;
2737         phys_guiregbase[m64_num] = guiregbase;
2738         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2739                guiregbase);
2740         return 0;
2741
2742       mach64_invalid:
2743         phys_vmembase[m64_num] = 0;
2744         return -1;
2745 }
2746 #endif /* CONFIG_ATARI */
2747
2748     /*
2749      *  Blank the display.
2750      */
2751
2752 static int atyfb_blank(int blank, struct fb_info *info)
2753 {
2754         struct atyfb_par *par = (struct atyfb_par *) info->par;
2755         u32 gen_cntl;
2756
2757         if (par->lock_blank || par->asleep)
2758                 return 0;
2759
2760 #ifdef CONFIG_FB_ATY_BACKLIGHT
2761 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2762         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2763             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2764                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2765                 pm &= ~PWR_BLON;
2766                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2767         }
2768 #endif
2769
2770         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2771         gen_cntl &= ~0x400004c;
2772         switch (blank) {
2773                 case FB_BLANK_UNBLANK:
2774                         break;
2775                 case FB_BLANK_NORMAL:
2776                         gen_cntl |= 0x4000040;
2777                         break;
2778                 case FB_BLANK_VSYNC_SUSPEND:
2779                         gen_cntl |= 0x4000048;
2780                         break;
2781                 case FB_BLANK_HSYNC_SUSPEND:
2782                         gen_cntl |= 0x4000044;
2783                         break;
2784                 case FB_BLANK_POWERDOWN:
2785                         gen_cntl |= 0x400004c;
2786                         break;
2787         }
2788         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2789
2790 #ifdef CONFIG_FB_ATY_BACKLIGHT
2791 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2792         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2793             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2794                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2795                 pm |= PWR_BLON;
2796                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2797         }
2798 #endif
2799
2800         return 0;
2801 }
2802
2803 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2804                        const struct atyfb_par *par)
2805 {
2806         aty_st_8(DAC_W_INDEX, regno, par);
2807         aty_st_8(DAC_DATA, red, par);
2808         aty_st_8(DAC_DATA, green, par);
2809         aty_st_8(DAC_DATA, blue, par);
2810 }
2811
2812     /*
2813      *  Set a single color register. The values supplied are already
2814      *  rounded down to the hardware's capabilities (according to the
2815      *  entries in the var structure). Return != 0 for invalid regno.
2816      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2817      */
2818
2819 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2820         u_int transp, struct fb_info *info)
2821 {
2822         struct atyfb_par *par = (struct atyfb_par *) info->par;
2823         int i, depth;
2824         u32 *pal = info->pseudo_palette;
2825
2826         depth = info->var.bits_per_pixel;
2827         if (depth == 16)
2828                 depth = (info->var.green.length == 5) ? 15 : 16;
2829
2830         if (par->asleep)
2831                 return 0;
2832
2833         if (regno > 255 ||
2834             (depth == 16 && regno > 63) ||
2835             (depth == 15 && regno > 31))
2836                 return 1;
2837
2838         red >>= 8;
2839         green >>= 8;
2840         blue >>= 8;
2841
2842         par->palette[regno].red = red;
2843         par->palette[regno].green = green;
2844         par->palette[regno].blue = blue;
2845
2846         if (regno < 16) {
2847                 switch (depth) {
2848                 case 15:
2849                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2850                         break;
2851                 case 16:
2852                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2853                         break;
2854                 case 24:
2855                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2856                         break;
2857                 case 32:
2858                         i = (regno << 8) | regno;
2859                         pal[regno] = (i << 16) | i;
2860                         break;
2861                 }
2862         }
2863
2864         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2865         if (M64_HAS(EXTRA_BRIGHT))
2866                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2867         aty_st_8(DAC_CNTL, i, par);
2868         aty_st_8(DAC_MASK, 0xff, par);
2869
2870         if (M64_HAS(INTEGRATED)) {
2871                 if (depth == 16) {
2872                         if (regno < 32)
2873                                 aty_st_pal(regno << 3, red,
2874                                            par->palette[regno<<1].green,
2875                                            blue, par);
2876                         red = par->palette[regno>>1].red;
2877                         blue = par->palette[regno>>1].blue;
2878                         regno <<= 2;
2879                 } else if (depth == 15) {
2880                         regno <<= 3;
2881                         for(i = 0; i < 8; i++) {
2882                             aty_st_pal(regno + i, red, green, blue, par);
2883                         }
2884                 }
2885         }
2886         aty_st_pal(regno, red, green, blue, par);
2887
2888         return 0;
2889 }
2890
2891 #ifdef CONFIG_PCI
2892
2893 #ifdef __sparc__
2894
2895 extern void (*prom_palette) (int);
2896
2897 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2898                         struct fb_info *info, unsigned long addr)
2899 {
2900         struct atyfb_par *par = info->par;
2901         struct pcidev_cookie *pcp;
2902         char prop[128];
2903         int node, len, i, j, ret;
2904         u32 mem, chip_id;
2905
2906         /* Do not attach when we have a serial console. */
2907         if (!con_is_present())
2908                 return -ENXIO;
2909
2910         /*
2911          * Map memory-mapped registers.
2912          */
2913         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2914         info->fix.mmio_start = addr + 0x7ffc00UL;
2915
2916         /*
2917          * Map in big-endian aperture.
2918          */
2919         info->screen_base = (char *) (addr + 0x800000UL);
2920         info->fix.smem_start = addr + 0x800000UL;
2921
2922         /*
2923          * Figure mmap addresses from PCI config space.
2924          * Split Framebuffer in big- and little-endian halfs.
2925          */
2926         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2927                 /* nothing */ ;
2928         j = i + 4;
2929
2930         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2931         if (!par->mmap_map) {
2932                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2933                 return -ENOMEM;
2934         }
2935         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2936
2937         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2938                 struct resource *rp = &pdev->resource[i];
2939                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2940                 unsigned long base;
2941                 u32 size, pbase;
2942
2943                 base = rp->start;
2944
2945                 io = (rp->flags & IORESOURCE_IO);
2946
2947                 size = rp->end - base + 1;
2948
2949                 pci_read_config_dword(pdev, breg, &pbase);
2950
2951                 if (io)
2952                         size &= ~1;
2953
2954                 /*
2955                  * Map the framebuffer a second time, this time without
2956                  * the braindead _PAGE_IE setting. This is used by the
2957                  * fixed Xserver, but we need to maintain the old mapping
2958                  * to stay compatible with older ones...
2959                  */
2960                 if (base == addr) {
2961                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2962                         par->mmap_map[j].poff = base & PAGE_MASK;
2963                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2964                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2965                         par->mmap_map[j].prot_flag = _PAGE_E;
2966                         j++;
2967                 }
2968
2969                 /*
2970                  * Here comes the old framebuffer mapping with _PAGE_IE
2971                  * set for the big endian half of the framebuffer...
2972                  */
2973                 if (base == addr) {
2974                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2975                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2976                         par->mmap_map[j].size = 0x800000;
2977                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2978                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2979                         size -= 0x800000;
2980                         j++;
2981                 }
2982
2983                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2984                 par->mmap_map[j].poff = base & PAGE_MASK;
2985                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2986                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2987                 par->mmap_map[j].prot_flag = _PAGE_E;
2988                 j++;
2989         }
2990
2991         if((ret = correct_chipset(par)))
2992                 return ret;
2993
2994         if (IS_XL(pdev->device)) {
2995                 /*
2996                  * Fix PROMs idea of MEM_CNTL settings...
2997                  */
2998                 mem = aty_ld_le32(MEM_CNTL, par);
2999                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3000                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3001                         switch (mem & 0x0f) {
3002                         case 3:
3003                                 mem = (mem & ~(0x0f)) | 2;
3004                                 break;
3005                         case 7:
3006                                 mem = (mem & ~(0x0f)) | 3;
3007                                 break;
3008                         case 9:
3009                                 mem = (mem & ~(0x0f)) | 4;
3010                                 break;
3011                         case 11:
3012                                 mem = (mem & ~(0x0f)) | 5;
3013                                 break;
3014                         default:
3015                                 break;
3016                         }
3017                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3018                                 mem &= ~(0x00700000);
3019                 }
3020                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
3021                 aty_st_le32(MEM_CNTL, mem, par);
3022         }
3023
3024         /*
3025          * If this is the console device, we will set default video
3026          * settings to what the PROM left us with.
3027          */
3028         node = prom_getchild(prom_root_node);
3029         node = prom_searchsiblings(node, "aliases");
3030         if (node) {
3031                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3032                 if (len > 0) {
3033                         prop[len] = '\0';
3034                         node = prom_finddevice(prop);
3035                 } else
3036                         node = 0;
3037         }
3038
3039         pcp = pdev->sysdata;
3040         if (node == pcp->prom_node->node) {
3041                 struct fb_var_screeninfo *var = &default_var;
3042                 unsigned int N, P, Q, M, T, R;
3043                 u32 v_total, h_total;
3044                 struct crtc crtc;
3045                 u8 pll_regs[16];
3046                 u8 clock_cntl;
3047
3048                 crtc.vxres = prom_getintdefault(node, "width", 1024);
3049                 crtc.vyres = prom_getintdefault(node, "height", 768);
3050                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3051                 var->xoffset = var->yoffset = 0;
3052                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3053                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3054                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3055                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3056                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3057                 aty_crtc_to_var(&crtc, var);
3058
3059                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3060                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3061
3062                 /*
3063                  * Read the PLL to figure actual Refresh Rate.
3064                  */
3065                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3066                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3067                 for (i = 0; i < 16; i++)
3068                         pll_regs[i] = aty_ld_pll_ct(i, par);
3069
3070                 /*
3071                  * PLL Reference Divider M:
3072                  */
3073                 M = pll_regs[2];
3074
3075                 /*
3076                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3077                  */
3078                 N = pll_regs[7 + (clock_cntl & 3)];
3079
3080                 /*
3081                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3082                  */
3083                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3084
3085                 /*
3086                  * PLL Divider Q:
3087                  */
3088                 Q = N / P;
3089
3090                 /*
3091                  * Target Frequency:
3092                  *
3093                  *      T * M
3094                  * Q = -------
3095                  *      2 * R
3096                  *
3097                  * where R is XTALIN (= 14318 or 29498 kHz).
3098                  */
3099                 if (IS_XL(pdev->device))
3100                         R = 29498;
3101                 else
3102                         R = 14318;
3103
3104                 T = 2 * Q * R / M;
3105
3106                 default_var.pixclock = 1000000000 / T;
3107         }
3108
3109         return 0;
3110 }
3111
3112 #else /* __sparc__ */
3113
3114 #ifdef __i386__
3115 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3116 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3117 {
3118         u32 driv_inf_tab, sig;
3119         u16 lcd_ofs;
3120
3121         /* To support an LCD panel, we should know it's dimensions and
3122          *  it's desired pixel clock.
3123          * There are two ways to do it:
3124          *  - Check the startup video mode and calculate the panel
3125          *    size from it. This is unreliable.
3126          *  - Read it from the driver information table in the video BIOS.
3127         */
3128         /* Address of driver information table is at offset 0x78. */
3129         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3130
3131         /* Check for the driver information table signature. */
3132         sig = (*(u32 *)driv_inf_tab);
3133         if ((sig == 0x54504c24) || /* Rage LT pro */
3134                 (sig == 0x544d5224) || /* Rage mobility */
3135                 (sig == 0x54435824) || /* Rage XC */
3136                 (sig == 0x544c5824)) { /* Rage XL */
3137                 PRINTKI("BIOS contains driver information table.\n");
3138                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3139                 par->lcd_table = 0;
3140                 if (lcd_ofs != 0) {
3141                         par->lcd_table = bios_base + lcd_ofs;
3142                 }
3143         }
3144
3145         if (par->lcd_table != 0) {
3146                 char model[24];
3147                 char strbuf[16];
3148                 char refresh_rates_buf[100];
3149                 int id, tech, f, i, m, default_refresh_rate;
3150                 char *txtcolour;
3151                 char *txtmonitor;
3152                 char *txtdual;
3153                 char *txtformat;
3154                 u16 width, height, panel_type, refresh_rates;
3155                 u16 *lcdmodeptr;
3156                 u32 format;
3157                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3158                 /* The most important information is the panel size at
3159                  * offset 25 and 27, but there's some other nice information
3160                  * which we print to the screen.
3161                  */
3162                 id = *(u8 *)par->lcd_table;
3163                 strncpy(model,(char *)par->lcd_table+1,24);
3164                 model[23]=0;
3165
3166                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3167                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3168                 panel_type = *(u16 *)(par->lcd_table+29);
3169                 if (panel_type & 1)
3170                         txtcolour = "colour";
3171                 else
3172                         txtcolour = "monochrome";
3173                 if (panel_type & 2)
3174                         txtdual = "dual (split) ";
3175                 else
3176                         txtdual = "";
3177                 tech = (panel_type>>2) & 63;
3178                 switch (tech) {
3179                 case 0:
3180                         txtmonitor = "passive matrix";
3181                         break;
3182                 case 1:
3183                         txtmonitor = "active matrix";
3184                         break;
3185                 case 2:
3186                         txtmonitor = "active addressed STN";
3187                         break;
3188                 case 3:
3189                         txtmonitor = "EL";
3190                         break;
3191                 case 4:
3192                         txtmonitor = "plasma";
3193                         break;
3194                 default:
3195                         txtmonitor = "unknown";
3196                 }
3197                 format = *(u32 *)(par->lcd_table+57);
3198                 if (tech == 0 || tech == 2) {
3199                         switch (format & 7) {
3200                         case 0:
3201                                 txtformat = "12 bit interface";
3202                                 break;
3203                         case 1:
3204                                 txtformat = "16 bit interface";
3205                                 break;
3206                         case 2:
3207                                 txtformat = "24 bit interface";
3208                                 break;
3209                         default:
3210                                 txtformat = "unkown format";
3211                         }
3212                 } else {
3213                         switch (format & 7) {
3214                         case 0:
3215                                 txtformat = "8 colours";
3216                                 break;
3217                         case 1:
3218                                 txtformat = "512 colours";
3219                                 break;
3220                         case 2:
3221                                 txtformat = "4096 colours";
3222                                 break;
3223                         case 4:
3224                                 txtformat = "262144 colours (LT mode)";
3225                                 break;
3226                         case 5:
3227                                 txtformat = "16777216 colours";
3228                                 break;
3229                         case 6:
3230                                 txtformat = "262144 colours (FDPI-2 mode)";
3231                                 break;
3232                         default:
3233                                 txtformat = "unkown format";
3234                         }
3235                 }
3236                 PRINTKI("%s%s %s monitor detected: %s\n",
3237                         txtdual ,txtcolour, txtmonitor, model);
3238                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3239                         id, width, height, txtformat);
3240                 refresh_rates_buf[0] = 0;
3241                 refresh_rates = *(u16 *)(par->lcd_table+62);
3242                 m = 1;
3243                 f = 0;
3244                 for (i=0;i<16;i++) {
3245                         if (refresh_rates & m) {
3246                                 if (f == 0) {
3247                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3248                                         f++;
3249                                 } else {
3250                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3251                                 }
3252                                 strcat(refresh_rates_buf,strbuf);
3253                         }
3254                         m = m << 1;
3255                 }
3256                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3257                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3258                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3259                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3260                 /* We now need to determine the crtc parameters for the
3261                  * LCD monitor. This is tricky, because they are not stored
3262                  * individually in the BIOS. Instead, the BIOS contains a
3263                  * table of display modes that work for this monitor.
3264                  *
3265                  * The idea is that we search for a mode of the same dimensions
3266                  * as the dimensions of the LCD monitor. Say our LCD monitor
3267                  * is 800x600 pixels, we search for a 800x600 monitor.
3268                  * The CRTC parameters we find here are the ones that we need
3269                  * to use to simulate other resolutions on the LCD screen.
3270                  */
3271                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3272                 while (*lcdmodeptr != 0) {
3273                         u32 modeptr;
3274                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3275                         modeptr = bios_base + *lcdmodeptr;
3276
3277                         mwidth = *((u16 *)(modeptr+0));
3278                         mheight = *((u16 *)(modeptr+2));
3279
3280                         if (mwidth == width && mheight == height) {
3281                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3282                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3283                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3284                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3285                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3286                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3287
3288                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3289                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3290                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3291                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3292
3293                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3294                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3295                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3296                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3297
3298                                 par->lcd_vtotal++;
3299                                 par->lcd_vdisp++;
3300                                 lcd_vsync_start++;
3301
3302                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3303                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3304                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3305                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3306                                 break;
3307                         }
3308
3309                         lcdmodeptr++;
3310                 }
3311                 if (*lcdmodeptr == 0) {
3312                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3313                         /* To do: Switch to CRT if possible. */
3314                 } else {
3315                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3316                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3317                                 par->lcd_hdisp,
3318                                 par->lcd_hdisp + par->lcd_right_margin,
3319                                 par->lcd_hdisp + par->lcd_right_margin
3320                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3321                                 par->lcd_htotal,
3322                                 par->lcd_vdisp,
3323                                 par->lcd_vdisp + par->lcd_lower_margin,
3324                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3325                                 par->lcd_vtotal);
3326                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3327                                 par->lcd_pixclock,
3328                                 par->lcd_hblank_len - (par->lcd_right_margin +
3329                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3330                                 par->lcd_hdisp,
3331                                 par->lcd_right_margin,
3332                                 par->lcd_hsync_len,
3333                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3334                                 par->lcd_vdisp,
3335                                 par->lcd_lower_margin,
3336                                 par->lcd_vsync_len);
3337                 }
3338         }
3339 }
3340 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3341
3342 static int __devinit init_from_bios(struct atyfb_par *par)
3343 {
3344         u32 bios_base, rom_addr;
3345         int ret;
3346
3347         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3348         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3349
3350         /* The BIOS starts with 0xaa55. */
3351         if (*((u16 *)bios_base) == 0xaa55) {
3352
3353                 u8 *bios_ptr;
3354                 u16 rom_table_offset, freq_table_offset;
3355                 PLL_BLOCK_MACH64 pll_block;
3356
3357                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3358
3359                 /* check for frequncy table */
3360                 bios_ptr = (u8*)bios_base;
3361                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3362                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3363                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3364
3365                 PRINTKI("BIOS frequency table:\n");
3366                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3367                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3368                         pll_block.ref_freq, pll_block.ref_divider);
3369                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3370                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3371                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3372
3373                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3374                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3375                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3376                 par->pll_limits.ref_div = pll_block.ref_divider;
3377                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3378                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3379                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3380                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3381 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3382                 aty_init_lcd(par, bios_base);
3383 #endif
3384                 ret = 0;
3385         } else {
3386                 PRINTKE("no BIOS frequency table found, use parameters\n");
3387                 ret = -ENXIO;
3388         }
3389         iounmap((void* __iomem )bios_base);
3390
3391         return ret;
3392 }
3393 #endif /* __i386__ */
3394
3395 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3396 {
3397         struct atyfb_par *par = info->par;
3398         u16 tmp;
3399         unsigned long raddr;
3400         struct resource *rrp;
3401         int ret = 0;
3402
3403         raddr = addr + 0x7ff000UL;
3404         rrp = &pdev->resource[2];
3405         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3406                 par->aux_start = rrp->start;
3407                 par->aux_size = rrp->end - rrp->start + 1;
3408                 raddr = rrp->start;
3409                 PRINTKI("using auxiliary register aperture\n");
3410         }
3411
3412         info->fix.mmio_start = raddr;
3413         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3414         if (par->ati_regbase == 0)
3415                 return -ENOMEM;
3416
3417         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3418         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3419
3420         /*
3421          * Enable memory-space accesses using config-space
3422          * command register.
3423          */
3424         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3425         if (!(tmp & PCI_COMMAND_MEMORY)) {
3426                 tmp |= PCI_COMMAND_MEMORY;
3427                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3428         }
3429 #ifdef __BIG_ENDIAN
3430         /* Use the big-endian aperture */
3431         addr += 0x800000;
3432 #endif
3433
3434         /* Map in frame buffer */
3435         info->fix.smem_start = addr;
3436         info->screen_base = ioremap(addr, 0x800000);
3437         if (info->screen_base == NULL) {
3438                 ret = -ENOMEM;
3439                 goto atyfb_setup_generic_fail;
3440         }
3441
3442         if((ret = correct_chipset(par)))
3443                 goto atyfb_setup_generic_fail;
3444 #ifdef __i386__
3445         if((ret = init_from_bios(par)))
3446                 goto atyfb_setup_generic_fail;
3447 #endif
3448         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3449                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3450         else
3451                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3452
3453         /* according to ATI, we should use clock 3 for acelerated mode */
3454         par->clk_wr_offset = 3;
3455
3456         return 0;
3457
3458 atyfb_setup_generic_fail:
3459         iounmap(par->ati_regbase);
3460         par->ati_regbase = NULL;
3461         if (info->screen_base) {
3462                 iounmap(info->screen_base);
3463                 info->screen_base = NULL;
3464         }
3465         return ret;
3466 }
3467
3468 #endif /* !__sparc__ */
3469
3470 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3471 {
3472         unsigned long addr, res_start, res_size;
3473         struct fb_info *info;
3474         struct resource *rp;
3475         struct atyfb_par *par;
3476         int i, rc = -ENOMEM;
3477
3478         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3479                 if (pdev->device == aty_chips[i].pci_id)
3480                         break;
3481
3482         if (i < 0)
3483                 return -ENODEV;
3484
3485         /* Enable device in PCI config */
3486         if (pci_enable_device(pdev)) {
3487                 PRINTKE("Cannot enable PCI device\n");
3488                 return -ENXIO;
3489         }
3490
3491         /* Find which resource to use */
3492         rp = &pdev->resource[0];
3493         if (rp->flags & IORESOURCE_IO)
3494                 rp = &pdev->resource[1];
3495         addr = rp->start;
3496         if (!addr)
3497                 return -ENXIO;
3498
3499         /* Reserve space */
3500         res_start = rp->start;
3501         res_size = rp->end - rp->start + 1;
3502         if (!request_mem_region (res_start, res_size, "atyfb"))
3503                 return -EBUSY;
3504
3505         /* Allocate framebuffer */
3506         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3507         if (!info) {
3508                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3509                 return -ENOMEM;
3510         }
3511         par = info->par;
3512         info->fix = atyfb_fix;
3513         info->device = &pdev->dev;
3514         par->pci_id = aty_chips[i].pci_id;
3515         par->res_start = res_start;
3516         par->res_size = res_size;
3517         par->irq = pdev->irq;
3518         par->pdev = pdev;
3519
3520         /* Setup "info" structure */
3521 #ifdef __sparc__
3522         rc = atyfb_setup_sparc(pdev, info, addr);
3523 #else
3524         rc = atyfb_setup_generic(pdev, info, addr);
3525 #endif
3526         if (rc)
3527                 goto err_release_mem;
3528
3529         pci_set_drvdata(pdev, info);
3530
3531         /* Init chip & register framebuffer */
3532         if (aty_init(info))
3533                 goto err_release_io;
3534
3535 #ifdef __sparc__
3536         if (!prom_palette)
3537                 prom_palette = atyfb_palette;
3538
3539         /*
3540          * Add /dev/fb mmap values.
3541          */
3542         par->mmap_map[0].voff = 0x8000000000000000UL;
3543         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3544         par->mmap_map[0].size = info->fix.smem_len;
3545         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3546         par->mmap_map[0].prot_flag = _PAGE_E;
3547         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3548         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3549         par->mmap_map[1].size = PAGE_SIZE;
3550         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3551         par->mmap_map[1].prot_flag = _PAGE_E;
3552 #endif /* __sparc__ */
3553
3554         return 0;
3555
3556 err_release_io:
3557 #ifdef __sparc__
3558         kfree(par->mmap_map);
3559 #else
3560         if (par->ati_regbase)
3561                 iounmap(par->ati_regbase);
3562         if (info->screen_base)
3563                 iounmap(info->screen_base);
3564 #endif
3565 err_release_mem:
3566         if (par->aux_start)
3567                 release_mem_region(par->aux_start, par->aux_size);
3568
3569         release_mem_region(par->res_start, par->res_size);
3570         framebuffer_release(info);
3571
3572         return rc;
3573 }
3574
3575 #endif /* CONFIG_PCI */
3576
3577 #ifdef CONFIG_ATARI
3578
3579 static int __init atyfb_atari_probe(void)
3580 {
3581         struct atyfb_par *par;
3582         struct fb_info *info;
3583         int m64_num;
3584         u32 clock_r;
3585         int num_found = 0;
3586
3587         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3588                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3589                     !phys_guiregbase[m64_num]) {
3590                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3591                         continue;
3592                 }
3593
3594                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3595                 if (!info) {
3596                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3597                         return -ENOMEM;
3598                 }
3599                 par = info->par;
3600
3601                 info->fix = atyfb_fix;
3602
3603                 par->irq = (unsigned int) -1; /* something invalid */
3604
3605                 /*
3606                  *  Map the video memory (physical address given) to somewhere in the
3607                  *  kernel address space.
3608                  */
3609                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3610                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3611                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3612                                                 0xFC00ul;
3613                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3614
3615                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3616                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3617
3618                 switch (clock_r & 0x003F) {
3619                 case 0x12:
3620                         par->clk_wr_offset = 3; /*  */
3621                         break;
3622                 case 0x34:
3623                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3624                         break;
3625                 case 0x16:
3626                         par->clk_wr_offset = 1; /*  */
3627                         break;
3628                 case 0x38:
3629                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3630                         break;
3631                 }
3632
3633                 /* Fake pci_id for correct_chipset() */
3634                 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3635                 case 0x00d7:
3636                         par->pci_id = PCI_CHIP_MACH64GX;
3637                         break;
3638                 case 0x0057:
3639                         par->pci_id = PCI_CHIP_MACH64CX;
3640                         break;
3641                 default:
3642                         break;
3643                 }
3644
3645                 if (correct_chipset(par) || aty_init(info)) {
3646                         iounmap(info->screen_base);
3647                         iounmap(par->ati_regbase);
3648                         framebuffer_release(info);
3649                 } else {
3650                         num_found++;
3651                 }
3652         }
3653
3654         return num_found ? 0 : -ENXIO;
3655 }
3656
3657 #endif /* CONFIG_ATARI */
3658
3659 #ifdef CONFIG_PCI
3660
3661 static void __devexit atyfb_remove(struct fb_info *info)
3662 {
3663         struct atyfb_par *par = (struct atyfb_par *) info->par;
3664
3665         /* restore video mode */
3666         aty_set_crtc(par, &saved_crtc);
3667         par->pll_ops->set_pll(info, &saved_pll);
3668
3669         unregister_framebuffer(info);
3670
3671 #ifdef CONFIG_FB_ATY_BACKLIGHT
3672         if (M64_HAS(MOBIL_BUS))
3673                 aty_bl_exit(info->bl_dev);
3674 #endif
3675
3676 #ifdef CONFIG_MTRR
3677         if (par->mtrr_reg >= 0) {
3678             mtrr_del(par->mtrr_reg, 0, 0);
3679             par->mtrr_reg = -1;
3680         }
3681         if (par->mtrr_aper >= 0) {
3682             mtrr_del(par->mtrr_aper, 0, 0);
3683             par->mtrr_aper = -1;
3684         }
3685 #endif
3686 #ifndef __sparc__
3687         if (par->ati_regbase)
3688                 iounmap(par->ati_regbase);
3689         if (info->screen_base)
3690                 iounmap(info->screen_base);
3691 #ifdef __BIG_ENDIAN
3692         if (info->sprite.addr)
3693                 iounmap(info->sprite.addr);
3694 #endif
3695 #endif
3696 #ifdef __sparc__
3697         kfree(par->mmap_map);
3698 #endif
3699         if (par->aux_start)
3700                 release_mem_region(par->aux_start, par->aux_size);
3701
3702         if (par->res_start)
3703                 release_mem_region(par->res_start, par->res_size);
3704
3705         framebuffer_release(info);
3706 }
3707
3708
3709 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3710 {
3711         struct fb_info *info = pci_get_drvdata(pdev);
3712
3713         atyfb_remove(info);
3714 }
3715
3716 /*
3717  * This driver uses its own matching table. That will be more difficult
3718  * to fix, so for now, we just match against any ATI ID and let the
3719  * probe() function find out what's up. That also mean we don't have
3720  * a module ID table though.
3721  */
3722 static struct pci_device_id atyfb_pci_tbl[] = {
3723         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3724           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3725         { 0, }
3726 };
3727
3728 static struct pci_driver atyfb_driver = {
3729         .name           = "atyfb",
3730         .id_table       = atyfb_pci_tbl,
3731         .probe          = atyfb_pci_probe,
3732         .remove         = __devexit_p(atyfb_pci_remove),
3733 #ifdef CONFIG_PM
3734         .suspend        = atyfb_pci_suspend,
3735         .resume         = atyfb_pci_resume,
3736 #endif /* CONFIG_PM */
3737 };
3738
3739 #endif /* CONFIG_PCI */
3740
3741 #ifndef MODULE
3742 static int __init atyfb_setup(char *options)
3743 {
3744         char *this_opt;
3745
3746         if (!options || !*options)
3747                 return 0;
3748
3749         while ((this_opt = strsep(&options, ",")) != NULL) {
3750                 if (!strncmp(this_opt, "noaccel", 7)) {
3751                         noaccel = 1;
3752 #ifdef CONFIG_MTRR
3753                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3754                         nomtrr = 1;
3755 #endif
3756                 } else if (!strncmp(this_opt, "vram:", 5))
3757                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3758                 else if (!strncmp(this_opt, "pll:", 4))
3759                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3760                 else if (!strncmp(this_opt, "mclk:", 5))
3761                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3762                 else if (!strncmp(this_opt, "xclk:", 5))
3763                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3764                 else if (!strncmp(this_opt, "comp_sync:", 10))
3765                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3766                 else if (!strncmp(this_opt, "backlight:", 10))
3767                         backlight = simple_strtoul(this_opt+10, NULL, 0);
3768 #ifdef CONFIG_PPC
3769                 else if (!strncmp(this_opt, "vmode:", 6)) {
3770                         unsigned int vmode =
3771                             simple_strtoul(this_opt + 6, NULL, 0);
3772                         if (vmode > 0 && vmode <= VMODE_MAX)
3773                                 default_vmode = vmode;
3774                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3775                         unsigned int cmode =
3776                             simple_strtoul(this_opt + 6, NULL, 0);
3777                         switch (cmode) {
3778                         case 0:
3779                         case 8:
3780                                 default_cmode = CMODE_8;
3781                                 break;
3782                         case 15:
3783                         case 16:
3784                                 default_cmode = CMODE_16;
3785                                 break;
3786                         case 24:
3787                         case 32:
3788                                 default_cmode = CMODE_32;
3789                                 break;
3790                         }
3791                 }
3792 #endif
3793 #ifdef CONFIG_ATARI
3794                 /*
3795                  * Why do we need this silly Mach64 argument?
3796                  * We are already here because of mach64= so its redundant.
3797                  */
3798                 else if (MACH_IS_ATARI
3799                          && (!strncmp(this_opt, "Mach64:", 7))) {
3800                         static unsigned char m64_num;
3801                         static char mach64_str[80];
3802                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3803                         if (!store_video_par(mach64_str, m64_num)) {
3804                                 m64_num++;
3805                                 mach64_count = m64_num;
3806                         }
3807                 }
3808 #endif
3809                 else
3810                         mode = this_opt;
3811         }
3812         return 0;
3813 }
3814 #endif  /*  MODULE  */
3815
3816 static int __init atyfb_init(void)
3817 {
3818     int err1 = 1, err2 = 1;
3819 #ifndef MODULE
3820     char *option = NULL;
3821
3822     if (fb_get_options("atyfb", &option))
3823         return -ENODEV;
3824     atyfb_setup(option);
3825 #endif
3826
3827 #ifdef CONFIG_PCI
3828     err1 = pci_register_driver(&atyfb_driver);
3829 #endif
3830 #ifdef CONFIG_ATARI
3831     err2 = atyfb_atari_probe();
3832 #endif
3833
3834     return (err1 && err2) ? -ENODEV : 0;
3835 }
3836
3837 static void __exit atyfb_exit(void)
3838 {
3839 #ifdef CONFIG_PCI
3840         pci_unregister_driver(&atyfb_driver);
3841 #endif
3842 }
3843
3844 module_init(atyfb_init);
3845 module_exit(atyfb_exit);
3846
3847 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3848 MODULE_LICENSE("GPL");
3849 module_param(noaccel, bool, 0);
3850 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3851 module_param(vram, int, 0);
3852 MODULE_PARM_DESC(vram, "int: override size of video ram");
3853 module_param(pll, int, 0);
3854 MODULE_PARM_DESC(pll, "int: override video clock");
3855 module_param(mclk, int, 0);
3856 MODULE_PARM_DESC(mclk, "int: override memory clock");
3857 module_param(xclk, int, 0);
3858 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3859 module_param(comp_sync, int, 0);
3860 MODULE_PARM_DESC(comp_sync,
3861                  "Set composite sync signal to low (0) or high (1)");
3862 module_param(mode, charp, 0);
3863 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3864 #ifdef CONFIG_MTRR
3865 module_param(nomtrr, bool, 0);
3866 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3867 #endif