Merge git://bedivere.hansenpartnership.com/git/scsi-rc-fixes-2.6
[linux-2.6.git] / drivers / usb / musb / ux500_dma.c
1 /*
2  * drivers/usb/musb/ux500_dma.c
3  *
4  * U8500 and U5500 DMA support code
5  *
6  * Copyright (C) 2009 STMicroelectronics
7  * Copyright (C) 2011 ST-Ericsson SA
8  * Authors:
9  *      Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
10  *      Praveena Nadahally <praveen.nadahally@stericsson.com>
11  *      Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
12  *
13  * This program is free software: you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation, either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
25  */
26
27 #include <linux/device.h>
28 #include <linux/interrupt.h>
29 #include <linux/platform_device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pfn.h>
33 #include <mach/usb.h>
34 #include "musb_core.h"
35
36 struct ux500_dma_channel {
37         struct dma_channel channel;
38         struct ux500_dma_controller *controller;
39         struct musb_hw_ep *hw_ep;
40         struct work_struct channel_work;
41         struct dma_chan *dma_chan;
42         unsigned int cur_len;
43         dma_cookie_t cookie;
44         u8 ch_num;
45         u8 is_tx;
46         u8 is_allocated;
47 };
48
49 struct ux500_dma_controller {
50         struct dma_controller controller;
51         struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
52         struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
53         u32     num_rx_channels;
54         u32     num_tx_channels;
55         void *private_data;
56         dma_addr_t phy_base;
57 };
58
59 /* Work function invoked from DMA callback to handle tx transfers. */
60 static void ux500_tx_work(struct work_struct *data)
61 {
62         struct ux500_dma_channel *ux500_channel = container_of(data,
63                 struct ux500_dma_channel, channel_work);
64         struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
65         struct musb *musb = hw_ep->musb;
66         unsigned long flags;
67
68         dev_dbg(musb->controller, "DMA tx transfer done on hw_ep=%d\n",
69                 hw_ep->epnum);
70
71         spin_lock_irqsave(&musb->lock, flags);
72         ux500_channel->channel.actual_len = ux500_channel->cur_len;
73         ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
74         musb_dma_completion(musb, hw_ep->epnum,
75                                 ux500_channel->is_tx);
76         spin_unlock_irqrestore(&musb->lock, flags);
77 }
78
79 /* Work function invoked from DMA callback to handle rx transfers. */
80 static void ux500_rx_work(struct work_struct *data)
81 {
82         struct ux500_dma_channel *ux500_channel = container_of(data,
83                 struct ux500_dma_channel, channel_work);
84         struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
85         struct musb *musb = hw_ep->musb;
86         unsigned long flags;
87
88         dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
89                 hw_ep->epnum);
90
91         spin_lock_irqsave(&musb->lock, flags);
92         ux500_channel->channel.actual_len = ux500_channel->cur_len;
93         ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
94         musb_dma_completion(musb, hw_ep->epnum,
95                 ux500_channel->is_tx);
96         spin_unlock_irqrestore(&musb->lock, flags);
97 }
98
99 void ux500_dma_callback(void *private_data)
100 {
101         struct dma_channel *channel = (struct dma_channel *)private_data;
102         struct ux500_dma_channel *ux500_channel = channel->private_data;
103
104         schedule_work(&ux500_channel->channel_work);
105 }
106
107 static bool ux500_configure_channel(struct dma_channel *channel,
108                                 u16 packet_sz, u8 mode,
109                                 dma_addr_t dma_addr, u32 len)
110 {
111         struct ux500_dma_channel *ux500_channel = channel->private_data;
112         struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
113         struct dma_chan *dma_chan = ux500_channel->dma_chan;
114         struct dma_async_tx_descriptor *dma_desc;
115         enum dma_data_direction direction;
116         struct scatterlist sg;
117         struct dma_slave_config slave_conf;
118         enum dma_slave_buswidth addr_width;
119         dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) +
120                                         ux500_channel->controller->phy_base);
121         struct musb *musb = ux500_channel->controller->private_data;
122
123         dev_dbg(musb->controller,
124                 "packet_sz=%d, mode=%d, dma_addr=0x%x, len=%d is_tx=%d\n",
125                 packet_sz, mode, dma_addr, len, ux500_channel->is_tx);
126
127         ux500_channel->cur_len = len;
128
129         sg_init_table(&sg, 1);
130         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
131                                             offset_in_page(dma_addr));
132         sg_dma_address(&sg) = dma_addr;
133         sg_dma_len(&sg) = len;
134
135         direction = ux500_channel->is_tx ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
136         addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
137                                         DMA_SLAVE_BUSWIDTH_4_BYTES;
138
139         slave_conf.direction = direction;
140         slave_conf.src_addr = usb_fifo_addr;
141         slave_conf.src_addr_width = addr_width;
142         slave_conf.src_maxburst = 16;
143         slave_conf.dst_addr = usb_fifo_addr;
144         slave_conf.dst_addr_width = addr_width;
145         slave_conf.dst_maxburst = 16;
146
147         dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG,
148                                              (unsigned long) &slave_conf);
149
150         dma_desc = dma_chan->device->
151                         device_prep_slave_sg(dma_chan, &sg, 1, direction,
152                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
153         if (!dma_desc)
154                 return false;
155
156         dma_desc->callback = ux500_dma_callback;
157         dma_desc->callback_param = channel;
158         ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
159
160         dma_async_issue_pending(dma_chan);
161
162         return true;
163 }
164
165 static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
166                                 struct musb_hw_ep *hw_ep, u8 is_tx)
167 {
168         struct ux500_dma_controller *controller = container_of(c,
169                         struct ux500_dma_controller, controller);
170         struct ux500_dma_channel *ux500_channel = NULL;
171         struct musb *musb = controller->private_data;
172         u8 ch_num = hw_ep->epnum - 1;
173         u32 max_ch;
174
175         /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
176          * to specified hw_ep. For example DMA channel 0 can only be allocated
177          * to hw_ep 1 and 9.
178          */
179         if (ch_num > 7)
180                 ch_num -= 8;
181
182         max_ch = is_tx ? controller->num_tx_channels :
183                         controller->num_rx_channels;
184
185         if (ch_num >= max_ch)
186                 return NULL;
187
188         ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
189                                 &(controller->rx_channel[ch_num]) ;
190
191         /* Check if channel is already used. */
192         if (ux500_channel->is_allocated)
193                 return NULL;
194
195         ux500_channel->hw_ep = hw_ep;
196         ux500_channel->is_allocated = 1;
197
198         dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
199                 hw_ep->epnum, is_tx, ch_num);
200
201         return &(ux500_channel->channel);
202 }
203
204 static void ux500_dma_channel_release(struct dma_channel *channel)
205 {
206         struct ux500_dma_channel *ux500_channel = channel->private_data;
207         struct musb *musb = ux500_channel->controller->private_data;
208
209         dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
210
211         if (ux500_channel->is_allocated) {
212                 ux500_channel->is_allocated = 0;
213                 channel->status = MUSB_DMA_STATUS_FREE;
214                 channel->actual_len = 0;
215         }
216 }
217
218 static int ux500_dma_is_compatible(struct dma_channel *channel,
219                 u16 maxpacket, void *buf, u32 length)
220 {
221         if ((maxpacket & 0x3)           ||
222                 ((int)buf & 0x3)        ||
223                 (length < 512)          ||
224                 (length & 0x3))
225                 return false;
226         else
227                 return true;
228 }
229
230 static int ux500_dma_channel_program(struct dma_channel *channel,
231                                 u16 packet_sz, u8 mode,
232                                 dma_addr_t dma_addr, u32 len)
233 {
234         int ret;
235
236         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
237                 channel->status == MUSB_DMA_STATUS_BUSY);
238
239         if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
240                 return false;
241
242         channel->status = MUSB_DMA_STATUS_BUSY;
243         channel->actual_len = 0;
244         ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
245         if (!ret)
246                 channel->status = MUSB_DMA_STATUS_FREE;
247
248         return ret;
249 }
250
251 static int ux500_dma_channel_abort(struct dma_channel *channel)
252 {
253         struct ux500_dma_channel *ux500_channel = channel->private_data;
254         struct ux500_dma_controller *controller = ux500_channel->controller;
255         struct musb *musb = controller->private_data;
256         void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
257         u16 csr;
258
259         dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
260                 ux500_channel->ch_num, ux500_channel->is_tx);
261
262         if (channel->status == MUSB_DMA_STATUS_BUSY) {
263                 if (ux500_channel->is_tx) {
264                         csr = musb_readw(epio, MUSB_TXCSR);
265                         csr &= ~(MUSB_TXCSR_AUTOSET |
266                                  MUSB_TXCSR_DMAENAB |
267                                  MUSB_TXCSR_DMAMODE);
268                         musb_writew(epio, MUSB_TXCSR, csr);
269                 } else {
270                         csr = musb_readw(epio, MUSB_RXCSR);
271                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
272                                  MUSB_RXCSR_DMAENAB |
273                                  MUSB_RXCSR_DMAMODE);
274                         musb_writew(epio, MUSB_RXCSR, csr);
275                 }
276
277                 ux500_channel->dma_chan->device->
278                                 device_control(ux500_channel->dma_chan,
279                                         DMA_TERMINATE_ALL, 0);
280                 channel->status = MUSB_DMA_STATUS_FREE;
281         }
282         return 0;
283 }
284
285 static int ux500_dma_controller_stop(struct dma_controller *c)
286 {
287         struct ux500_dma_controller *controller = container_of(c,
288                         struct ux500_dma_controller, controller);
289         struct ux500_dma_channel *ux500_channel;
290         struct dma_channel *channel;
291         u8 ch_num;
292
293         for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
294                 channel = &controller->rx_channel[ch_num].channel;
295                 ux500_channel = channel->private_data;
296
297                 ux500_dma_channel_release(channel);
298
299                 if (ux500_channel->dma_chan)
300                         dma_release_channel(ux500_channel->dma_chan);
301         }
302
303         for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
304                 channel = &controller->tx_channel[ch_num].channel;
305                 ux500_channel = channel->private_data;
306
307                 ux500_dma_channel_release(channel);
308
309                 if (ux500_channel->dma_chan)
310                         dma_release_channel(ux500_channel->dma_chan);
311         }
312
313         return 0;
314 }
315
316 static int ux500_dma_controller_start(struct dma_controller *c)
317 {
318         struct ux500_dma_controller *controller = container_of(c,
319                         struct ux500_dma_controller, controller);
320         struct ux500_dma_channel *ux500_channel = NULL;
321         struct musb *musb = controller->private_data;
322         struct device *dev = musb->controller;
323         struct musb_hdrc_platform_data *plat = dev->platform_data;
324         struct ux500_musb_board_data *data = plat->board_data;
325         struct dma_channel *dma_channel = NULL;
326         u32 ch_num;
327         u8 dir;
328         u8 is_tx = 0;
329
330         void **param_array;
331         struct ux500_dma_channel *channel_array;
332         u32 ch_count;
333         void (*musb_channel_work)(struct work_struct *);
334         dma_cap_mask_t mask;
335
336         if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
337                 (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
338                 return -EINVAL;
339
340         controller->num_rx_channels = data->num_rx_channels;
341         controller->num_tx_channels = data->num_tx_channels;
342
343         dma_cap_zero(mask);
344         dma_cap_set(DMA_SLAVE, mask);
345
346         /* Prepare the loop for RX channels */
347         channel_array = controller->rx_channel;
348         ch_count = data->num_rx_channels;
349         param_array = data->dma_rx_param_array;
350         musb_channel_work = ux500_rx_work;
351
352         for (dir = 0; dir < 2; dir++) {
353                 for (ch_num = 0; ch_num < ch_count; ch_num++) {
354                         ux500_channel = &channel_array[ch_num];
355                         ux500_channel->controller = controller;
356                         ux500_channel->ch_num = ch_num;
357                         ux500_channel->is_tx = is_tx;
358
359                         dma_channel = &(ux500_channel->channel);
360                         dma_channel->private_data = ux500_channel;
361                         dma_channel->status = MUSB_DMA_STATUS_FREE;
362                         dma_channel->max_len = SZ_16M;
363
364                         ux500_channel->dma_chan = dma_request_channel(mask,
365                                                         data->dma_filter,
366                                                         param_array[ch_num]);
367                         if (!ux500_channel->dma_chan) {
368                                 ERR("Dma pipe allocation error dir=%d ch=%d\n",
369                                         dir, ch_num);
370
371                                 /* Release already allocated channels */
372                                 ux500_dma_controller_stop(c);
373
374                                 return -EBUSY;
375                         }
376
377                         INIT_WORK(&ux500_channel->channel_work,
378                                 musb_channel_work);
379                 }
380
381                 /* Prepare the loop for TX channels */
382                 channel_array = controller->tx_channel;
383                 ch_count = data->num_tx_channels;
384                 param_array = data->dma_tx_param_array;
385                 musb_channel_work = ux500_tx_work;
386                 is_tx = 1;
387         }
388
389         return 0;
390 }
391
392 void dma_controller_destroy(struct dma_controller *c)
393 {
394         struct ux500_dma_controller *controller = container_of(c,
395                         struct ux500_dma_controller, controller);
396
397         kfree(controller);
398 }
399
400 struct dma_controller *__init
401 dma_controller_create(struct musb *musb, void __iomem *base)
402 {
403         struct ux500_dma_controller *controller;
404         struct platform_device *pdev = to_platform_device(musb->controller);
405         struct resource *iomem;
406
407         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
408         if (!controller)
409                 return NULL;
410
411         controller->private_data = musb;
412
413         /* Save physical address for DMA controller. */
414         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
415         controller->phy_base = (dma_addr_t) iomem->start;
416
417         controller->controller.start = ux500_dma_controller_start;
418         controller->controller.stop = ux500_dma_controller_stop;
419         controller->controller.channel_alloc = ux500_dma_channel_allocate;
420         controller->controller.channel_release = ux500_dma_channel_release;
421         controller->controller.channel_program = ux500_dma_channel_program;
422         controller->controller.channel_abort = ux500_dma_channel_abort;
423         controller->controller.is_compatible = ux500_dma_is_compatible;
424
425         return &controller->controller;
426 }