b42a6fb45b22e27b7179dba895e78f4b8abc032d
[linux-2.6.git] / drivers / usb / host / xhci-mem.c
1 /*
2  * xHCI host controller driver
3  *
4  * Copyright (C) 2008 Intel Corp.
5  *
6  * Author: Sarah Sharp
7  * Some code borrowed from the Linux EHCI driver.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16  * for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software Foundation,
20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
27
28 #include "xhci.h"
29
30 /*
31  * Allocates a generic ring segment from the ring pool, sets the dma address,
32  * initializes the segment to zero, and sets the private next pointer to NULL.
33  *
34  * Section 4.11.1.1:
35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
36  */
37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
38                                         unsigned int cycle_state, gfp_t flags)
39 {
40         struct xhci_segment *seg;
41         dma_addr_t      dma;
42         int             i;
43
44         seg = kzalloc(sizeof *seg, flags);
45         if (!seg)
46                 return NULL;
47
48         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
49         if (!seg->trbs) {
50                 kfree(seg);
51                 return NULL;
52         }
53
54         memset(seg->trbs, 0, SEGMENT_SIZE);
55         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56         if (cycle_state == 0) {
57                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
58                         seg->trbs[i].link.control |= TRB_CYCLE;
59         }
60         seg->dma = dma;
61         seg->next = NULL;
62
63         return seg;
64 }
65
66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
67 {
68         if (seg->trbs) {
69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
70                 seg->trbs = NULL;
71         }
72         kfree(seg);
73 }
74
75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
76                                 struct xhci_segment *first)
77 {
78         struct xhci_segment *seg;
79
80         seg = first->next;
81         while (seg != first) {
82                 struct xhci_segment *next = seg->next;
83                 xhci_segment_free(xhci, seg);
84                 seg = next;
85         }
86         xhci_segment_free(xhci, first);
87 }
88
89 /*
90  * Make the prev segment point to the next segment.
91  *
92  * Change the last TRB in the prev segment to be a Link TRB which points to the
93  * DMA address of the next segment.  The caller needs to set any Link TRB
94  * related flags, such as End TRB, Toggle Cycle, and no snoop.
95  */
96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
97                 struct xhci_segment *next, enum xhci_ring_type type)
98 {
99         u32 val;
100
101         if (!prev || !next)
102                 return;
103         prev->next = next;
104         if (type != TYPE_EVENT) {
105                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
106                         cpu_to_le64(next->dma);
107
108                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
109                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
110                 val &= ~TRB_TYPE_BITMASK;
111                 val |= TRB_TYPE(TRB_LINK);
112                 /* Always set the chain bit with 0.95 hardware */
113                 /* Set chain bit for isoc rings on AMD 0.96 host */
114                 if (xhci_link_trb_quirk(xhci) ||
115                                 (type == TYPE_ISOC &&
116                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
117                         val |= TRB_CHAIN;
118                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
119         }
120 }
121
122 /*
123  * Link the ring to the new segments.
124  * Set Toggle Cycle for the new ring if needed.
125  */
126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
127                 struct xhci_segment *first, struct xhci_segment *last,
128                 unsigned int num_segs)
129 {
130         struct xhci_segment *next;
131
132         if (!ring || !first || !last)
133                 return;
134
135         next = ring->enq_seg->next;
136         xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
137         xhci_link_segments(xhci, last, next, ring->type);
138         ring->num_segs += num_segs;
139         ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
140
141         if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
142                 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
143                         &= ~cpu_to_le32(LINK_TOGGLE);
144                 last->trbs[TRBS_PER_SEGMENT-1].link.control
145                         |= cpu_to_le32(LINK_TOGGLE);
146                 ring->last_seg = last;
147         }
148 }
149
150 /* XXX: Do we need the hcd structure in all these functions? */
151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
152 {
153         if (!ring)
154                 return;
155
156         if (ring->first_seg)
157                 xhci_free_segments_for_ring(xhci, ring->first_seg);
158
159         kfree(ring);
160 }
161
162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
163                                         unsigned int cycle_state)
164 {
165         /* The ring is empty, so the enqueue pointer == dequeue pointer */
166         ring->enqueue = ring->first_seg->trbs;
167         ring->enq_seg = ring->first_seg;
168         ring->dequeue = ring->enqueue;
169         ring->deq_seg = ring->first_seg;
170         /* The ring is initialized to 0. The producer must write 1 to the cycle
171          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
172          * compare CCS to the cycle bit to check ownership, so CCS = 1.
173          *
174          * New rings are initialized with cycle state equal to 1; if we are
175          * handling ring expansion, set the cycle state equal to the old ring.
176          */
177         ring->cycle_state = cycle_state;
178         /* Not necessary for new rings, but needed for re-initialized rings */
179         ring->enq_updates = 0;
180         ring->deq_updates = 0;
181
182         /*
183          * Each segment has a link TRB, and leave an extra TRB for SW
184          * accounting purpose
185          */
186         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
187 }
188
189 /* Allocate segments and link them for a ring */
190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
191                 struct xhci_segment **first, struct xhci_segment **last,
192                 unsigned int num_segs, unsigned int cycle_state,
193                 enum xhci_ring_type type, gfp_t flags)
194 {
195         struct xhci_segment *prev;
196
197         prev = xhci_segment_alloc(xhci, cycle_state, flags);
198         if (!prev)
199                 return -ENOMEM;
200         num_segs--;
201
202         *first = prev;
203         while (num_segs > 0) {
204                 struct xhci_segment     *next;
205
206                 next = xhci_segment_alloc(xhci, cycle_state, flags);
207                 if (!next) {
208                         prev = *first;
209                         while (prev) {
210                                 next = prev->next;
211                                 xhci_segment_free(xhci, prev);
212                                 prev = next;
213                         }
214                         return -ENOMEM;
215                 }
216                 xhci_link_segments(xhci, prev, next, type);
217
218                 prev = next;
219                 num_segs--;
220         }
221         xhci_link_segments(xhci, prev, *first, type);
222         *last = prev;
223
224         return 0;
225 }
226
227 /**
228  * Create a new ring with zero or more segments.
229  *
230  * Link each segment together into a ring.
231  * Set the end flag and the cycle toggle bit on the last segment.
232  * See section 4.9.1 and figures 15 and 16.
233  */
234 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
235                 unsigned int num_segs, unsigned int cycle_state,
236                 enum xhci_ring_type type, gfp_t flags)
237 {
238         struct xhci_ring        *ring;
239         int ret;
240
241         ring = kzalloc(sizeof *(ring), flags);
242         if (!ring)
243                 return NULL;
244
245         ring->num_segs = num_segs;
246         INIT_LIST_HEAD(&ring->td_list);
247         ring->type = type;
248         if (num_segs == 0)
249                 return ring;
250
251         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
252                         &ring->last_seg, num_segs, cycle_state, type, flags);
253         if (ret)
254                 goto fail;
255
256         /* Only event ring does not use link TRB */
257         if (type != TYPE_EVENT) {
258                 /* See section 4.9.2.1 and 6.4.4.1 */
259                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
260                         cpu_to_le32(LINK_TOGGLE);
261         }
262         xhci_initialize_ring_info(ring, cycle_state);
263         return ring;
264
265 fail:
266         kfree(ring);
267         return NULL;
268 }
269
270 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
271                 struct xhci_virt_device *virt_dev,
272                 unsigned int ep_index)
273 {
274         int rings_cached;
275
276         rings_cached = virt_dev->num_rings_cached;
277         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
278                 virt_dev->ring_cache[rings_cached] =
279                         virt_dev->eps[ep_index].ring;
280                 virt_dev->num_rings_cached++;
281                 xhci_dbg(xhci, "Cached old ring, "
282                                 "%d ring%s cached\n",
283                                 virt_dev->num_rings_cached,
284                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
285         } else {
286                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
287                 xhci_dbg(xhci, "Ring cache full (%d rings), "
288                                 "freeing ring\n",
289                                 virt_dev->num_rings_cached);
290         }
291         virt_dev->eps[ep_index].ring = NULL;
292 }
293
294 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
295  * pointers to the beginning of the ring.
296  */
297 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
298                         struct xhci_ring *ring, unsigned int cycle_state,
299                         enum xhci_ring_type type)
300 {
301         struct xhci_segment     *seg = ring->first_seg;
302         int i;
303
304         do {
305                 memset(seg->trbs, 0,
306                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
307                 if (cycle_state == 0) {
308                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
309                                 seg->trbs[i].link.control |= TRB_CYCLE;
310                 }
311                 /* All endpoint rings have link TRBs */
312                 xhci_link_segments(xhci, seg, seg->next, type);
313                 seg = seg->next;
314         } while (seg != ring->first_seg);
315         ring->type = type;
316         xhci_initialize_ring_info(ring, cycle_state);
317         /* td list should be empty since all URBs have been cancelled,
318          * but just in case...
319          */
320         INIT_LIST_HEAD(&ring->td_list);
321 }
322
323 /*
324  * Expand an existing ring.
325  * Look for a cached ring or allocate a new ring which has same segment numbers
326  * and link the two rings.
327  */
328 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
329                                 unsigned int num_trbs, gfp_t flags)
330 {
331         struct xhci_segment     *first;
332         struct xhci_segment     *last;
333         unsigned int            num_segs;
334         unsigned int            num_segs_needed;
335         int                     ret;
336
337         num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
338                                 (TRBS_PER_SEGMENT - 1);
339
340         /* Allocate number of segments we needed, or double the ring size */
341         num_segs = ring->num_segs > num_segs_needed ?
342                         ring->num_segs : num_segs_needed;
343
344         ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
345                         num_segs, ring->cycle_state, ring->type, flags);
346         if (ret)
347                 return -ENOMEM;
348
349         xhci_link_rings(xhci, ring, first, last, num_segs);
350         xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
351                         ring->num_segs);
352
353         return 0;
354 }
355
356 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
357
358 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
359                                                     int type, gfp_t flags)
360 {
361         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
362         if (!ctx)
363                 return NULL;
364
365         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
366         ctx->type = type;
367         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
368         if (type == XHCI_CTX_TYPE_INPUT)
369                 ctx->size += CTX_SIZE(xhci->hcc_params);
370
371         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
372         memset(ctx->bytes, 0, ctx->size);
373         return ctx;
374 }
375
376 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
377                              struct xhci_container_ctx *ctx)
378 {
379         if (!ctx)
380                 return;
381         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
382         kfree(ctx);
383 }
384
385 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
386                                               struct xhci_container_ctx *ctx)
387 {
388         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
389         return (struct xhci_input_control_ctx *)ctx->bytes;
390 }
391
392 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
393                                         struct xhci_container_ctx *ctx)
394 {
395         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
396                 return (struct xhci_slot_ctx *)ctx->bytes;
397
398         return (struct xhci_slot_ctx *)
399                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
400 }
401
402 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
403                                     struct xhci_container_ctx *ctx,
404                                     unsigned int ep_index)
405 {
406         /* increment ep index by offset of start of ep ctx array */
407         ep_index++;
408         if (ctx->type == XHCI_CTX_TYPE_INPUT)
409                 ep_index++;
410
411         return (struct xhci_ep_ctx *)
412                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
413 }
414
415
416 /***************** Streams structures manipulation *************************/
417
418 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
419                 unsigned int num_stream_ctxs,
420                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
421 {
422         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
423
424         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
425                 dma_free_coherent(&pdev->dev,
426                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
427                                 stream_ctx, dma);
428         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
429                 return dma_pool_free(xhci->small_streams_pool,
430                                 stream_ctx, dma);
431         else
432                 return dma_pool_free(xhci->medium_streams_pool,
433                                 stream_ctx, dma);
434 }
435
436 /*
437  * The stream context array for each endpoint with bulk streams enabled can
438  * vary in size, based on:
439  *  - how many streams the endpoint supports,
440  *  - the maximum primary stream array size the host controller supports,
441  *  - and how many streams the device driver asks for.
442  *
443  * The stream context array must be a power of 2, and can be as small as
444  * 64 bytes or as large as 1MB.
445  */
446 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
447                 unsigned int num_stream_ctxs, dma_addr_t *dma,
448                 gfp_t mem_flags)
449 {
450         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
451
452         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
453                 return dma_alloc_coherent(&pdev->dev,
454                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
455                                 dma, mem_flags);
456         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
457                 return dma_pool_alloc(xhci->small_streams_pool,
458                                 mem_flags, dma);
459         else
460                 return dma_pool_alloc(xhci->medium_streams_pool,
461                                 mem_flags, dma);
462 }
463
464 struct xhci_ring *xhci_dma_to_transfer_ring(
465                 struct xhci_virt_ep *ep,
466                 u64 address)
467 {
468         if (ep->ep_state & EP_HAS_STREAMS)
469                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
470                                 address >> SEGMENT_SHIFT);
471         return ep->ring;
472 }
473
474 /* Only use this when you know stream_info is valid */
475 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
476 static struct xhci_ring *dma_to_stream_ring(
477                 struct xhci_stream_info *stream_info,
478                 u64 address)
479 {
480         return radix_tree_lookup(&stream_info->trb_address_map,
481                         address >> SEGMENT_SHIFT);
482 }
483 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
484
485 struct xhci_ring *xhci_stream_id_to_ring(
486                 struct xhci_virt_device *dev,
487                 unsigned int ep_index,
488                 unsigned int stream_id)
489 {
490         struct xhci_virt_ep *ep = &dev->eps[ep_index];
491
492         if (stream_id == 0)
493                 return ep->ring;
494         if (!ep->stream_info)
495                 return NULL;
496
497         if (stream_id > ep->stream_info->num_streams)
498                 return NULL;
499         return ep->stream_info->stream_rings[stream_id];
500 }
501
502 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
503 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
504                 unsigned int num_streams,
505                 struct xhci_stream_info *stream_info)
506 {
507         u32 cur_stream;
508         struct xhci_ring *cur_ring;
509         u64 addr;
510
511         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
512                 struct xhci_ring *mapped_ring;
513                 int trb_size = sizeof(union xhci_trb);
514
515                 cur_ring = stream_info->stream_rings[cur_stream];
516                 for (addr = cur_ring->first_seg->dma;
517                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
518                                 addr += trb_size) {
519                         mapped_ring = dma_to_stream_ring(stream_info, addr);
520                         if (cur_ring != mapped_ring) {
521                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
522                                                 "didn't map to stream ID %u; "
523                                                 "mapped to ring %p\n",
524                                                 (unsigned long long) addr,
525                                                 cur_stream,
526                                                 mapped_ring);
527                                 return -EINVAL;
528                         }
529                 }
530                 /* One TRB after the end of the ring segment shouldn't return a
531                  * pointer to the current ring (although it may be a part of a
532                  * different ring).
533                  */
534                 mapped_ring = dma_to_stream_ring(stream_info, addr);
535                 if (mapped_ring != cur_ring) {
536                         /* One TRB before should also fail */
537                         addr = cur_ring->first_seg->dma - trb_size;
538                         mapped_ring = dma_to_stream_ring(stream_info, addr);
539                 }
540                 if (mapped_ring == cur_ring) {
541                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
542                                         "mapped to valid stream ID %u; "
543                                         "mapped ring = %p\n",
544                                         (unsigned long long) addr,
545                                         cur_stream,
546                                         mapped_ring);
547                         return -EINVAL;
548                 }
549         }
550         return 0;
551 }
552 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
553
554 /*
555  * Change an endpoint's internal structure so it supports stream IDs.  The
556  * number of requested streams includes stream 0, which cannot be used by device
557  * drivers.
558  *
559  * The number of stream contexts in the stream context array may be bigger than
560  * the number of streams the driver wants to use.  This is because the number of
561  * stream context array entries must be a power of two.
562  *
563  * We need a radix tree for mapping physical addresses of TRBs to which stream
564  * ID they belong to.  We need to do this because the host controller won't tell
565  * us which stream ring the TRB came from.  We could store the stream ID in an
566  * event data TRB, but that doesn't help us for the cancellation case, since the
567  * endpoint may stop before it reaches that event data TRB.
568  *
569  * The radix tree maps the upper portion of the TRB DMA address to a ring
570  * segment that has the same upper portion of DMA addresses.  For example, say I
571  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
572  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
573  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
574  * pass the radix tree a key to get the right stream ID:
575  *
576  *      0x10c90fff >> 10 = 0x43243
577  *      0x10c912c0 >> 10 = 0x43244
578  *      0x10c91400 >> 10 = 0x43245
579  *
580  * Obviously, only those TRBs with DMA addresses that are within the segment
581  * will make the radix tree return the stream ID for that ring.
582  *
583  * Caveats for the radix tree:
584  *
585  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
586  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
587  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
588  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
589  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
590  * extended systems (where the DMA address can be bigger than 32-bits),
591  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
592  */
593 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
594                 unsigned int num_stream_ctxs,
595                 unsigned int num_streams, gfp_t mem_flags)
596 {
597         struct xhci_stream_info *stream_info;
598         u32 cur_stream;
599         struct xhci_ring *cur_ring;
600         unsigned long key;
601         u64 addr;
602         int ret;
603
604         xhci_dbg(xhci, "Allocating %u streams and %u "
605                         "stream context array entries.\n",
606                         num_streams, num_stream_ctxs);
607         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
608                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
609                 return NULL;
610         }
611         xhci->cmd_ring_reserved_trbs++;
612
613         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
614         if (!stream_info)
615                 goto cleanup_trbs;
616
617         stream_info->num_streams = num_streams;
618         stream_info->num_stream_ctxs = num_stream_ctxs;
619
620         /* Initialize the array of virtual pointers to stream rings. */
621         stream_info->stream_rings = kzalloc(
622                         sizeof(struct xhci_ring *)*num_streams,
623                         mem_flags);
624         if (!stream_info->stream_rings)
625                 goto cleanup_info;
626
627         /* Initialize the array of DMA addresses for stream rings for the HW. */
628         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
629                         num_stream_ctxs, &stream_info->ctx_array_dma,
630                         mem_flags);
631         if (!stream_info->stream_ctx_array)
632                 goto cleanup_ctx;
633         memset(stream_info->stream_ctx_array, 0,
634                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
635
636         /* Allocate everything needed to free the stream rings later */
637         stream_info->free_streams_command =
638                 xhci_alloc_command(xhci, true, true, mem_flags);
639         if (!stream_info->free_streams_command)
640                 goto cleanup_ctx;
641
642         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
643
644         /* Allocate rings for all the streams that the driver will use,
645          * and add their segment DMA addresses to the radix tree.
646          * Stream 0 is reserved.
647          */
648         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
649                 stream_info->stream_rings[cur_stream] =
650                         xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
651                 cur_ring = stream_info->stream_rings[cur_stream];
652                 if (!cur_ring)
653                         goto cleanup_rings;
654                 cur_ring->stream_id = cur_stream;
655                 /* Set deq ptr, cycle bit, and stream context type */
656                 addr = cur_ring->first_seg->dma |
657                         SCT_FOR_CTX(SCT_PRI_TR) |
658                         cur_ring->cycle_state;
659                 stream_info->stream_ctx_array[cur_stream].stream_ring =
660                         cpu_to_le64(addr);
661                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
662                                 cur_stream, (unsigned long long) addr);
663
664                 key = (unsigned long)
665                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
666                 ret = radix_tree_insert(&stream_info->trb_address_map,
667                                 key, cur_ring);
668                 if (ret) {
669                         xhci_ring_free(xhci, cur_ring);
670                         stream_info->stream_rings[cur_stream] = NULL;
671                         goto cleanup_rings;
672                 }
673         }
674         /* Leave the other unused stream ring pointers in the stream context
675          * array initialized to zero.  This will cause the xHC to give us an
676          * error if the device asks for a stream ID we don't have setup (if it
677          * was any other way, the host controller would assume the ring is
678          * "empty" and wait forever for data to be queued to that stream ID).
679          */
680 #if XHCI_DEBUG
681         /* Do a little test on the radix tree to make sure it returns the
682          * correct values.
683          */
684         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
685                 goto cleanup_rings;
686 #endif
687
688         return stream_info;
689
690 cleanup_rings:
691         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
692                 cur_ring = stream_info->stream_rings[cur_stream];
693                 if (cur_ring) {
694                         addr = cur_ring->first_seg->dma;
695                         radix_tree_delete(&stream_info->trb_address_map,
696                                         addr >> SEGMENT_SHIFT);
697                         xhci_ring_free(xhci, cur_ring);
698                         stream_info->stream_rings[cur_stream] = NULL;
699                 }
700         }
701         xhci_free_command(xhci, stream_info->free_streams_command);
702 cleanup_ctx:
703         kfree(stream_info->stream_rings);
704 cleanup_info:
705         kfree(stream_info);
706 cleanup_trbs:
707         xhci->cmd_ring_reserved_trbs--;
708         return NULL;
709 }
710 /*
711  * Sets the MaxPStreams field and the Linear Stream Array field.
712  * Sets the dequeue pointer to the stream context array.
713  */
714 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
715                 struct xhci_ep_ctx *ep_ctx,
716                 struct xhci_stream_info *stream_info)
717 {
718         u32 max_primary_streams;
719         /* MaxPStreams is the number of stream context array entries, not the
720          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
721          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
722          */
723         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
724         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
725                         1 << (max_primary_streams + 1));
726         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
727         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
728                                        | EP_HAS_LSA);
729         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
730 }
731
732 /*
733  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
734  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
735  * not at the beginning of the ring).
736  */
737 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
738                 struct xhci_ep_ctx *ep_ctx,
739                 struct xhci_virt_ep *ep)
740 {
741         dma_addr_t addr;
742         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
743         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
744         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
745 }
746
747 /* Frees all stream contexts associated with the endpoint,
748  *
749  * Caller should fix the endpoint context streams fields.
750  */
751 void xhci_free_stream_info(struct xhci_hcd *xhci,
752                 struct xhci_stream_info *stream_info)
753 {
754         int cur_stream;
755         struct xhci_ring *cur_ring;
756         dma_addr_t addr;
757
758         if (!stream_info)
759                 return;
760
761         for (cur_stream = 1; cur_stream < stream_info->num_streams;
762                         cur_stream++) {
763                 cur_ring = stream_info->stream_rings[cur_stream];
764                 if (cur_ring) {
765                         addr = cur_ring->first_seg->dma;
766                         radix_tree_delete(&stream_info->trb_address_map,
767                                         addr >> SEGMENT_SHIFT);
768                         xhci_ring_free(xhci, cur_ring);
769                         stream_info->stream_rings[cur_stream] = NULL;
770                 }
771         }
772         xhci_free_command(xhci, stream_info->free_streams_command);
773         xhci->cmd_ring_reserved_trbs--;
774         if (stream_info->stream_ctx_array)
775                 xhci_free_stream_ctx(xhci,
776                                 stream_info->num_stream_ctxs,
777                                 stream_info->stream_ctx_array,
778                                 stream_info->ctx_array_dma);
779
780         if (stream_info)
781                 kfree(stream_info->stream_rings);
782         kfree(stream_info);
783 }
784
785
786 /***************** Device context manipulation *************************/
787
788 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
789                 struct xhci_virt_ep *ep)
790 {
791         init_timer(&ep->stop_cmd_timer);
792         ep->stop_cmd_timer.data = (unsigned long) ep;
793         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
794         ep->xhci = xhci;
795 }
796
797 static void xhci_free_tt_info(struct xhci_hcd *xhci,
798                 struct xhci_virt_device *virt_dev,
799                 int slot_id)
800 {
801         struct list_head *tt_list_head;
802         struct xhci_tt_bw_info *tt_info, *next;
803         bool slot_found = false;
804
805         /* If the device never made it past the Set Address stage,
806          * it may not have the real_port set correctly.
807          */
808         if (virt_dev->real_port == 0 ||
809                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
810                 xhci_dbg(xhci, "Bad real port.\n");
811                 return;
812         }
813
814         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
815         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
816                 /* Multi-TT hubs will have more than one entry */
817                 if (tt_info->slot_id == slot_id) {
818                         slot_found = true;
819                         list_del(&tt_info->tt_list);
820                         kfree(tt_info);
821                 } else if (slot_found) {
822                         break;
823                 }
824         }
825 }
826
827 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
828                 struct xhci_virt_device *virt_dev,
829                 struct usb_device *hdev,
830                 struct usb_tt *tt, gfp_t mem_flags)
831 {
832         struct xhci_tt_bw_info          *tt_info;
833         unsigned int                    num_ports;
834         int                             i, j;
835
836         if (!tt->multi)
837                 num_ports = 1;
838         else
839                 num_ports = hdev->maxchild;
840
841         for (i = 0; i < num_ports; i++, tt_info++) {
842                 struct xhci_interval_bw_table *bw_table;
843
844                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
845                 if (!tt_info)
846                         goto free_tts;
847                 INIT_LIST_HEAD(&tt_info->tt_list);
848                 list_add(&tt_info->tt_list,
849                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
850                 tt_info->slot_id = virt_dev->udev->slot_id;
851                 if (tt->multi)
852                         tt_info->ttport = i+1;
853                 bw_table = &tt_info->bw_table;
854                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
855                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
856         }
857         return 0;
858
859 free_tts:
860         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
861         return -ENOMEM;
862 }
863
864
865 /* All the xhci_tds in the ring's TD list should be freed at this point.
866  * Should be called with xhci->lock held if there is any chance the TT lists
867  * will be manipulated by the configure endpoint, allocate device, or update
868  * hub functions while this function is removing the TT entries from the list.
869  */
870 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
871 {
872         struct xhci_virt_device *dev;
873         int i;
874         int old_active_eps = 0;
875
876         /* Slot ID 0 is reserved */
877         if (slot_id == 0 || !xhci->devs[slot_id])
878                 return;
879
880         dev = xhci->devs[slot_id];
881         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
882         if (!dev)
883                 return;
884
885         if (dev->tt_info)
886                 old_active_eps = dev->tt_info->active_eps;
887
888         for (i = 0; i < 31; ++i) {
889                 if (dev->eps[i].ring)
890                         xhci_ring_free(xhci, dev->eps[i].ring);
891                 if (dev->eps[i].stream_info)
892                         xhci_free_stream_info(xhci,
893                                         dev->eps[i].stream_info);
894                 /* Endpoints on the TT/root port lists should have been removed
895                  * when usb_disable_device() was called for the device.
896                  * We can't drop them anyway, because the udev might have gone
897                  * away by this point, and we can't tell what speed it was.
898                  */
899                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
900                         xhci_warn(xhci, "Slot %u endpoint %u "
901                                         "not removed from BW list!\n",
902                                         slot_id, i);
903         }
904         /* If this is a hub, free the TT(s) from the TT list */
905         xhci_free_tt_info(xhci, dev, slot_id);
906         /* If necessary, update the number of active TTs on this root port */
907         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
908
909         if (dev->ring_cache) {
910                 for (i = 0; i < dev->num_rings_cached; i++)
911                         xhci_ring_free(xhci, dev->ring_cache[i]);
912                 kfree(dev->ring_cache);
913         }
914
915         if (dev->in_ctx)
916                 xhci_free_container_ctx(xhci, dev->in_ctx);
917         if (dev->out_ctx)
918                 xhci_free_container_ctx(xhci, dev->out_ctx);
919
920         kfree(xhci->devs[slot_id]);
921         xhci->devs[slot_id] = NULL;
922 }
923
924 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
925                 struct usb_device *udev, gfp_t flags)
926 {
927         struct xhci_virt_device *dev;
928         int i;
929
930         /* Slot ID 0 is reserved */
931         if (slot_id == 0 || xhci->devs[slot_id]) {
932                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
933                 return 0;
934         }
935
936         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
937         if (!xhci->devs[slot_id])
938                 return 0;
939         dev = xhci->devs[slot_id];
940
941         /* Allocate the (output) device context that will be used in the HC. */
942         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
943         if (!dev->out_ctx)
944                 goto fail;
945
946         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
947                         (unsigned long long)dev->out_ctx->dma);
948
949         /* Allocate the (input) device context for address device command */
950         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
951         if (!dev->in_ctx)
952                 goto fail;
953
954         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
955                         (unsigned long long)dev->in_ctx->dma);
956
957         /* Initialize the cancellation list and watchdog timers for each ep */
958         for (i = 0; i < 31; i++) {
959                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
960                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
961                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
962         }
963
964         /* Allocate endpoint 0 ring */
965         dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
966         if (!dev->eps[0].ring)
967                 goto fail;
968
969         /* Allocate pointers to the ring cache */
970         dev->ring_cache = kzalloc(
971                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
972                         flags);
973         if (!dev->ring_cache)
974                 goto fail;
975         dev->num_rings_cached = 0;
976
977         init_completion(&dev->cmd_completion);
978         INIT_LIST_HEAD(&dev->cmd_list);
979         dev->udev = udev;
980
981         /* Point to output device context in dcbaa. */
982         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
983         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
984                  slot_id,
985                  &xhci->dcbaa->dev_context_ptrs[slot_id],
986                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
987
988         return 1;
989 fail:
990         xhci_free_virt_device(xhci, slot_id);
991         return 0;
992 }
993
994 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
995                 struct usb_device *udev)
996 {
997         struct xhci_virt_device *virt_dev;
998         struct xhci_ep_ctx      *ep0_ctx;
999         struct xhci_ring        *ep_ring;
1000
1001         virt_dev = xhci->devs[udev->slot_id];
1002         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1003         ep_ring = virt_dev->eps[0].ring;
1004         /*
1005          * FIXME we don't keep track of the dequeue pointer very well after a
1006          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1007          * host to our enqueue pointer.  This should only be called after a
1008          * configured device has reset, so all control transfers should have
1009          * been completed or cancelled before the reset.
1010          */
1011         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1012                                                         ep_ring->enqueue)
1013                                    | ep_ring->cycle_state);
1014 }
1015
1016 /*
1017  * The xHCI roothub may have ports of differing speeds in any order in the port
1018  * status registers.  xhci->port_array provides an array of the port speed for
1019  * each offset into the port status registers.
1020  *
1021  * The xHCI hardware wants to know the roothub port number that the USB device
1022  * is attached to (or the roothub port its ancestor hub is attached to).  All we
1023  * know is the index of that port under either the USB 2.0 or the USB 3.0
1024  * roothub, but that doesn't give us the real index into the HW port status
1025  * registers.  Scan through the xHCI roothub port array, looking for the Nth
1026  * entry of the correct port speed.  Return the port number of that entry.
1027  */
1028 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1029                 struct usb_device *udev)
1030 {
1031         struct usb_device *top_dev;
1032         unsigned int num_similar_speed_ports;
1033         unsigned int faked_port_num;
1034         int i;
1035
1036         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1037                         top_dev = top_dev->parent)
1038                 /* Found device below root hub */;
1039         faked_port_num = top_dev->portnum;
1040         for (i = 0, num_similar_speed_ports = 0;
1041                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
1042                 u8 port_speed = xhci->port_array[i];
1043
1044                 /*
1045                  * Skip ports that don't have known speeds, or have duplicate
1046                  * Extended Capabilities port speed entries.
1047                  */
1048                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1049                         continue;
1050
1051                 /*
1052                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1053                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1054                  * matches the device speed, it's a similar speed port.
1055                  */
1056                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
1057                         num_similar_speed_ports++;
1058                 if (num_similar_speed_ports == faked_port_num)
1059                         /* Roothub ports are numbered from 1 to N */
1060                         return i+1;
1061         }
1062         return 0;
1063 }
1064
1065 /* Setup an xHCI virtual device for a Set Address command */
1066 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1067 {
1068         struct xhci_virt_device *dev;
1069         struct xhci_ep_ctx      *ep0_ctx;
1070         struct xhci_slot_ctx    *slot_ctx;
1071         u32                     port_num;
1072         struct usb_device *top_dev;
1073
1074         dev = xhci->devs[udev->slot_id];
1075         /* Slot ID 0 is reserved */
1076         if (udev->slot_id == 0 || !dev) {
1077                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1078                                 udev->slot_id);
1079                 return -EINVAL;
1080         }
1081         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1082         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1083
1084         /* 3) Only the control endpoint is valid - one endpoint context */
1085         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1086         switch (udev->speed) {
1087         case USB_SPEED_SUPER:
1088                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1089                 break;
1090         case USB_SPEED_HIGH:
1091                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1092                 break;
1093         case USB_SPEED_FULL:
1094                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1095                 break;
1096         case USB_SPEED_LOW:
1097                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1098                 break;
1099         case USB_SPEED_WIRELESS:
1100                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1101                 return -EINVAL;
1102                 break;
1103         default:
1104                 /* Speed was set earlier, this shouldn't happen. */
1105                 BUG();
1106         }
1107         /* Find the root hub port this device is under */
1108         port_num = xhci_find_real_port_number(xhci, udev);
1109         if (!port_num)
1110                 return -EINVAL;
1111         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1112         /* Set the port number in the virtual_device to the faked port number */
1113         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1114                         top_dev = top_dev->parent)
1115                 /* Found device below root hub */;
1116         dev->fake_port = top_dev->portnum;
1117         dev->real_port = port_num;
1118         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1119         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1120
1121         /* Find the right bandwidth table that this device will be a part of.
1122          * If this is a full speed device attached directly to a root port (or a
1123          * decendent of one), it counts as a primary bandwidth domain, not a
1124          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1125          * will never be created for the HS root hub.
1126          */
1127         if (!udev->tt || !udev->tt->hub->parent) {
1128                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1129         } else {
1130                 struct xhci_root_port_bw_info *rh_bw;
1131                 struct xhci_tt_bw_info *tt_bw;
1132
1133                 rh_bw = &xhci->rh_bw[port_num - 1];
1134                 /* Find the right TT. */
1135                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1136                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1137                                 continue;
1138
1139                         if (!dev->udev->tt->multi ||
1140                                         (udev->tt->multi &&
1141                                          tt_bw->ttport == dev->udev->ttport)) {
1142                                 dev->bw_table = &tt_bw->bw_table;
1143                                 dev->tt_info = tt_bw;
1144                                 break;
1145                         }
1146                 }
1147                 if (!dev->tt_info)
1148                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1149         }
1150
1151         /* Is this a LS/FS device under an external HS hub? */
1152         if (udev->tt && udev->tt->hub->parent) {
1153                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1154                                                 (udev->ttport << 8));
1155                 if (udev->tt->multi)
1156                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1157         }
1158         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1159         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1160
1161         /* Step 4 - ring already allocated */
1162         /* Step 5 */
1163         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1164         /*
1165          * XXX: Not sure about wireless USB devices.
1166          */
1167         switch (udev->speed) {
1168         case USB_SPEED_SUPER:
1169                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1170                 break;
1171         case USB_SPEED_HIGH:
1172         /* USB core guesses at a 64-byte max packet first for FS devices */
1173         case USB_SPEED_FULL:
1174                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1175                 break;
1176         case USB_SPEED_LOW:
1177                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1178                 break;
1179         case USB_SPEED_WIRELESS:
1180                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1181                 return -EINVAL;
1182                 break;
1183         default:
1184                 /* New speed? */
1185                 BUG();
1186         }
1187         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1188         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1189
1190         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1191                                    dev->eps[0].ring->cycle_state);
1192
1193         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1194
1195         return 0;
1196 }
1197
1198 /*
1199  * Convert interval expressed as 2^(bInterval - 1) == interval into
1200  * straight exponent value 2^n == interval.
1201  *
1202  */
1203 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1204                 struct usb_host_endpoint *ep)
1205 {
1206         unsigned int interval;
1207
1208         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1209         if (interval != ep->desc.bInterval - 1)
1210                 dev_warn(&udev->dev,
1211                          "ep %#x - rounding interval to %d %sframes\n",
1212                          ep->desc.bEndpointAddress,
1213                          1 << interval,
1214                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1215
1216         if (udev->speed == USB_SPEED_FULL) {
1217                 /*
1218                  * Full speed isoc endpoints specify interval in frames,
1219                  * not microframes. We are using microframes everywhere,
1220                  * so adjust accordingly.
1221                  */
1222                 interval += 3;  /* 1 frame = 2^3 uframes */
1223         }
1224
1225         return interval;
1226 }
1227
1228 /*
1229  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1230  * microframes, rounded down to nearest power of 2.
1231  */
1232 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1233                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1234                 unsigned int min_exponent, unsigned int max_exponent)
1235 {
1236         unsigned int interval;
1237
1238         interval = fls(desc_interval) - 1;
1239         interval = clamp_val(interval, min_exponent, max_exponent);
1240         if ((1 << interval) != desc_interval)
1241                 dev_warn(&udev->dev,
1242                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1243                          ep->desc.bEndpointAddress,
1244                          1 << interval,
1245                          desc_interval);
1246
1247         return interval;
1248 }
1249
1250 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1251                 struct usb_host_endpoint *ep)
1252 {
1253         if (ep->desc.bInterval == 0)
1254                 return 0;
1255         return xhci_microframes_to_exponent(udev, ep,
1256                         ep->desc.bInterval, 0, 15);
1257 }
1258
1259
1260 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1261                 struct usb_host_endpoint *ep)
1262 {
1263         return xhci_microframes_to_exponent(udev, ep,
1264                         ep->desc.bInterval * 8, 3, 10);
1265 }
1266
1267 /* Return the polling or NAK interval.
1268  *
1269  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1270  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1271  *
1272  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1273  * is set to 0.
1274  */
1275 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1276                 struct usb_host_endpoint *ep)
1277 {
1278         unsigned int interval = 0;
1279
1280         switch (udev->speed) {
1281         case USB_SPEED_HIGH:
1282                 /* Max NAK rate */
1283                 if (usb_endpoint_xfer_control(&ep->desc) ||
1284                     usb_endpoint_xfer_bulk(&ep->desc)) {
1285                         interval = xhci_parse_microframe_interval(udev, ep);
1286                         break;
1287                 }
1288                 /* Fall through - SS and HS isoc/int have same decoding */
1289
1290         case USB_SPEED_SUPER:
1291                 if (usb_endpoint_xfer_int(&ep->desc) ||
1292                     usb_endpoint_xfer_isoc(&ep->desc)) {
1293                         interval = xhci_parse_exponent_interval(udev, ep);
1294                 }
1295                 break;
1296
1297         case USB_SPEED_FULL:
1298                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1299                         interval = xhci_parse_exponent_interval(udev, ep);
1300                         break;
1301                 }
1302                 /*
1303                  * Fall through for interrupt endpoint interval decoding
1304                  * since it uses the same rules as low speed interrupt
1305                  * endpoints.
1306                  */
1307
1308         case USB_SPEED_LOW:
1309                 if (usb_endpoint_xfer_int(&ep->desc) ||
1310                     usb_endpoint_xfer_isoc(&ep->desc)) {
1311
1312                         interval = xhci_parse_frame_interval(udev, ep);
1313                 }
1314                 break;
1315
1316         default:
1317                 BUG();
1318         }
1319         return EP_INTERVAL(interval);
1320 }
1321
1322 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1323  * High speed endpoint descriptors can define "the number of additional
1324  * transaction opportunities per microframe", but that goes in the Max Burst
1325  * endpoint context field.
1326  */
1327 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1328                 struct usb_host_endpoint *ep)
1329 {
1330         if (udev->speed != USB_SPEED_SUPER ||
1331                         !usb_endpoint_xfer_isoc(&ep->desc))
1332                 return 0;
1333         return ep->ss_ep_comp.bmAttributes;
1334 }
1335
1336 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1337                 struct usb_host_endpoint *ep)
1338 {
1339         int in;
1340         u32 type;
1341
1342         in = usb_endpoint_dir_in(&ep->desc);
1343         if (usb_endpoint_xfer_control(&ep->desc)) {
1344                 type = EP_TYPE(CTRL_EP);
1345         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1346                 if (in)
1347                         type = EP_TYPE(BULK_IN_EP);
1348                 else
1349                         type = EP_TYPE(BULK_OUT_EP);
1350         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1351                 if (in)
1352                         type = EP_TYPE(ISOC_IN_EP);
1353                 else
1354                         type = EP_TYPE(ISOC_OUT_EP);
1355         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1356                 if (in)
1357                         type = EP_TYPE(INT_IN_EP);
1358                 else
1359                         type = EP_TYPE(INT_OUT_EP);
1360         } else {
1361                 BUG();
1362         }
1363         return type;
1364 }
1365
1366 /* Return the maximum endpoint service interval time (ESIT) payload.
1367  * Basically, this is the maxpacket size, multiplied by the burst size
1368  * and mult size.
1369  */
1370 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1371                 struct usb_device *udev,
1372                 struct usb_host_endpoint *ep)
1373 {
1374         int max_burst;
1375         int max_packet;
1376
1377         /* Only applies for interrupt or isochronous endpoints */
1378         if (usb_endpoint_xfer_control(&ep->desc) ||
1379                         usb_endpoint_xfer_bulk(&ep->desc))
1380                 return 0;
1381
1382         if (udev->speed == USB_SPEED_SUPER)
1383                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1384
1385         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1386         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1387         /* A 0 in max burst means 1 transfer per ESIT */
1388         return max_packet * (max_burst + 1);
1389 }
1390
1391 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1392  * Drivers will have to call usb_alloc_streams() to do that.
1393  */
1394 int xhci_endpoint_init(struct xhci_hcd *xhci,
1395                 struct xhci_virt_device *virt_dev,
1396                 struct usb_device *udev,
1397                 struct usb_host_endpoint *ep,
1398                 gfp_t mem_flags)
1399 {
1400         unsigned int ep_index;
1401         struct xhci_ep_ctx *ep_ctx;
1402         struct xhci_ring *ep_ring;
1403         unsigned int max_packet;
1404         unsigned int max_burst;
1405         enum xhci_ring_type type;
1406         u32 max_esit_payload;
1407
1408         ep_index = xhci_get_endpoint_index(&ep->desc);
1409         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1410
1411         type = usb_endpoint_type(&ep->desc);
1412         /* Set up the endpoint ring */
1413         virt_dev->eps[ep_index].new_ring =
1414                 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1415         if (!virt_dev->eps[ep_index].new_ring) {
1416                 /* Attempt to use the ring cache */
1417                 if (virt_dev->num_rings_cached == 0)
1418                         return -ENOMEM;
1419                 virt_dev->eps[ep_index].new_ring =
1420                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1421                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1422                 virt_dev->num_rings_cached--;
1423                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1424                                         1, type);
1425         }
1426         virt_dev->eps[ep_index].skip = false;
1427         ep_ring = virt_dev->eps[ep_index].new_ring;
1428         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1429
1430         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1431                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1432
1433         /* FIXME dig Mult and streams info out of ep companion desc */
1434
1435         /* Allow 3 retries for everything but isoc;
1436          * CErr shall be set to 0 for Isoch endpoints.
1437          */
1438         if (!usb_endpoint_xfer_isoc(&ep->desc))
1439                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1440         else
1441                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1442
1443         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1444
1445         /* Set the max packet size and max burst */
1446         switch (udev->speed) {
1447         case USB_SPEED_SUPER:
1448                 max_packet = usb_endpoint_maxp(&ep->desc);
1449                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1450                 /* dig out max burst from ep companion desc */
1451                 max_packet = ep->ss_ep_comp.bMaxBurst;
1452                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1453                 break;
1454         case USB_SPEED_HIGH:
1455                 /* bits 11:12 specify the number of additional transaction
1456                  * opportunities per microframe (USB 2.0, section 9.6.6)
1457                  */
1458                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1459                                 usb_endpoint_xfer_int(&ep->desc)) {
1460                         max_burst = (usb_endpoint_maxp(&ep->desc)
1461                                      & 0x1800) >> 11;
1462                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1463                 }
1464                 /* Fall through */
1465         case USB_SPEED_FULL:
1466         case USB_SPEED_LOW:
1467                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1468                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1469                 break;
1470         default:
1471                 BUG();
1472         }
1473         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1474         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1475
1476         /*
1477          * XXX no idea how to calculate the average TRB buffer length for bulk
1478          * endpoints, as the driver gives us no clue how big each scatter gather
1479          * list entry (or buffer) is going to be.
1480          *
1481          * For isochronous and interrupt endpoints, we set it to the max
1482          * available, until we have new API in the USB core to allow drivers to
1483          * declare how much bandwidth they actually need.
1484          *
1485          * Normally, it would be calculated by taking the total of the buffer
1486          * lengths in the TD and then dividing by the number of TRBs in a TD,
1487          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1488          * use Event Data TRBs, and we don't chain in a link TRB on short
1489          * transfers, we're basically dividing by 1.
1490          *
1491          * xHCI 1.0 specification indicates that the Average TRB Length should
1492          * be set to 8 for control endpoints.
1493          */
1494         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1495                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1496         else
1497                 ep_ctx->tx_info |=
1498                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1499
1500         /* FIXME Debug endpoint context */
1501         return 0;
1502 }
1503
1504 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1505                 struct xhci_virt_device *virt_dev,
1506                 struct usb_host_endpoint *ep)
1507 {
1508         unsigned int ep_index;
1509         struct xhci_ep_ctx *ep_ctx;
1510
1511         ep_index = xhci_get_endpoint_index(&ep->desc);
1512         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1513
1514         ep_ctx->ep_info = 0;
1515         ep_ctx->ep_info2 = 0;
1516         ep_ctx->deq = 0;
1517         ep_ctx->tx_info = 0;
1518         /* Don't free the endpoint ring until the set interface or configuration
1519          * request succeeds.
1520          */
1521 }
1522
1523 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1524 {
1525         bw_info->ep_interval = 0;
1526         bw_info->mult = 0;
1527         bw_info->num_packets = 0;
1528         bw_info->max_packet_size = 0;
1529         bw_info->type = 0;
1530         bw_info->max_esit_payload = 0;
1531 }
1532
1533 void xhci_update_bw_info(struct xhci_hcd *xhci,
1534                 struct xhci_container_ctx *in_ctx,
1535                 struct xhci_input_control_ctx *ctrl_ctx,
1536                 struct xhci_virt_device *virt_dev)
1537 {
1538         struct xhci_bw_info *bw_info;
1539         struct xhci_ep_ctx *ep_ctx;
1540         unsigned int ep_type;
1541         int i;
1542
1543         for (i = 1; i < 31; ++i) {
1544                 bw_info = &virt_dev->eps[i].bw_info;
1545
1546                 /* We can't tell what endpoint type is being dropped, but
1547                  * unconditionally clearing the bandwidth info for non-periodic
1548                  * endpoints should be harmless because the info will never be
1549                  * set in the first place.
1550                  */
1551                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1552                         /* Dropped endpoint */
1553                         xhci_clear_endpoint_bw_info(bw_info);
1554                         continue;
1555                 }
1556
1557                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1558                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1559                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1560
1561                         /* Ignore non-periodic endpoints */
1562                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1563                                         ep_type != ISOC_IN_EP &&
1564                                         ep_type != INT_IN_EP)
1565                                 continue;
1566
1567                         /* Added or changed endpoint */
1568                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1569                                         le32_to_cpu(ep_ctx->ep_info));
1570                         /* Number of packets and mult are zero-based in the
1571                          * input context, but we want one-based for the
1572                          * interval table.
1573                          */
1574                         bw_info->mult = CTX_TO_EP_MULT(
1575                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1576                         bw_info->num_packets = CTX_TO_MAX_BURST(
1577                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1578                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1579                                         le32_to_cpu(ep_ctx->ep_info2));
1580                         bw_info->type = ep_type;
1581                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1582                                         le32_to_cpu(ep_ctx->tx_info));
1583                 }
1584         }
1585 }
1586
1587 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1588  * Useful when you want to change one particular aspect of the endpoint and then
1589  * issue a configure endpoint command.
1590  */
1591 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1592                 struct xhci_container_ctx *in_ctx,
1593                 struct xhci_container_ctx *out_ctx,
1594                 unsigned int ep_index)
1595 {
1596         struct xhci_ep_ctx *out_ep_ctx;
1597         struct xhci_ep_ctx *in_ep_ctx;
1598
1599         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1600         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1601
1602         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1603         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1604         in_ep_ctx->deq = out_ep_ctx->deq;
1605         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1606 }
1607
1608 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1609  * Useful when you want to change one particular aspect of the endpoint and then
1610  * issue a configure endpoint command.  Only the context entries field matters,
1611  * but we'll copy the whole thing anyway.
1612  */
1613 void xhci_slot_copy(struct xhci_hcd *xhci,
1614                 struct xhci_container_ctx *in_ctx,
1615                 struct xhci_container_ctx *out_ctx)
1616 {
1617         struct xhci_slot_ctx *in_slot_ctx;
1618         struct xhci_slot_ctx *out_slot_ctx;
1619
1620         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1621         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1622
1623         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1624         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1625         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1626         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1627 }
1628
1629 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1630 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1631 {
1632         int i;
1633         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1634         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1635
1636         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1637
1638         if (!num_sp)
1639                 return 0;
1640
1641         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1642         if (!xhci->scratchpad)
1643                 goto fail_sp;
1644
1645         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1646                                      num_sp * sizeof(u64),
1647                                      &xhci->scratchpad->sp_dma, flags);
1648         if (!xhci->scratchpad->sp_array)
1649                 goto fail_sp2;
1650
1651         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1652         if (!xhci->scratchpad->sp_buffers)
1653                 goto fail_sp3;
1654
1655         xhci->scratchpad->sp_dma_buffers =
1656                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1657
1658         if (!xhci->scratchpad->sp_dma_buffers)
1659                 goto fail_sp4;
1660
1661         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1662         for (i = 0; i < num_sp; i++) {
1663                 dma_addr_t dma;
1664                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1665                                 flags);
1666                 if (!buf)
1667                         goto fail_sp5;
1668
1669                 xhci->scratchpad->sp_array[i] = dma;
1670                 xhci->scratchpad->sp_buffers[i] = buf;
1671                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1672         }
1673
1674         return 0;
1675
1676  fail_sp5:
1677         for (i = i - 1; i >= 0; i--) {
1678                 dma_free_coherent(dev, xhci->page_size,
1679                                     xhci->scratchpad->sp_buffers[i],
1680                                     xhci->scratchpad->sp_dma_buffers[i]);
1681         }
1682         kfree(xhci->scratchpad->sp_dma_buffers);
1683
1684  fail_sp4:
1685         kfree(xhci->scratchpad->sp_buffers);
1686
1687  fail_sp3:
1688         dma_free_coherent(dev, num_sp * sizeof(u64),
1689                             xhci->scratchpad->sp_array,
1690                             xhci->scratchpad->sp_dma);
1691
1692  fail_sp2:
1693         kfree(xhci->scratchpad);
1694         xhci->scratchpad = NULL;
1695
1696  fail_sp:
1697         return -ENOMEM;
1698 }
1699
1700 static void scratchpad_free(struct xhci_hcd *xhci)
1701 {
1702         int num_sp;
1703         int i;
1704         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1705
1706         if (!xhci->scratchpad)
1707                 return;
1708
1709         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1710
1711         for (i = 0; i < num_sp; i++) {
1712                 dma_free_coherent(&pdev->dev, xhci->page_size,
1713                                     xhci->scratchpad->sp_buffers[i],
1714                                     xhci->scratchpad->sp_dma_buffers[i]);
1715         }
1716         kfree(xhci->scratchpad->sp_dma_buffers);
1717         kfree(xhci->scratchpad->sp_buffers);
1718         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1719                             xhci->scratchpad->sp_array,
1720                             xhci->scratchpad->sp_dma);
1721         kfree(xhci->scratchpad);
1722         xhci->scratchpad = NULL;
1723 }
1724
1725 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1726                 bool allocate_in_ctx, bool allocate_completion,
1727                 gfp_t mem_flags)
1728 {
1729         struct xhci_command *command;
1730
1731         command = kzalloc(sizeof(*command), mem_flags);
1732         if (!command)
1733                 return NULL;
1734
1735         if (allocate_in_ctx) {
1736                 command->in_ctx =
1737                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1738                                         mem_flags);
1739                 if (!command->in_ctx) {
1740                         kfree(command);
1741                         return NULL;
1742                 }
1743         }
1744
1745         if (allocate_completion) {
1746                 command->completion =
1747                         kzalloc(sizeof(struct completion), mem_flags);
1748                 if (!command->completion) {
1749                         xhci_free_container_ctx(xhci, command->in_ctx);
1750                         kfree(command);
1751                         return NULL;
1752                 }
1753                 init_completion(command->completion);
1754         }
1755
1756         command->status = 0;
1757         INIT_LIST_HEAD(&command->cmd_list);
1758         return command;
1759 }
1760
1761 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1762 {
1763         if (urb_priv) {
1764                 kfree(urb_priv->td[0]);
1765                 kfree(urb_priv);
1766         }
1767 }
1768
1769 void xhci_free_command(struct xhci_hcd *xhci,
1770                 struct xhci_command *command)
1771 {
1772         xhci_free_container_ctx(xhci,
1773                         command->in_ctx);
1774         kfree(command->completion);
1775         kfree(command);
1776 }
1777
1778 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1779 {
1780         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1781         struct dev_info *dev_info, *next;
1782         struct xhci_cd  *cur_cd, *next_cd;
1783         unsigned long   flags;
1784         int size;
1785         int i, j, num_ports;
1786
1787         /* Free the Event Ring Segment Table and the actual Event Ring */
1788         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1789         if (xhci->erst.entries)
1790                 dma_free_coherent(&pdev->dev, size,
1791                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1792         xhci->erst.entries = NULL;
1793         xhci_dbg(xhci, "Freed ERST\n");
1794         if (xhci->event_ring)
1795                 xhci_ring_free(xhci, xhci->event_ring);
1796         xhci->event_ring = NULL;
1797         xhci_dbg(xhci, "Freed event ring\n");
1798
1799         xhci->cmd_ring_reserved_trbs = 0;
1800         if (xhci->cmd_ring)
1801                 xhci_ring_free(xhci, xhci->cmd_ring);
1802         xhci->cmd_ring = NULL;
1803         xhci_dbg(xhci, "Freed command ring\n");
1804         list_for_each_entry_safe(cur_cd, next_cd,
1805                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1806                 list_del(&cur_cd->cancel_cmd_list);
1807                 kfree(cur_cd);
1808         }
1809
1810         for (i = 1; i < MAX_HC_SLOTS; ++i)
1811                 xhci_free_virt_device(xhci, i);
1812
1813         if (xhci->segment_pool)
1814                 dma_pool_destroy(xhci->segment_pool);
1815         xhci->segment_pool = NULL;
1816         xhci_dbg(xhci, "Freed segment pool\n");
1817
1818         if (xhci->device_pool)
1819                 dma_pool_destroy(xhci->device_pool);
1820         xhci->device_pool = NULL;
1821         xhci_dbg(xhci, "Freed device context pool\n");
1822
1823         if (xhci->small_streams_pool)
1824                 dma_pool_destroy(xhci->small_streams_pool);
1825         xhci->small_streams_pool = NULL;
1826         xhci_dbg(xhci, "Freed small stream array pool\n");
1827
1828         if (xhci->medium_streams_pool)
1829                 dma_pool_destroy(xhci->medium_streams_pool);
1830         xhci->medium_streams_pool = NULL;
1831         xhci_dbg(xhci, "Freed medium stream array pool\n");
1832
1833         if (xhci->dcbaa)
1834                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1835                                 xhci->dcbaa, xhci->dcbaa->dma);
1836         xhci->dcbaa = NULL;
1837
1838         scratchpad_free(xhci);
1839
1840         spin_lock_irqsave(&xhci->lock, flags);
1841         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1842                 list_del(&dev_info->list);
1843                 kfree(dev_info);
1844         }
1845         spin_unlock_irqrestore(&xhci->lock, flags);
1846
1847         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1848         for (i = 0; i < num_ports; i++) {
1849                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1850                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1851                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1852                         while (!list_empty(ep))
1853                                 list_del_init(ep->next);
1854                 }
1855         }
1856
1857         for (i = 0; i < num_ports; i++) {
1858                 struct xhci_tt_bw_info *tt, *n;
1859                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1860                         list_del(&tt->tt_list);
1861                         kfree(tt);
1862                 }
1863         }
1864
1865         xhci->num_usb2_ports = 0;
1866         xhci->num_usb3_ports = 0;
1867         xhci->num_active_eps = 0;
1868         kfree(xhci->usb2_ports);
1869         kfree(xhci->usb3_ports);
1870         kfree(xhci->port_array);
1871         kfree(xhci->rh_bw);
1872
1873         xhci->page_size = 0;
1874         xhci->page_shift = 0;
1875         xhci->bus_state[0].bus_suspended = 0;
1876         xhci->bus_state[1].bus_suspended = 0;
1877 }
1878
1879 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1880                 struct xhci_segment *input_seg,
1881                 union xhci_trb *start_trb,
1882                 union xhci_trb *end_trb,
1883                 dma_addr_t input_dma,
1884                 struct xhci_segment *result_seg,
1885                 char *test_name, int test_number)
1886 {
1887         unsigned long long start_dma;
1888         unsigned long long end_dma;
1889         struct xhci_segment *seg;
1890
1891         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1892         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1893
1894         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1895         if (seg != result_seg) {
1896                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1897                                 test_name, test_number);
1898                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1899                                 "input DMA 0x%llx\n",
1900                                 input_seg,
1901                                 (unsigned long long) input_dma);
1902                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1903                                 "ending TRB %p (0x%llx DMA)\n",
1904                                 start_trb, start_dma,
1905                                 end_trb, end_dma);
1906                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1907                                 result_seg, seg);
1908                 return -1;
1909         }
1910         return 0;
1911 }
1912
1913 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1914 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1915 {
1916         struct {
1917                 dma_addr_t              input_dma;
1918                 struct xhci_segment     *result_seg;
1919         } simple_test_vector [] = {
1920                 /* A zeroed DMA field should fail */
1921                 { 0, NULL },
1922                 /* One TRB before the ring start should fail */
1923                 { xhci->event_ring->first_seg->dma - 16, NULL },
1924                 /* One byte before the ring start should fail */
1925                 { xhci->event_ring->first_seg->dma - 1, NULL },
1926                 /* Starting TRB should succeed */
1927                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1928                 /* Ending TRB should succeed */
1929                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1930                         xhci->event_ring->first_seg },
1931                 /* One byte after the ring end should fail */
1932                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1933                 /* One TRB after the ring end should fail */
1934                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1935                 /* An address of all ones should fail */
1936                 { (dma_addr_t) (~0), NULL },
1937         };
1938         struct {
1939                 struct xhci_segment     *input_seg;
1940                 union xhci_trb          *start_trb;
1941                 union xhci_trb          *end_trb;
1942                 dma_addr_t              input_dma;
1943                 struct xhci_segment     *result_seg;
1944         } complex_test_vector [] = {
1945                 /* Test feeding a valid DMA address from a different ring */
1946                 {       .input_seg = xhci->event_ring->first_seg,
1947                         .start_trb = xhci->event_ring->first_seg->trbs,
1948                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1949                         .input_dma = xhci->cmd_ring->first_seg->dma,
1950                         .result_seg = NULL,
1951                 },
1952                 /* Test feeding a valid end TRB from a different ring */
1953                 {       .input_seg = xhci->event_ring->first_seg,
1954                         .start_trb = xhci->event_ring->first_seg->trbs,
1955                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1956                         .input_dma = xhci->cmd_ring->first_seg->dma,
1957                         .result_seg = NULL,
1958                 },
1959                 /* Test feeding a valid start and end TRB from a different ring */
1960                 {       .input_seg = xhci->event_ring->first_seg,
1961                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1962                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1963                         .input_dma = xhci->cmd_ring->first_seg->dma,
1964                         .result_seg = NULL,
1965                 },
1966                 /* TRB in this ring, but after this TD */
1967                 {       .input_seg = xhci->event_ring->first_seg,
1968                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1969                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1970                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1971                         .result_seg = NULL,
1972                 },
1973                 /* TRB in this ring, but before this TD */
1974                 {       .input_seg = xhci->event_ring->first_seg,
1975                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1976                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1977                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1978                         .result_seg = NULL,
1979                 },
1980                 /* TRB in this ring, but after this wrapped TD */
1981                 {       .input_seg = xhci->event_ring->first_seg,
1982                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1983                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1984                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1985                         .result_seg = NULL,
1986                 },
1987                 /* TRB in this ring, but before this wrapped TD */
1988                 {       .input_seg = xhci->event_ring->first_seg,
1989                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1990                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1991                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1992                         .result_seg = NULL,
1993                 },
1994                 /* TRB not in this ring, and we have a wrapped TD */
1995                 {       .input_seg = xhci->event_ring->first_seg,
1996                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1997                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1998                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1999                         .result_seg = NULL,
2000                 },
2001         };
2002
2003         unsigned int num_tests;
2004         int i, ret;
2005
2006         num_tests = ARRAY_SIZE(simple_test_vector);
2007         for (i = 0; i < num_tests; i++) {
2008                 ret = xhci_test_trb_in_td(xhci,
2009                                 xhci->event_ring->first_seg,
2010                                 xhci->event_ring->first_seg->trbs,
2011                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2012                                 simple_test_vector[i].input_dma,
2013                                 simple_test_vector[i].result_seg,
2014                                 "Simple", i);
2015                 if (ret < 0)
2016                         return ret;
2017         }
2018
2019         num_tests = ARRAY_SIZE(complex_test_vector);
2020         for (i = 0; i < num_tests; i++) {
2021                 ret = xhci_test_trb_in_td(xhci,
2022                                 complex_test_vector[i].input_seg,
2023                                 complex_test_vector[i].start_trb,
2024                                 complex_test_vector[i].end_trb,
2025                                 complex_test_vector[i].input_dma,
2026                                 complex_test_vector[i].result_seg,
2027                                 "Complex", i);
2028                 if (ret < 0)
2029                         return ret;
2030         }
2031         xhci_dbg(xhci, "TRB math tests passed.\n");
2032         return 0;
2033 }
2034
2035 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2036 {
2037         u64 temp;
2038         dma_addr_t deq;
2039
2040         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2041                         xhci->event_ring->dequeue);
2042         if (deq == 0 && !in_interrupt())
2043                 xhci_warn(xhci, "WARN something wrong with SW event ring "
2044                                 "dequeue ptr.\n");
2045         /* Update HC event ring dequeue pointer */
2046         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2047         temp &= ERST_PTR_MASK;
2048         /* Don't clear the EHB bit (which is RW1C) because
2049          * there might be more events to service.
2050          */
2051         temp &= ~ERST_EHB;
2052         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2053                         "preserving EHB bit\n");
2054         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2055                         &xhci->ir_set->erst_dequeue);
2056 }
2057
2058 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2059                 __le32 __iomem *addr, u8 major_revision)
2060 {
2061         u32 temp, port_offset, port_count;
2062         int i;
2063
2064         if (major_revision > 0x03) {
2065                 xhci_warn(xhci, "Ignoring unknown port speed, "
2066                                 "Ext Cap %p, revision = 0x%x\n",
2067                                 addr, major_revision);
2068                 /* Ignoring port protocol we can't understand. FIXME */
2069                 return;
2070         }
2071
2072         /* Port offset and count in the third dword, see section 7.2 */
2073         temp = xhci_readl(xhci, addr + 2);
2074         port_offset = XHCI_EXT_PORT_OFF(temp);
2075         port_count = XHCI_EXT_PORT_COUNT(temp);
2076         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2077                         "count = %u, revision = 0x%x\n",
2078                         addr, port_offset, port_count, major_revision);
2079         /* Port count includes the current port offset */
2080         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2081                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2082                 return;
2083
2084         /* Check the host's USB2 LPM capability */
2085         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2086                         (temp & XHCI_L1C)) {
2087                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2088                 xhci->sw_lpm_support = 1;
2089         }
2090
2091         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2092                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2093                 xhci->sw_lpm_support = 1;
2094                 if (temp & XHCI_HLC) {
2095                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2096                         xhci->hw_lpm_support = 1;
2097                 }
2098         }
2099
2100         port_offset--;
2101         for (i = port_offset; i < (port_offset + port_count); i++) {
2102                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2103                 if (xhci->port_array[i] != 0) {
2104                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2105                                         " port %u\n", addr, i);
2106                         xhci_warn(xhci, "Port was marked as USB %u, "
2107                                         "duplicated as USB %u\n",
2108                                         xhci->port_array[i], major_revision);
2109                         /* Only adjust the roothub port counts if we haven't
2110                          * found a similar duplicate.
2111                          */
2112                         if (xhci->port_array[i] != major_revision &&
2113                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2114                                 if (xhci->port_array[i] == 0x03)
2115                                         xhci->num_usb3_ports--;
2116                                 else
2117                                         xhci->num_usb2_ports--;
2118                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2119                         }
2120                         /* FIXME: Should we disable the port? */
2121                         continue;
2122                 }
2123                 xhci->port_array[i] = major_revision;
2124                 if (major_revision == 0x03)
2125                         xhci->num_usb3_ports++;
2126                 else
2127                         xhci->num_usb2_ports++;
2128         }
2129         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2130 }
2131
2132 /*
2133  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2134  * specify what speeds each port is supposed to be.  We can't count on the port
2135  * speed bits in the PORTSC register being correct until a device is connected,
2136  * but we need to set up the two fake roothubs with the correct number of USB
2137  * 3.0 and USB 2.0 ports at host controller initialization time.
2138  */
2139 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2140 {
2141         __le32 __iomem *addr;
2142         u32 offset;
2143         unsigned int num_ports;
2144         int i, j, port_index;
2145
2146         addr = &xhci->cap_regs->hcc_params;
2147         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2148         if (offset == 0) {
2149                 xhci_err(xhci, "No Extended Capability registers, "
2150                                 "unable to set up roothub.\n");
2151                 return -ENODEV;
2152         }
2153
2154         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2155         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2156         if (!xhci->port_array)
2157                 return -ENOMEM;
2158
2159         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2160         if (!xhci->rh_bw)
2161                 return -ENOMEM;
2162         for (i = 0; i < num_ports; i++) {
2163                 struct xhci_interval_bw_table *bw_table;
2164
2165                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2166                 bw_table = &xhci->rh_bw[i].bw_table;
2167                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2168                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2169         }
2170
2171         /*
2172          * For whatever reason, the first capability offset is from the
2173          * capability register base, not from the HCCPARAMS register.
2174          * See section 5.3.6 for offset calculation.
2175          */
2176         addr = &xhci->cap_regs->hc_capbase + offset;
2177         while (1) {
2178                 u32 cap_id;
2179
2180                 cap_id = xhci_readl(xhci, addr);
2181                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2182                         xhci_add_in_port(xhci, num_ports, addr,
2183                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2184                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2185                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2186                                 == num_ports)
2187                         break;
2188                 /*
2189                  * Once you're into the Extended Capabilities, the offset is
2190                  * always relative to the register holding the offset.
2191                  */
2192                 addr += offset;
2193         }
2194
2195         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2196                 xhci_warn(xhci, "No ports on the roothubs?\n");
2197                 return -ENODEV;
2198         }
2199         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2200                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2201
2202         /* Place limits on the number of roothub ports so that the hub
2203          * descriptors aren't longer than the USB core will allocate.
2204          */
2205         if (xhci->num_usb3_ports > 15) {
2206                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2207                 xhci->num_usb3_ports = 15;
2208         }
2209         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2210                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2211                                 USB_MAXCHILDREN);
2212                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2213         }
2214
2215         /*
2216          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2217          * Not sure how the USB core will handle a hub with no ports...
2218          */
2219         if (xhci->num_usb2_ports) {
2220                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2221                                 xhci->num_usb2_ports, flags);
2222                 if (!xhci->usb2_ports)
2223                         return -ENOMEM;
2224
2225                 port_index = 0;
2226                 for (i = 0; i < num_ports; i++) {
2227                         if (xhci->port_array[i] == 0x03 ||
2228                                         xhci->port_array[i] == 0 ||
2229                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2230                                 continue;
2231
2232                         xhci->usb2_ports[port_index] =
2233                                 &xhci->op_regs->port_status_base +
2234                                 NUM_PORT_REGS*i;
2235                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2236                                         "addr = %p\n", i,
2237                                         xhci->usb2_ports[port_index]);
2238                         port_index++;
2239                         if (port_index == xhci->num_usb2_ports)
2240                                 break;
2241                 }
2242         }
2243         if (xhci->num_usb3_ports) {
2244                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2245                                 xhci->num_usb3_ports, flags);
2246                 if (!xhci->usb3_ports)
2247                         return -ENOMEM;
2248
2249                 port_index = 0;
2250                 for (i = 0; i < num_ports; i++)
2251                         if (xhci->port_array[i] == 0x03) {
2252                                 xhci->usb3_ports[port_index] =
2253                                         &xhci->op_regs->port_status_base +
2254                                         NUM_PORT_REGS*i;
2255                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2256                                                 "addr = %p\n", i,
2257                                                 xhci->usb3_ports[port_index]);
2258                                 port_index++;
2259                                 if (port_index == xhci->num_usb3_ports)
2260                                         break;
2261                         }
2262         }
2263         return 0;
2264 }
2265
2266 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2267 {
2268         dma_addr_t      dma;
2269         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2270         unsigned int    val, val2;
2271         u64             val_64;
2272         struct xhci_segment     *seg;
2273         u32 page_size, temp;
2274         int i;
2275
2276         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2277         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2278         for (i = 0; i < 16; i++) {
2279                 if ((0x1 & page_size) != 0)
2280                         break;
2281                 page_size = page_size >> 1;
2282         }
2283         if (i < 16)
2284                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2285         else
2286                 xhci_warn(xhci, "WARN: no supported page size\n");
2287         /* Use 4K pages, since that's common and the minimum the HC supports */
2288         xhci->page_shift = 12;
2289         xhci->page_size = 1 << xhci->page_shift;
2290         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2291
2292         /*
2293          * Program the Number of Device Slots Enabled field in the CONFIG
2294          * register with the max value of slots the HC can handle.
2295          */
2296         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2297         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2298                         (unsigned int) val);
2299         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2300         val |= (val2 & ~HCS_SLOTS_MASK);
2301         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2302                         (unsigned int) val);
2303         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2304
2305         /*
2306          * Section 5.4.8 - doorbell array must be
2307          * "physically contiguous and 64-byte (cache line) aligned".
2308          */
2309         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2310                         GFP_KERNEL);
2311         if (!xhci->dcbaa)
2312                 goto fail;
2313         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2314         xhci->dcbaa->dma = dma;
2315         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2316                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2317         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2318
2319         /*
2320          * Initialize the ring segment pool.  The ring must be a contiguous
2321          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2322          * however, the command ring segment needs 64-byte aligned segments,
2323          * so we pick the greater alignment need.
2324          */
2325         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2326                         SEGMENT_SIZE, 64, xhci->page_size);
2327
2328         /* See Table 46 and Note on Figure 55 */
2329         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2330                         2112, 64, xhci->page_size);
2331         if (!xhci->segment_pool || !xhci->device_pool)
2332                 goto fail;
2333
2334         /* Linear stream context arrays don't have any boundary restrictions,
2335          * and only need to be 16-byte aligned.
2336          */
2337         xhci->small_streams_pool =
2338                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2339                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2340         xhci->medium_streams_pool =
2341                 dma_pool_create("xHCI 1KB stream ctx arrays",
2342                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2343         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2344          * will be allocated with dma_alloc_coherent()
2345          */
2346
2347         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2348                 goto fail;
2349
2350         /* Set up the command ring to have one segments for now. */
2351         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2352         if (!xhci->cmd_ring)
2353                 goto fail;
2354         INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2355         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2356         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2357                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2358
2359         /* Set the address in the Command Ring Control register */
2360         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2361         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2362                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2363                 xhci->cmd_ring->cycle_state;
2364         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2365         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2366         xhci_dbg_cmd_ptrs(xhci);
2367
2368         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2369         val &= DBOFF_MASK;
2370         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2371                         " from cap regs base addr\n", val);
2372         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2373         xhci_dbg_regs(xhci);
2374         xhci_print_run_regs(xhci);
2375         /* Set ir_set to interrupt register set 0 */
2376         xhci->ir_set = &xhci->run_regs->ir_set[0];
2377
2378         /*
2379          * Event ring setup: Allocate a normal ring, but also setup
2380          * the event ring segment table (ERST).  Section 4.9.3.
2381          */
2382         xhci_dbg(xhci, "// Allocating event ring\n");
2383         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2384                                                 flags);
2385         if (!xhci->event_ring)
2386                 goto fail;
2387         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2388                 goto fail;
2389
2390         xhci->erst.entries = dma_alloc_coherent(dev,
2391                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2392                         GFP_KERNEL);
2393         if (!xhci->erst.entries)
2394                 goto fail;
2395         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2396                         (unsigned long long)dma);
2397
2398         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2399         xhci->erst.num_entries = ERST_NUM_SEGS;
2400         xhci->erst.erst_dma_addr = dma;
2401         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2402                         xhci->erst.num_entries,
2403                         xhci->erst.entries,
2404                         (unsigned long long)xhci->erst.erst_dma_addr);
2405
2406         /* set ring base address and size for each segment table entry */
2407         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2408                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2409                 entry->seg_addr = cpu_to_le64(seg->dma);
2410                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2411                 entry->rsvd = 0;
2412                 seg = seg->next;
2413         }
2414
2415         /* set ERST count with the number of entries in the segment table */
2416         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2417         val &= ERST_SIZE_MASK;
2418         val |= ERST_NUM_SEGS;
2419         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2420                         val);
2421         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2422
2423         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2424         /* set the segment table base address */
2425         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2426                         (unsigned long long)xhci->erst.erst_dma_addr);
2427         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2428         val_64 &= ERST_PTR_MASK;
2429         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2430         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2431
2432         /* Set the event ring dequeue address */
2433         xhci_set_hc_event_deq(xhci);
2434         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2435         xhci_print_ir_set(xhci, 0);
2436
2437         /*
2438          * XXX: Might need to set the Interrupter Moderation Register to
2439          * something other than the default (~1ms minimum between interrupts).
2440          * See section 5.5.1.2.
2441          */
2442         init_completion(&xhci->addr_dev);
2443         for (i = 0; i < MAX_HC_SLOTS; ++i)
2444                 xhci->devs[i] = NULL;
2445         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2446                 xhci->bus_state[0].resume_done[i] = 0;
2447                 xhci->bus_state[1].resume_done[i] = 0;
2448         }
2449
2450         if (scratchpad_alloc(xhci, flags))
2451                 goto fail;
2452         if (xhci_setup_port_arrays(xhci, flags))
2453                 goto fail;
2454
2455         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2456
2457         /* Enable USB 3.0 device notifications for function remote wake, which
2458          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2459          * U3 (device suspend).
2460          */
2461         temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2462         temp &= ~DEV_NOTE_MASK;
2463         temp |= DEV_NOTE_FWAKE;
2464         xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2465
2466         return 0;
2467
2468 fail:
2469         xhci_warn(xhci, "Couldn't initialize memory\n");
2470         xhci_halt(xhci);
2471         xhci_reset(xhci);
2472         xhci_mem_cleanup(xhci);
2473         return -ENOMEM;
2474 }