drivers/usb/host/xhci-dbg.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include "xhci.h"
  24
  25 #define XHCI_INIT_VALUE 0x0
  26
  27 /* Add verbose debugging later, just print everything for now */
  28
  29 void xhci_dbg_regs(struct xhci_hcd *xhci)
  30 {
  31         u32 temp;
  32
  33         xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
  34                         xhci->cap_regs);
  35         temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
  36         xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
  37                         &xhci->cap_regs->hc_capbase, temp);
  38         xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
  39                         (unsigned int) HC_LENGTH(temp));
  40 #if 0
  41         xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
  42                         (unsigned int) HC_VERSION(temp));
  43 #endif
  44
  45         xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
  46
  47         temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
  48         xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
  49                         &xhci->cap_regs->run_regs_off,
  50                         (unsigned int) temp & RTSOFF_MASK);
  51         xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
  52
  53         temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
  54         xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
  55         xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
  56 }
  57
  58 static void xhci_print_cap_regs(struct xhci_hcd *xhci)
  59 {
  60         u32 temp;
  61
  62         xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
  63
  64         temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
  65         xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
  66                         (unsigned int) temp);
  67         xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
  68                         (unsigned int) HC_LENGTH(temp));
  69         xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
  70                         (unsigned int) HC_VERSION(temp));
  71
  72         temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
  73         xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
  74                         (unsigned int) temp);
  75         xhci_dbg(xhci, "  Max device slots: %u\n",
  76                         (unsigned int) HCS_MAX_SLOTS(temp));
  77         xhci_dbg(xhci, "  Max interrupters: %u\n",
  78                         (unsigned int) HCS_MAX_INTRS(temp));
  79         xhci_dbg(xhci, "  Max ports: %u\n",
  80                         (unsigned int) HCS_MAX_PORTS(temp));
  81
  82         temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
  83         xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
  84                         (unsigned int) temp);
  85         xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
  86                         (unsigned int) HCS_IST(temp));
  87         xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
  88                         (unsigned int) HCS_ERST_MAX(temp));
  89
  90         temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  91         xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
  92                         (unsigned int) temp);
  93         xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
  94                         (unsigned int) HCS_U1_LATENCY(temp));
  95         xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
  96                         (unsigned int) HCS_U2_LATENCY(temp));
  97
  98         temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  99         xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
 100         xhci_dbg(xhci, "  HC generates %s bit addresses\n",
 101                         HCC_64BIT_ADDR(temp) ? "64" : "32");
 102         /* FIXME */
 103         xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");
 104
 105         temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
 106         xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
 107 }
 108
 109 static void xhci_print_command_reg(struct xhci_hcd *xhci)
 110 {
 111         u32 temp;
 112
 113         temp = xhci_readl(xhci, &xhci->op_regs->command);
 114         xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
 115         xhci_dbg(xhci, "  HC is %s\n",
 116                         (temp & CMD_RUN) ? "running" : "being stopped");
 117         xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
 118                         (temp & CMD_RESET) ? "not " : "");
 119         xhci_dbg(xhci, "  Event Interrupts %s\n",
 120                         (temp & CMD_EIE) ? "enabled " : "disabled");
 121         xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
 122                         (temp & CMD_EIE) ? "enabled " : "disabled");
 123         xhci_dbg(xhci, "  HC has %sfinished light reset\n",
 124                         (temp & CMD_LRESET) ? "not " : "");
 125 }
 126
 127 static void xhci_print_status(struct xhci_hcd *xhci)
 128 {
 129         u32 temp;
 130
 131         temp = xhci_readl(xhci, &xhci->op_regs->status);
 132         xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
 133         xhci_dbg(xhci, "  Event ring is %sempty\n",
 134                         (temp & STS_EINT) ? "not " : "");
 135         xhci_dbg(xhci, "  %sHost System Error\n",
 136                         (temp & STS_FATAL) ? "WARNING: " : "No ");
 137         xhci_dbg(xhci, "  HC is %s\n",
 138                         (temp & STS_HALT) ? "halted" : "running");
 139 }
 140
 141 static void xhci_print_op_regs(struct xhci_hcd *xhci)
 142 {
 143         xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
 144         xhci_print_command_reg(xhci);
 145         xhci_print_status(xhci);
 146 }
 147
 148 static void xhci_print_ports(struct xhci_hcd *xhci)
 149 {
 150         u32 __iomem *addr;
 151         int i, j;
 152         int ports;
 153         char *names[NUM_PORT_REGS] = {
 154                 "status",
 155                 "power",
 156                 "link",
 157                 "reserved",
 158         };
 159
 160         ports = HCS_MAX_PORTS(xhci->hcs_params1);
 161         addr = &xhci->op_regs->port_status_base;
 162         for (i = 0; i < ports; i++) {
 163                 for (j = 0; j < NUM_PORT_REGS; ++j) {
 164                         xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
 165                                         addr, names[j],
 166                                         (unsigned int) xhci_readl(xhci, addr));
 167                         addr++;
 168                 }
 169         }
 170 }
 171
 172 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
 173 {
 174         struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
 175         void __iomem *addr;
 176         u32 temp;
 177         u64 temp_64;
 178
 179         addr = &ir_set->irq_pending;
 180         temp = xhci_readl(xhci, addr);
 181         if (temp == XHCI_INIT_VALUE)
 182                 return;
 183
 184         xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);
 185
 186         xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
 187                         (unsigned int)temp);
 188
 189         addr = &ir_set->irq_control;
 190         temp = xhci_readl(xhci, addr);
 191         xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
 192                         (unsigned int)temp);
 193
 194         addr = &ir_set->erst_size;
 195         temp = xhci_readl(xhci, addr);
 196         xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
 197                         (unsigned int)temp);
 198
 199         addr = &ir_set->rsvd;
 200         temp = xhci_readl(xhci, addr);
 201         if (temp != XHCI_INIT_VALUE)
 202                 xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
 203                                 addr, (unsigned int)temp);
 204
 205         addr = &ir_set->erst_base;
 206         temp_64 = xhci_read_64(xhci, addr);
 207         xhci_dbg(xhci, "  %p: ir_set.erst_base = @%08llx\n",
 208                         addr, temp_64);
 209
 210         addr = &ir_set->erst_dequeue;
 211         temp_64 = xhci_read_64(xhci, addr);
 212         xhci_dbg(xhci, "  %p: ir_set.erst_dequeue = @%08llx\n",
 213                         addr, temp_64);
 214 }
 215
 216 void xhci_print_run_regs(struct xhci_hcd *xhci)
 217 {
 218         u32 temp;
 219         int i;
 220
 221         xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
 222         temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
 223         xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
 224                         &xhci->run_regs->microframe_index,
 225                         (unsigned int) temp);
 226         for (i = 0; i < 7; ++i) {
 227                 temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
 228                 if (temp != XHCI_INIT_VALUE)
 229                         xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
 230                                         &xhci->run_regs->rsvd[i],
 231                                         i, (unsigned int) temp);
 232         }
 233 }
 234
 235 void xhci_print_registers(struct xhci_hcd *xhci)
 236 {
 237         xhci_print_cap_regs(xhci);
 238         xhci_print_op_regs(xhci);
 239         xhci_print_ports(xhci);
 240 }
 241
 242 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
 243 {
 244         int i;
 245         for (i = 0; i < 4; ++i)
 246                 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
 247                                 i*4, trb->generic.field[i]);
 248 }
 249
 250 /**
 251  * Debug a transfer request block (TRB).
 252  */
 253 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
 254 {
 255         u64     address;
 256         u32     type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
 257
 258         switch (type) {
 259         case TRB_TYPE(TRB_LINK):
 260                 xhci_dbg(xhci, "Link TRB:\n");
 261                 xhci_print_trb_offsets(xhci, trb);
 262
 263                 address = trb->link.segment_ptr;
 264                 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
 265
 266                 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
 267                                 GET_INTR_TARGET(trb->link.intr_target));
 268                 xhci_dbg(xhci, "Cycle bit = %u\n",
 269                                 (unsigned int) (trb->link.control & TRB_CYCLE));
 270                 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
 271                                 (unsigned int) (trb->link.control & LINK_TOGGLE));
 272                 xhci_dbg(xhci, "No Snoop bit = %u\n",
 273                                 (unsigned int) (trb->link.control & TRB_NO_SNOOP));
 274                 break;
 275         case TRB_TYPE(TRB_TRANSFER):
 276                 address = trb->trans_event.buffer;
 277                 /*
 278                  * FIXME: look at flags to figure out if it's an address or if
 279                  * the data is directly in the buffer field.
 280                  */
 281                 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
 282                 break;
 283         case TRB_TYPE(TRB_COMPLETION):
 284                 address = trb->event_cmd.cmd_trb;
 285                 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
 286                 xhci_dbg(xhci, "Completion status = %u\n",
 287                                 (unsigned int) GET_COMP_CODE(trb->event_cmd.status));
 288                 xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
 289                 break;
 290         default:
 291                 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
 292                                 (unsigned int) type>>10);
 293                 xhci_print_trb_offsets(xhci, trb);
 294                 break;
 295         }
 296 }
 297
 298 /**
 299  * Debug a segment with an xHCI ring.
 300  *
 301  * @return The Link TRB of the segment, or NULL if there is no Link TRB
 302  * (which is a bug, since all segments must have a Link TRB).
 303  *
 304  * Prints out all TRBs in the segment, even those after the Link TRB.
 305  *
 306  * XXX: should we print out TRBs that the HC owns?  As long as we don't
 307  * write, that should be fine...  We shouldn't expect that the memory pointed to
 308  * by the TRB is valid at all.  Do we care about ones the HC owns?  Probably,
 309  * for HC debugging.
 310  */
 311 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
 312 {
 313         int i;
 314         u32 addr = (u32) seg->dma;
 315         union xhci_trb *trb = seg->trbs;
 316
 317         for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
 318                 trb = &seg->trbs[i];
 319                 xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
 320                                 lower_32_bits(trb->link.segment_ptr),
 321                                 upper_32_bits(trb->link.segment_ptr),
 322                                 (unsigned int) trb->link.intr_target,
 323                                 (unsigned int) trb->link.control);
 324                 addr += sizeof(*trb);
 325         }
 326 }
 327
 328 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 329 {
 330         xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
 331                         ring->dequeue,
 332                         (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
 333                                                             ring->dequeue));
 334         xhci_dbg(xhci, "Ring deq updated %u times\n",
 335                         ring->deq_updates);
 336         xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
 337                         ring->enqueue,
 338                         (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
 339                                                             ring->enqueue));
 340         xhci_dbg(xhci, "Ring enq updated %u times\n",
 341                         ring->enq_updates);
 342 }
 343
 344 /**
 345  * Debugging for an xHCI ring, which is a queue broken into multiple segments.
 346  *
 347  * Print out each segment in the ring.  Check that the DMA address in
 348  * each link segment actually matches the segment's stored DMA address.
 349  * Check that the link end bit is only set at the end of the ring.
 350  * Check that the dequeue and enqueue pointers point to real data in this ring
 351  * (not some other ring).
 352  */
 353 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
 354 {
 355         /* FIXME: Throw an error if any segment doesn't have a Link TRB */
 356         struct xhci_segment *seg;
 357         struct xhci_segment *first_seg = ring->first_seg;
 358         xhci_debug_segment(xhci, first_seg);
 359
 360         if (!ring->enq_updates && !ring->deq_updates) {
 361                 xhci_dbg(xhci, "  Ring has not been updated\n");
 362                 return;
 363         }
 364         for (seg = first_seg->next; seg != first_seg; seg = seg->next)
 365                 xhci_debug_segment(xhci, seg);
 366 }
 367
 368 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
 369                 unsigned int slot_id, unsigned int ep_index,
 370                 struct xhci_virt_ep *ep)
 371 {
 372         int i;
 373         struct xhci_ring *ring;
 374
 375         if (ep->ep_state & EP_HAS_STREAMS) {
 376                 for (i = 1; i < ep->stream_info->num_streams; i++) {
 377                         ring = ep->stream_info->stream_rings[i];
 378                         xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n",
 379                                 slot_id, ep_index, i);
 380                         xhci_debug_segment(xhci, ring->deq_seg);
 381                 }
 382         } else {
 383                 ring = ep->ring;
 384                 if (!ring)
 385                         return;
 386                 xhci_dbg(xhci, "Dev %d endpoint ring %d:\n",
 387                                 slot_id, ep_index);
 388                 xhci_debug_segment(xhci, ring->deq_seg);
 389         }
 390 }
 391
 392 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
 393 {
 394         u32 addr = (u32) erst->erst_dma_addr;
 395         int i;
 396         struct xhci_erst_entry *entry;
 397
 398         for (i = 0; i < erst->num_entries; ++i) {
 399                 entry = &erst->entries[i];
 400                 xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
 401                                 (unsigned int) addr,
 402                                 lower_32_bits(entry->seg_addr),
 403                                 upper_32_bits(entry->seg_addr),
 404                                 (unsigned int) entry->seg_size,
 405                                 (unsigned int) entry->rsvd);
 406                 addr += sizeof(*entry);
 407         }
 408 }
 409
 410 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
 411 {
 412         u64 val;
 413
 414         val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 415         xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
 416                         lower_32_bits(val));
 417         xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
 418                         upper_32_bits(val));
 419 }
 420
 421 /* Print the last 32 bytes for 64-byte contexts */
 422 static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma)
 423 {
 424         int i;
 425         for (i = 0; i < 4; ++i) {
 426                 xhci_dbg(xhci, "@%p (virt) @%08llx "
 427                          "(dma) %#08llx - rsvd64[%d]\n",
 428                          &ctx[4 + i], (unsigned long long)dma,
 429                          ctx[4 + i], i);
 430                 dma += 8;
 431         }
 432 }
 433
 434 char *xhci_get_slot_state(struct xhci_hcd *xhci,
 435                 struct xhci_container_ctx *ctx)
 436 {
 437         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 438
 439         switch (GET_SLOT_STATE(slot_ctx->dev_state)) {
 440         case 0:
 441                 return "enabled/disabled";
 442         case 1:
 443                 return "default";
 444         case 2:
 445                 return "addressed";
 446         case 3:
 447                 return "configured";
 448         default:
 449                 return "reserved";
 450         }
 451 }
 452
 453 static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx)
 454 {
 455         /* Fields are 32 bits wide, DMA addresses are in bytes */
 456         int field_size = 32 / 8;
 457         int i;
 458
 459         struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 460         dma_addr_t dma = ctx->dma +
 461                 ((unsigned long)slot_ctx - (unsigned long)ctx->bytes);
 462         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 463
 464         xhci_dbg(xhci, "Slot Context:\n");
 465         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
 466                         &slot_ctx->dev_info,
 467                         (unsigned long long)dma, slot_ctx->dev_info);
 468         dma += field_size;
 469         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
 470                         &slot_ctx->dev_info2,
 471                         (unsigned long long)dma, slot_ctx->dev_info2);
 472         dma += field_size;
 473         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
 474                         &slot_ctx->tt_info,
 475                         (unsigned long long)dma, slot_ctx->tt_info);
 476         dma += field_size;
 477         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
 478                         &slot_ctx->dev_state,
 479                         (unsigned long long)dma, slot_ctx->dev_state);
 480         dma += field_size;
 481         for (i = 0; i < 4; ++i) {
 482                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
 483                                 &slot_ctx->reserved[i], (unsigned long long)dma,
 484                                 slot_ctx->reserved[i], i);
 485                 dma += field_size;
 486         }
 487
 488         if (csz)
 489                 dbg_rsvd64(xhci, (u64 *)slot_ctx, dma);
 490 }
 491
 492 static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci,
 493                      struct xhci_container_ctx *ctx,
 494                      unsigned int last_ep)
 495 {
 496         int i, j;
 497         int last_ep_ctx = 31;
 498         /* Fields are 32 bits wide, DMA addresses are in bytes */
 499         int field_size = 32 / 8;
 500         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 501
 502         if (last_ep < 31)
 503                 last_ep_ctx = last_ep + 1;
 504         for (i = 0; i < last_ep_ctx; ++i) {
 505                 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i);
 506                 dma_addr_t dma = ctx->dma +
 507                         ((unsigned long)ep_ctx - (unsigned long)ctx->bytes);
 508
 509                 xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
 510                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
 511                                 &ep_ctx->ep_info,
 512                                 (unsigned long long)dma, ep_ctx->ep_info);
 513                 dma += field_size;
 514                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
 515                                 &ep_ctx->ep_info2,
 516                                 (unsigned long long)dma, ep_ctx->ep_info2);
 517                 dma += field_size;
 518                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n",
 519                                 &ep_ctx->deq,
 520                                 (unsigned long long)dma, ep_ctx->deq);
 521                 dma += 2*field_size;
 522                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
 523                                 &ep_ctx->tx_info,
 524                                 (unsigned long long)dma, ep_ctx->tx_info);
 525                 dma += field_size;
 526                 for (j = 0; j < 3; ++j) {
 527                         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
 528                                         &ep_ctx->reserved[j],
 529                                         (unsigned long long)dma,
 530                                         ep_ctx->reserved[j], j);
 531                         dma += field_size;
 532                 }
 533
 534                 if (csz)
 535                         dbg_rsvd64(xhci, (u64 *)ep_ctx, dma);
 536         }
 537 }
 538
 539 void xhci_dbg_ctx(struct xhci_hcd *xhci,
 540                   struct xhci_container_ctx *ctx,
 541                   unsigned int last_ep)
 542 {
 543         int i;
 544         /* Fields are 32 bits wide, DMA addresses are in bytes */
 545         int field_size = 32 / 8;
 546         struct xhci_slot_ctx *slot_ctx;
 547         dma_addr_t dma = ctx->dma;
 548         int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params);
 549
 550         if (ctx->type == XHCI_CTX_TYPE_INPUT) {
 551                 struct xhci_input_control_ctx *ctrl_ctx =
 552                         xhci_get_input_control_ctx(xhci, ctx);
 553                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
 554                          &ctrl_ctx->drop_flags, (unsigned long long)dma,
 555                          ctrl_ctx->drop_flags);
 556                 dma += field_size;
 557                 xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
 558                          &ctrl_ctx->add_flags, (unsigned long long)dma,
 559                          ctrl_ctx->add_flags);
 560                 dma += field_size;
 561                 for (i = 0; i < 6; ++i) {
 562                         xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n",
 563                                  &ctrl_ctx->rsvd2[i], (unsigned long long)dma,
 564                                  ctrl_ctx->rsvd2[i], i);
 565                         dma += field_size;
 566                 }
 567
 568                 if (csz)
 569                         dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma);
 570         }
 571
 572         slot_ctx = xhci_get_slot_ctx(xhci, ctx);
 573         xhci_dbg_slot_ctx(xhci, ctx);
 574         xhci_dbg_ep_ctx(xhci, ctx, last_ep);
 575 }