b426c1e8a679c5cefec61e97746ef74aa2b789f7
[linux-2.6.git] / drivers / usb / host / ohci-hcd.c
1 /*
2  * OHCI HCD (Host Controller Driver) for USB.
3  *
4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6  *
7  * [ Initialisation is based on Linus'  ]
8  * [ uhci code and gregs ohci fragments ]
9  * [ (C) Copyright 1999 Linus Torvalds  ]
10  * [ (C) Copyright 1999 Gregory P. Smith]
11  *
12  *
13  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14  * interfaces (though some non-x86 Intel chips use it).  It supports
15  * smarter hardware than UHCI.  A download link for the spec available
16  * through the http://www.usb.org website.
17  *
18  * This file is licenced under the GPL.
19  */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/usb/hcd.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/dmapool.h>
38 #include <linux/workqueue.h>
39 #include <linux/debugfs.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
45 #include <asm/byteorder.h>
46
47
48 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
49 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
50
51 /*-------------------------------------------------------------------------*/
52
53 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
54
55 /* For initializing controller (mask in an HCFS mode too) */
56 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
57 #define OHCI_INTR_INIT \
58                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
59                 | OHCI_INTR_RD | OHCI_INTR_WDH)
60
61 #ifdef __hppa__
62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
63 #define IR_DISABLE
64 #endif
65
66 #ifdef CONFIG_ARCH_OMAP
67 /* OMAP doesn't support IR (no SMM; not needed) */
68 #define IR_DISABLE
69 #endif
70
71 /*-------------------------------------------------------------------------*/
72
73 static const char       hcd_name [] = "ohci_hcd";
74
75 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
76
77 #include "ohci.h"
78
79 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80 static int ohci_init (struct ohci_hcd *ohci);
81 static void ohci_stop (struct usb_hcd *hcd);
82
83 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
84 static int ohci_restart (struct ohci_hcd *ohci);
85 #endif
86
87 #ifdef CONFIG_PCI
88 static void quirk_amd_pll(int state);
89 static void amd_iso_dev_put(void);
90 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
91 #else
92 static inline void quirk_amd_pll(int state)
93 {
94         return;
95 }
96 static inline void amd_iso_dev_put(void)
97 {
98         return;
99 }
100 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
101 {
102         return;
103 }
104 #endif
105
106
107 #include "ohci-hub.c"
108 #include "ohci-dbg.c"
109 #include "ohci-mem.c"
110 #include "ohci-q.c"
111
112
113 /*
114  * On architectures with edge-triggered interrupts we must never return
115  * IRQ_NONE.
116  */
117 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
118 #define IRQ_NOTMINE     IRQ_HANDLED
119 #else
120 #define IRQ_NOTMINE     IRQ_NONE
121 #endif
122
123
124 /* Some boards misreport power switching/overcurrent */
125 static int distrust_firmware = 1;
126 module_param (distrust_firmware, bool, 0);
127 MODULE_PARM_DESC (distrust_firmware,
128         "true to distrust firmware power/overcurrent setup");
129
130 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
131 static int no_handshake = 0;
132 module_param (no_handshake, bool, 0);
133 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
134
135 /*-------------------------------------------------------------------------*/
136
137 /*
138  * queue up an urb for anything except the root hub
139  */
140 static int ohci_urb_enqueue (
141         struct usb_hcd  *hcd,
142         struct urb      *urb,
143         gfp_t           mem_flags
144 ) {
145         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
146         struct ed       *ed;
147         urb_priv_t      *urb_priv;
148         unsigned int    pipe = urb->pipe;
149         int             i, size = 0;
150         unsigned long   flags;
151         int             retval = 0;
152
153 #ifdef OHCI_VERBOSE_DEBUG
154         urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
155 #endif
156
157         /* every endpoint has a ed, locate and maybe (re)initialize it */
158         if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
159                 return -ENOMEM;
160
161         /* for the private part of the URB we need the number of TDs (size) */
162         switch (ed->type) {
163                 case PIPE_CONTROL:
164                         /* td_submit_urb() doesn't yet handle these */
165                         if (urb->transfer_buffer_length > 4096)
166                                 return -EMSGSIZE;
167
168                         /* 1 TD for setup, 1 for ACK, plus ... */
169                         size = 2;
170                         /* FALLTHROUGH */
171                 // case PIPE_INTERRUPT:
172                 // case PIPE_BULK:
173                 default:
174                         /* one TD for every 4096 Bytes (can be upto 8K) */
175                         size += urb->transfer_buffer_length / 4096;
176                         /* ... and for any remaining bytes ... */
177                         if ((urb->transfer_buffer_length % 4096) != 0)
178                                 size++;
179                         /* ... and maybe a zero length packet to wrap it up */
180                         if (size == 0)
181                                 size++;
182                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
183                                 && (urb->transfer_buffer_length
184                                         % usb_maxpacket (urb->dev, pipe,
185                                                 usb_pipeout (pipe))) == 0)
186                                 size++;
187                         break;
188                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
189                         size = urb->number_of_packets;
190                         break;
191         }
192
193         /* allocate the private part of the URB */
194         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
195                         mem_flags);
196         if (!urb_priv)
197                 return -ENOMEM;
198         INIT_LIST_HEAD (&urb_priv->pending);
199         urb_priv->length = size;
200         urb_priv->ed = ed;
201
202         /* allocate the TDs (deferring hash chain updates) */
203         for (i = 0; i < size; i++) {
204                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
205                 if (!urb_priv->td [i]) {
206                         urb_priv->length = i;
207                         urb_free_priv (ohci, urb_priv);
208                         return -ENOMEM;
209                 }
210         }
211
212         spin_lock_irqsave (&ohci->lock, flags);
213
214         /* don't submit to a dead HC */
215         if (!HCD_HW_ACCESSIBLE(hcd)) {
216                 retval = -ENODEV;
217                 goto fail;
218         }
219         if (!HC_IS_RUNNING(hcd->state)) {
220                 retval = -ENODEV;
221                 goto fail;
222         }
223         retval = usb_hcd_link_urb_to_ep(hcd, urb);
224         if (retval)
225                 goto fail;
226
227         /* schedule the ed if needed */
228         if (ed->state == ED_IDLE) {
229                 retval = ed_schedule (ohci, ed);
230                 if (retval < 0) {
231                         usb_hcd_unlink_urb_from_ep(hcd, urb);
232                         goto fail;
233                 }
234                 if (ed->type == PIPE_ISOCHRONOUS) {
235                         u16     frame = ohci_frame_no(ohci);
236
237                         /* delay a few frames before the first TD */
238                         frame += max_t (u16, 8, ed->interval);
239                         frame &= ~(ed->interval - 1);
240                         frame |= ed->branch;
241                         urb->start_frame = frame;
242
243                         /* yes, only URB_ISO_ASAP is supported, and
244                          * urb->start_frame is never used as input.
245                          */
246                 }
247         } else if (ed->type == PIPE_ISOCHRONOUS)
248                 urb->start_frame = ed->last_iso + ed->interval;
249
250         /* fill the TDs and link them to the ed; and
251          * enable that part of the schedule, if needed
252          * and update count of queued periodic urbs
253          */
254         urb->hcpriv = urb_priv;
255         td_submit_urb (ohci, urb);
256
257 fail:
258         if (retval)
259                 urb_free_priv (ohci, urb_priv);
260         spin_unlock_irqrestore (&ohci->lock, flags);
261         return retval;
262 }
263
264 /*
265  * decouple the URB from the HC queues (TDs, urb_priv).
266  * reporting is always done
267  * asynchronously, and we might be dealing with an urb that's
268  * partially transferred, or an ED with other urbs being unlinked.
269  */
270 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
271 {
272         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
273         unsigned long           flags;
274         int                     rc;
275
276 #ifdef OHCI_VERBOSE_DEBUG
277         urb_print(urb, "UNLINK", 1, status);
278 #endif
279
280         spin_lock_irqsave (&ohci->lock, flags);
281         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
282         if (rc) {
283                 ;       /* Do nothing */
284         } else if (HC_IS_RUNNING(hcd->state)) {
285                 urb_priv_t  *urb_priv;
286
287                 /* Unless an IRQ completed the unlink while it was being
288                  * handed to us, flag it for unlink and giveback, and force
289                  * some upcoming INTR_SF to call finish_unlinks()
290                  */
291                 urb_priv = urb->hcpriv;
292                 if (urb_priv) {
293                         if (urb_priv->ed->state == ED_OPER)
294                                 start_ed_unlink (ohci, urb_priv->ed);
295                 }
296         } else {
297                 /*
298                  * with HC dead, we won't respect hc queue pointers
299                  * any more ... just clean up every urb's memory.
300                  */
301                 if (urb->hcpriv)
302                         finish_urb(ohci, urb, status);
303         }
304         spin_unlock_irqrestore (&ohci->lock, flags);
305         return rc;
306 }
307
308 /*-------------------------------------------------------------------------*/
309
310 /* frees config/altsetting state for endpoints,
311  * including ED memory, dummy TD, and bulk/intr data toggle
312  */
313
314 static void
315 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
316 {
317         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
318         unsigned long           flags;
319         struct ed               *ed = ep->hcpriv;
320         unsigned                limit = 1000;
321
322         /* ASSERT:  any requests/urbs are being unlinked */
323         /* ASSERT:  nobody can be submitting urbs for this any more */
324
325         if (!ed)
326                 return;
327
328 rescan:
329         spin_lock_irqsave (&ohci->lock, flags);
330
331         if (!HC_IS_RUNNING (hcd->state)) {
332 sanitize:
333                 ed->state = ED_IDLE;
334                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
335                         ohci->eds_scheduled--;
336                 finish_unlinks (ohci, 0);
337         }
338
339         switch (ed->state) {
340         case ED_UNLINK:         /* wait for hw to finish? */
341                 /* major IRQ delivery trouble loses INTR_SF too... */
342                 if (limit-- == 0) {
343                         ohci_warn(ohci, "ED unlink timeout\n");
344                         if (quirk_zfmicro(ohci)) {
345                                 ohci_warn(ohci, "Attempting ZF TD recovery\n");
346                                 ohci->ed_to_check = ed;
347                                 ohci->zf_delay = 2;
348                         }
349                         goto sanitize;
350                 }
351                 spin_unlock_irqrestore (&ohci->lock, flags);
352                 schedule_timeout_uninterruptible(1);
353                 goto rescan;
354         case ED_IDLE:           /* fully unlinked */
355                 if (list_empty (&ed->td_list)) {
356                         td_free (ohci, ed->dummy);
357                         ed_free (ohci, ed);
358                         break;
359                 }
360                 /* else FALL THROUGH */
361         default:
362                 /* caller was supposed to have unlinked any requests;
363                  * that's not our job.  can't recover; must leak ed.
364                  */
365                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
366                         ed, ep->desc.bEndpointAddress, ed->state,
367                         list_empty (&ed->td_list) ? "" : " (has tds)");
368                 td_free (ohci, ed->dummy);
369                 break;
370         }
371         ep->hcpriv = NULL;
372         spin_unlock_irqrestore (&ohci->lock, flags);
373 }
374
375 static int ohci_get_frame (struct usb_hcd *hcd)
376 {
377         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
378
379         return ohci_frame_no(ohci);
380 }
381
382 static void ohci_usb_reset (struct ohci_hcd *ohci)
383 {
384         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
385         ohci->hc_control &= OHCI_CTRL_RWC;
386         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
387 }
388
389 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
390  * other cases where the next software may expect clean state from the
391  * "firmware".  this is bus-neutral, unlike shutdown() methods.
392  */
393 static void
394 ohci_shutdown (struct usb_hcd *hcd)
395 {
396         struct ohci_hcd *ohci;
397
398         ohci = hcd_to_ohci (hcd);
399         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
400         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
401
402         /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
403         ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
404                         OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
405                         OHCI_CTRL_RWC);
406         ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
407
408         /* flush the writes */
409         (void) ohci_readl (ohci, &ohci->regs->control);
410 }
411
412 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
413 {
414         return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
415                 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
416                         == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
417                 && !list_empty(&ed->td_list);
418 }
419
420 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
421  * an interrupt TD but neglects to add it to the donelist.  On systems with
422  * this chipset, we need to periodically check the state of the queues to look
423  * for such "lost" TDs.
424  */
425 static void unlink_watchdog_func(unsigned long _ohci)
426 {
427         unsigned long   flags;
428         unsigned        max;
429         unsigned        seen_count = 0;
430         unsigned        i;
431         struct ed       **seen = NULL;
432         struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
433
434         spin_lock_irqsave(&ohci->lock, flags);
435         max = ohci->eds_scheduled;
436         if (!max)
437                 goto done;
438
439         if (ohci->ed_to_check)
440                 goto out;
441
442         seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
443         if (!seen)
444                 goto out;
445
446         for (i = 0; i < NUM_INTS; i++) {
447                 struct ed       *ed = ohci->periodic[i];
448
449                 while (ed) {
450                         unsigned        temp;
451
452                         /* scan this branch of the periodic schedule tree */
453                         for (temp = 0; temp < seen_count; temp++) {
454                                 if (seen[temp] == ed) {
455                                         /* we've checked it and what's after */
456                                         ed = NULL;
457                                         break;
458                                 }
459                         }
460                         if (!ed)
461                                 break;
462                         seen[seen_count++] = ed;
463                         if (!check_ed(ohci, ed)) {
464                                 ed = ed->ed_next;
465                                 continue;
466                         }
467
468                         /* HC's TD list is empty, but HCD sees at least one
469                          * TD that's not been sent through the donelist.
470                          */
471                         ohci->ed_to_check = ed;
472                         ohci->zf_delay = 2;
473
474                         /* The HC may wait until the next frame to report the
475                          * TD as done through the donelist and INTR_WDH.  (We
476                          * just *assume* it's not a multi-TD interrupt URB;
477                          * those could defer the IRQ more than one frame, using
478                          * DI...)  Check again after the next INTR_SF.
479                          */
480                         ohci_writel(ohci, OHCI_INTR_SF,
481                                         &ohci->regs->intrstatus);
482                         ohci_writel(ohci, OHCI_INTR_SF,
483                                         &ohci->regs->intrenable);
484
485                         /* flush those writes */
486                         (void) ohci_readl(ohci, &ohci->regs->control);
487
488                         goto out;
489                 }
490         }
491 out:
492         kfree(seen);
493         if (ohci->eds_scheduled)
494                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
495 done:
496         spin_unlock_irqrestore(&ohci->lock, flags);
497 }
498
499 /*-------------------------------------------------------------------------*
500  * HC functions
501  *-------------------------------------------------------------------------*/
502
503 /* init memory, and kick BIOS/SMM off */
504
505 static int ohci_init (struct ohci_hcd *ohci)
506 {
507         int ret;
508         struct usb_hcd *hcd = ohci_to_hcd(ohci);
509
510         if (distrust_firmware)
511                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
512
513         disable (ohci);
514         ohci->regs = hcd->regs;
515
516         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
517          * was never needed for most non-PCI systems ... remove the code?
518          */
519
520 #ifndef IR_DISABLE
521         /* SMM owns the HC?  not for long! */
522         if (!no_handshake && ohci_readl (ohci,
523                                         &ohci->regs->control) & OHCI_CTRL_IR) {
524                 u32 temp;
525
526                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
527
528                 /* this timeout is arbitrary.  we make it long, so systems
529                  * depending on usb keyboards may be usable even if the
530                  * BIOS/SMM code seems pretty broken.
531                  */
532                 temp = 500;     /* arbitrary: five seconds */
533
534                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
535                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
536                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
537                         msleep (10);
538                         if (--temp == 0) {
539                                 ohci_err (ohci, "USB HC takeover failed!"
540                                         "  (BIOS/SMM bug)\n");
541                                 return -EBUSY;
542                         }
543                 }
544                 ohci_usb_reset (ohci);
545         }
546 #endif
547
548         /* Disable HC interrupts */
549         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
550
551         /* flush the writes, and save key bits like RWC */
552         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
553                 ohci->hc_control |= OHCI_CTRL_RWC;
554
555         /* Read the number of ports unless overridden */
556         if (ohci->num_ports == 0)
557                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
558
559         if (ohci->hcca)
560                 return 0;
561
562         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
563                         sizeof *ohci->hcca, &ohci->hcca_dma, 0);
564         if (!ohci->hcca)
565                 return -ENOMEM;
566
567         if ((ret = ohci_mem_init (ohci)) < 0)
568                 ohci_stop (hcd);
569         else {
570                 create_debug_files (ohci);
571         }
572
573         return ret;
574 }
575
576 /*-------------------------------------------------------------------------*/
577
578 /* Start an OHCI controller, set the BUS operational
579  * resets USB and controller
580  * enable interrupts
581  */
582 static int ohci_run (struct ohci_hcd *ohci)
583 {
584         u32                     mask, val;
585         int                     first = ohci->fminterval == 0;
586         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
587
588         disable (ohci);
589
590         /* boot firmware should have set this up (5.1.1.3.1) */
591         if (first) {
592
593                 val = ohci_readl (ohci, &ohci->regs->fminterval);
594                 ohci->fminterval = val & 0x3fff;
595                 if (ohci->fminterval != FI)
596                         ohci_dbg (ohci, "fminterval delta %d\n",
597                                 ohci->fminterval - FI);
598                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
599                 /* also: power/overcurrent flags in roothub.a */
600         }
601
602         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
603          * to be checked in case boot firmware (BIOS/SMM/...) has set up
604          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
605          * If the bus glue detected wakeup capability then it should
606          * already be enabled; if so we'll just enable it again.
607          */
608         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
609                 device_set_wakeup_capable(hcd->self.controller, 1);
610
611         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
612         case OHCI_USB_OPER:
613                 val = 0;
614                 break;
615         case OHCI_USB_SUSPEND:
616         case OHCI_USB_RESUME:
617                 ohci->hc_control &= OHCI_CTRL_RWC;
618                 ohci->hc_control |= OHCI_USB_RESUME;
619                 val = 10 /* msec wait */;
620                 break;
621         // case OHCI_USB_RESET:
622         default:
623                 ohci->hc_control &= OHCI_CTRL_RWC;
624                 ohci->hc_control |= OHCI_USB_RESET;
625                 val = 50 /* msec wait */;
626                 break;
627         }
628         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
629         // flush the writes
630         (void) ohci_readl (ohci, &ohci->regs->control);
631         msleep(val);
632
633         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
634
635         /* 2msec timelimit here means no irqs/preempt */
636         spin_lock_irq (&ohci->lock);
637
638 retry:
639         /* HC Reset requires max 10 us delay */
640         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
641         val = 30;       /* ... allow extra time */
642         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
643                 if (--val == 0) {
644                         spin_unlock_irq (&ohci->lock);
645                         ohci_err (ohci, "USB HC reset timed out!\n");
646                         return -1;
647                 }
648                 udelay (1);
649         }
650
651         /* now we're in the SUSPEND state ... must go OPERATIONAL
652          * within 2msec else HC enters RESUME
653          *
654          * ... but some hardware won't init fmInterval "by the book"
655          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
656          * this if we write fmInterval after we're OPERATIONAL.
657          * Unclear about ALi, ServerWorks, and others ... this could
658          * easily be a longstanding bug in chip init on Linux.
659          */
660         if (ohci->flags & OHCI_QUIRK_INITRESET) {
661                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
662                 // flush those writes
663                 (void) ohci_readl (ohci, &ohci->regs->control);
664         }
665
666         /* Tell the controller where the control and bulk lists are
667          * The lists are empty now. */
668         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
669         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
670
671         /* a reset clears this */
672         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
673
674         periodic_reinit (ohci);
675
676         /* some OHCI implementations are finicky about how they init.
677          * bogus values here mean not even enumeration could work.
678          */
679         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
680                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
681                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
682                         ohci->flags |= OHCI_QUIRK_INITRESET;
683                         ohci_dbg (ohci, "enabling initreset quirk\n");
684                         goto retry;
685                 }
686                 spin_unlock_irq (&ohci->lock);
687                 ohci_err (ohci, "init err (%08x %04x)\n",
688                         ohci_readl (ohci, &ohci->regs->fminterval),
689                         ohci_readl (ohci, &ohci->regs->periodicstart));
690                 return -EOVERFLOW;
691         }
692
693         /* use rhsc irqs after khubd is fully initialized */
694         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
695         hcd->uses_new_polling = 1;
696
697         /* start controller operations */
698         ohci->hc_control &= OHCI_CTRL_RWC;
699         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
700         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
701         hcd->state = HC_STATE_RUNNING;
702
703         /* wake on ConnectStatusChange, matching external hubs */
704         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
705
706         /* Choose the interrupts we care about now, others later on demand */
707         mask = OHCI_INTR_INIT;
708         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
709         ohci_writel (ohci, mask, &ohci->regs->intrenable);
710
711         /* handle root hub init quirks ... */
712         val = roothub_a (ohci);
713         val &= ~(RH_A_PSM | RH_A_OCPM);
714         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
715                 /* NSC 87560 and maybe others */
716                 val |= RH_A_NOCP;
717                 val &= ~(RH_A_POTPGT | RH_A_NPS);
718                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
719         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
720                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
721                 /* hub power always on; required for AMD-756 and some
722                  * Mac platforms.  ganged overcurrent reporting, if any.
723                  */
724                 val |= RH_A_NPS;
725                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
726         }
727         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
728         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
729                                                 &ohci->regs->roothub.b);
730         // flush those writes
731         (void) ohci_readl (ohci, &ohci->regs->control);
732
733         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
734         spin_unlock_irq (&ohci->lock);
735
736         // POTPGT delay is bits 24-31, in 2 ms units.
737         mdelay ((val >> 23) & 0x1fe);
738         hcd->state = HC_STATE_RUNNING;
739
740         if (quirk_zfmicro(ohci)) {
741                 /* Create timer to watch for bad queue state on ZF Micro */
742                 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
743                                 (unsigned long) ohci);
744
745                 ohci->eds_scheduled = 0;
746                 ohci->ed_to_check = NULL;
747         }
748
749         ohci_dump (ohci, 1);
750
751         return 0;
752 }
753
754 /*-------------------------------------------------------------------------*/
755
756 /* an interrupt happens */
757
758 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
759 {
760         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
761         struct ohci_regs __iomem *regs = ohci->regs;
762         int                     ints;
763
764         /* Read interrupt status (and flush pending writes).  We ignore the
765          * optimization of checking the LSB of hcca->done_head; it doesn't
766          * work on all systems (edge triggering for OHCI can be a factor).
767          */
768         ints = ohci_readl(ohci, &regs->intrstatus);
769
770         /* Check for an all 1's result which is a typical consequence
771          * of dead, unclocked, or unplugged (CardBus...) devices
772          */
773         if (ints == ~(u32)0) {
774                 disable (ohci);
775                 ohci_dbg (ohci, "device removed!\n");
776                 return IRQ_HANDLED;
777         }
778
779         /* We only care about interrupts that are enabled */
780         ints &= ohci_readl(ohci, &regs->intrenable);
781
782         /* interrupt for some other device? */
783         if (ints == 0)
784                 return IRQ_NOTMINE;
785
786         if (ints & OHCI_INTR_UE) {
787                 // e.g. due to PCI Master/Target Abort
788                 if (quirk_nec(ohci)) {
789                         /* Workaround for a silicon bug in some NEC chips used
790                          * in Apple's PowerBooks. Adapted from Darwin code.
791                          */
792                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
793
794                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
795
796                         schedule_work (&ohci->nec_work);
797                 } else {
798                         disable (ohci);
799                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
800                 }
801
802                 ohci_dump (ohci, 1);
803                 ohci_usb_reset (ohci);
804         }
805
806         if (ints & OHCI_INTR_RHSC) {
807                 ohci_vdbg(ohci, "rhsc\n");
808                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
809                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
810                                 &regs->intrstatus);
811
812                 /* NOTE: Vendors didn't always make the same implementation
813                  * choices for RHSC.  Many followed the spec; RHSC triggers
814                  * on an edge, like setting and maybe clearing a port status
815                  * change bit.  With others it's level-triggered, active
816                  * until khubd clears all the port status change bits.  We'll
817                  * always disable it here and rely on polling until khubd
818                  * re-enables it.
819                  */
820                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
821                 usb_hcd_poll_rh_status(hcd);
822         }
823
824         /* For connect and disconnect events, we expect the controller
825          * to turn on RHSC along with RD.  But for remote wakeup events
826          * this might not happen.
827          */
828         else if (ints & OHCI_INTR_RD) {
829                 ohci_vdbg(ohci, "resume detect\n");
830                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
831                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
832                 if (ohci->autostop) {
833                         spin_lock (&ohci->lock);
834                         ohci_rh_resume (ohci);
835                         spin_unlock (&ohci->lock);
836                 } else
837                         usb_hcd_resume_root_hub(hcd);
838         }
839
840         if (ints & OHCI_INTR_WDH) {
841                 spin_lock (&ohci->lock);
842                 dl_done_list (ohci);
843                 spin_unlock (&ohci->lock);
844         }
845
846         if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
847                 spin_lock(&ohci->lock);
848                 if (ohci->ed_to_check) {
849                         struct ed *ed = ohci->ed_to_check;
850
851                         if (check_ed(ohci, ed)) {
852                                 /* HC thinks the TD list is empty; HCD knows
853                                  * at least one TD is outstanding
854                                  */
855                                 if (--ohci->zf_delay == 0) {
856                                         struct td *td = list_entry(
857                                                 ed->td_list.next,
858                                                 struct td, td_list);
859                                         ohci_warn(ohci,
860                                                   "Reclaiming orphan TD %p\n",
861                                                   td);
862                                         takeback_td(ohci, td);
863                                         ohci->ed_to_check = NULL;
864                                 }
865                         } else
866                                 ohci->ed_to_check = NULL;
867                 }
868                 spin_unlock(&ohci->lock);
869         }
870
871         /* could track INTR_SO to reduce available PCI/... bandwidth */
872
873         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
874          * when there's still unlinking to be done (next frame).
875          */
876         spin_lock (&ohci->lock);
877         if (ohci->ed_rm_list)
878                 finish_unlinks (ohci, ohci_frame_no(ohci));
879         if ((ints & OHCI_INTR_SF) != 0
880                         && !ohci->ed_rm_list
881                         && !ohci->ed_to_check
882                         && HC_IS_RUNNING(hcd->state))
883                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
884         spin_unlock (&ohci->lock);
885
886         if (HC_IS_RUNNING(hcd->state)) {
887                 ohci_writel (ohci, ints, &regs->intrstatus);
888                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
889                 // flush those writes
890                 (void) ohci_readl (ohci, &ohci->regs->control);
891         }
892
893         return IRQ_HANDLED;
894 }
895
896 /*-------------------------------------------------------------------------*/
897
898 static void ohci_stop (struct usb_hcd *hcd)
899 {
900         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
901
902         ohci_dump (ohci, 1);
903
904         if (quirk_nec(ohci))
905                 flush_work_sync(&ohci->nec_work);
906
907         ohci_usb_reset (ohci);
908         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
909         free_irq(hcd->irq, hcd);
910         hcd->irq = -1;
911
912         if (quirk_zfmicro(ohci))
913                 del_timer(&ohci->unlink_watchdog);
914         if (quirk_amdiso(ohci))
915                 amd_iso_dev_put();
916
917         remove_debug_files (ohci);
918         ohci_mem_cleanup (ohci);
919         if (ohci->hcca) {
920                 dma_free_coherent (hcd->self.controller,
921                                 sizeof *ohci->hcca,
922                                 ohci->hcca, ohci->hcca_dma);
923                 ohci->hcca = NULL;
924                 ohci->hcca_dma = 0;
925         }
926 }
927
928 /*-------------------------------------------------------------------------*/
929
930 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
931
932 /* must not be called from interrupt context */
933 static int ohci_restart (struct ohci_hcd *ohci)
934 {
935         int temp;
936         int i;
937         struct urb_priv *priv;
938
939         spin_lock_irq(&ohci->lock);
940         disable (ohci);
941
942         /* Recycle any "live" eds/tds (and urbs). */
943         if (!list_empty (&ohci->pending))
944                 ohci_dbg(ohci, "abort schedule...\n");
945         list_for_each_entry (priv, &ohci->pending, pending) {
946                 struct urb      *urb = priv->td[0]->urb;
947                 struct ed       *ed = priv->ed;
948
949                 switch (ed->state) {
950                 case ED_OPER:
951                         ed->state = ED_UNLINK;
952                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
953                         ed_deschedule (ohci, ed);
954
955                         ed->ed_next = ohci->ed_rm_list;
956                         ed->ed_prev = NULL;
957                         ohci->ed_rm_list = ed;
958                         /* FALLTHROUGH */
959                 case ED_UNLINK:
960                         break;
961                 default:
962                         ohci_dbg(ohci, "bogus ed %p state %d\n",
963                                         ed, ed->state);
964                 }
965
966                 if (!urb->unlinked)
967                         urb->unlinked = -ESHUTDOWN;
968         }
969         finish_unlinks (ohci, 0);
970         spin_unlock_irq(&ohci->lock);
971
972         /* paranoia, in case that didn't work: */
973
974         /* empty the interrupt branches */
975         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
976         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
977
978         /* no EDs to remove */
979         ohci->ed_rm_list = NULL;
980
981         /* empty control and bulk lists */
982         ohci->ed_controltail = NULL;
983         ohci->ed_bulktail    = NULL;
984
985         if ((temp = ohci_run (ohci)) < 0) {
986                 ohci_err (ohci, "can't restart, %d\n", temp);
987                 return temp;
988         }
989         ohci_dbg(ohci, "restart complete\n");
990         return 0;
991 }
992
993 #endif
994
995 /*-------------------------------------------------------------------------*/
996
997 MODULE_AUTHOR (DRIVER_AUTHOR);
998 MODULE_DESCRIPTION(DRIVER_DESC);
999 MODULE_LICENSE ("GPL");
1000
1001 #ifdef CONFIG_PCI
1002 #include "ohci-pci.c"
1003 #define PCI_DRIVER              ohci_pci_driver
1004 #endif
1005
1006 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1007 #include "ohci-sa1111.c"
1008 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1009 #endif
1010
1011 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1012 #include "ohci-s3c2410.c"
1013 #define PLATFORM_DRIVER         ohci_hcd_s3c2410_driver
1014 #endif
1015
1016 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1017 #include "ohci-omap.c"
1018 #define OMAP1_PLATFORM_DRIVER   ohci_hcd_omap_driver
1019 #endif
1020
1021 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1022 #include "ohci-omap3.c"
1023 #define OMAP3_PLATFORM_DRIVER   ohci_hcd_omap3_driver
1024 #endif
1025
1026 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1027 #include "ohci-pxa27x.c"
1028 #define PLATFORM_DRIVER         ohci_hcd_pxa27x_driver
1029 #endif
1030
1031 #ifdef CONFIG_ARCH_EP93XX
1032 #include "ohci-ep93xx.c"
1033 #define PLATFORM_DRIVER         ohci_hcd_ep93xx_driver
1034 #endif
1035
1036 #ifdef CONFIG_MIPS_ALCHEMY
1037 #include "ohci-au1xxx.c"
1038 #define PLATFORM_DRIVER         ohci_hcd_au1xxx_driver
1039 #endif
1040
1041 #ifdef CONFIG_PNX8550
1042 #include "ohci-pnx8550.c"
1043 #define PLATFORM_DRIVER         ohci_hcd_pnx8550_driver
1044 #endif
1045
1046 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1047 #include "ohci-ppc-soc.c"
1048 #define PLATFORM_DRIVER         ohci_hcd_ppc_soc_driver
1049 #endif
1050
1051 #ifdef CONFIG_ARCH_AT91
1052 #include "ohci-at91.c"
1053 #define PLATFORM_DRIVER         ohci_hcd_at91_driver
1054 #endif
1055
1056 #ifdef CONFIG_ARCH_PNX4008
1057 #include "ohci-pnx4008.c"
1058 #define PLATFORM_DRIVER         usb_hcd_pnx4008_driver
1059 #endif
1060
1061 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1062 #include "ohci-da8xx.c"
1063 #define PLATFORM_DRIVER         ohci_hcd_da8xx_driver
1064 #endif
1065
1066 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1067     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1068     defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1069     defined(CONFIG_CPU_SUBTYPE_SH7786)
1070 #include "ohci-sh.c"
1071 #define PLATFORM_DRIVER         ohci_hcd_sh_driver
1072 #endif
1073
1074
1075 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1076 #include "ohci-ppc-of.c"
1077 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1078 #endif
1079
1080 #ifdef CONFIG_PLAT_SPEAR
1081 #include "ohci-spear.c"
1082 #define PLATFORM_DRIVER         spear_ohci_hcd_driver
1083 #endif
1084
1085 #ifdef CONFIG_PPC_PS3
1086 #include "ohci-ps3.c"
1087 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1088 #endif
1089
1090 #ifdef CONFIG_USB_OHCI_HCD_SSB
1091 #include "ohci-ssb.c"
1092 #define SSB_OHCI_DRIVER         ssb_ohci_driver
1093 #endif
1094
1095 #ifdef CONFIG_MFD_SM501
1096 #include "ohci-sm501.c"
1097 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1098 #endif
1099
1100 #ifdef CONFIG_MFD_TC6393XB
1101 #include "ohci-tmio.c"
1102 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1103 #endif
1104
1105 #ifdef CONFIG_MACH_JZ4740
1106 #include "ohci-jz4740.c"
1107 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1108 #endif
1109
1110 #ifdef CONFIG_USB_OCTEON_OHCI
1111 #include "ohci-octeon.c"
1112 #define PLATFORM_DRIVER         ohci_octeon_driver
1113 #endif
1114
1115 #ifdef CONFIG_USB_CNS3XXX_OHCI
1116 #include "ohci-cns3xxx.c"
1117 #define PLATFORM_DRIVER         ohci_hcd_cns3xxx_driver
1118 #endif
1119
1120 #if     !defined(PCI_DRIVER) &&         \
1121         !defined(PLATFORM_DRIVER) &&    \
1122         !defined(OMAP1_PLATFORM_DRIVER) &&      \
1123         !defined(OMAP3_PLATFORM_DRIVER) &&      \
1124         !defined(OF_PLATFORM_DRIVER) && \
1125         !defined(SA1111_DRIVER) &&      \
1126         !defined(PS3_SYSTEM_BUS_DRIVER) && \
1127         !defined(SM501_OHCI_DRIVER) && \
1128         !defined(TMIO_OHCI_DRIVER) && \
1129         !defined(SSB_OHCI_DRIVER)
1130 #error "missing bus glue for ohci-hcd"
1131 #endif
1132
1133 static int __init ohci_hcd_mod_init(void)
1134 {
1135         int retval = 0;
1136
1137         if (usb_disabled())
1138                 return -ENODEV;
1139
1140         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1141         pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1142                 sizeof (struct ed), sizeof (struct td));
1143         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1144
1145 #ifdef DEBUG
1146         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1147         if (!ohci_debug_root) {
1148                 retval = -ENOENT;
1149                 goto error_debug;
1150         }
1151 #endif
1152
1153 #ifdef PS3_SYSTEM_BUS_DRIVER
1154         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1155         if (retval < 0)
1156                 goto error_ps3;
1157 #endif
1158
1159 #ifdef PLATFORM_DRIVER
1160         retval = platform_driver_register(&PLATFORM_DRIVER);
1161         if (retval < 0)
1162                 goto error_platform;
1163 #endif
1164
1165 #ifdef OMAP1_PLATFORM_DRIVER
1166         retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1167         if (retval < 0)
1168                 goto error_omap1_platform;
1169 #endif
1170
1171 #ifdef OMAP3_PLATFORM_DRIVER
1172         retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1173         if (retval < 0)
1174                 goto error_omap3_platform;
1175 #endif
1176
1177 #ifdef OF_PLATFORM_DRIVER
1178         retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1179         if (retval < 0)
1180                 goto error_of_platform;
1181 #endif
1182
1183 #ifdef SA1111_DRIVER
1184         retval = sa1111_driver_register(&SA1111_DRIVER);
1185         if (retval < 0)
1186                 goto error_sa1111;
1187 #endif
1188
1189 #ifdef PCI_DRIVER
1190         retval = pci_register_driver(&PCI_DRIVER);
1191         if (retval < 0)
1192                 goto error_pci;
1193 #endif
1194
1195 #ifdef SSB_OHCI_DRIVER
1196         retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1197         if (retval)
1198                 goto error_ssb;
1199 #endif
1200
1201 #ifdef SM501_OHCI_DRIVER
1202         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1203         if (retval < 0)
1204                 goto error_sm501;
1205 #endif
1206
1207 #ifdef TMIO_OHCI_DRIVER
1208         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1209         if (retval < 0)
1210                 goto error_tmio;
1211 #endif
1212
1213         return retval;
1214
1215         /* Error path */
1216 #ifdef TMIO_OHCI_DRIVER
1217         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1218  error_tmio:
1219 #endif
1220 #ifdef SM501_OHCI_DRIVER
1221         platform_driver_unregister(&SM501_OHCI_DRIVER);
1222  error_sm501:
1223 #endif
1224 #ifdef SSB_OHCI_DRIVER
1225         ssb_driver_unregister(&SSB_OHCI_DRIVER);
1226  error_ssb:
1227 #endif
1228 #ifdef PCI_DRIVER
1229         pci_unregister_driver(&PCI_DRIVER);
1230  error_pci:
1231 #endif
1232 #ifdef SA1111_DRIVER
1233         sa1111_driver_unregister(&SA1111_DRIVER);
1234  error_sa1111:
1235 #endif
1236 #ifdef OF_PLATFORM_DRIVER
1237         of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1238  error_of_platform:
1239 #endif
1240 #ifdef PLATFORM_DRIVER
1241         platform_driver_unregister(&PLATFORM_DRIVER);
1242  error_platform:
1243 #endif
1244 #ifdef OMAP1_PLATFORM_DRIVER
1245         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1246  error_omap1_platform:
1247 #endif
1248 #ifdef OMAP3_PLATFORM_DRIVER
1249         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1250  error_omap3_platform:
1251 #endif
1252 #ifdef PS3_SYSTEM_BUS_DRIVER
1253         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1254  error_ps3:
1255 #endif
1256 #ifdef DEBUG
1257         debugfs_remove(ohci_debug_root);
1258         ohci_debug_root = NULL;
1259  error_debug:
1260 #endif
1261
1262         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1263         return retval;
1264 }
1265 module_init(ohci_hcd_mod_init);
1266
1267 static void __exit ohci_hcd_mod_exit(void)
1268 {
1269 #ifdef TMIO_OHCI_DRIVER
1270         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1271 #endif
1272 #ifdef SM501_OHCI_DRIVER
1273         platform_driver_unregister(&SM501_OHCI_DRIVER);
1274 #endif
1275 #ifdef SSB_OHCI_DRIVER
1276         ssb_driver_unregister(&SSB_OHCI_DRIVER);
1277 #endif
1278 #ifdef PCI_DRIVER
1279         pci_unregister_driver(&PCI_DRIVER);
1280 #endif
1281 #ifdef SA1111_DRIVER
1282         sa1111_driver_unregister(&SA1111_DRIVER);
1283 #endif
1284 #ifdef OF_PLATFORM_DRIVER
1285         of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1286 #endif
1287 #ifdef PLATFORM_DRIVER
1288         platform_driver_unregister(&PLATFORM_DRIVER);
1289 #endif
1290 #ifdef OMAP3_PLATFORM_DRIVER
1291         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1292 #endif
1293 #ifdef PS3_SYSTEM_BUS_DRIVER
1294         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1295 #endif
1296 #ifdef DEBUG
1297         debugfs_remove(ohci_debug_root);
1298 #endif
1299         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1300 }
1301 module_exit(ohci_hcd_mod_exit);
1302