drivers: resolve compilation time warnings
[linux-2.6.git] / drivers / usb / host / ehci-tegra.c
1 /*
2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2009 - 2012 NVIDIA Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/platform_data/tegra_usb.h>
22 #include <linux/irq.h>
23 #include <linux/usb/otg.h>
24 #include <mach/usb_phy.h>
25 #include <mach/iomap.h>
26
27 #define TEGRA_USB_PORTSC_PHCD           (1 << 23)
28
29 #define TEGRA_USB_SUSP_CTRL_OFFSET      0x400
30 #define TEGRA_USB_SUSP_CLR                      (1 << 5)
31 #define TEGRA_USB_PHY_CLK_VALID                 (1 << 7)
32 #define TEGRA_USB_SRT                           (1 << 25)
33 #define TEGRA_USB_PHY_CLK_VALID_INT_ENB         (1 << 9)
34 #define TEGRA_USB_PHY_CLK_VALID_INT_STS         (1 << 8)
35
36 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
37 #define TEGRA_USB_PORTSC1_OFFSET        0x184
38 #else
39 #define TEGRA_USB_PORTSC1_OFFSET        0x174
40 #endif
41 #define TEGRA_USB_PORTSC1_WKCN                  (1 << 20)
42
43 #define TEGRA_LVL2_CLK_GATE_OVRB        0xfc
44 #define TEGRA_USB2_CLK_OVR_ON                   (1 << 10)
45
46 #define TEGRA_USB_DMA_ALIGN 32
47
48 #define STS_SRI (1<<7)  /*      SOF Recieved    */
49
50 #define HOSTPC_REG_OFFSET               0x1b4
51
52 #define HOSTPC1_DEVLC_STS               (1 << 28)
53 #define HOSTPC1_DEVLC_PTS(x)            (((x) & 0x7) << 29)
54
55 #define USB1_PREFETCH_ID               6
56 #define USB2_PREFETCH_ID               18
57 #define USB3_PREFETCH_ID               17
58
59 struct tegra_ehci_hcd {
60         struct ehci_hcd *ehci;
61         struct tegra_usb_phy *phy;
62         struct clk *clk;
63         struct clk *emc_clk;
64         struct clk *sclk_clk;
65         struct otg_transceiver *transceiver;
66         int host_resumed;
67         int bus_suspended;
68         int port_resuming;
69         int power_down_on_bus_suspend;
70         int default_enable;
71         enum tegra_usb_phy_port_speed port_speed;
72         struct work_struct clk_timer_work;
73         struct timer_list clk_timer;
74         bool clock_enabled;
75         bool timer_event;
76         struct mutex tegra_ehci_hcd_mutex;
77         unsigned int irq;
78         bool bus_suspended_fail;
79 };
80
81 static void tegra_ehci_power_up(struct usb_hcd *hcd, bool is_dpd)
82 {
83         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
84
85         if (!tegra->default_enable)
86                 clk_enable(tegra->clk);
87         tegra_usb_phy_power_on(tegra->phy, is_dpd);
88         tegra->host_resumed = 1;
89 }
90
91 static void tegra_ehci_power_down(struct usb_hcd *hcd, bool is_dpd)
92 {
93         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
94
95         tegra->host_resumed = 0;
96         tegra_usb_phy_power_off(tegra->phy, is_dpd);
97         if (!tegra->default_enable)
98                 clk_disable(tegra->clk);
99 }
100
101 static int tegra_ehci_internal_port_reset(
102         struct ehci_hcd *ehci,
103         u32 __iomem     *portsc_reg
104 )
105 {
106         u32             temp;
107         unsigned long   flags;
108         int             retval = 0;
109         int             i, tries;
110         u32             saved_usbintr;
111
112         spin_lock_irqsave(&ehci->lock, flags);
113         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
114         /* disable USB interrupt */
115         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
116         spin_unlock_irqrestore(&ehci->lock, flags);
117
118         /*
119          * Here we have to do Port Reset at most twice for
120          * Port Enable bit to be set.
121          */
122         for (i = 0; i < 2; i++) {
123                 temp = ehci_readl(ehci, portsc_reg);
124                 temp |= PORT_RESET;
125                 ehci_writel(ehci, temp, portsc_reg);
126                 mdelay(10);
127                 temp &= ~PORT_RESET;
128                 ehci_writel(ehci, temp, portsc_reg);
129                 mdelay(1);
130                 tries = 100;
131                 do {
132                         mdelay(1);
133                         /*
134                          * Up to this point, Port Enable bit is
135                          * expected to be set after 2 ms waiting.
136                          * USB1 usually takes extra 45 ms, for safety,
137                          * we take 100 ms as timeout.
138                          */
139                         temp = ehci_readl(ehci, portsc_reg);
140                 } while (!(temp & PORT_PE) && tries--);
141                 if (temp & PORT_PE)
142                         break;
143         }
144         if (i == 2)
145                 retval = -ETIMEDOUT;
146
147         /*
148          * Clear Connect Status Change bit if it's set.
149          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
150          */
151         if (temp & PORT_CSC)
152                 ehci_writel(ehci, PORT_CSC, portsc_reg);
153
154         /*
155          * Write to clear any interrupt status bits that might be set
156          * during port reset.
157          */
158         temp = ehci_readl(ehci, &ehci->regs->status);
159         ehci_writel(ehci, temp, &ehci->regs->status);
160
161         /* restore original interrupt enable bits */
162         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
163         return retval;
164 }
165
166 static irqreturn_t tegra_ehci_irq (struct usb_hcd *hcd)
167 {
168         struct ehci_hcd *ehci = hcd_to_ehci (hcd);
169         struct ehci_regs __iomem *hw = ehci->regs;
170         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
171         u32 val;
172         irqreturn_t irq_status;
173         bool pmc_remote_wakeup = false;
174
175         /* Fence read for coherency of AHB master intiated writes */
176         if (tegra->phy->instance == 0)
177                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
178         else if (tegra->phy->instance == 1)
179                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
180         else if (tegra->phy->instance == 2)
181                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
182
183         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
184                 (tegra->ehci->has_hostpc)) {
185                 /* check if there is any remote wake event */
186                 if (tegra_usb_phy_is_remotewake_detected(tegra->phy)) {
187                         pmc_remote_wakeup = true;
188                         spin_lock (&ehci->lock);
189                         usb_hcd_resume_root_hub(hcd);
190                         spin_unlock (&ehci->lock);
191                 }
192         }
193         if (tegra->phy->hotplug) {
194                 spin_lock(&ehci->lock);
195                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
196                 if ((val  & TEGRA_USB_PHY_CLK_VALID_INT_STS)) {
197                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB |
198                                 TEGRA_USB_PHY_CLK_VALID_INT_STS;
199                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
200
201                         val = readl(&hw->status);
202                         if (!(val  & STS_PCD)) {
203                                 spin_unlock(&ehci->lock);
204                                 return 0;
205                         }
206                         val = readl(hcd->regs + TEGRA_USB_PORTSC1_OFFSET);
207                         val &= ~(TEGRA_USB_PORTSC1_WKCN | PORT_RWC_BITS);
208                         writel(val , (hcd->regs + TEGRA_USB_PORTSC1_OFFSET));
209                 }
210                 spin_unlock(&ehci->lock);
211         }
212
213         irq_status = ehci_irq(hcd);
214
215         if (pmc_remote_wakeup) {
216                 ehci->controller_remote_wakeup = false;
217         }
218
219         if (ehci->controller_remote_wakeup) {
220                 ehci->controller_remote_wakeup = false;
221                 /* disable interrupts */
222                 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
223                 tegra_usb_phy_preresume(tegra->phy, true);
224                 tegra->port_resuming = 1;
225         }
226         return irq_status;
227 }
228
229 static int tegra_ehci_hub_control(
230         struct usb_hcd  *hcd,
231         u16             typeReq,
232         u16             wValue,
233         u16             wIndex,
234         char            *buf,
235         u16             wLength
236 )
237 {
238         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
239         int             ports = HCS_N_PORTS(ehci->hcs_params);
240         u32             temp, status, cmd_run;
241         u32 __iomem     *status_reg;
242         u32             usbsts_reg;
243
244         unsigned long   flags;
245         int             retval = 0;
246         unsigned        selector;
247         struct          tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
248         bool            hsic = false;
249
250         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
251         if (!tegra->host_resumed) {
252                 if (buf)
253                         memset (buf, 0, wLength);
254                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
255                 return retval;
256         }
257
258         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
259
260         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
261
262         spin_lock_irqsave(&ehci->lock, flags);
263
264         /*
265          * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
266          * that are write on clear, by writing back the register read value, so
267          * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
268          */
269         if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
270                 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
271                 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
272                 goto done;
273         } else if (typeReq == GetPortStatus) {
274                 temp = ehci_readl(ehci, status_reg);
275                 /* check port is in resume state */
276                 if (tegra->port_resuming) {
277                         int delay = ehci->reset_done[wIndex-1] - jiffies;
278                         /* Sometimes it seems we get called too soon... In that case, wait.*/
279                         if (delay > 0) {
280                                 ehci_dbg(ehci, "GetPortStatus called too soon, waiting %dms...\n", delay);
281                                 mdelay(jiffies_to_msecs(delay));
282                         }
283                         /* Ensure the port PORT_SUSPEND and PORT_RESUME has cleared */
284                         if (handshake(ehci, status_reg, (PORT_SUSPEND | PORT_RESUME), 0, 25000)) {
285                                 pr_err("%s: timeout waiting for SUSPEND to clear\n", __func__);
286                         }
287                         tegra->port_resuming = 0;
288                         tegra_usb_phy_postresume(tegra->phy, false);
289                         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
290                                 ehci->command |= CMD_RUN;
291                                 cmd_run = ehci_readl(ehci, &ehci->regs->command);
292                                 cmd_run |= CMD_RUN;
293                                 /*
294                                  * ehci run bit is disabled to avoid SOF.
295                                  * 2LS WAR is executed by now enable the run bit.
296                                  */
297                                 ehci_writel(ehci, cmd_run, &ehci->regs->command);
298                                 /* Now we can safely re-enable irqs */
299                                 ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
300                         }
301                 }
302
303         } else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
304                 temp = ehci_readl(ehci, status_reg);
305                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
306                         retval = -EPIPE;
307                         goto done;
308                 }
309
310                 temp &= ~PORT_WKCONN_E;
311                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
312                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
313
314                 /* Need a 4ms delay before the controller goes to suspend */
315                 mdelay(4);
316
317                 /*
318                  * If a transaction is in progress, there may be a delay in
319                  * suspending the port. Poll until the port is suspended.
320                  */
321                 if (handshake(ehci, status_reg, PORT_SUSPEND,
322                                                 PORT_SUSPEND, 5000))
323                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
324
325                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
326                 /*
327                  * If RUN bit is disabled interrupt is not generated after suspend.
328                  * This change on T20 will allow ASE interrupt generated after suspend
329                  * which will unlink the qheads.
330                  */
331 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
332                 if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
333                         /* Disable RUN bit. */
334                         ehci->command &= ~CMD_RUN;
335                         cmd_run = ehci_readl(ehci, &ehci->regs->command);
336                         cmd_run &= ~CMD_RUN;
337                         ehci_writel(ehci, cmd_run, &ehci->regs->command);
338                         if (handshake (ehci, &ehci->regs->status,
339                                                   STS_HALT, STS_HALT, 16 * 125))
340                                 pr_err("%s() timeout waiting for STS_HALT\n", __func__);
341                 }
342 #endif
343                 tegra_usb_phy_postsuspend(tegra->phy, false);
344
345                 goto done;
346         }
347
348         /* For USB1 port we need to issue Port Reset twice internally */
349         if (tegra->phy->instance == 0 &&
350            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
351                 spin_unlock_irqrestore(&ehci->lock, flags);
352                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
353                 return tegra_ehci_internal_port_reset(ehci, status_reg);
354         }
355
356         /*
357          * Tegra host controller will time the resume operation to clear the bit
358          * when the port control state switches to HS or FS Idle. This behavior
359          * is different from EHCI where the host controller driver is required
360          * to set this bit to a zero after the resume duration is timed in the
361          * driver.
362          */
363         else if (typeReq == ClearPortFeature &&
364                                         wValue == USB_PORT_FEAT_SUSPEND) {
365                 temp = ehci_readl(ehci, status_reg);
366                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
367                         retval = -EPIPE;
368                         goto done;
369                 }
370
371                 if (!(temp & PORT_SUSPEND))
372                         goto done;
373
374                 tegra->port_resuming = 1;
375
376                 if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
377                         /* disable interrupts */
378                         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
379                         /* Disable RUN bit. */
380                         ehci->command &= ~CMD_RUN;
381                         cmd_run = ehci_readl(ehci, &ehci->regs->command);
382                         cmd_run &= ~CMD_RUN;
383                         ehci_writel(ehci, cmd_run, &ehci->regs->command);
384                         if (handshake (ehci, &ehci->regs->status,
385                                                   STS_HALT, STS_HALT, 16 * 125))
386                                 pr_err("%s() timeout waiting for STS_HALT\n", __func__);
387                 }
388
389                 /* Disable disconnect detection during port resume */
390                 tegra_usb_phy_preresume(tegra->phy, false);
391 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
392                 if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP) {
393 #endif
394                 ehci_dbg(ehci, "%s:USBSTS = 0x%x", __func__,
395                         ehci_readl(ehci, &ehci->regs->status));
396                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
397                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
398                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
399                 udelay(20);
400
401                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
402                         pr_err("%s: timeout set for STS_SRI\n", __func__);
403
404                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
405                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
406
407                 if (handshake(ehci, &ehci->regs->status, STS_SRI, 0, 2000))
408                         pr_err("%s: timeout clear STS_SRI\n", __func__);
409
410                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
411                         pr_err("%s: timeout set STS_SRI\n", __func__);
412
413                 udelay(20);
414 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
415                 }
416 #endif
417                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
418                 /* start resume signaling */
419                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
420
421                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
422                 /* whoever resumes must GetPortStatus to complete it!! */
423                 goto done;
424         }
425
426         /* Handle port reset here */
427         if ((hsic) && (typeReq == SetPortFeature) &&
428                 ((wValue == USB_PORT_FEAT_RESET) || (wValue == USB_PORT_FEAT_POWER))) {
429                 selector = wIndex >> 8;
430                 wIndex &= 0xff;
431                 if (!wIndex || wIndex > ports) {
432                         retval = -EPIPE;
433                         goto done;
434                 }
435                 wIndex--;
436                 status = 0;
437                 temp = ehci_readl(ehci, status_reg);
438                 if (temp & PORT_OWNER)
439                         goto done;
440                 temp &= ~PORT_RWC_BITS;
441
442                 switch (wValue) {
443                 case USB_PORT_FEAT_RESET:
444                 {
445                         if (temp & PORT_RESUME) {
446                                 retval = -EPIPE;
447                                 goto done;
448                         }
449                         /* line status bits may report this as low speed,
450                         * which can be fine if this root hub has a
451                         * transaction translator built in.
452                         */
453                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
454                                         && !ehci_is_TDI(ehci) && PORT_USB11 (temp)) {
455                                 ehci_dbg (ehci, "port %d low speed --> companion\n", wIndex + 1);
456                                 temp |= PORT_OWNER;
457                                 ehci_writel(ehci, temp, status_reg);
458                         } else {
459                                 ehci_vdbg(ehci, "port %d reset\n", wIndex + 1);
460                                 temp &= ~PORT_PE;
461                                 /*
462                                 * caller must wait, then call GetPortStatus
463                                 * usb 2.0 spec says 50 ms resets on root
464                                 */
465                                 ehci->reset_done[wIndex] = jiffies + msecs_to_jiffies(50);
466                                 ehci_writel(ehci, temp, status_reg);
467                                 if (hsic && (wIndex == 0))
468                                         tegra_usb_phy_bus_reset(tegra->phy);
469                         }
470
471                         break;
472                 }
473                 case USB_PORT_FEAT_POWER:
474                 {
475                         if (HCS_PPC(ehci->hcs_params))
476                                 ehci_writel(ehci, temp | PORT_POWER, status_reg);
477                         if (hsic && (wIndex == 0))
478                                 tegra_usb_phy_bus_connect(tegra->phy);
479                         break;
480                 }
481                 }
482                 goto done;
483         }
484
485         spin_unlock_irqrestore(&ehci->lock, flags);
486
487         /* Handle the hub control events here */
488         retval = ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
489         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
490         return retval;
491 done:
492         spin_unlock_irqrestore(&ehci->lock, flags);
493         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
494         return retval;
495 }
496
497 #ifdef CONFIG_PM
498 static void tegra_ehci_restart(struct usb_hcd *hcd, bool is_dpd)
499 {
500         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
501         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
502         unsigned int temp;
503
504         ehci->controller_resets_phy = 0;
505         tegra_ehci_pre_reset(tegra->phy, false);
506         ehci_reset(ehci);
507         tegra_ehci_post_reset(tegra->phy, false);
508
509         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI)
510                 ehci->controller_resets_phy = 1;
511
512         /* setup the frame list and Async q heads */
513         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
514         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
515         /* setup the command register and set the controller in RUN mode */
516         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
517 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
518         /* dont start RS here for HSIC, it will be set by bus_reset */
519         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_HSIC)
520 #endif
521                 ehci->command |= CMD_RUN;
522         ehci_writel(ehci, ehci->command, &ehci->regs->command);
523
524         /* Enable the root Port Power */
525         if (HCS_PPC(ehci->hcs_params)) {
526                 temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
527                 ehci_writel(ehci, temp | PORT_POWER, &ehci->regs->port_status[0]);
528         }
529
530         down_write(&ehci_cf_port_reset_rwsem);
531         if(is_dpd)
532                 hcd->state = HC_STATE_SUSPENDED;
533         else
534                 hcd->state = HC_STATE_RUNNING;
535         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
536         /* flush posted writes */
537         ehci_readl(ehci, &ehci->regs->command);
538         up_write(&ehci_cf_port_reset_rwsem);
539
540         /* Turn On Interrupts */
541         ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
542 }
543
544 static int tegra_usb_suspend(struct usb_hcd *hcd, bool is_dpd)
545 {
546         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
547         struct ehci_regs __iomem *hw = tegra->ehci->regs;
548         unsigned long flags;
549         int hsic = 0;
550
551         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
552
553         spin_lock_irqsave(&tegra->ehci->lock, flags);
554
555         if (tegra->ehci->has_hostpc)
556                 tegra->port_speed = (readl(hcd->regs + HOSTPC_REG_OFFSET) >> 25) & 0x3;
557         else
558                 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
559         ehci_halt(tegra->ehci);
560 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
561         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
562                 /*
563                  * Ehci run bit is disabled by now read this into command variable
564                  * so that bus resume will not enable run bit immedialty.
565                  * this is required for 2LS WAR on UTMIP interface.
566                  */
567                 tegra->ehci->command = ehci_readl(tegra->ehci,
568                                                 &tegra->ehci->regs->command);
569         }
570 #endif
571
572         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
573
574         tegra_ehci_power_down(hcd, is_dpd);
575         return 0;
576 }
577
578 static int tegra_usb_resume(struct usb_hcd *hcd, bool is_dpd)
579 {
580         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
581         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
582         struct ehci_regs __iomem *hw = ehci->regs;
583         unsigned long val;
584         bool hsic;
585         bool null_ulpi;
586         bool utmip_remote_wakeup = false;
587
588         null_ulpi = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI);
589         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
590
591         tegra_ehci_power_up(hcd, is_dpd);
592         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
593
594         if ((tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) || (hsic) ||
595             (null_ulpi))
596                 goto restart;
597
598         /* Force the phy to keep data lines in suspend state */
599         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
600
601         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
602                 ehci_reset(ehci);
603         }
604
605         /* Enable host mode */
606         tdi_reset(ehci);
607
608         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
609                 (tegra->ehci->has_hostpc)) {
610                 val = readl(hcd->regs + HOSTPC_REG_OFFSET);
611                 val &= ~HOSTPC1_DEVLC_PTS(~0);
612                 val |= HOSTPC1_DEVLC_STS;
613                 writel(val, hcd->regs + HOSTPC_REG_OFFSET);
614         }
615
616         /* Enable Port Power */
617         val = readl(&hw->port_status[0]);
618         val |= PORT_POWER;
619         writel(val, &hw->port_status[0]);
620         udelay(10);
621
622         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
623                 (tegra->ehci->has_hostpc) && (tegra->phy->remote_wakeup)) {
624                 utmip_remote_wakeup = true;
625         }
626
627         /* Check if the phy resume from LP0. When the phy resume from LP0
628          * USB register will be reset. */
629         if (!readl(&hw->async_next)) {
630 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
631                 /* Start the controller */
632                 val = readl(&hw->command);
633                 writel((val | CMD_RUN), &hw->command);
634 #endif
635                 /* Program the field PTC based on the saved speed mode */
636                 val = readl(&hw->port_status[0]);
637                 val &= ~PORT_TEST(~0);
638                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
639                         val |= PORT_TEST_FORCE;
640                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
641                         val |= PORT_TEST(6);
642                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
643                         val |= PORT_TEST(7);
644                 writel(val, &hw->port_status[0]);
645                 udelay(10);
646
647                 /* Disable test mode by setting PTC field to NORMAL_OP */
648                 val = readl(&hw->port_status[0]);
649                 val &= ~PORT_TEST(~0);
650                 writel(val, &hw->port_status[0]);
651                 udelay(10);
652         }
653
654         /* Poll until CCS is enabled */
655         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
656                                                  PORT_CONNECT, 2000)) {
657                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
658                 goto restart;
659         }
660
661         /* Poll until PE is enabled */
662         if (handshake(ehci, &hw->port_status[0], PORT_PE,
663                                                  PORT_PE, 2000)) {
664                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
665                 goto restart;
666         }
667
668         /* Clear the PCI status, to avoid an interrupt taken upon resume */
669         val = readl(&hw->status);
670         val |= STS_PCD;
671         writel(val, &hw->status);
672
673         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
674         val = readl(&hw->port_status[0]);
675         if ((val & PORT_POWER) && (val & PORT_PE)) {
676                 val |= PORT_SUSPEND;
677                 writel(val, &hw->port_status[0]);
678
679                 /* Need a 4ms delay before the controller goes to suspend */
680                 mdelay(4);
681
682                 /* Wait until port suspend completes */
683                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
684                                                          PORT_SUSPEND, 1000)) {
685                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
686                                                                 __func__);
687                         goto restart;
688                 }
689         }
690
691         tegra_ehci_phy_restore_end(tegra->phy);
692         if (utmip_remote_wakeup) {
693                 ehci->command |= CMD_RUN;
694                 ehci_writel(ehci, ehci->command, &ehci->regs->command);
695         }
696         return 0;
697
698 restart:
699         if (null_ulpi) {
700                 bool LP0 = !readl(&hw->async_next);
701
702                 if (LP0) {
703                         static int cnt = 1;
704
705                         pr_info("LP0 restart %d\n", cnt++);
706                         tegra_ehci_phy_restore_start(tegra->phy,
707                                                      tegra->port_speed);
708                 }
709
710                 val = readl(&hw->port_status[0]);
711                 if (!((val & PORT_POWER) && (val & PORT_PE))) {
712                         tegra_ehci_restart(hcd, is_dpd);
713                 }
714
715                 if (LP0)
716                         tegra_ehci_phy_restore_end(tegra->phy);
717
718                 return 0;
719         }
720
721         if ((tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) && (!hsic))
722                 tegra_ehci_phy_restore_end(tegra->phy);
723         if (hsic) {
724                 val = readl(&hw->port_status[0]);
725                 if (!((val & PORT_POWER) && (val & PORT_PE)))
726                         tegra_ehci_restart(hcd, false);
727
728                 tegra_usb_phy_bus_idle(tegra->phy);
729                 if (!tegra_usb_phy_is_device_connected(tegra->phy))
730                         pr_err("%s: no hsic device conenction\n", __func__);
731         } else {
732                 tegra_ehci_restart(hcd, false);
733         }
734
735         return 0;
736 }
737 #endif
738
739 /*
740  * Disable PHY clock valid interrupts and wait for the interrupt handler to
741  * finish.
742  *
743  * Requires a lock on tegra_ehci_hcd_mutex
744  * Must not be called with a lock on ehci->lock
745  */
746 static void tegra_ehci_disable_phy_interrupt(struct usb_hcd *hcd) {
747         struct tegra_ehci_hcd *tegra;
748         u32 val;
749         if (hcd->irq >= 0) {
750                 tegra = dev_get_drvdata(hcd->self.controller);
751                 if (tegra->phy->hotplug) {
752                         /* Disable PHY clock valid interrupts */
753                         val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
754                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB;
755                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
756                 }
757                 /* Wait for the interrupt handler to finish */
758                 synchronize_irq(hcd->irq);
759         }
760 }
761
762 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
763 {
764         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
765
766         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
767         tegra_ehci_disable_phy_interrupt(hcd);
768         /* ehci_shutdown touches the USB controller registers, make sure
769          * controller has clocks to it */
770         if (!tegra->host_resumed)
771                 tegra_ehci_power_up(hcd, false);
772
773         ehci_shutdown(hcd);
774
775         /* we are ready to shut down, powerdown the phy */
776         tegra_ehci_power_down(hcd, false);
777         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
778 }
779
780 static int tegra_ehci_setup(struct usb_hcd *hcd)
781 {
782         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
783         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
784         int retval;
785
786         /* EHCI registers start at offset 0x100 */
787         ehci->caps = hcd->regs + 0x100;
788         ehci->regs = hcd->regs + 0x100 +
789                 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
790
791         dbg_hcs_params(ehci, "reset");
792         dbg_hcc_params(ehci, "reset");
793
794         /* cache this readonly data; minimize chip reads */
795         ehci->hcs_params = readl(&ehci->caps->hcs_params);
796
797 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
798         ehci->has_hostpc = 1;
799 #endif
800         hcd->has_tt = 1;
801
802         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_NULL_ULPI) {
803                 ehci_reset(ehci);
804                 tegra_ehci_post_reset(tegra->phy, false);
805         }
806
807         retval = ehci_halt(ehci);
808         if (retval)
809                 return retval;
810
811         /* data structure init */
812         retval = ehci_init(hcd);
813         if (retval)
814                 return retval;
815
816         ehci->sbrn = 0x20;
817         ehci->controller_remote_wakeup = false;
818
819         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
820                 tegra_ehci_pre_reset(tegra->phy, false);
821                 ehci_reset(ehci);
822                 tegra_ehci_post_reset(tegra->phy, false);
823
824                 /*
825                  * Resetting the controller has the side effect of resetting the PHY.
826                  * So, never reset the controller after the calling
827                  * tegra_ehci_reinit API.
828                  */
829                 ehci->controller_resets_phy = 1;
830         }
831
832         ehci_port_power(ehci, 1);
833         return retval;
834 }
835
836 #ifdef CONFIG_PM
837 static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
838 {
839         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
840         int error_status = 0;
841
842         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
843         tegra->bus_suspended_fail = false;
844         tegra_ehci_disable_phy_interrupt(hcd);
845         /* ehci_shutdown touches the USB controller registers, make sure
846          * controller has clocks to it */
847         if (!tegra->host_resumed)
848                 tegra_ehci_power_up(hcd, false);
849         error_status = ehci_bus_suspend(hcd);
850         if (error_status)
851                 tegra->bus_suspended_fail = true;
852         if (!error_status && tegra->power_down_on_bus_suspend) {
853                 tegra_usb_suspend(hcd, false);
854                 tegra->bus_suspended = 1;
855         }
856         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
857
858         return error_status;
859 }
860
861 static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
862 {
863         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
864         int ehci_bus_resumed;
865
866         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
867         if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
868                 tegra_usb_resume(hcd, false);
869                 tegra->bus_suspended = 0;
870         }
871
872         ehci_bus_resumed = ehci_bus_resume(hcd);
873         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
874         return ehci_bus_resumed;
875 }
876 #endif
877
878 struct dma_aligned_buffer {
879         void *kmalloc_ptr;
880         void *old_xfer_buffer;
881         u8 data[0];
882 };
883
884 static void free_dma_aligned_buffer(struct urb *urb)
885 {
886         struct dma_aligned_buffer *temp = container_of(urb->transfer_buffer,
887                 struct dma_aligned_buffer, data);
888
889         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
890                 return;
891
892         if(usb_urb_dir_in(urb))
893                 memcpy(temp->old_xfer_buffer, temp->data,
894                        urb->transfer_buffer_length);
895         urb->transfer_buffer = temp->old_xfer_buffer;
896         kfree(temp->kmalloc_ptr);
897         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
898 }
899
900 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
901 {
902         struct dma_aligned_buffer *temp, *kmalloc_ptr;
903         size_t kmalloc_size;
904
905         if (urb->num_sgs || urb->sg ||
906             urb->transfer_buffer_length == 0 ||
907             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
908                 return 0;
909
910         /* Allocate a buffer with enough padding for alignment */
911         kmalloc_size = urb->transfer_buffer_length +
912                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
913
914         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
915         if (!kmalloc_ptr)
916                 return -ENOMEM;
917
918         /* Position our struct dma_aligned_buffer such that data is aligned */
919         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
920         temp->kmalloc_ptr = kmalloc_ptr;
921         temp->old_xfer_buffer = urb->transfer_buffer;
922         if (!usb_urb_dir_in(urb))
923                 memcpy(temp->data, urb->transfer_buffer,
924                        urb->transfer_buffer_length);
925         urb->transfer_buffer = temp->data;
926         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
927
928         return 0;
929 }
930
931 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
932                                       gfp_t mem_flags)
933 {
934         int ret;
935
936         ret = alloc_dma_aligned_buffer(urb, mem_flags);
937         if (ret)
938                 return ret;
939
940         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
941         if (ret)
942                 free_dma_aligned_buffer(urb);
943
944         return ret;
945 }
946
947 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
948 {
949         usb_hcd_unmap_urb_for_dma(hcd, urb);
950         free_dma_aligned_buffer(urb);
951 }
952
953 void clk_timer_callback(unsigned long data)
954 {
955         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd*) data;
956         unsigned long flags;
957
958         if (!timer_pending(&tegra->clk_timer)) {
959                 spin_lock_irqsave(&tegra->ehci->lock, flags);
960                 tegra->timer_event = 1;
961                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
962                 schedule_work(&tegra->clk_timer_work);
963         }
964 }
965
966 static void clk_timer_work_handler(struct work_struct* clk_timer_work) {
967         struct tegra_ehci_hcd *tegra = container_of(clk_timer_work,
968                                                 struct tegra_ehci_hcd, clk_timer_work);
969         int ret;
970         unsigned long flags;
971         bool clock_enabled, timer_event;
972
973         spin_lock_irqsave(&tegra->ehci->lock, flags);
974         clock_enabled = tegra->clock_enabled;
975         timer_event = tegra->timer_event;
976         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
977
978         if (timer_event) {
979                 spin_lock_irqsave(&tegra->ehci->lock, flags);
980                 tegra->clock_enabled = 0;
981                 tegra->timer_event = 0;
982                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
983                 clk_disable(tegra->emc_clk);
984                 clk_disable(tegra->sclk_clk);
985                 return;
986         }
987
988         if ((!clock_enabled)) {
989                 ret = mod_timer(&tegra->clk_timer, jiffies + msecs_to_jiffies(2000));
990                 if (ret)
991                         pr_err("tegra_ehci_urb_enqueue timer modify failed \n");
992                 clk_enable(tegra->emc_clk);
993                 clk_enable(tegra->sclk_clk);
994                 spin_lock_irqsave(&tegra->ehci->lock, flags);
995                 tegra->clock_enabled = 1;
996                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
997         } else {
998                 if (timer_pending(&tegra->clk_timer)) {
999                         mod_timer_pending (&tegra->clk_timer, jiffies
1000                                                 + msecs_to_jiffies(2000));
1001                 }
1002         }
1003 }
1004
1005 static int tegra_ehci_urb_enqueue (
1006         struct usb_hcd  *hcd,
1007         struct urb      *urb,
1008         gfp_t           mem_flags)
1009 {
1010         struct tegra_ehci_hcd *pdata;
1011         int xfertype;
1012         int transfer_buffer_length;
1013         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1014         unsigned long flags;
1015         pdata = dev_get_drvdata(hcd->self.controller);
1016
1017         xfertype = usb_endpoint_type(&urb->ep->desc);
1018         transfer_buffer_length = urb->transfer_buffer_length;
1019         spin_lock_irqsave(&ehci->lock,flags);
1020         /* Turn on the USB busy hints */
1021         switch (xfertype) {
1022                 case USB_ENDPOINT_XFER_INT:
1023                 if (transfer_buffer_length < 255) {
1024                 /* Do nothing for interrupt buffers < 255 */
1025                 } else {
1026                         /* signal to set the busy hints */
1027                         schedule_work(&pdata->clk_timer_work);
1028                 }
1029                 break;
1030                 case USB_ENDPOINT_XFER_ISOC:
1031                 case USB_ENDPOINT_XFER_BULK:
1032                         /* signal to set the busy hints */
1033                         schedule_work(&pdata->clk_timer_work);
1034                 break;
1035                 case USB_ENDPOINT_XFER_CONTROL:
1036                 default:
1037                         /* Do nothing special here */
1038                 break;
1039         }
1040         spin_unlock_irqrestore(&ehci->lock,flags);
1041         return ehci_urb_enqueue(hcd, urb, mem_flags);
1042 }
1043
1044 static const struct hc_driver tegra_ehci_hc_driver = {
1045         .description            = hcd_name,
1046         .product_desc           = "Tegra EHCI Host Controller",
1047         .hcd_priv_size          = sizeof(struct ehci_hcd),
1048         .flags                  = HCD_USB2 | HCD_MEMORY,
1049
1050         /* standard ehci functions */
1051         .start                  = ehci_run,
1052         .stop                   = ehci_stop,
1053         .urb_dequeue            = ehci_urb_dequeue,
1054         .endpoint_disable       = ehci_endpoint_disable,
1055         .endpoint_reset         = ehci_endpoint_reset,
1056         .get_frame_number       = ehci_get_frame,
1057         .hub_status_data        = ehci_hub_status_data,
1058         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1059         .relinquish_port        = ehci_relinquish_port,
1060         .port_handed_over       = ehci_port_handed_over,
1061
1062         /* modified ehci functions for tegra */
1063         .reset                  = tegra_ehci_setup,
1064         .irq                    = tegra_ehci_irq,
1065         .shutdown               = tegra_ehci_shutdown,
1066         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
1067         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
1068         .hub_control            = tegra_ehci_hub_control,
1069         .urb_enqueue            = tegra_ehci_urb_enqueue,
1070 #ifdef CONFIG_PM
1071         .bus_suspend            = tegra_ehci_bus_suspend,
1072         .bus_resume             = tegra_ehci_bus_resume,
1073 #endif
1074 };
1075
1076 static int tegra_ehci_probe(struct platform_device *pdev)
1077 {
1078         struct resource *res;
1079         struct usb_hcd *hcd;
1080         struct tegra_ehci_hcd *tegra;
1081         struct tegra_ehci_platform_data *pdata;
1082         int err = 0;
1083         int irq;
1084         int instance = pdev->id;
1085
1086         pdata = pdev->dev.platform_data;
1087         if (!pdata) {
1088                 dev_err(&pdev->dev, "Platform data missing\n");
1089                 return -EINVAL;
1090         }
1091
1092         tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
1093         if (!tegra)
1094                 return -ENOMEM;
1095
1096         mutex_init(&tegra->tegra_ehci_hcd_mutex);
1097
1098         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
1099                                         dev_name(&pdev->dev));
1100         if (!hcd) {
1101                 dev_err(&pdev->dev, "Unable to create HCD\n");
1102                 err = -ENOMEM;
1103                 goto fail_hcd;
1104         }
1105
1106         platform_set_drvdata(pdev, tegra);
1107         tegra->default_enable = pdata->default_enable;
1108
1109         tegra->clk = clk_get(&pdev->dev, NULL);
1110         if (IS_ERR(tegra->clk)) {
1111                 dev_err(&pdev->dev, "Can't get ehci clock\n");
1112                 err = PTR_ERR(tegra->clk);
1113                 goto fail_clk;
1114         }
1115
1116         err = clk_enable(tegra->clk);
1117         if (err)
1118                 goto fail_clken;
1119
1120
1121         tegra->sclk_clk = clk_get(&pdev->dev, "sclk");
1122         if (IS_ERR(tegra->sclk_clk)) {
1123                 dev_err(&pdev->dev, "Can't get sclk clock\n");
1124                 err = PTR_ERR(tegra->sclk_clk);
1125                 goto fail_sclk_clk;
1126         }
1127
1128         clk_set_rate(tegra->sclk_clk, 80000000);
1129
1130         tegra->emc_clk = clk_get(&pdev->dev, "emc");
1131         if (IS_ERR(tegra->emc_clk)) {
1132                 dev_err(&pdev->dev, "Can't get emc clock\n");
1133                 err = PTR_ERR(tegra->emc_clk);
1134                 goto fail_emc_clk;
1135         }
1136         init_timer(&tegra->clk_timer);
1137         tegra->clk_timer.function = clk_timer_callback;
1138         tegra->clk_timer.data = (unsigned long) tegra;
1139
1140 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1141         /* Set DDR busy hints to 150MHz. For Tegra 2x SOC, DDR rate is half of EMC rate */
1142         clk_set_rate(tegra->emc_clk, 300000000);
1143 #else
1144         /* Set DDR busy hints to 100MHz. For Tegra 3x SOC DDR rate equals to EMC rate */
1145         clk_set_rate(tegra->emc_clk, 100000000);
1146 #endif
1147
1148         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1149         if (!res) {
1150                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1151                 err = -ENXIO;
1152                 goto fail_io;
1153         }
1154         hcd->rsrc_start = res->start;
1155         hcd->rsrc_len = resource_size(res);
1156         hcd->regs = ioremap(res->start, resource_size(res));
1157         if (!hcd->regs) {
1158                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1159                 err = -ENOMEM;
1160                 goto fail_io;
1161         }
1162
1163         INIT_WORK(&tegra->clk_timer_work, clk_timer_work_handler);
1164
1165         tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
1166                                         TEGRA_USB_PHY_MODE_HOST, pdata->phy_type);
1167         if (IS_ERR(tegra->phy)) {
1168                 dev_err(&pdev->dev, "Failed to open USB phy\n");
1169                 err = -ENXIO;
1170                 goto fail_phy;
1171         }
1172         tegra->phy->hotplug = pdata->hotplug;
1173
1174         err = tegra_usb_phy_power_on(tegra->phy, true);
1175         if (err) {
1176                 dev_err(&pdev->dev, "Failed to power on the phy\n");
1177                 goto fail;
1178         }
1179
1180         tegra->host_resumed = 1;
1181         tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
1182         tegra->ehci = hcd_to_ehci(hcd);
1183
1184         irq = platform_get_irq(pdev, 0);
1185         if (!irq) {
1186                 dev_err(&pdev->dev, "Failed to get IRQ\n");
1187                 err = -ENODEV;
1188                 goto fail;
1189         }
1190         set_irq_flags(irq, IRQF_VALID);
1191         tegra->irq = irq;
1192
1193 #ifdef CONFIG_USB_OTG_UTILS
1194         if (pdata->operating_mode == TEGRA_USB_OTG) {
1195                 tegra->transceiver = otg_get_transceiver();
1196                 if (tegra->transceiver)
1197                         otg_set_host(tegra->transceiver, &hcd->self);
1198         }
1199 #endif
1200
1201         err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
1202         if (err) {
1203                 dev_err(&pdev->dev, "Failed to add USB HCD error = %d\n", err);
1204                 goto fail;
1205         }
1206
1207         err = enable_irq_wake(tegra->irq);
1208         if (err < 0) {
1209                 dev_warn(&pdev->dev,
1210                         "Couldn't enable USB host mode wakeup, irq=%d, "
1211                         "error=%d\n", tegra->irq, err);
1212                 err = 0;
1213                 tegra->irq = 0;
1214         }
1215
1216         return err;
1217
1218 fail:
1219 #ifdef CONFIG_USB_OTG_UTILS
1220         if (tegra->transceiver) {
1221                 otg_set_host(tegra->transceiver, NULL);
1222                 otg_put_transceiver(tegra->transceiver);
1223         }
1224 #endif
1225         tegra_usb_phy_close(tegra->phy);
1226 fail_phy:
1227         iounmap(hcd->regs);
1228 fail_io:
1229         clk_disable(tegra->emc_clk);
1230         clk_put(tegra->emc_clk);
1231 fail_emc_clk:
1232         clk_disable(tegra->sclk_clk);
1233         clk_put(tegra->sclk_clk);
1234 fail_sclk_clk:
1235         clk_disable(tegra->clk);
1236 fail_clken:
1237         clk_put(tegra->clk);
1238 fail_clk:
1239         usb_put_hcd(hcd);
1240 fail_hcd:
1241         kfree(tegra);
1242         return err;
1243 }
1244
1245 #ifdef CONFIG_PM
1246 static int tegra_ehci_resume_noirq(struct device *dev)
1247 {
1248         struct platform_device *pdev = to_platform_device(dev);
1249         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1250         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1251         int ret;
1252
1253         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
1254         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1255                 if (tegra->default_enable)
1256                         clk_enable(tegra->clk);
1257                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1258                 return 0;
1259         }
1260
1261         if (tegra->default_enable)
1262                 clk_enable(tegra->clk);
1263
1264         ret = tegra_usb_resume(hcd, true);
1265         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1266         return ret;
1267 }
1268
1269 static int tegra_ehci_suspend_noirq(struct device *dev)
1270 {
1271         struct platform_device *pdev = to_platform_device(dev);
1272         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1273         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1274         int ret;
1275         u32 val;
1276
1277         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
1278         /* if bus suspend is failed means there is remote wakeup resume,
1279                 then abort the PM suspend */
1280         if (tegra->bus_suspended_fail) {
1281                 tegra->bus_suspended_fail = false;
1282                 pr_err("%s: bus suspend failed, aborting driver suspend\n", __func__);
1283                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1284                 return -EBUSY;
1285         }
1286         if (tegra->phy->hotplug) {
1287                 /* Disable PHY clock valid interrupts while going into suspend*/
1288                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
1289                 val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB;
1290                 writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
1291         }
1292
1293         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1294                 if (tegra->default_enable)
1295                         clk_disable(tegra->clk);
1296                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1297                 return 0;
1298         }
1299
1300         if (time_before(jiffies, tegra->ehci->next_statechange))
1301                 msleep(10);
1302
1303         ret = tegra_usb_suspend(hcd, true);
1304         if (tegra->default_enable)
1305                 clk_disable(tegra->clk);
1306         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1307         return ret;
1308 }
1309
1310 static struct dev_pm_ops tegra_ehci_dev_pm_ops = {
1311         .suspend_noirq = tegra_ehci_suspend_noirq,
1312         .resume_noirq = tegra_ehci_resume_noirq,
1313 };
1314
1315 #endif
1316
1317 static int tegra_ehci_remove(struct platform_device *pdev)
1318 {
1319         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1320         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1321
1322         if (tegra == NULL || hcd == NULL)
1323                 return -EINVAL;
1324         /* make sure controller is on as we will touch its registers */
1325         if (!tegra->host_resumed)
1326                 tegra_ehci_power_up(hcd, true);
1327
1328 #ifdef CONFIG_USB_OTG_UTILS
1329         if (tegra->transceiver) {
1330                 otg_set_host(tegra->transceiver, NULL);
1331                 otg_put_transceiver(tegra->transceiver);
1332         }
1333 #endif
1334
1335         /* Turn Off Interrupts */
1336         ehci_writel(tegra->ehci, 0, &tegra->ehci->regs->intr_enable);
1337         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1338         if (tegra->irq)
1339                 disable_irq_wake(tegra->irq);
1340         usb_remove_hcd(hcd);
1341         usb_put_hcd(hcd);
1342         tegra_usb_phy_power_off(tegra->phy, true);
1343         tegra_usb_phy_close(tegra->phy);
1344         iounmap(hcd->regs);
1345
1346         del_timer_sync(&tegra->clk_timer);
1347
1348         clk_disable(tegra->clk);
1349         clk_put(tegra->clk);
1350
1351         if (tegra->clock_enabled) {
1352                 clk_disable(tegra->sclk_clk);
1353                 clk_disable(tegra->emc_clk);
1354         }
1355         clk_put(tegra->sclk_clk);
1356         clk_put(tegra->emc_clk);
1357
1358         kfree(tegra);
1359         return 0;
1360 }
1361
1362 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
1363 {
1364         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1365         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1366
1367         if (hcd->driver->shutdown)
1368                 hcd->driver->shutdown(hcd);
1369 }
1370
1371 static struct platform_driver tegra_ehci_driver = {
1372         .probe          = tegra_ehci_probe,
1373         .remove         = tegra_ehci_remove,
1374         .shutdown       = tegra_ehci_hcd_shutdown,
1375         .driver         = {
1376                 .name   = "tegra-ehci",
1377 #ifdef CONFIG_PM
1378                 .pm     = &tegra_ehci_dev_pm_ops,
1379 #endif
1380         }
1381 };