arm: tegra: usb: Adding phy_restore functions for null ULPI
[linux-2.6.git] / drivers / usb / host / ehci-tegra.c
1 /*
2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2009 - 2011 NVIDIA Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/platform_data/tegra_usb.h>
22 #include <linux/irq.h>
23 #include <linux/usb/otg.h>
24 #include <mach/usb_phy.h>
25 #include <mach/iomap.h>
26
27 #define TEGRA_USB_PORTSC_PHCD           (1 << 23)
28
29 #define TEGRA_USB_SUSP_CTRL_OFFSET      0x400
30 #define TEGRA_USB_SUSP_CLR                      (1 << 5)
31 #define TEGRA_USB_PHY_CLK_VALID                 (1 << 7)
32 #define TEGRA_USB_SRT                           (1 << 25)
33 #define TEGRA_USB_PHY_CLK_VALID_INT_ENB         (1 << 9)
34 #define TEGRA_USB_PHY_CLK_VALID_INT_STS         (1 << 8)
35
36 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
37 #define TEGRA_USB_PORTSC1_OFFSET        0x184
38 #else
39 #define TEGRA_USB_PORTSC1_OFFSET        0x174
40 #endif
41 #define TEGRA_USB_PORTSC1_WKCN                  (1 << 20)
42
43 #define TEGRA_LVL2_CLK_GATE_OVRB        0xfc
44 #define TEGRA_USB2_CLK_OVR_ON                   (1 << 10)
45
46 #define TEGRA_USB_DMA_ALIGN 32
47
48 #define STS_SRI (1<<7)  /*      SOF Recieved    */
49
50 #define TEGRA_HSIC_CONNECTION_MAX_RETRIES 5
51 #define HOSTPC_REG_OFFSET               0x1b4
52
53 #define HOSTPC1_DEVLC_STS               (1 << 28)
54 #define HOSTPC1_DEVLC_PTS(x)            (((x) & 0x7) << 29)
55
56 struct tegra_ehci_hcd {
57         struct ehci_hcd *ehci;
58         struct tegra_usb_phy *phy;
59         struct clk *clk;
60         struct clk *emc_clk;
61         struct clk *sclk_clk;
62         struct otg_transceiver *transceiver;
63         int host_resumed;
64         int bus_suspended;
65         int port_resuming;
66         int power_down_on_bus_suspend;
67         int hotplug;
68         struct delayed_work work;
69         enum tegra_usb_phy_port_speed port_speed;
70         struct work_struct clk_timer_work;
71         struct timer_list clk_timer;
72         bool clock_enabled;
73         bool timer_event;
74         int hsic_connect_retries;
75         struct mutex tegra_ehci_hcd_mutex;
76 };
77
78 static void tegra_ehci_power_up(struct usb_hcd *hcd, bool is_dpd)
79 {
80         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
81
82 #ifndef CONFIG_USB_HOTPLUG
83         clk_enable(tegra->clk);
84 #endif
85         tegra_usb_phy_power_on(tegra->phy, is_dpd);
86         tegra->host_resumed = 1;
87 }
88
89 static void tegra_ehci_power_down(struct usb_hcd *hcd, bool is_dpd)
90 {
91         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
92
93         tegra->host_resumed = 0;
94         tegra_usb_phy_power_off(tegra->phy, is_dpd);
95 #ifndef CONFIG_USB_HOTPLUG
96         clk_disable(tegra->clk);
97 #endif
98 }
99
100 static int tegra_ehci_internal_port_reset(
101         struct ehci_hcd *ehci,
102         u32 __iomem     *portsc_reg
103 )
104 {
105         u32             temp;
106         unsigned long   flags;
107         int             retval = 0;
108         int             i, tries;
109         u32             saved_usbintr;
110
111         spin_lock_irqsave(&ehci->lock, flags);
112         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
113         /* disable USB interrupt */
114         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
115         spin_unlock_irqrestore(&ehci->lock, flags);
116
117         /*
118          * Here we have to do Port Reset at most twice for
119          * Port Enable bit to be set.
120          */
121         for (i = 0; i < 2; i++) {
122                 temp = ehci_readl(ehci, portsc_reg);
123                 temp |= PORT_RESET;
124                 ehci_writel(ehci, temp, portsc_reg);
125                 mdelay(10);
126                 temp &= ~PORT_RESET;
127                 ehci_writel(ehci, temp, portsc_reg);
128                 mdelay(1);
129                 tries = 100;
130                 do {
131                         mdelay(1);
132                         /*
133                          * Up to this point, Port Enable bit is
134                          * expected to be set after 2 ms waiting.
135                          * USB1 usually takes extra 45 ms, for safety,
136                          * we take 100 ms as timeout.
137                          */
138                         temp = ehci_readl(ehci, portsc_reg);
139                 } while (!(temp & PORT_PE) && tries--);
140                 if (temp & PORT_PE)
141                         break;
142         }
143         if (i == 2)
144                 retval = -ETIMEDOUT;
145
146         /*
147          * Clear Connect Status Change bit if it's set.
148          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
149          */
150         if (temp & PORT_CSC)
151                 ehci_writel(ehci, PORT_CSC, portsc_reg);
152
153         /*
154          * Write to clear any interrupt status bits that might be set
155          * during port reset.
156          */
157         temp = ehci_readl(ehci, &ehci->regs->status);
158         ehci_writel(ehci, temp, &ehci->regs->status);
159
160         /* restore original interrupt enable bits */
161         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
162         return retval;
163 }
164
165 static irqreturn_t tegra_ehci_irq (struct usb_hcd *hcd)
166 {
167         struct ehci_hcd *ehci = hcd_to_ehci (hcd);
168         struct ehci_regs __iomem *hw = ehci->regs;
169         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
170         u32 val;
171
172         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
173                 (tegra->ehci->has_hostpc)) {
174                 /* check if there is any remote wake event */
175                 if (tegra_usb_phy_is_remotewake_detected(tegra->phy)) {
176                         spin_lock (&ehci->lock);
177                         usb_hcd_resume_root_hub(hcd);
178                         spin_unlock (&ehci->lock);
179                 }
180         }
181         if (tegra->hotplug) {
182                 spin_lock(&ehci->lock);
183                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
184                 if ((val  & TEGRA_USB_PHY_CLK_VALID_INT_STS)) {
185                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB |
186                                 TEGRA_USB_PHY_CLK_VALID_INT_STS;
187                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
188
189                         val = readl(hcd->regs + TEGRA_USB_PORTSC1_OFFSET);
190                         val &= ~TEGRA_USB_PORTSC1_WKCN;
191                         writel(val , (hcd->regs + TEGRA_USB_PORTSC1_OFFSET));
192
193                         val = readl(&hw->status);
194                         if (!(val  & STS_PCD)) {
195                                 spin_unlock(&ehci->lock);
196                                 return 0;
197                         }
198                 }
199                 spin_unlock(&ehci->lock);
200         }
201         return ehci_irq(hcd);
202 }
203
204 static int tegra_ehci_hub_control(
205         struct usb_hcd  *hcd,
206         u16             typeReq,
207         u16             wValue,
208         u16             wIndex,
209         char            *buf,
210         u16             wLength
211 )
212 {
213         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
214         int             ports = HCS_N_PORTS(ehci->hcs_params);
215         u32             temp, status;
216         u32 __iomem     *status_reg;
217         u32             usbsts_reg;
218
219         unsigned long   flags;
220         int             retval = 0;
221         unsigned        selector;
222         struct          tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
223         bool            hsic = false;
224
225         if (!tegra->host_resumed) {
226                 if (buf)
227                         memset (buf, 0, wLength);
228                 return retval;
229         }
230
231         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
232
233         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
234
235         spin_lock_irqsave(&ehci->lock, flags);
236
237         /*
238          * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
239          * that are write on clear, by writing back the register read value, so
240          * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
241          */
242         if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
243                 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
244                 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
245                 goto done;
246         } else if (typeReq == GetPortStatus) {
247                 temp = ehci_readl(ehci, status_reg);
248                 if (tegra->port_resuming && !(temp & PORT_SUSPEND) &&
249                     time_after_eq(jiffies, ehci->reset_done[wIndex-1])) {
250                         /* Resume completed, re-enable disconnect detection */
251                         tegra->port_resuming = 0;
252                         clear_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
253                         ehci->reset_done[wIndex-1] = 0;
254                         tegra_usb_phy_postresume(tegra->phy, false);
255 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
256                         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
257                                 ehci->command |= CMD_RUN;
258                                 /*
259                                  * ehci run bit is disabled to avoid SOF.
260                                  * 2LS WAR is executed by now enable the run bit.
261                                  */
262                                 ehci_writel(ehci, ehci->command,
263                                         &ehci->regs->command);
264                         }
265 #endif
266                 }
267         } else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
268                 temp = ehci_readl(ehci, status_reg);
269                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
270                         retval = -EPIPE;
271                         goto done;
272                 }
273
274                 temp &= ~PORT_WKCONN_E;
275                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
276                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
277
278                 /* Need a 4ms delay before the controller goes to suspend */
279                 mdelay(4);
280
281                 /*
282                  * If a transaction is in progress, there may be a delay in
283                  * suspending the port. Poll until the port is suspended.
284                  */
285                 if (handshake(ehci, status_reg, PORT_SUSPEND,
286                                                 PORT_SUSPEND, 5000))
287                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
288
289                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
290
291                 tegra_usb_phy_postsuspend(tegra->phy, false);
292
293                 goto done;
294         }
295
296         /* For USB1 port we need to issue Port Reset twice internally */
297         if (tegra->phy->instance == 0 &&
298            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
299                 spin_unlock_irqrestore(&ehci->lock, flags);
300                 return tegra_ehci_internal_port_reset(ehci, status_reg);
301         }
302
303         /*
304          * Tegra host controller will time the resume operation to clear the bit
305          * when the port control state switches to HS or FS Idle. This behavior
306          * is different from EHCI where the host controller driver is required
307          * to set this bit to a zero after the resume duration is timed in the
308          * driver.
309          */
310         else if (typeReq == ClearPortFeature &&
311                                         wValue == USB_PORT_FEAT_SUSPEND) {
312                 temp = ehci_readl(ehci, status_reg);
313                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
314                         retval = -EPIPE;
315                         goto done;
316                 }
317
318                 if (!(temp & PORT_SUSPEND))
319                         goto done;
320
321                 tegra->port_resuming = 1;
322
323                 /* Disable disconnect detection during port resume */
324                 tegra_usb_phy_preresume(tegra->phy, false);
325 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
326                 if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP) {
327 #endif
328                 ehci_dbg(ehci, "%s:USBSTS = 0x%x", __func__,
329                         ehci_readl(ehci, &ehci->regs->status));
330                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
331                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
332                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
333                 udelay(20);
334
335                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
336                         pr_err("%s: timeout set for STS_SRI\n", __func__);
337
338                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
339                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
340
341                 if (handshake(ehci, &ehci->regs->status, STS_SRI, 0, 2000))
342                         pr_err("%s: timeout clear STS_SRI\n", __func__);
343
344                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
345                         pr_err("%s: timeout set STS_SRI\n", __func__);
346
347                 udelay(20);
348 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
349                 }
350 #endif
351                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
352                 /* start resume signaling */
353                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
354
355                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
356                 /* whoever resumes must GetPortStatus to complete it!! */
357                 goto done;
358         }
359
360         /* Handle port reset here */
361 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
362         if ((hsic) && (typeReq == SetPortFeature) &&
363                 ((wValue == USB_PORT_FEAT_RESET) || (wValue == USB_PORT_FEAT_POWER))) {
364 #else
365         if ((hsic) && (typeReq == SetPortFeature) &&
366                 (wValue == USB_PORT_FEAT_POWER)) {
367 #endif
368                 selector = wIndex >> 8;
369                 wIndex &= 0xff;
370                 if (!wIndex || wIndex > ports) {
371                         retval = -EPIPE;
372                         goto done;
373                 }
374                 wIndex--;
375                 status = 0;
376                 temp = ehci_readl(ehci, status_reg);
377                 if (temp & PORT_OWNER)
378                         goto done;
379                 temp &= ~PORT_RWC_BITS;
380
381                 switch (wValue) {
382 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
383                 case USB_PORT_FEAT_RESET:
384                 {
385                         if (temp & PORT_RESUME) {
386                                 retval = -EPIPE;
387                                 goto done;
388                         }
389                         /* line status bits may report this as low speed,
390                         * which can be fine if this root hub has a
391                         * transaction translator built in.
392                         */
393                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
394                                         && !ehci_is_TDI(ehci) && PORT_USB11 (temp)) {
395                                 ehci_dbg (ehci, "port %d low speed --> companion\n", wIndex + 1);
396                                 temp |= PORT_OWNER;
397                                 ehci_writel(ehci, temp, status_reg);
398                         } else {
399                                 ehci_vdbg(ehci, "port %d reset\n", wIndex + 1);
400                                 temp &= ~PORT_PE;
401                                 /*
402                                 * caller must wait, then call GetPortStatus
403                                 * usb 2.0 spec says 50 ms resets on root
404                                 */
405                                 ehci->reset_done[wIndex] = jiffies + msecs_to_jiffies(50);
406                                 ehci_writel(ehci, temp, status_reg);
407                                 if (hsic && (wIndex == 0))
408                                         tegra_usb_phy_bus_reset(tegra->phy);
409                         }
410
411                         break;
412                 }
413 #endif
414                 case USB_PORT_FEAT_POWER:
415                 {
416                         if (HCS_PPC(ehci->hcs_params))
417                                 ehci_writel(ehci, temp | PORT_POWER, status_reg);
418                         if (hsic && (wIndex == 0))
419                                 tegra_usb_phy_bus_connect(tegra->phy);
420                         break;
421                 }
422                 }
423                 goto done;
424         }
425
426         spin_unlock_irqrestore(&ehci->lock, flags);
427
428         /* Handle the hub control events here */
429         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
430 done:
431         spin_unlock_irqrestore(&ehci->lock, flags);
432         return retval;
433 }
434
435 #ifdef CONFIG_PM
436 static void tegra_ehci_restart(struct usb_hcd *hcd)
437 {
438         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
439         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
440         unsigned int temp;
441
442         ehci->controller_resets_phy = 0;
443         tegra_ehci_pre_reset(tegra->phy, false);
444         ehci_reset(ehci);
445         tegra_ehci_post_reset(tegra->phy, false);
446
447         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI)
448                 ehci->controller_resets_phy = 1;
449
450         /* setup the frame list and Async q heads */
451         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
452         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
453         /* setup the command register and set the controller in RUN mode */
454         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
455         ehci->command |= CMD_RUN;
456         ehci_writel(ehci, ehci->command, &ehci->regs->command);
457
458         /* Enable the root Port Power */
459         if (HCS_PPC(ehci->hcs_params)) {
460                 temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
461                 ehci_writel(ehci, temp | PORT_POWER, &ehci->regs->port_status[0]);
462         }
463
464         down_write(&ehci_cf_port_reset_rwsem);
465         hcd->state = HC_STATE_RUNNING;
466         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
467         /* flush posted writes */
468         ehci_readl(ehci, &ehci->regs->command);
469         up_write(&ehci_cf_port_reset_rwsem);
470
471         /* Turn On Interrupts */
472         ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
473 }
474
475 static int tegra_usb_suspend(struct usb_hcd *hcd, bool is_dpd)
476 {
477         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
478         struct ehci_regs __iomem *hw = tegra->ehci->regs;
479         unsigned long flags;
480         int hsic = 0;
481
482         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
483
484         spin_lock_irqsave(&tegra->ehci->lock, flags);
485
486         if (tegra->ehci->has_hostpc)
487                 tegra->port_speed = (readl(hcd->regs + HOSTPC_REG_OFFSET) >> 25) & 0x3;
488         else
489                 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
490         ehci_halt(tegra->ehci);
491 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
492         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
493                 /*
494                  * Ehci run bit is disabled by now read this into command variable
495                  * so that bus resume will not enable run bit immedialty.
496                  * this is required for 2LS WAR on UTMIP interface.
497                  */
498                 tegra->ehci->command = ehci_readl(tegra->ehci,
499                                                 &tegra->ehci->regs->command);
500         }
501 #endif
502
503         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
504
505         tegra_ehci_power_down(hcd, is_dpd);
506         return 0;
507 }
508
509 static int tegra_usb_resume(struct usb_hcd *hcd, bool is_dpd)
510 {
511         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
512         struct usb_device *udev = hcd->self.root_hub;
513         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
514         struct ehci_regs __iomem *hw = ehci->regs;
515         unsigned long val;
516         bool hsic;
517         bool null_ulpi;
518
519         null_ulpi = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI);
520         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
521
522         tegra_ehci_power_up(hcd, is_dpd);
523         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
524
525         if ((tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) || (hsic) ||
526             (null_ulpi))
527                 goto restart;
528
529         /* Force the phy to keep data lines in suspend state */
530         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
531
532         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
533                 (tegra->ehci->has_hostpc)) {
534                 ehci_reset(ehci);
535         }
536
537         /* Enable host mode */
538         tdi_reset(ehci);
539
540         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
541                 (tegra->ehci->has_hostpc)) {
542                 val = readl(hcd->regs + HOSTPC_REG_OFFSET);
543                 val &= ~HOSTPC1_DEVLC_PTS(~0);
544                 val |= HOSTPC1_DEVLC_STS;
545                 writel(val, hcd->regs + HOSTPC_REG_OFFSET);
546         }
547
548         /* Enable Port Power */
549         val = readl(&hw->port_status[0]);
550         val |= PORT_POWER;
551         writel(val, &hw->port_status[0]);
552         udelay(10);
553
554         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
555                 (tegra->ehci->has_hostpc) && (tegra->phy->remote_wakeup)) {
556                 ehci->command |= CMD_RUN;
557                 ehci_writel(ehci, ehci->command, &ehci->regs->command);
558         }
559
560         /* Check if the phy resume from LP0. When the phy resume from LP0
561          * USB register will be reset. */
562         if (!readl(&hw->async_next)) {
563                 /* Program the field PTC based on the saved speed mode */
564                 val = readl(&hw->port_status[0]);
565                 val &= ~PORT_TEST(~0);
566                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
567                         val |= PORT_TEST_FORCE;
568                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
569                         val |= PORT_TEST(6);
570                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
571                         val |= PORT_TEST(7);
572                 writel(val, &hw->port_status[0]);
573                 udelay(10);
574
575                 /* Disable test mode by setting PTC field to NORMAL_OP */
576                 val = readl(&hw->port_status[0]);
577                 val &= ~PORT_TEST(~0);
578                 writel(val, &hw->port_status[0]);
579                 udelay(10);
580         }
581
582         /* Poll until CCS is enabled */
583         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
584                                                  PORT_CONNECT, 2000)) {
585                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
586                 goto restart;
587         }
588
589         /* Poll until PE is enabled */
590         if (handshake(ehci, &hw->port_status[0], PORT_PE,
591                                                  PORT_PE, 2000)) {
592                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
593                 goto restart;
594         }
595
596         /* Clear the PCI status, to avoid an interrupt taken upon resume */
597         val = readl(&hw->status);
598         val |= STS_PCD;
599         writel(val, &hw->status);
600
601         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
602         val = readl(&hw->port_status[0]);
603         if ((val & PORT_POWER) && (val & PORT_PE)) {
604                 val |= PORT_SUSPEND;
605                 writel(val, &hw->port_status[0]);
606
607                 /* Need a 4ms delay before the controller goes to suspend */
608                 mdelay(4);
609
610                 /* Wait until port suspend completes */
611                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
612                                                          PORT_SUSPEND, 1000)) {
613                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
614                                                                 __func__);
615                         goto restart;
616                 }
617         }
618
619         tegra_ehci_phy_restore_end(tegra->phy);
620         return 0;
621
622 restart:
623         if (null_ulpi) {
624                 bool LP0 = !readl(&hw->async_next);
625
626                 if (LP0) {
627                         static int cnt = 1;
628
629                         pr_info("LP0 restart %d\n", cnt++);
630                         tegra_ehci_phy_restore_start(tegra->phy,
631                                                      tegra->port_speed);
632                 }
633
634                 val = readl(&hw->port_status[0]);
635                 if (!((val & PORT_POWER) && (val & PORT_PE))) {
636                         tegra_ehci_restart(hcd);
637                         usb_set_device_state(udev, USB_STATE_CONFIGURED);
638                 }
639
640                 if (LP0)
641                         tegra_ehci_phy_restore_end(tegra->phy);
642
643                 return 0;
644         }
645
646         if ((tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) && (!hsic))
647                 tegra_ehci_phy_restore_end(tegra->phy);
648         if (hsic) {
649                 val = readl(&hw->port_status[0]);
650                 if (!((val & PORT_POWER) && (val & PORT_PE))) {
651                         tegra_ehci_restart(hcd);
652                         usb_set_device_state(udev, USB_STATE_CONFIGURED);
653                 }
654                 tegra_usb_phy_bus_idle(tegra->phy);
655                 tegra->hsic_connect_retries = 0;
656                 if (!tegra_usb_phy_is_device_connected(tegra->phy))
657                         schedule_delayed_work(&tegra->work, 50);
658         } else {
659                 tegra_ehci_restart(hcd);
660         }
661
662         return 0;
663 }
664 #endif
665
666 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
667 {
668         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
669
670         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
671         /* ehci_shutdown touches the USB controller registers, make sure
672          * controller has clocks to it */
673         if (!tegra->host_resumed)
674                 tegra_ehci_power_up(hcd, false);
675
676         ehci_shutdown(hcd);
677
678         /* we are ready to shut down, powerdown the phy */
679         tegra_ehci_power_down(hcd, false);
680         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
681 }
682
683 static int tegra_ehci_setup(struct usb_hcd *hcd)
684 {
685         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
686         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
687         int retval;
688
689         /* EHCI registers start at offset 0x100 */
690         ehci->caps = hcd->regs + 0x100;
691         ehci->regs = hcd->regs + 0x100 +
692                 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
693
694         dbg_hcs_params(ehci, "reset");
695         dbg_hcc_params(ehci, "reset");
696
697         /* cache this readonly data; minimize chip reads */
698         ehci->hcs_params = readl(&ehci->caps->hcs_params);
699
700 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
701         ehci->has_hostpc = 1;
702 #endif
703         hcd->has_tt = 1;
704
705         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_NULL_ULPI) {
706                 ehci_reset(ehci);
707                 tegra_ehci_post_reset(tegra->phy, false);
708         }
709
710         retval = ehci_halt(ehci);
711         if (retval)
712                 return retval;
713
714         /* data structure init */
715         retval = ehci_init(hcd);
716         if (retval)
717                 return retval;
718
719         ehci->sbrn = 0x20;
720
721         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
722                 tegra_ehci_pre_reset(tegra->phy, false);
723                 ehci_reset(ehci);
724                 tegra_ehci_post_reset(tegra->phy, false);
725
726                 /*
727                  * Resetting the controller has the side effect of resetting the PHY.
728                  * So, never reset the controller after the calling
729                  * tegra_ehci_reinit API.
730                  */
731                 ehci->controller_resets_phy = 1;
732         }
733
734         ehci_port_power(ehci, 1);
735         return retval;
736 }
737
738 #ifdef CONFIG_PM
739 static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
740 {
741         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
742         int error_status = 0;
743
744         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
745         /* ehci_shutdown touches the USB controller registers, make sure
746          * controller has clocks to it */
747         if (!tegra->host_resumed)
748                 tegra_ehci_power_up(hcd, false);
749         error_status = ehci_bus_suspend(hcd);
750         if (!error_status && tegra->power_down_on_bus_suspend) {
751                 tegra_usb_suspend(hcd, false);
752                 tegra->bus_suspended = 1;
753         }
754         tegra_usb_phy_postsuspend(tegra->phy, false);
755         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
756
757         return error_status;
758 }
759
760 static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
761 {
762         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
763         int ehci_bus_resumed;
764
765         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
766         if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
767                 tegra_usb_resume(hcd, false);
768                 tegra->bus_suspended = 0;
769         }
770
771         ehci_bus_resumed = ehci_bus_resume(hcd);
772         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
773         return ehci_bus_resumed;
774 }
775 #endif
776
777 struct temp_buffer {
778         void *kmalloc_ptr;
779         void *old_xfer_buffer;
780         u8 data[0];
781 };
782
783 static void free_temp_buffer(struct urb *urb)
784 {
785         enum dma_data_direction dir;
786         struct temp_buffer *temp;
787
788         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
789                 return;
790
791         dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
792
793         temp = container_of(urb->transfer_buffer, struct temp_buffer,
794                             data);
795
796         if (dir == DMA_FROM_DEVICE)
797                 memcpy(temp->old_xfer_buffer, temp->data,
798                        urb->transfer_buffer_length);
799         urb->transfer_buffer = temp->old_xfer_buffer;
800         kfree(temp->kmalloc_ptr);
801
802         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
803 }
804
805 static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
806 {
807         enum dma_data_direction dir;
808         struct temp_buffer *temp, *kmalloc_ptr;
809         size_t kmalloc_size;
810
811         if (urb->num_sgs || urb->sg ||
812             urb->transfer_buffer_length == 0 ||
813             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
814                 return 0;
815
816         dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
817
818         /* Allocate a buffer with enough padding for alignment */
819         kmalloc_size = urb->transfer_buffer_length +
820                 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
821
822         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
823         if (!kmalloc_ptr)
824                 return -ENOMEM;
825
826         /* Position our struct temp_buffer such that data is aligned */
827         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
828
829         temp->kmalloc_ptr = kmalloc_ptr;
830         temp->old_xfer_buffer = urb->transfer_buffer;
831         if (dir == DMA_TO_DEVICE)
832                 memcpy(temp->data, urb->transfer_buffer,
833                        urb->transfer_buffer_length);
834         urb->transfer_buffer = temp->data;
835
836         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
837
838         return 0;
839 }
840
841 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
842                                       gfp_t mem_flags)
843 {
844         int ret;
845
846         ret = alloc_temp_buffer(urb, mem_flags);
847         if (ret)
848                 return ret;
849
850         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
851         if (ret)
852                 free_temp_buffer(urb);
853
854         return ret;
855 }
856
857 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
858 {
859         usb_hcd_unmap_urb_for_dma(hcd, urb);
860         free_temp_buffer(urb);
861 }
862
863 static void tegra_hsic_connection_work(struct work_struct *work)
864 {
865         struct tegra_ehci_hcd *tegra =
866                 container_of(work, struct tegra_ehci_hcd, work.work);
867         if (tegra_usb_phy_is_device_connected(tegra->phy)) {
868                 cancel_delayed_work(&tegra->work);
869                 return;
870         }
871         /* Few cases HSIC device may not be connected, so   *
872         ** skip this check after configured max re-tries.   */
873         if (tegra->hsic_connect_retries++ > TEGRA_HSIC_CONNECTION_MAX_RETRIES)
874                 return;
875
876         schedule_delayed_work(&tegra->work, jiffies + msecs_to_jiffies(50));
877         return;
878 }
879
880 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
881 /* Stored ehci handle for hsic insatnce */
882 struct usb_hcd *ehci_handle;
883 int ehci_tegra_irq;
884
885 static ssize_t show_ehci_power(struct device *dev,
886                         struct device_attribute *attr,
887                         char *buf)
888 {
889         return sprintf(buf, "EHCI Power %s\n", (ehci_handle) ? "on" : "off");
890 }
891
892 static ssize_t store_ehci_power(struct device *dev,
893                 struct device_attribute *attr,
894                 const char *buf, size_t count)
895 {
896         int power_on;
897         int retval;
898         struct tegra_ehci_hcd *tegra = dev_get_drvdata(dev);
899         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
900
901         if (sscanf(buf, "%d", &power_on) != 1)
902                 return -EINVAL;
903
904         if (power_on == 0 && ehci_handle != NULL) {
905                 usb_remove_hcd(hcd);
906                 tegra_ehci_power_down(hcd, false);
907                 ehci_handle = NULL;
908         } else if (power_on == 1) {
909                 if (ehci_handle)
910                         usb_remove_hcd(hcd);
911                 tegra_ehci_power_up(hcd, false);
912                 retval = usb_add_hcd(hcd, ehci_tegra_irq,
913                                         IRQF_DISABLED | IRQF_SHARED);
914                 if (retval < 0)
915                         printk(KERN_ERR "power_on error\n");
916                 ehci_handle = hcd;
917         }
918
919         return count;
920 }
921
922 static DEVICE_ATTR(ehci_power, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP,
923                 show_ehci_power, store_ehci_power);
924
925 static inline int create_ehci_sys_file(struct ehci_hcd *ehci)
926 {
927         return device_create_file(ehci_to_hcd(ehci)->self.controller,
928                                                         &dev_attr_ehci_power);
929 }
930
931 static inline void remove_ehci_sys_file(struct ehci_hcd *ehci)
932 {
933         device_remove_file(ehci_to_hcd(ehci)->self.controller,
934                                                 &dev_attr_ehci_power);
935 }
936
937 #endif
938
939 void clk_timer_callback(unsigned long data)
940 {
941         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd*) data;
942         unsigned long flags;
943
944         if (!timer_pending(&tegra->clk_timer)) {
945                 spin_lock_irqsave(&tegra->ehci->lock, flags);
946                 tegra->timer_event = 1;
947                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
948                 schedule_work(&tegra->clk_timer_work);
949         }
950 }
951
952 static void clk_timer_work_handler(struct work_struct* clk_timer_work) {
953         struct tegra_ehci_hcd *tegra = container_of(clk_timer_work,
954                                                 struct tegra_ehci_hcd, clk_timer_work);
955         int ret;
956         unsigned long flags;
957         bool clock_enabled, timer_event;
958
959         spin_lock_irqsave(&tegra->ehci->lock, flags);
960         clock_enabled = tegra->clock_enabled;
961         timer_event = tegra->timer_event;
962         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
963
964         if (timer_event) {
965                 spin_lock_irqsave(&tegra->ehci->lock, flags);
966                 tegra->clock_enabled = 0;
967                 tegra->timer_event = 0;
968                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
969                 clk_disable(tegra->emc_clk);
970                 clk_disable(tegra->sclk_clk);
971                 return;
972         }
973
974         if ((!clock_enabled)) {
975                 ret = mod_timer(&tegra->clk_timer, jiffies + msecs_to_jiffies(2000));
976                 if (ret)
977                         pr_err("tegra_ehci_urb_enqueue timer modify failed \n");
978                 clk_enable(tegra->emc_clk);
979                 clk_enable(tegra->sclk_clk);
980                 spin_lock_irqsave(&tegra->ehci->lock, flags);
981                 tegra->clock_enabled = 1;
982                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
983         } else {
984                 if (timer_pending(&tegra->clk_timer)) {
985                         mod_timer_pending (&tegra->clk_timer, jiffies
986                                                 + msecs_to_jiffies(2000));
987                 }
988         }
989 }
990
991 static int tegra_ehci_urb_enqueue (
992         struct usb_hcd  *hcd,
993         struct urb      *urb,
994         gfp_t           mem_flags)
995 {
996         struct tegra_ehci_hcd *pdata;
997         int xfertype;
998         int transfer_buffer_length;
999         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1000         unsigned long flags;
1001         pdata = dev_get_drvdata(hcd->self.controller);
1002
1003         xfertype = usb_endpoint_type(&urb->ep->desc);
1004         transfer_buffer_length = urb->transfer_buffer_length;
1005         spin_lock_irqsave(&ehci->lock,flags);
1006         /* Turn on the USB busy hints */
1007         switch (xfertype) {
1008                 case USB_ENDPOINT_XFER_INT:
1009                 if (transfer_buffer_length < 255) {
1010                 /* Do nothing for interrupt buffers < 255 */
1011                 } else {
1012                         /* signal to set the busy hints */
1013                         schedule_work(&pdata->clk_timer_work);
1014                 }
1015                 break;
1016                 case USB_ENDPOINT_XFER_ISOC:
1017                 case USB_ENDPOINT_XFER_BULK:
1018                         /* signal to set the busy hints */
1019                         schedule_work(&pdata->clk_timer_work);
1020                 break;
1021                 case USB_ENDPOINT_XFER_CONTROL:
1022                 default:
1023                         /* Do nothing special here */
1024                 break;
1025         }
1026         spin_unlock_irqrestore(&ehci->lock,flags);
1027         return ehci_urb_enqueue(hcd, urb, mem_flags);
1028 }
1029
1030 static const struct hc_driver tegra_ehci_hc_driver = {
1031         .description            = hcd_name,
1032         .product_desc           = "Tegra EHCI Host Controller",
1033         .hcd_priv_size          = sizeof(struct ehci_hcd),
1034
1035         .flags                  = HCD_USB2 | HCD_MEMORY,
1036
1037         .reset                  = tegra_ehci_setup,
1038         .irq                    = tegra_ehci_irq,
1039
1040         .start                  = ehci_run,
1041         .stop                   = ehci_stop,
1042         .shutdown               = tegra_ehci_shutdown,
1043         .urb_enqueue            = tegra_ehci_urb_enqueue,
1044         .urb_dequeue            = ehci_urb_dequeue,
1045         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
1046         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
1047         .endpoint_disable       = ehci_endpoint_disable,
1048         .endpoint_reset         = ehci_endpoint_reset,
1049         .get_frame_number       = ehci_get_frame,
1050         .hub_status_data        = ehci_hub_status_data,
1051         .hub_control            = tegra_ehci_hub_control,
1052         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1053 #ifdef CONFIG_PM
1054         .bus_suspend            = tegra_ehci_bus_suspend,
1055         .bus_resume             = tegra_ehci_bus_resume,
1056 #endif
1057         .relinquish_port        = ehci_relinquish_port,
1058         .port_handed_over       = ehci_port_handed_over,
1059 };
1060
1061 static int tegra_ehci_probe(struct platform_device *pdev)
1062 {
1063         struct resource *res;
1064         struct usb_hcd *hcd;
1065         struct tegra_ehci_hcd *tegra;
1066         struct tegra_ehci_platform_data *pdata;
1067         int err = 0;
1068         int irq;
1069         int instance = pdev->id;
1070
1071         pdata = pdev->dev.platform_data;
1072         if (!pdata) {
1073                 dev_err(&pdev->dev, "Platform data missing\n");
1074                 return -EINVAL;
1075         }
1076
1077         tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
1078         if (!tegra)
1079                 return -ENOMEM;
1080
1081         mutex_init(&tegra->tegra_ehci_hcd_mutex);
1082
1083         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
1084                                         dev_name(&pdev->dev));
1085         if (!hcd) {
1086                 dev_err(&pdev->dev, "Unable to create HCD\n");
1087                 err = -ENOMEM;
1088                 goto fail_hcd;
1089         }
1090
1091         platform_set_drvdata(pdev, tegra);
1092
1093         tegra->clk = clk_get(&pdev->dev, NULL);
1094         if (IS_ERR(tegra->clk)) {
1095                 dev_err(&pdev->dev, "Can't get ehci clock\n");
1096                 err = PTR_ERR(tegra->clk);
1097                 goto fail_clk;
1098         }
1099
1100         err = clk_enable(tegra->clk);
1101         if (err)
1102                 goto fail_clken;
1103
1104
1105         tegra->sclk_clk = clk_get(&pdev->dev, "sclk");
1106         if (IS_ERR(tegra->sclk_clk)) {
1107                 dev_err(&pdev->dev, "Can't get sclk clock\n");
1108                 err = PTR_ERR(tegra->sclk_clk);
1109                 goto fail_sclk_clk;
1110         }
1111
1112         clk_set_rate(tegra->sclk_clk, 80000000);
1113
1114         tegra->emc_clk = clk_get(&pdev->dev, "emc");
1115         if (IS_ERR(tegra->emc_clk)) {
1116                 dev_err(&pdev->dev, "Can't get emc clock\n");
1117                 err = PTR_ERR(tegra->emc_clk);
1118                 goto fail_emc_clk;
1119         }
1120         init_timer(&tegra->clk_timer);
1121         tegra->clk_timer.function = clk_timer_callback;
1122         tegra->clk_timer.data = (unsigned long) tegra;
1123
1124 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1125         /* Set DDR busy hints to 150MHz. For Tegra 2x SOC, DDR rate is half of EMC rate */
1126         clk_set_rate(tegra->emc_clk, 300000000);
1127 #else
1128         /* Set DDR busy hints to 150MHz. For Tegra 3x SOC DDR rate equals to EMC rate */
1129         clk_set_rate(tegra->emc_clk, 150000000);
1130 #endif
1131
1132         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1133         if (!res) {
1134                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1135                 err = -ENXIO;
1136                 goto fail_io;
1137         }
1138         hcd->rsrc_start = res->start;
1139         hcd->rsrc_len = resource_size(res);
1140         hcd->regs = ioremap(res->start, resource_size(res));
1141         if (!hcd->regs) {
1142                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1143                 err = -ENOMEM;
1144                 goto fail_io;
1145         }
1146
1147         INIT_DELAYED_WORK(&tegra->work, tegra_hsic_connection_work);
1148
1149         INIT_WORK(&tegra->clk_timer_work, clk_timer_work_handler);
1150
1151         tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
1152                                         TEGRA_USB_PHY_MODE_HOST, pdata->phy_type);
1153         if (IS_ERR(tegra->phy)) {
1154                 dev_err(&pdev->dev, "Failed to open USB phy\n");
1155                 err = -ENXIO;
1156                 goto fail_phy;
1157         }
1158
1159         err = tegra_usb_phy_power_on(tegra->phy, true);
1160         if (err) {
1161                 dev_err(&pdev->dev, "Failed to power on the phy\n");
1162                 goto fail;
1163         }
1164
1165         tegra->host_resumed = 1;
1166         tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
1167         tegra->hotplug = pdata->hotplug;
1168         tegra->ehci = hcd_to_ehci(hcd);
1169
1170         irq = platform_get_irq(pdev, 0);
1171         if (!irq) {
1172                 dev_err(&pdev->dev, "Failed to get IRQ\n");
1173                 err = -ENODEV;
1174                 goto fail;
1175         }
1176         set_irq_flags(irq, IRQF_VALID);
1177
1178 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
1179         if (instance == 1) {
1180                 ehci_tegra_irq = irq;
1181                 create_ehci_sys_file(tegra->ehci);
1182         }
1183 #endif
1184
1185 #ifdef CONFIG_USB_OTG_UTILS
1186         if (pdata->operating_mode == TEGRA_USB_OTG) {
1187                 tegra->transceiver = otg_get_transceiver();
1188                 if (tegra->transceiver)
1189                         otg_set_host(tegra->transceiver, &hcd->self);
1190         }
1191 #endif
1192
1193         err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
1194         if (err) {
1195                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
1196                 goto fail;
1197         }
1198
1199 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
1200         if (instance == 1)
1201                 ehci_handle = hcd;
1202 #endif
1203         return err;
1204
1205 fail:
1206 #ifdef CONFIG_USB_OTG_UTILS
1207         if (tegra->transceiver) {
1208                 otg_set_host(tegra->transceiver, NULL);
1209                 otg_put_transceiver(tegra->transceiver);
1210         }
1211 #endif
1212         tegra_usb_phy_close(tegra->phy);
1213 fail_phy:
1214         iounmap(hcd->regs);
1215 fail_io:
1216         clk_disable(tegra->emc_clk);
1217         clk_put(tegra->emc_clk);
1218 fail_emc_clk:
1219         clk_disable(tegra->sclk_clk);
1220         clk_put(tegra->sclk_clk);
1221 fail_sclk_clk:
1222         clk_disable(tegra->clk);
1223 fail_clken:
1224         clk_put(tegra->clk);
1225 fail_clk:
1226         usb_put_hcd(hcd);
1227 fail_hcd:
1228         kfree(tegra);
1229         return err;
1230 }
1231
1232 #ifdef CONFIG_PM
1233 static int tegra_ehci_resume(struct platform_device *pdev)
1234 {
1235         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1236         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1237
1238         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1239 #ifdef CONFIG_USB_HOTPLUG
1240                 clk_enable(tegra->clk);
1241 #endif
1242                 return 0;
1243         }
1244
1245 #ifdef CONFIG_USB_HOTPLUG
1246         clk_enable(tegra->clk);
1247 #endif
1248         return tegra_usb_resume(hcd, true);
1249 }
1250
1251 static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
1252 {
1253         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1254         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1255         int ret;
1256
1257         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1258 #ifdef CONFIG_USB_HOTPLUG
1259                 clk_disable(tegra->clk);
1260 #endif
1261                 return 0;
1262         }
1263
1264         if (time_before(jiffies, tegra->ehci->next_statechange))
1265                 msleep(10);
1266
1267         ret = tegra_usb_suspend(hcd, true);
1268 #ifdef CONFIG_USB_HOTPLUG
1269         clk_disable(tegra->clk);
1270 #endif
1271         return ret;
1272 }
1273 #endif
1274
1275 static int tegra_ehci_remove(struct platform_device *pdev)
1276 {
1277         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1278         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1279
1280         if (tegra == NULL || hcd == NULL)
1281                 return -EINVAL;
1282         /* make sure controller is on as we will touch its registers */
1283         if (!tegra->host_resumed)
1284                 tegra_ehci_power_up(hcd, true);
1285
1286 #ifdef CONFIG_USB_OTG_UTILS
1287         if (tegra->transceiver) {
1288                 otg_set_host(tegra->transceiver, NULL);
1289                 otg_put_transceiver(tegra->transceiver);
1290         }
1291 #endif
1292
1293 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
1294         if (tegra->phy->instance == 1) {
1295                 remove_ehci_sys_file(hcd_to_ehci(hcd));
1296                 ehci_handle = NULL;
1297         }
1298 #endif
1299
1300         /* Turn Off Interrupts */
1301         ehci_writel(tegra->ehci, 0, &tegra->ehci->regs->intr_enable);
1302         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1303         usb_remove_hcd(hcd);
1304         usb_put_hcd(hcd);
1305         cancel_delayed_work(&tegra->work);
1306         tegra_usb_phy_power_off(tegra->phy, true);
1307         tegra_usb_phy_close(tegra->phy);
1308         iounmap(hcd->regs);
1309
1310         del_timer_sync(&tegra->clk_timer);
1311
1312         clk_disable(tegra->clk);
1313         clk_put(tegra->clk);
1314
1315         if (tegra->clock_enabled){
1316                 clk_disable(tegra->sclk_clk);
1317                 clk_disable(tegra->emc_clk);
1318         }
1319         clk_put(tegra->sclk_clk);
1320         clk_put(tegra->emc_clk);
1321
1322         kfree(tegra);
1323         return 0;
1324 }
1325
1326 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
1327 {
1328         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1329         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1330
1331         if (hcd->driver->shutdown)
1332                 hcd->driver->shutdown(hcd);
1333 }
1334
1335 static struct platform_driver tegra_ehci_driver = {
1336         .probe          = tegra_ehci_probe,
1337         .remove         = tegra_ehci_remove,
1338 #ifdef CONFIG_PM
1339         .suspend        = tegra_ehci_suspend,
1340         .resume         = tegra_ehci_resume,
1341 #endif
1342         .shutdown       = tegra_ehci_hcd_shutdown,
1343         .driver         = {
1344                 .name   = "tegra-ehci",
1345         }
1346 };