1df169df3602456d3e9f509f3e9618b9cad0f681
[linux-2.6.git] / drivers / usb / host / ehci-tegra.c
1 /*
2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2009 - 2011 NVIDIA Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/platform_data/tegra_usb.h>
22 #include <linux/irq.h>
23 #include <linux/usb/otg.h>
24 #include <mach/usb_phy.h>
25 #include <mach/iomap.h>
26
27 #define TEGRA_USB_PORTSC_PHCD           (1 << 23)
28
29 #define TEGRA_USB_SUSP_CTRL_OFFSET      0x400
30 #define TEGRA_USB_SUSP_CLR                      (1 << 5)
31 #define TEGRA_USB_PHY_CLK_VALID                 (1 << 7)
32 #define TEGRA_USB_SRT                           (1 << 25)
33 #define TEGRA_USB_PHY_CLK_VALID_INT_ENB         (1 << 9)
34 #define TEGRA_USB_PHY_CLK_VALID_INT_STS         (1 << 8)
35
36 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
37 #define TEGRA_USB_PORTSC1_OFFSET        0x184
38 #else
39 #define TEGRA_USB_PORTSC1_OFFSET        0x174
40 #endif
41 #define TEGRA_USB_PORTSC1_WKCN                  (1 << 20)
42
43 #define TEGRA_LVL2_CLK_GATE_OVRB        0xfc
44 #define TEGRA_USB2_CLK_OVR_ON                   (1 << 10)
45
46 #define TEGRA_USB_DMA_ALIGN 32
47
48 #define STS_SRI (1<<7)  /*      SOF Recieved    */
49
50 #define TEGRA_HSIC_CONNECTION_MAX_RETRIES 5
51 #define HOSTPC_REG_OFFSET               0x1b4
52
53 #define HOSTPC1_DEVLC_STS               (1 << 28)
54 #define HOSTPC1_DEVLC_PTS(x)            (((x) & 0x7) << 29)
55
56 struct tegra_ehci_hcd {
57         struct ehci_hcd *ehci;
58         struct tegra_usb_phy *phy;
59         struct clk *clk;
60         struct clk *emc_clk;
61         struct clk *sclk_clk;
62         struct otg_transceiver *transceiver;
63         int host_resumed;
64         int bus_suspended;
65         int port_resuming;
66         int power_down_on_bus_suspend;
67         int hotplug;
68         struct delayed_work work;
69         enum tegra_usb_phy_port_speed port_speed;
70         struct work_struct clk_timer_work;
71         struct timer_list clk_timer;
72         bool clock_enabled;
73         bool timer_event;
74         int hsic_connect_retries;
75         struct mutex tegra_ehci_hcd_mutex;
76 };
77
78 static void tegra_ehci_power_up(struct usb_hcd *hcd, bool is_dpd)
79 {
80         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
81
82 #ifndef CONFIG_USB_HOTPLUG
83         clk_enable(tegra->clk);
84 #endif
85         tegra_usb_phy_power_on(tegra->phy, is_dpd);
86         tegra->host_resumed = 1;
87 }
88
89 static void tegra_ehci_power_down(struct usb_hcd *hcd, bool is_dpd)
90 {
91         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
92
93         tegra->host_resumed = 0;
94         tegra_usb_phy_power_off(tegra->phy, is_dpd);
95 #ifndef CONFIG_USB_HOTPLUG
96         clk_disable(tegra->clk);
97 #endif
98 }
99
100 static int tegra_ehci_internal_port_reset(
101         struct ehci_hcd *ehci,
102         u32 __iomem     *portsc_reg
103 )
104 {
105         u32             temp;
106         unsigned long   flags;
107         int             retval = 0;
108         int             i, tries;
109         u32             saved_usbintr;
110
111         spin_lock_irqsave(&ehci->lock, flags);
112         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
113         /* disable USB interrupt */
114         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
115         spin_unlock_irqrestore(&ehci->lock, flags);
116
117         /*
118          * Here we have to do Port Reset at most twice for
119          * Port Enable bit to be set.
120          */
121         for (i = 0; i < 2; i++) {
122                 temp = ehci_readl(ehci, portsc_reg);
123                 temp |= PORT_RESET;
124                 ehci_writel(ehci, temp, portsc_reg);
125                 mdelay(10);
126                 temp &= ~PORT_RESET;
127                 ehci_writel(ehci, temp, portsc_reg);
128                 mdelay(1);
129                 tries = 100;
130                 do {
131                         mdelay(1);
132                         /*
133                          * Up to this point, Port Enable bit is
134                          * expected to be set after 2 ms waiting.
135                          * USB1 usually takes extra 45 ms, for safety,
136                          * we take 100 ms as timeout.
137                          */
138                         temp = ehci_readl(ehci, portsc_reg);
139                 } while (!(temp & PORT_PE) && tries--);
140                 if (temp & PORT_PE)
141                         break;
142         }
143         if (i == 2)
144                 retval = -ETIMEDOUT;
145
146         /*
147          * Clear Connect Status Change bit if it's set.
148          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
149          */
150         if (temp & PORT_CSC)
151                 ehci_writel(ehci, PORT_CSC, portsc_reg);
152
153         /*
154          * Write to clear any interrupt status bits that might be set
155          * during port reset.
156          */
157         temp = ehci_readl(ehci, &ehci->regs->status);
158         ehci_writel(ehci, temp, &ehci->regs->status);
159
160         /* restore original interrupt enable bits */
161         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
162         return retval;
163 }
164
165 static irqreturn_t tegra_ehci_irq (struct usb_hcd *hcd)
166 {
167         struct ehci_hcd *ehci = hcd_to_ehci (hcd);
168         struct ehci_regs __iomem *hw = ehci->regs;
169         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
170         u32 val;
171
172         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
173                 (tegra->ehci->has_hostpc)) {
174                 /* check if there is any remote wake event */
175                 if (tegra_usb_phy_is_remotewake_detected(tegra->phy)) {
176                         spin_lock (&ehci->lock);
177                         usb_hcd_resume_root_hub(hcd);
178                         spin_unlock (&ehci->lock);
179                 }
180         }
181         if (tegra->hotplug) {
182                 spin_lock(&ehci->lock);
183                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
184                 if ((val  & TEGRA_USB_PHY_CLK_VALID_INT_STS)) {
185                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB |
186                                 TEGRA_USB_PHY_CLK_VALID_INT_STS;
187                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
188
189                         val = readl(hcd->regs + TEGRA_USB_PORTSC1_OFFSET);
190                         val &= ~TEGRA_USB_PORTSC1_WKCN;
191                         writel(val , (hcd->regs + TEGRA_USB_PORTSC1_OFFSET));
192
193                         val = readl(&hw->status);
194                         if (!(val  & STS_PCD)) {
195                                 spin_unlock(&ehci->lock);
196                                 return 0;
197                         }
198                 }
199                 spin_unlock(&ehci->lock);
200         }
201         return ehci_irq(hcd);
202 }
203
204 static int tegra_ehci_hub_control(
205         struct usb_hcd  *hcd,
206         u16             typeReq,
207         u16             wValue,
208         u16             wIndex,
209         char            *buf,
210         u16             wLength
211 )
212 {
213         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
214         int             ports = HCS_N_PORTS(ehci->hcs_params);
215         u32             temp, status;
216         u32 __iomem     *status_reg;
217         u32             usbsts_reg;
218
219         unsigned long   flags;
220         int             retval = 0;
221         unsigned        selector;
222         struct          tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
223         bool            hsic = false;
224
225         if (!tegra->host_resumed) {
226                 if (buf)
227                         memset (buf, 0, wLength);
228                 return retval;
229         }
230
231         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
232
233         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
234
235         spin_lock_irqsave(&ehci->lock, flags);
236
237         /*
238          * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
239          * that are write on clear, by writing back the register read value, so
240          * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
241          */
242         if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
243                 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
244                 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
245                 goto done;
246         } else if (typeReq == GetPortStatus) {
247                 temp = ehci_readl(ehci, status_reg);
248                 if (tegra->port_resuming && !(temp & PORT_SUSPEND) &&
249                     time_after_eq(jiffies, ehci->reset_done[wIndex-1])) {
250                         /* Resume completed, re-enable disconnect detection */
251                         tegra->port_resuming = 0;
252                         clear_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
253                         ehci->reset_done[wIndex-1] = 0;
254                         tegra_usb_phy_postresume(tegra->phy, false);
255 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
256                         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
257                                 ehci->command |= CMD_RUN;
258                                 /*
259                                  * ehci run bit is disabled to avoid SOF.
260                                  * 2LS WAR is executed by now enable the run bit.
261                                  */
262                                 ehci_writel(ehci, ehci->command,
263                                         &ehci->regs->command);
264                         }
265 #endif
266                 }
267         } else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
268                 temp = ehci_readl(ehci, status_reg);
269                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
270                         retval = -EPIPE;
271                         goto done;
272                 }
273
274                 temp &= ~PORT_WKCONN_E;
275                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
276                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
277
278                 /* Need a 4ms delay before the controller goes to suspend */
279                 mdelay(4);
280
281                 /*
282                  * If a transaction is in progress, there may be a delay in
283                  * suspending the port. Poll until the port is suspended.
284                  */
285                 if (handshake(ehci, status_reg, PORT_SUSPEND,
286                                                 PORT_SUSPEND, 5000))
287                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
288
289                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
290
291                 tegra_usb_phy_postsuspend(tegra->phy, false);
292
293                 goto done;
294         }
295
296         /* For USB1 port we need to issue Port Reset twice internally */
297         if (tegra->phy->instance == 0 &&
298            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
299                 spin_unlock_irqrestore(&ehci->lock, flags);
300                 return tegra_ehci_internal_port_reset(ehci, status_reg);
301         }
302
303         /*
304          * Tegra host controller will time the resume operation to clear the bit
305          * when the port control state switches to HS or FS Idle. This behavior
306          * is different from EHCI where the host controller driver is required
307          * to set this bit to a zero after the resume duration is timed in the
308          * driver.
309          */
310         else if (typeReq == ClearPortFeature &&
311                                         wValue == USB_PORT_FEAT_SUSPEND) {
312                 temp = ehci_readl(ehci, status_reg);
313                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
314                         retval = -EPIPE;
315                         goto done;
316                 }
317
318                 if (!(temp & PORT_SUSPEND))
319                         goto done;
320
321                 tegra->port_resuming = 1;
322
323                 /* Disable disconnect detection during port resume */
324                 tegra_usb_phy_preresume(tegra->phy, false);
325 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
326                 if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP) {
327 #endif
328                 ehci_dbg(ehci, "%s:USBSTS = 0x%x", __func__,
329                         ehci_readl(ehci, &ehci->regs->status));
330                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
331                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
332                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
333                 udelay(20);
334
335                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
336                         pr_err("%s: timeout set for STS_SRI\n", __func__);
337
338                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
339                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
340
341                 if (handshake(ehci, &ehci->regs->status, STS_SRI, 0, 2000))
342                         pr_err("%s: timeout clear STS_SRI\n", __func__);
343
344                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
345                         pr_err("%s: timeout set STS_SRI\n", __func__);
346
347                 udelay(20);
348 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
349                 }
350 #endif
351                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
352                 /* start resume signaling */
353                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
354
355                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
356                 /* whoever resumes must GetPortStatus to complete it!! */
357                 goto done;
358         }
359
360         /* Handle port reset here */
361 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
362         if ((hsic) && (typeReq == SetPortFeature) &&
363                 ((wValue == USB_PORT_FEAT_RESET) || (wValue == USB_PORT_FEAT_POWER))) {
364 #else
365         if ((hsic) && (typeReq == SetPortFeature) &&
366                 (wValue == USB_PORT_FEAT_POWER)) {
367 #endif
368                 selector = wIndex >> 8;
369                 wIndex &= 0xff;
370                 if (!wIndex || wIndex > ports) {
371                         retval = -EPIPE;
372                         goto done;
373                 }
374                 wIndex--;
375                 status = 0;
376                 temp = ehci_readl(ehci, status_reg);
377                 if (temp & PORT_OWNER)
378                         goto done;
379                 temp &= ~PORT_RWC_BITS;
380
381                 switch (wValue) {
382 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
383                 case USB_PORT_FEAT_RESET:
384                 {
385                         if (temp & PORT_RESUME) {
386                                 retval = -EPIPE;
387                                 goto done;
388                         }
389                         /* line status bits may report this as low speed,
390                         * which can be fine if this root hub has a
391                         * transaction translator built in.
392                         */
393                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
394                                         && !ehci_is_TDI(ehci) && PORT_USB11 (temp)) {
395                                 ehci_dbg (ehci, "port %d low speed --> companion\n", wIndex + 1);
396                                 temp |= PORT_OWNER;
397                                 ehci_writel(ehci, temp, status_reg);
398                         } else {
399                                 ehci_vdbg(ehci, "port %d reset\n", wIndex + 1);
400                                 temp &= ~PORT_PE;
401                                 /*
402                                 * caller must wait, then call GetPortStatus
403                                 * usb 2.0 spec says 50 ms resets on root
404                                 */
405                                 ehci->reset_done[wIndex] = jiffies + msecs_to_jiffies(50);
406                                 ehci_writel(ehci, temp, status_reg);
407                                 if (hsic && (wIndex == 0))
408                                         tegra_usb_phy_bus_reset(tegra->phy);
409                         }
410
411                         break;
412                 }
413 #endif
414                 case USB_PORT_FEAT_POWER:
415                 {
416                         if (HCS_PPC(ehci->hcs_params))
417                                 ehci_writel(ehci, temp | PORT_POWER, status_reg);
418                         if (hsic && (wIndex == 0))
419                                 tegra_usb_phy_bus_connect(tegra->phy);
420                         break;
421                 }
422                 }
423                 goto done;
424         }
425
426         spin_unlock_irqrestore(&ehci->lock, flags);
427
428         /* Handle the hub control events here */
429         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
430 done:
431         spin_unlock_irqrestore(&ehci->lock, flags);
432         return retval;
433 }
434
435 #ifdef CONFIG_PM
436 static void tegra_ehci_restart(struct usb_hcd *hcd)
437 {
438         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
439         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
440         unsigned int temp;
441
442         ehci->controller_resets_phy = 0;
443         tegra_ehci_pre_reset(tegra->phy, false);
444         ehci_reset(ehci);
445         tegra_ehci_post_reset(tegra->phy, false);
446
447         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI)
448                 ehci->controller_resets_phy = 1;
449
450         /* setup the frame list and Async q heads */
451         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
452         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
453         /* setup the command register and set the controller in RUN mode */
454         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
455         ehci->command |= CMD_RUN;
456         ehci_writel(ehci, ehci->command, &ehci->regs->command);
457
458         /* Enable the root Port Power */
459         if (HCS_PPC(ehci->hcs_params)) {
460                 temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
461                 ehci_writel(ehci, temp | PORT_POWER, &ehci->regs->port_status[0]);
462         }
463
464         down_write(&ehci_cf_port_reset_rwsem);
465         hcd->state = HC_STATE_RUNNING;
466         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
467         /* flush posted writes */
468         ehci_readl(ehci, &ehci->regs->command);
469         up_write(&ehci_cf_port_reset_rwsem);
470
471         /* Turn On Interrupts */
472         ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
473 }
474
475 static int tegra_usb_suspend(struct usb_hcd *hcd, bool is_dpd)
476 {
477         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
478         struct ehci_regs __iomem *hw = tegra->ehci->regs;
479         unsigned long flags;
480         int hsic = 0;
481
482         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
483
484         spin_lock_irqsave(&tegra->ehci->lock, flags);
485
486         if (tegra->ehci->has_hostpc)
487                 tegra->port_speed = (readl(hcd->regs + HOSTPC_REG_OFFSET) >> 25) & 0x3;
488         else
489                 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
490         ehci_halt(tegra->ehci);
491 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
492         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
493                 /*
494                  * Ehci run bit is disabled by now read this into command variable
495                  * so that bus resume will not enable run bit immedialty.
496                  * this is required for 2LS WAR on UTMIP interface.
497                  */
498                 tegra->ehci->command = ehci_readl(tegra->ehci,
499                                                 &tegra->ehci->regs->command);
500         }
501 #endif
502
503         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
504
505         tegra_ehci_power_down(hcd, is_dpd);
506         return 0;
507 }
508
509 static int tegra_usb_resume(struct usb_hcd *hcd, bool is_dpd)
510 {
511         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
512         struct usb_device *udev = hcd->self.root_hub;
513         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
514         struct ehci_regs __iomem *hw = ehci->regs;
515         unsigned long val;
516         int hsic = 0;
517
518         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
519
520         tegra_ehci_power_up(hcd, is_dpd);
521         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
522
523         if ((tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) || (hsic))
524                 goto restart;
525
526         /* Force the phy to keep data lines in suspend state */
527         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
528
529         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
530                 (tegra->ehci->has_hostpc)) {
531                 ehci_reset(ehci);
532         }
533
534         /* Enable host mode */
535         tdi_reset(ehci);
536
537         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
538                 (tegra->ehci->has_hostpc)) {
539                 val = readl(hcd->regs + HOSTPC_REG_OFFSET);
540                 val &= ~HOSTPC1_DEVLC_PTS(~0);
541                 val |= HOSTPC1_DEVLC_STS;
542                 writel(val, hcd->regs + HOSTPC_REG_OFFSET);
543         }
544
545         /* Enable Port Power */
546         val = readl(&hw->port_status[0]);
547         val |= PORT_POWER;
548         writel(val, &hw->port_status[0]);
549         udelay(10);
550
551         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
552                 (tegra->ehci->has_hostpc) && (tegra->phy->remote_wakeup)) {
553                 ehci->command |= CMD_RUN;
554                 ehci_writel(ehci, ehci->command, &ehci->regs->command);
555         }
556
557         /* Check if the phy resume from LP0. When the phy resume from LP0
558          * USB register will be reset. */
559         if (!readl(&hw->async_next)) {
560                 /* Program the field PTC based on the saved speed mode */
561                 val = readl(&hw->port_status[0]);
562                 val &= ~PORT_TEST(~0);
563                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
564                         val |= PORT_TEST_FORCE;
565                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
566                         val |= PORT_TEST(6);
567                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
568                         val |= PORT_TEST(7);
569                 writel(val, &hw->port_status[0]);
570                 udelay(10);
571
572                 /* Disable test mode by setting PTC field to NORMAL_OP */
573                 val = readl(&hw->port_status[0]);
574                 val &= ~PORT_TEST(~0);
575                 writel(val, &hw->port_status[0]);
576                 udelay(10);
577         }
578
579         /* Poll until CCS is enabled */
580         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
581                                                  PORT_CONNECT, 2000)) {
582                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
583                 goto restart;
584         }
585
586         /* Poll until PE is enabled */
587         if (handshake(ehci, &hw->port_status[0], PORT_PE,
588                                                  PORT_PE, 2000)) {
589                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
590                 goto restart;
591         }
592
593         /* Clear the PCI status, to avoid an interrupt taken upon resume */
594         val = readl(&hw->status);
595         val |= STS_PCD;
596         writel(val, &hw->status);
597
598         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
599         val = readl(&hw->port_status[0]);
600         if ((val & PORT_POWER) && (val & PORT_PE)) {
601                 val |= PORT_SUSPEND;
602                 writel(val, &hw->port_status[0]);
603
604                 /* Need a 4ms delay before the controller goes to suspend */
605                 mdelay(4);
606
607                 /* Wait until port suspend completes */
608                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
609                                                          PORT_SUSPEND, 1000)) {
610                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
611                                                                 __func__);
612                         goto restart;
613                 }
614         }
615
616         tegra_ehci_phy_restore_end(tegra->phy);
617         return 0;
618
619 restart:
620         if ((tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) && (!hsic))
621                 tegra_ehci_phy_restore_end(tegra->phy);
622         if (hsic) {
623                 val = readl(&hw->port_status[0]);
624                 if (!((val & PORT_POWER) && (val & PORT_PE))) {
625                         tegra_ehci_restart(hcd);
626                         usb_set_device_state(udev, USB_STATE_CONFIGURED);
627                 }
628                 tegra_usb_phy_bus_idle(tegra->phy);
629                 tegra->hsic_connect_retries = 0;
630                 if (!tegra_usb_phy_is_device_connected(tegra->phy))
631                         schedule_delayed_work(&tegra->work, 50);
632         } else {
633                 tegra_ehci_restart(hcd);
634         }
635
636         return 0;
637 }
638 #endif
639
640 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
641 {
642         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
643
644         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
645         /* ehci_shutdown touches the USB controller registers, make sure
646          * controller has clocks to it */
647         if (!tegra->host_resumed)
648                 tegra_ehci_power_up(hcd, false);
649
650         ehci_shutdown(hcd);
651
652         /* we are ready to shut down, powerdown the phy */
653         tegra_ehci_power_down(hcd, false);
654         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
655 }
656
657 static int tegra_ehci_setup(struct usb_hcd *hcd)
658 {
659         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
660         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
661         int retval;
662
663         /* EHCI registers start at offset 0x100 */
664         ehci->caps = hcd->regs + 0x100;
665         ehci->regs = hcd->regs + 0x100 +
666                 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
667
668         dbg_hcs_params(ehci, "reset");
669         dbg_hcc_params(ehci, "reset");
670
671         /* cache this readonly data; minimize chip reads */
672         ehci->hcs_params = readl(&ehci->caps->hcs_params);
673
674 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
675         ehci->has_hostpc = 1;
676 #endif
677         hcd->has_tt = 1;
678
679         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_NULL_ULPI) {
680                 ehci_reset(ehci);
681                 tegra_ehci_post_reset(tegra->phy, false);
682         }
683
684         retval = ehci_halt(ehci);
685         if (retval)
686                 return retval;
687
688         /* data structure init */
689         retval = ehci_init(hcd);
690         if (retval)
691                 return retval;
692
693         ehci->sbrn = 0x20;
694
695         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
696                 tegra_ehci_pre_reset(tegra->phy, false);
697                 ehci_reset(ehci);
698                 tegra_ehci_post_reset(tegra->phy, false);
699
700                 /*
701                  * Resetting the controller has the side effect of resetting the PHY.
702                  * So, never reset the controller after the calling
703                  * tegra_ehci_reinit API.
704                  */
705                 ehci->controller_resets_phy = 1;
706         }
707
708         ehci_port_power(ehci, 1);
709         return retval;
710 }
711
712 #ifdef CONFIG_PM
713 static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
714 {
715         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
716         int error_status = 0;
717
718         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
719         /* ehci_shutdown touches the USB controller registers, make sure
720          * controller has clocks to it */
721         if (!tegra->host_resumed)
722                 tegra_ehci_power_up(hcd, false);
723         error_status = ehci_bus_suspend(hcd);
724         if (!error_status && tegra->power_down_on_bus_suspend) {
725                 tegra_usb_suspend(hcd, false);
726                 tegra->bus_suspended = 1;
727         }
728         tegra_usb_phy_postsuspend(tegra->phy, false);
729         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
730
731         return error_status;
732 }
733
734 static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
735 {
736         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
737         int ehci_bus_resumed;
738
739         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
740         if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
741                 tegra_usb_resume(hcd, false);
742                 tegra->bus_suspended = 0;
743         }
744
745         ehci_bus_resumed = ehci_bus_resume(hcd);
746         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
747         return ehci_bus_resumed;
748 }
749 #endif
750
751 struct temp_buffer {
752         void *kmalloc_ptr;
753         void *old_xfer_buffer;
754         u8 data[0];
755 };
756
757 static void free_temp_buffer(struct urb *urb)
758 {
759         enum dma_data_direction dir;
760         struct temp_buffer *temp;
761
762         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
763                 return;
764
765         dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
766
767         temp = container_of(urb->transfer_buffer, struct temp_buffer,
768                             data);
769
770         if (dir == DMA_FROM_DEVICE)
771                 memcpy(temp->old_xfer_buffer, temp->data,
772                        urb->transfer_buffer_length);
773         urb->transfer_buffer = temp->old_xfer_buffer;
774         kfree(temp->kmalloc_ptr);
775
776         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
777 }
778
779 static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
780 {
781         enum dma_data_direction dir;
782         struct temp_buffer *temp, *kmalloc_ptr;
783         size_t kmalloc_size;
784
785         if (urb->num_sgs || urb->sg ||
786             urb->transfer_buffer_length == 0 ||
787             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
788                 return 0;
789
790         dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
791
792         /* Allocate a buffer with enough padding for alignment */
793         kmalloc_size = urb->transfer_buffer_length +
794                 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
795
796         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
797         if (!kmalloc_ptr)
798                 return -ENOMEM;
799
800         /* Position our struct temp_buffer such that data is aligned */
801         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
802
803         temp->kmalloc_ptr = kmalloc_ptr;
804         temp->old_xfer_buffer = urb->transfer_buffer;
805         if (dir == DMA_TO_DEVICE)
806                 memcpy(temp->data, urb->transfer_buffer,
807                        urb->transfer_buffer_length);
808         urb->transfer_buffer = temp->data;
809
810         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
811
812         return 0;
813 }
814
815 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
816                                       gfp_t mem_flags)
817 {
818         int ret;
819
820         ret = alloc_temp_buffer(urb, mem_flags);
821         if (ret)
822                 return ret;
823
824         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
825         if (ret)
826                 free_temp_buffer(urb);
827
828         return ret;
829 }
830
831 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
832 {
833         usb_hcd_unmap_urb_for_dma(hcd, urb);
834         free_temp_buffer(urb);
835 }
836
837 static void tegra_hsic_connection_work(struct work_struct *work)
838 {
839         struct tegra_ehci_hcd *tegra =
840                 container_of(work, struct tegra_ehci_hcd, work.work);
841         if (tegra_usb_phy_is_device_connected(tegra->phy)) {
842                 cancel_delayed_work(&tegra->work);
843                 return;
844         }
845         /* Few cases HSIC device may not be connected, so   *
846         ** skip this check after configured max re-tries.   */
847         if (tegra->hsic_connect_retries++ > TEGRA_HSIC_CONNECTION_MAX_RETRIES)
848                 return;
849
850         schedule_delayed_work(&tegra->work, jiffies + msecs_to_jiffies(50));
851         return;
852 }
853
854 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
855 /* Stored ehci handle for hsic insatnce */
856 struct usb_hcd *ehci_handle;
857 int ehci_tegra_irq;
858
859 static ssize_t show_ehci_power(struct device *dev,
860                         struct device_attribute *attr,
861                         char *buf)
862 {
863         return sprintf(buf, "EHCI Power %s\n", (ehci_handle) ? "on" : "off");
864 }
865
866 static ssize_t store_ehci_power(struct device *dev,
867                 struct device_attribute *attr,
868                 const char *buf, size_t count)
869 {
870         int power_on;
871         int retval;
872         struct tegra_ehci_hcd *tegra = dev_get_drvdata(dev);
873         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
874
875         if (sscanf(buf, "%d", &power_on) != 1)
876                 return -EINVAL;
877
878         if (power_on == 0 && ehci_handle != NULL) {
879                 usb_remove_hcd(hcd);
880                 tegra_ehci_power_down(hcd, false);
881                 ehci_handle = NULL;
882         } else if (power_on == 1) {
883                 if (ehci_handle)
884                         usb_remove_hcd(hcd);
885                 tegra_ehci_power_up(hcd, false);
886                 retval = usb_add_hcd(hcd, ehci_tegra_irq,
887                                         IRQF_DISABLED | IRQF_SHARED);
888                 if (retval < 0)
889                         printk(KERN_ERR "power_on error\n");
890                 ehci_handle = hcd;
891         }
892
893         return count;
894 }
895
896 static DEVICE_ATTR(ehci_power, S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP,
897                 show_ehci_power, store_ehci_power);
898
899 static inline int create_ehci_sys_file(struct ehci_hcd *ehci)
900 {
901         return device_create_file(ehci_to_hcd(ehci)->self.controller,
902                                                         &dev_attr_ehci_power);
903 }
904
905 static inline void remove_ehci_sys_file(struct ehci_hcd *ehci)
906 {
907         device_remove_file(ehci_to_hcd(ehci)->self.controller,
908                                                 &dev_attr_ehci_power);
909 }
910
911 #endif
912
913 void clk_timer_callback(unsigned long data)
914 {
915         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd*) data;
916         unsigned long flags;
917
918         if (!timer_pending(&tegra->clk_timer)) {
919                 spin_lock_irqsave(&tegra->ehci->lock, flags);
920                 tegra->timer_event = 1;
921                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
922                 schedule_work(&tegra->clk_timer_work);
923         }
924 }
925
926 static void clk_timer_work_handler(struct work_struct* clk_timer_work) {
927         struct tegra_ehci_hcd *tegra = container_of(clk_timer_work,
928                                                 struct tegra_ehci_hcd, clk_timer_work);
929         int ret;
930         unsigned long flags;
931         bool clock_enabled, timer_event;
932
933         spin_lock_irqsave(&tegra->ehci->lock, flags);
934         clock_enabled = tegra->clock_enabled;
935         timer_event = tegra->timer_event;
936         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
937
938         if (timer_event) {
939                 spin_lock_irqsave(&tegra->ehci->lock, flags);
940                 tegra->clock_enabled = 0;
941                 tegra->timer_event = 0;
942                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
943                 clk_disable(tegra->emc_clk);
944                 clk_disable(tegra->sclk_clk);
945                 return;
946         }
947
948         if ((!clock_enabled)) {
949                 ret = mod_timer(&tegra->clk_timer, jiffies + msecs_to_jiffies(2000));
950                 if (ret)
951                         pr_err("tegra_ehci_urb_enqueue timer modify failed \n");
952                 clk_enable(tegra->emc_clk);
953                 clk_enable(tegra->sclk_clk);
954                 spin_lock_irqsave(&tegra->ehci->lock, flags);
955                 tegra->clock_enabled = 1;
956                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
957         } else {
958                 if (timer_pending(&tegra->clk_timer)) {
959                         mod_timer_pending (&tegra->clk_timer, jiffies
960                                                 + msecs_to_jiffies(2000));
961                 }
962         }
963 }
964
965 static int tegra_ehci_urb_enqueue (
966         struct usb_hcd  *hcd,
967         struct urb      *urb,
968         gfp_t           mem_flags)
969 {
970         struct tegra_ehci_hcd *pdata;
971         int xfertype;
972         int transfer_buffer_length;
973         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
974         unsigned long flags;
975         pdata = dev_get_drvdata(hcd->self.controller);
976
977         xfertype = usb_endpoint_type(&urb->ep->desc);
978         transfer_buffer_length = urb->transfer_buffer_length;
979         spin_lock_irqsave(&ehci->lock,flags);
980         /* Turn on the USB busy hints */
981         switch (xfertype) {
982                 case USB_ENDPOINT_XFER_INT:
983                 if (transfer_buffer_length < 255) {
984                 /* Do nothing for interrupt buffers < 255 */
985                 } else {
986                         /* signal to set the busy hints */
987                         schedule_work(&pdata->clk_timer_work);
988                 }
989                 break;
990                 case USB_ENDPOINT_XFER_ISOC:
991                 case USB_ENDPOINT_XFER_BULK:
992                         /* signal to set the busy hints */
993                         schedule_work(&pdata->clk_timer_work);
994                 break;
995                 case USB_ENDPOINT_XFER_CONTROL:
996                 default:
997                         /* Do nothing special here */
998                 break;
999         }
1000         spin_unlock_irqrestore(&ehci->lock,flags);
1001         return ehci_urb_enqueue(hcd, urb, mem_flags);
1002 }
1003
1004 static const struct hc_driver tegra_ehci_hc_driver = {
1005         .description            = hcd_name,
1006         .product_desc           = "Tegra EHCI Host Controller",
1007         .hcd_priv_size          = sizeof(struct ehci_hcd),
1008
1009         .flags                  = HCD_USB2 | HCD_MEMORY,
1010
1011         .reset                  = tegra_ehci_setup,
1012         .irq                    = tegra_ehci_irq,
1013
1014         .start                  = ehci_run,
1015         .stop                   = ehci_stop,
1016         .shutdown               = tegra_ehci_shutdown,
1017         .urb_enqueue            = tegra_ehci_urb_enqueue,
1018         .urb_dequeue            = ehci_urb_dequeue,
1019         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
1020         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
1021         .endpoint_disable       = ehci_endpoint_disable,
1022         .endpoint_reset         = ehci_endpoint_reset,
1023         .get_frame_number       = ehci_get_frame,
1024         .hub_status_data        = ehci_hub_status_data,
1025         .hub_control            = tegra_ehci_hub_control,
1026         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1027 #ifdef CONFIG_PM
1028         .bus_suspend            = tegra_ehci_bus_suspend,
1029         .bus_resume             = tegra_ehci_bus_resume,
1030 #endif
1031         .relinquish_port        = ehci_relinquish_port,
1032         .port_handed_over       = ehci_port_handed_over,
1033 };
1034
1035 static int tegra_ehci_probe(struct platform_device *pdev)
1036 {
1037         struct resource *res;
1038         struct usb_hcd *hcd;
1039         struct tegra_ehci_hcd *tegra;
1040         struct tegra_ehci_platform_data *pdata;
1041         int err = 0;
1042         int irq;
1043         int instance = pdev->id;
1044
1045         pdata = pdev->dev.platform_data;
1046         if (!pdata) {
1047                 dev_err(&pdev->dev, "Platform data missing\n");
1048                 return -EINVAL;
1049         }
1050
1051         tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
1052         if (!tegra)
1053                 return -ENOMEM;
1054
1055         mutex_init(&tegra->tegra_ehci_hcd_mutex);
1056
1057         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
1058                                         dev_name(&pdev->dev));
1059         if (!hcd) {
1060                 dev_err(&pdev->dev, "Unable to create HCD\n");
1061                 err = -ENOMEM;
1062                 goto fail_hcd;
1063         }
1064
1065         platform_set_drvdata(pdev, tegra);
1066
1067         tegra->clk = clk_get(&pdev->dev, NULL);
1068         if (IS_ERR(tegra->clk)) {
1069                 dev_err(&pdev->dev, "Can't get ehci clock\n");
1070                 err = PTR_ERR(tegra->clk);
1071                 goto fail_clk;
1072         }
1073
1074         err = clk_enable(tegra->clk);
1075         if (err)
1076                 goto fail_clken;
1077
1078
1079         tegra->sclk_clk = clk_get(&pdev->dev, "sclk");
1080         if (IS_ERR(tegra->sclk_clk)) {
1081                 dev_err(&pdev->dev, "Can't get sclk clock\n");
1082                 err = PTR_ERR(tegra->sclk_clk);
1083                 goto fail_sclk_clk;
1084         }
1085
1086         clk_set_rate(tegra->sclk_clk, 80000000);
1087
1088         tegra->emc_clk = clk_get(&pdev->dev, "emc");
1089         if (IS_ERR(tegra->emc_clk)) {
1090                 dev_err(&pdev->dev, "Can't get emc clock\n");
1091                 err = PTR_ERR(tegra->emc_clk);
1092                 goto fail_emc_clk;
1093         }
1094         init_timer(&tegra->clk_timer);
1095         tegra->clk_timer.function = clk_timer_callback;
1096         tegra->clk_timer.data = (unsigned long) tegra;
1097
1098 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1099         /* Set DDR busy hints to 150MHz. For Tegra 2x SOC, DDR rate is half of EMC rate */
1100         clk_set_rate(tegra->emc_clk, 300000000);
1101 #else
1102         /* Set DDR busy hints to 150MHz. For Tegra 3x SOC DDR rate equals to EMC rate */
1103         clk_set_rate(tegra->emc_clk, 150000000);
1104 #endif
1105
1106         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1107         if (!res) {
1108                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1109                 err = -ENXIO;
1110                 goto fail_io;
1111         }
1112         hcd->rsrc_start = res->start;
1113         hcd->rsrc_len = resource_size(res);
1114         hcd->regs = ioremap(res->start, resource_size(res));
1115         if (!hcd->regs) {
1116                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1117                 err = -ENOMEM;
1118                 goto fail_io;
1119         }
1120
1121         INIT_DELAYED_WORK(&tegra->work, tegra_hsic_connection_work);
1122
1123         INIT_WORK(&tegra->clk_timer_work, clk_timer_work_handler);
1124
1125         tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
1126                                         TEGRA_USB_PHY_MODE_HOST, pdata->phy_type);
1127         if (IS_ERR(tegra->phy)) {
1128                 dev_err(&pdev->dev, "Failed to open USB phy\n");
1129                 err = -ENXIO;
1130                 goto fail_phy;
1131         }
1132
1133         err = tegra_usb_phy_power_on(tegra->phy, true);
1134         if (err) {
1135                 dev_err(&pdev->dev, "Failed to power on the phy\n");
1136                 goto fail;
1137         }
1138
1139         tegra->host_resumed = 1;
1140         tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
1141         tegra->hotplug = pdata->hotplug;
1142         tegra->ehci = hcd_to_ehci(hcd);
1143
1144         irq = platform_get_irq(pdev, 0);
1145         if (!irq) {
1146                 dev_err(&pdev->dev, "Failed to get IRQ\n");
1147                 err = -ENODEV;
1148                 goto fail;
1149         }
1150         set_irq_flags(irq, IRQF_VALID);
1151
1152 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
1153         if (instance == 1) {
1154                 ehci_tegra_irq = irq;
1155                 create_ehci_sys_file(tegra->ehci);
1156         }
1157 #endif
1158
1159 #ifdef CONFIG_USB_OTG_UTILS
1160         if (pdata->operating_mode == TEGRA_USB_OTG) {
1161                 tegra->transceiver = otg_get_transceiver();
1162                 if (tegra->transceiver)
1163                         otg_set_host(tegra->transceiver, &hcd->self);
1164         }
1165 #endif
1166
1167         err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
1168         if (err) {
1169                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
1170                 goto fail;
1171         }
1172
1173 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
1174         if (instance == 1)
1175                 ehci_handle = hcd;
1176 #endif
1177         return err;
1178
1179 fail:
1180 #ifdef CONFIG_USB_OTG_UTILS
1181         if (tegra->transceiver) {
1182                 otg_set_host(tegra->transceiver, NULL);
1183                 otg_put_transceiver(tegra->transceiver);
1184         }
1185 #endif
1186         tegra_usb_phy_close(tegra->phy);
1187 fail_phy:
1188         iounmap(hcd->regs);
1189 fail_io:
1190         clk_disable(tegra->emc_clk);
1191         clk_put(tegra->emc_clk);
1192 fail_emc_clk:
1193         clk_disable(tegra->sclk_clk);
1194         clk_put(tegra->sclk_clk);
1195 fail_sclk_clk:
1196         clk_disable(tegra->clk);
1197 fail_clken:
1198         clk_put(tegra->clk);
1199 fail_clk:
1200         usb_put_hcd(hcd);
1201 fail_hcd:
1202         kfree(tegra);
1203         return err;
1204 }
1205
1206 #ifdef CONFIG_PM
1207 static int tegra_ehci_resume(struct platform_device *pdev)
1208 {
1209         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1210         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1211
1212         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1213 #ifdef CONFIG_USB_HOTPLUG
1214                 clk_enable(tegra->clk);
1215 #endif
1216                 return 0;
1217         }
1218
1219 #ifdef CONFIG_USB_HOTPLUG
1220         clk_enable(tegra->clk);
1221 #endif
1222         return tegra_usb_resume(hcd, true);
1223 }
1224
1225 static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
1226 {
1227         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1228         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1229         int ret;
1230
1231         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1232 #ifdef CONFIG_USB_HOTPLUG
1233                 clk_disable(tegra->clk);
1234 #endif
1235                 return 0;
1236         }
1237
1238         if (time_before(jiffies, tegra->ehci->next_statechange))
1239                 msleep(10);
1240
1241         ret = tegra_usb_suspend(hcd, true);
1242 #ifdef CONFIG_USB_HOTPLUG
1243         clk_disable(tegra->clk);
1244 #endif
1245         return ret;
1246 }
1247 #endif
1248
1249 static int tegra_ehci_remove(struct platform_device *pdev)
1250 {
1251         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1252         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1253
1254         if (tegra == NULL || hcd == NULL)
1255                 return -EINVAL;
1256         /* make sure controller is on as we will touch its registers */
1257         if (!tegra->host_resumed)
1258                 tegra_ehci_power_up(hcd, true);
1259
1260 #ifdef CONFIG_USB_OTG_UTILS
1261         if (tegra->transceiver) {
1262                 otg_set_host(tegra->transceiver, NULL);
1263                 otg_put_transceiver(tegra->transceiver);
1264         }
1265 #endif
1266
1267 #ifdef CONFIG_USB_EHCI_ONOFF_FEATURE
1268         if (tegra->phy->instance == 1) {
1269                 remove_ehci_sys_file(hcd_to_ehci(hcd));
1270                 ehci_handle = NULL;
1271         }
1272 #endif
1273
1274         /* Turn Off Interrupts */
1275         ehci_writel(tegra->ehci, 0, &tegra->ehci->regs->intr_enable);
1276         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1277         usb_remove_hcd(hcd);
1278         usb_put_hcd(hcd);
1279         cancel_delayed_work(&tegra->work);
1280         tegra_usb_phy_power_off(tegra->phy, true);
1281         tegra_usb_phy_close(tegra->phy);
1282         iounmap(hcd->regs);
1283
1284         del_timer_sync(&tegra->clk_timer);
1285
1286         clk_disable(tegra->clk);
1287         clk_put(tegra->clk);
1288
1289         if (tegra->clock_enabled){
1290                 clk_disable(tegra->sclk_clk);
1291                 clk_disable(tegra->emc_clk);
1292         }
1293         clk_put(tegra->sclk_clk);
1294         clk_put(tegra->emc_clk);
1295
1296         kfree(tegra);
1297         return 0;
1298 }
1299
1300 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
1301 {
1302         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1303         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1304
1305         if (hcd->driver->shutdown)
1306                 hcd->driver->shutdown(hcd);
1307 }
1308
1309 static struct platform_driver tegra_ehci_driver = {
1310         .probe          = tegra_ehci_probe,
1311         .remove         = tegra_ehci_remove,
1312 #ifdef CONFIG_PM
1313         .suspend        = tegra_ehci_suspend,
1314         .resume         = tegra_ehci_resume,
1315 #endif
1316         .shutdown       = tegra_ehci_hcd_shutdown,
1317         .driver         = {
1318                 .name   = "tegra-ehci",
1319         }
1320 };