usb: ehci: tegra: Fence read in unmap urb
[linux-2.6.git] / drivers / usb / host / ehci-tegra.c
1 /*
2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2009 - 2012 NVIDIA Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/platform_data/tegra_usb.h>
22 #include <linux/irq.h>
23 #include <linux/usb/otg.h>
24 #include <linux/gpio.h>
25 #include <linux/of.h>
26 #include <linux/of_gpio.h>
27
28 #include <mach/usb_phy.h>
29 #include <mach/iomap.h>
30
31 #define TEGRA_USB_PORTSC_PHCD           (1 << 23)
32
33 #define TEGRA_USB_SUSP_CTRL_OFFSET      0x400
34 #define TEGRA_USB_SUSP_CLR                      (1 << 5)
35 #define TEGRA_USB_PHY_CLK_VALID                 (1 << 7)
36 #define TEGRA_USB_SRT                           (1 << 25)
37 #define TEGRA_USB_PHY_CLK_VALID_INT_ENB         (1 << 9)
38 #define TEGRA_USB_PHY_CLK_VALID_INT_STS         (1 << 8)
39
40 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
41 #define TEGRA_USB_PORTSC1_OFFSET        0x184
42 #else
43 #define TEGRA_USB_PORTSC1_OFFSET        0x174
44 #endif
45 #define TEGRA_USB_PORTSC1_WKCN                  (1 << 20)
46
47 #define TEGRA_LVL2_CLK_GATE_OVRB        0xfc
48 #define TEGRA_USB2_CLK_OVR_ON                   (1 << 10)
49
50 #define TEGRA_USB_DMA_ALIGN 32
51
52 #define STS_SRI (1<<7)  /*      SOF Recieved    */
53
54 #define HOSTPC_REG_OFFSET               0x1b4
55
56 #define HOSTPC1_DEVLC_STS               (1 << 28)
57 #define HOSTPC1_DEVLC_PTS(x)            (((x) & 0x7) << 29)
58
59 #define USB1_PREFETCH_ID               6
60 #define USB2_PREFETCH_ID               18
61 #define USB3_PREFETCH_ID               17
62
63 struct tegra_ehci_hcd {
64         struct ehci_hcd *ehci;
65         struct tegra_usb_phy *phy;
66         struct clk *clk;
67         struct clk *emc_clk;
68         struct clk *sclk_clk;
69         struct usb_phy *transceiver;
70         int host_resumed;
71         int bus_suspended;
72         int port_resuming;
73         int power_down_on_bus_suspend;
74         int default_enable;
75         enum tegra_usb_phy_port_speed port_speed;
76         struct work_struct clk_timer_work;
77         struct timer_list clk_timer;
78         bool clock_enabled;
79         bool timer_event;
80         struct mutex tegra_ehci_hcd_mutex;
81         unsigned int irq;
82         bool bus_suspended_fail;
83 };
84
85 static void tegra_ehci_power_up(struct usb_hcd *hcd, bool is_dpd)
86 {
87         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
88
89         if (!tegra->default_enable)
90                 clk_enable(tegra->clk);
91         tegra_usb_phy_power_on(tegra->phy, is_dpd);
92         tegra->host_resumed = 1;
93 }
94
95 static void tegra_ehci_power_down(struct usb_hcd *hcd, bool is_dpd)
96 {
97         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
98
99         tegra->host_resumed = 0;
100         tegra_usb_phy_power_off(tegra->phy, is_dpd);
101         if (!tegra->default_enable)
102                 clk_disable(tegra->clk);
103 }
104
105 static int tegra_ehci_internal_port_reset(
106         struct ehci_hcd *ehci,
107         u32 __iomem     *portsc_reg
108 )
109 {
110         u32             temp;
111         unsigned long   flags;
112         int             retval = 0;
113         int             i, tries;
114         u32             saved_usbintr;
115
116         spin_lock_irqsave(&ehci->lock, flags);
117         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
118         /* disable USB interrupt */
119         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
120         spin_unlock_irqrestore(&ehci->lock, flags);
121
122         /*
123          * Here we have to do Port Reset at most twice for
124          * Port Enable bit to be set.
125          */
126         for (i = 0; i < 2; i++) {
127                 temp = ehci_readl(ehci, portsc_reg);
128                 temp |= PORT_RESET;
129                 ehci_writel(ehci, temp, portsc_reg);
130                 mdelay(10);
131                 temp &= ~PORT_RESET;
132                 ehci_writel(ehci, temp, portsc_reg);
133                 mdelay(1);
134                 tries = 100;
135                 do {
136                         mdelay(1);
137                         /*
138                          * Up to this point, Port Enable bit is
139                          * expected to be set after 2 ms waiting.
140                          * USB1 usually takes extra 45 ms, for safety,
141                          * we take 100 ms as timeout.
142                          */
143                         temp = ehci_readl(ehci, portsc_reg);
144                 } while (!(temp & PORT_PE) && tries--);
145                 if (temp & PORT_PE)
146                         break;
147         }
148         if (i == 2)
149                 retval = -ETIMEDOUT;
150
151         /*
152          * Clear Connect Status Change bit if it's set.
153          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
154          */
155         if (temp & PORT_CSC)
156                 ehci_writel(ehci, PORT_CSC, portsc_reg);
157
158         /*
159          * Write to clear any interrupt status bits that might be set
160          * during port reset.
161          */
162         temp = ehci_readl(ehci, &ehci->regs->status);
163         ehci_writel(ehci, temp, &ehci->regs->status);
164
165         /* restore original interrupt enable bits */
166         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
167         return retval;
168 }
169
170 static irqreturn_t tegra_ehci_irq (struct usb_hcd *hcd)
171 {
172         struct ehci_hcd *ehci = hcd_to_ehci (hcd);
173         struct ehci_regs __iomem *hw = ehci->regs;
174         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
175         u32 val;
176         irqreturn_t irq_status;
177         bool pmc_remote_wakeup = false;
178
179         /* Fence read for coherency of AHB master intiated writes */
180         if (tegra->phy->instance == 0)
181                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
182         else if (tegra->phy->instance == 1)
183                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
184         else if (tegra->phy->instance == 2)
185                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
186
187         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
188                 (tegra->ehci->has_hostpc)) {
189                 /* check if there is any remote wake event */
190                 if (tegra_usb_phy_is_remotewake_detected(tegra->phy)) {
191                         pmc_remote_wakeup = true;
192                         spin_lock (&ehci->lock);
193                         usb_hcd_resume_root_hub(hcd);
194                         spin_unlock (&ehci->lock);
195                 }
196         }
197         if (tegra->phy->hotplug) {
198                 spin_lock(&ehci->lock);
199                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
200                 if ((val  & TEGRA_USB_PHY_CLK_VALID_INT_STS)) {
201                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB |
202                                 TEGRA_USB_PHY_CLK_VALID_INT_STS;
203                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
204
205                         val = readl(&hw->status);
206                         if (!(val  & STS_PCD)) {
207                                 spin_unlock(&ehci->lock);
208                                 return 0;
209                         }
210                         val = readl(hcd->regs + TEGRA_USB_PORTSC1_OFFSET);
211                         val &= ~(TEGRA_USB_PORTSC1_WKCN | PORT_RWC_BITS);
212                         writel(val , (hcd->regs + TEGRA_USB_PORTSC1_OFFSET));
213                 }
214                 spin_unlock(&ehci->lock);
215         }
216
217         irq_status = ehci_irq(hcd);
218
219         if (pmc_remote_wakeup) {
220                 ehci->controller_remote_wakeup = false;
221         }
222
223         if (ehci->controller_remote_wakeup) {
224                 ehci->controller_remote_wakeup = false;
225                 /* disable interrupts */
226                 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
227                 tegra_usb_phy_preresume(tegra->phy, true);
228                 tegra->port_resuming = 1;
229         }
230         return irq_status;
231 }
232
233 static int tegra_ehci_hub_control(
234         struct usb_hcd  *hcd,
235         u16             typeReq,
236         u16             wValue,
237         u16             wIndex,
238         char            *buf,
239         u16             wLength
240 )
241 {
242         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
243         int             ports = HCS_N_PORTS(ehci->hcs_params);
244         u32             temp, status, cmd_run;
245         u32 __iomem     *status_reg;
246         u32             usbsts_reg;
247
248         unsigned long   flags;
249         int             retval = 0;
250         unsigned        selector;
251         struct          tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
252         bool            hsic = false;
253
254         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
255         if (!tegra->host_resumed) {
256                 if (buf)
257                         memset (buf, 0, wLength);
258                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
259                 return retval;
260         }
261
262         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
263
264         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
265
266         spin_lock_irqsave(&ehci->lock, flags);
267
268         /*
269          * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
270          * that are write on clear, by writing back the register read value, so
271          * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
272          */
273         if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
274                 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
275                 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
276                 goto done;
277         } else if (typeReq == GetPortStatus) {
278                 temp = ehci_readl(ehci, status_reg);
279                 /* check port is in resume state */
280                 if (tegra->port_resuming) {
281                         int delay = ehci->reset_done[wIndex-1] - jiffies;
282                         /* Sometimes it seems we get called too soon... In that case, wait.*/
283                         if (delay > 0) {
284                                 ehci_dbg(ehci, "GetPortStatus called too soon, waiting %dms...\n", delay);
285                                 mdelay(jiffies_to_msecs(delay));
286                         }
287                         /* Ensure the port PORT_SUSPEND and PORT_RESUME has cleared */
288                         if (handshake(ehci, status_reg, (PORT_SUSPEND | PORT_RESUME), 0, 25000)) {
289                                 pr_err("%s: timeout waiting for SUSPEND to clear\n", __func__);
290                         }
291                         tegra->port_resuming = 0;
292                         tegra_usb_phy_postresume(tegra->phy, false);
293                         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
294                                 ehci->command |= CMD_RUN;
295                                 cmd_run = ehci_readl(ehci, &ehci->regs->command);
296                                 cmd_run |= CMD_RUN;
297                                 /*
298                                  * ehci run bit is disabled to avoid SOF.
299                                  * 2LS WAR is executed by now enable the run bit.
300                                  */
301                                 ehci_writel(ehci, cmd_run, &ehci->regs->command);
302                                 /* Now we can safely re-enable irqs */
303                                 ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
304                         }
305                 }
306
307         } else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
308                 temp = ehci_readl(ehci, status_reg);
309                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
310                         retval = -EPIPE;
311                         goto done;
312                 }
313
314                 temp &= ~PORT_WKCONN_E;
315                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
316                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
317
318                 /* Need a 4ms delay before the controller goes to suspend */
319                 mdelay(4);
320
321                 /*
322                  * If a transaction is in progress, there may be a delay in
323                  * suspending the port. Poll until the port is suspended.
324                  */
325                 if (handshake(ehci, status_reg, PORT_SUSPEND,
326                                                 PORT_SUSPEND, 5000))
327                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
328
329                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
330                 /*
331                  * If RUN bit is disabled interrupt is not generated after suspend.
332                  * This change on T20 will allow ASE interrupt generated after suspend
333                  * which will unlink the qheads.
334                  */
335 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
336                 if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
337                         /* Disable RUN bit. */
338                         ehci->command &= ~CMD_RUN;
339                         cmd_run = ehci_readl(ehci, &ehci->regs->command);
340                         cmd_run &= ~CMD_RUN;
341                         ehci_writel(ehci, cmd_run, &ehci->regs->command);
342                         if (handshake (ehci, &ehci->regs->status,
343                                                   STS_HALT, STS_HALT, 16 * 125))
344                                 pr_err("%s() timeout waiting for STS_HALT\n", __func__);
345                 }
346 #endif
347                 tegra_usb_phy_postsuspend(tegra->phy, false);
348
349                 goto done;
350         }
351
352         /* For USB1 port we need to issue Port Reset twice internally */
353         if (tegra->phy->instance == 0 &&
354            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
355                 spin_unlock_irqrestore(&ehci->lock, flags);
356                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
357                 return tegra_ehci_internal_port_reset(ehci, status_reg);
358         }
359
360         /*
361          * Tegra host controller will time the resume operation to clear the bit
362          * when the port control state switches to HS or FS Idle. This behavior
363          * is different from EHCI where the host controller driver is required
364          * to set this bit to a zero after the resume duration is timed in the
365          * driver.
366          */
367         else if (typeReq == ClearPortFeature &&
368                                         wValue == USB_PORT_FEAT_SUSPEND) {
369                 temp = ehci_readl(ehci, status_reg);
370                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
371                         retval = -EPIPE;
372                         goto done;
373                 }
374
375                 if (!(temp & PORT_SUSPEND))
376                         goto done;
377
378                 tegra->port_resuming = 1;
379
380                 if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
381                         /* disable interrupts */
382                         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
383                         /* Disable RUN bit. */
384                         ehci->command &= ~CMD_RUN;
385                         cmd_run = ehci_readl(ehci, &ehci->regs->command);
386                         cmd_run &= ~CMD_RUN;
387                         ehci_writel(ehci, cmd_run, &ehci->regs->command);
388                         if (handshake (ehci, &ehci->regs->status,
389                                                   STS_HALT, STS_HALT, 16 * 125))
390                                 pr_err("%s() timeout waiting for STS_HALT\n", __func__);
391                 }
392
393                 /* Disable disconnect detection during port resume */
394                 tegra_usb_phy_preresume(tegra->phy, false);
395 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
396                 if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_UTMIP) {
397 #endif
398                 ehci_dbg(ehci, "%s:USBSTS = 0x%x", __func__,
399                         ehci_readl(ehci, &ehci->regs->status));
400                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
401                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
402                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
403                 udelay(20);
404
405                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
406                         pr_err("%s: timeout set for STS_SRI\n", __func__);
407
408                 usbsts_reg = ehci_readl(ehci, &ehci->regs->status);
409                 ehci_writel(ehci, usbsts_reg, &ehci->regs->status);
410
411                 if (handshake(ehci, &ehci->regs->status, STS_SRI, 0, 2000))
412                         pr_err("%s: timeout clear STS_SRI\n", __func__);
413
414                 if (handshake(ehci, &ehci->regs->status, STS_SRI, STS_SRI, 2000))
415                         pr_err("%s: timeout set STS_SRI\n", __func__);
416
417                 udelay(20);
418 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
419                 }
420 #endif
421                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
422                 /* start resume signaling */
423                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
424
425                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
426                 /* whoever resumes must GetPortStatus to complete it!! */
427                 goto done;
428         }
429
430         /* Handle port reset here */
431         if ((hsic) && (typeReq == SetPortFeature) &&
432                 ((wValue == USB_PORT_FEAT_RESET) || (wValue == USB_PORT_FEAT_POWER))) {
433                 selector = wIndex >> 8;
434                 wIndex &= 0xff;
435                 if (!wIndex || wIndex > ports) {
436                         retval = -EPIPE;
437                         goto done;
438                 }
439                 wIndex--;
440                 status = 0;
441                 temp = ehci_readl(ehci, status_reg);
442                 if (temp & PORT_OWNER)
443                         goto done;
444                 temp &= ~PORT_RWC_BITS;
445
446                 switch (wValue) {
447                 case USB_PORT_FEAT_RESET:
448                 {
449                         if (temp & PORT_RESUME) {
450                                 retval = -EPIPE;
451                                 goto done;
452                         }
453                         /* line status bits may report this as low speed,
454                         * which can be fine if this root hub has a
455                         * transaction translator built in.
456                         */
457                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
458                                         && !ehci_is_TDI(ehci) && PORT_USB11 (temp)) {
459                                 ehci_dbg (ehci, "port %d low speed --> companion\n", wIndex + 1);
460                                 temp |= PORT_OWNER;
461                                 ehci_writel(ehci, temp, status_reg);
462                         } else {
463                                 ehci_vdbg(ehci, "port %d reset\n", wIndex + 1);
464                                 temp &= ~PORT_PE;
465                                 /*
466                                 * caller must wait, then call GetPortStatus
467                                 * usb 2.0 spec says 50 ms resets on root
468                                 */
469                                 ehci->reset_done[wIndex] = jiffies + msecs_to_jiffies(50);
470                                 ehci_writel(ehci, temp, status_reg);
471                                 if (hsic && (wIndex == 0))
472                                         tegra_usb_phy_bus_reset(tegra->phy);
473                         }
474
475                         break;
476                 }
477                 case USB_PORT_FEAT_POWER:
478                 {
479                         if (HCS_PPC(ehci->hcs_params))
480                                 ehci_writel(ehci, temp | PORT_POWER, status_reg);
481                         if (hsic && (wIndex == 0))
482                                 tegra_usb_phy_bus_connect(tegra->phy);
483                         break;
484                 }
485                 }
486                 goto done;
487         }
488
489         spin_unlock_irqrestore(&ehci->lock, flags);
490
491         /* Handle the hub control events here */
492         retval = ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
493         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
494         return retval;
495 done:
496         spin_unlock_irqrestore(&ehci->lock, flags);
497         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
498         return retval;
499 }
500
501 #ifdef CONFIG_PM
502 static void tegra_ehci_restart(struct usb_hcd *hcd, bool is_dpd)
503 {
504         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
505         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
506         unsigned int temp;
507
508         ehci->controller_resets_phy = 0;
509         tegra_ehci_pre_reset(tegra->phy, false);
510         ehci_reset(ehci);
511         tegra_ehci_post_reset(tegra->phy, false);
512
513         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI)
514                 ehci->controller_resets_phy = 1;
515
516         /* setup the frame list and Async q heads */
517         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
518         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
519         /* setup the command register and set the controller in RUN mode */
520         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
521 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
522         /* dont start RS here for HSIC, it will be set by bus_reset */
523         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_HSIC)
524 #endif
525                 ehci->command |= CMD_RUN;
526         ehci_writel(ehci, ehci->command, &ehci->regs->command);
527
528         /* Enable the root Port Power */
529         if (HCS_PPC(ehci->hcs_params)) {
530                 temp = ehci_readl(ehci, &ehci->regs->port_status[0]);
531                 ehci_writel(ehci, temp | PORT_POWER, &ehci->regs->port_status[0]);
532         }
533
534         down_write(&ehci_cf_port_reset_rwsem);
535         if(is_dpd)
536                 hcd->state = HC_STATE_SUSPENDED;
537         else
538                 hcd->state = HC_STATE_RUNNING;
539         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
540         /* flush posted writes */
541         ehci_readl(ehci, &ehci->regs->command);
542         up_write(&ehci_cf_port_reset_rwsem);
543
544         /* Turn On Interrupts */
545         ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
546 }
547
548 static int tegra_usb_suspend(struct usb_hcd *hcd, bool is_dpd)
549 {
550         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
551         struct ehci_regs __iomem *hw = tegra->ehci->regs;
552         unsigned long flags;
553         int hsic = 0;
554
555         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
556
557         spin_lock_irqsave(&tegra->ehci->lock, flags);
558
559         if (tegra->ehci->has_hostpc)
560                 tegra->port_speed = (readl(hcd->regs + HOSTPC_REG_OFFSET) >> 25) & 0x3;
561         else
562                 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
563         ehci_halt(tegra->ehci);
564 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
565         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
566                 /*
567                  * Ehci run bit is disabled by now read this into command variable
568                  * so that bus resume will not enable run bit immedialty.
569                  * this is required for 2LS WAR on UTMIP interface.
570                  */
571                 tegra->ehci->command = ehci_readl(tegra->ehci,
572                                                 &tegra->ehci->regs->command);
573         }
574 #endif
575
576         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
577
578         tegra_ehci_power_down(hcd, is_dpd);
579         return 0;
580 }
581
582 static int tegra_usb_resume(struct usb_hcd *hcd, bool is_dpd)
583 {
584         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
585         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
586         struct ehci_regs __iomem *hw = ehci->regs;
587         unsigned long val;
588         bool hsic;
589         bool null_ulpi;
590         bool utmip_remote_wakeup = false;
591
592         null_ulpi = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI);
593         hsic = (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_HSIC);
594
595         tegra_ehci_power_up(hcd, is_dpd);
596         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
597
598         if ((tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) || (hsic) ||
599             (null_ulpi))
600                 goto restart;
601
602         /* Force the phy to keep data lines in suspend state */
603         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
604
605         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) {
606                 ehci_reset(ehci);
607         }
608
609         /* Enable host mode */
610         tdi_reset(ehci);
611
612         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
613                 (tegra->ehci->has_hostpc)) {
614                 val = readl(hcd->regs + HOSTPC_REG_OFFSET);
615                 val &= ~HOSTPC1_DEVLC_PTS(~0);
616                 val |= HOSTPC1_DEVLC_STS;
617                 writel(val, hcd->regs + HOSTPC_REG_OFFSET);
618         }
619
620         /* Enable Port Power */
621         val = readl(&hw->port_status[0]);
622         val |= PORT_POWER;
623         writel(val, &hw->port_status[0]);
624         udelay(10);
625
626         if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
627                 (tegra->ehci->has_hostpc) && (tegra->phy->remote_wakeup)) {
628                 utmip_remote_wakeup = true;
629         }
630
631         /* Check if the phy resume from LP0. When the phy resume from LP0
632          * USB register will be reset. */
633         if (!readl(&hw->async_next)) {
634 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
635                 /* Start the controller */
636                 val = readl(&hw->command);
637                 writel((val | CMD_RUN), &hw->command);
638 #endif
639                 /* Program the field PTC based on the saved speed mode */
640                 val = readl(&hw->port_status[0]);
641                 val &= ~PORT_TEST(~0);
642                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
643                         val |= PORT_TEST_FORCE;
644                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
645                         val |= PORT_TEST(6);
646                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
647                         val |= PORT_TEST(7);
648                 writel(val, &hw->port_status[0]);
649                 udelay(10);
650
651                 /* Disable test mode by setting PTC field to NORMAL_OP */
652                 val = readl(&hw->port_status[0]);
653                 val &= ~PORT_TEST(~0);
654                 writel(val, &hw->port_status[0]);
655                 udelay(10);
656         }
657
658         /* Poll until CCS is enabled */
659         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
660                                                  PORT_CONNECT, 2000)) {
661                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
662                 goto restart;
663         }
664
665         /* Poll until PE is enabled */
666         if (handshake(ehci, &hw->port_status[0], PORT_PE,
667                                                  PORT_PE, 2000)) {
668                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
669                 goto restart;
670         }
671
672         /* Clear the PCI status, to avoid an interrupt taken upon resume */
673         val = readl(&hw->status);
674         val |= STS_PCD;
675         writel(val, &hw->status);
676
677         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
678         val = readl(&hw->port_status[0]);
679         if ((val & PORT_POWER) && (val & PORT_PE)) {
680                 val |= PORT_SUSPEND;
681                 writel(val, &hw->port_status[0]);
682
683                 /* Need a 4ms delay before the controller goes to suspend */
684                 mdelay(4);
685
686                 /* Wait until port suspend completes */
687                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
688                                                          PORT_SUSPEND, 1000)) {
689                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
690                                                                 __func__);
691                         goto restart;
692                 }
693         }
694
695         tegra_ehci_phy_restore_end(tegra->phy);
696         if (utmip_remote_wakeup) {
697                 ehci->command |= CMD_RUN;
698                 ehci_writel(ehci, ehci->command, &ehci->regs->command);
699         }
700         return 0;
701
702 restart:
703         if (null_ulpi) {
704                 bool LP0 = !readl(&hw->async_next);
705
706                 if (LP0) {
707                         static int cnt = 1;
708
709                         pr_info("LP0 restart %d\n", cnt++);
710                         tegra_ehci_phy_restore_start(tegra->phy,
711                                                      tegra->port_speed);
712                 }
713
714                 val = readl(&hw->port_status[0]);
715                 if (!((val & PORT_POWER) && (val & PORT_PE))) {
716                         tegra_ehci_restart(hcd, is_dpd);
717                 }
718
719                 if (LP0)
720                         tegra_ehci_phy_restore_end(tegra->phy);
721
722                 return 0;
723         }
724
725         if ((tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) && (!hsic))
726                 tegra_ehci_phy_restore_end(tegra->phy);
727         if (hsic) {
728                 val = readl(&hw->port_status[0]);
729                 if (!((val & PORT_POWER) && (val & PORT_PE)))
730                         tegra_ehci_restart(hcd, false);
731
732                 tegra_usb_phy_bus_idle(tegra->phy);
733                 if (!tegra_usb_phy_is_device_connected(tegra->phy))
734                         pr_err("%s: no hsic device conenction\n", __func__);
735         } else {
736                 tegra_ehci_restart(hcd, false);
737         }
738
739         return 0;
740 }
741 #endif
742
743 /*
744  * Disable PHY clock valid interrupts and wait for the interrupt handler to
745  * finish.
746  *
747  * Requires a lock on tegra_ehci_hcd_mutex
748  * Must not be called with a lock on ehci->lock
749  */
750 static void tegra_ehci_disable_phy_interrupt(struct usb_hcd *hcd) {
751         struct tegra_ehci_hcd *tegra;
752         u32 val;
753         if (hcd->irq >= 0) {
754                 tegra = dev_get_drvdata(hcd->self.controller);
755                 if (tegra->phy->hotplug) {
756                         /* Disable PHY clock valid interrupts */
757                         val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
758                         val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB;
759                         writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
760                 }
761                 /* Wait for the interrupt handler to finish */
762                 synchronize_irq(hcd->irq);
763         }
764 }
765
766 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
767 {
768         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
769
770         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
771         tegra_ehci_disable_phy_interrupt(hcd);
772         /* ehci_shutdown touches the USB controller registers, make sure
773          * controller has clocks to it */
774         if (!tegra->host_resumed)
775                 tegra_ehci_power_up(hcd, false);
776
777         ehci_shutdown(hcd);
778
779         /* we are ready to shut down, powerdown the phy */
780         tegra_ehci_power_down(hcd, false);
781         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
782 }
783
784 static int tegra_ehci_setup(struct usb_hcd *hcd)
785 {
786         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
787         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
788         int retval;
789
790         /* EHCI registers start at offset 0x100 */
791         ehci->caps = hcd->regs + 0x100;
792         ehci->regs = hcd->regs + 0x100 +
793                 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
794
795         dbg_hcs_params(ehci, "reset");
796         dbg_hcc_params(ehci, "reset");
797
798         /* cache this readonly data; minimize chip reads */
799         ehci->hcs_params = readl(&ehci->caps->hcs_params);
800
801 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
802         ehci->has_hostpc = 1;
803 #endif
804         hcd->has_tt = 1;
805
806         if (tegra->phy->usb_phy_type != TEGRA_USB_PHY_TYPE_NULL_ULPI) {
807                 ehci_reset(ehci);
808                 tegra_ehci_post_reset(tegra->phy, false);
809         }
810
811         retval = ehci_halt(ehci);
812         if (retval)
813                 return retval;
814
815         /* data structure init */
816         retval = ehci_init(hcd);
817         if (retval)
818                 return retval;
819
820         ehci->sbrn = 0x20;
821         ehci->controller_remote_wakeup = false;
822
823         if (tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_NULL_ULPI) {
824                 tegra_ehci_pre_reset(tegra->phy, false);
825                 ehci_reset(ehci);
826                 tegra_ehci_post_reset(tegra->phy, false);
827
828                 /*
829                  * Resetting the controller has the side effect of resetting the PHY.
830                  * So, never reset the controller after the calling
831                  * tegra_ehci_reinit API.
832                  */
833                 ehci->controller_resets_phy = 1;
834         }
835
836         ehci_port_power(ehci, 1);
837         return retval;
838 }
839
840 #ifdef CONFIG_PM
841 static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
842 {
843         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
844         int error_status = 0;
845
846         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
847         tegra->bus_suspended_fail = false;
848         tegra_ehci_disable_phy_interrupt(hcd);
849         /* ehci_shutdown touches the USB controller registers, make sure
850          * controller has clocks to it */
851         if (!tegra->host_resumed)
852                 tegra_ehci_power_up(hcd, false);
853         error_status = ehci_bus_suspend(hcd);
854         if (error_status)
855                 tegra->bus_suspended_fail = true;
856         if (!error_status && tegra->power_down_on_bus_suspend) {
857                 tegra_usb_suspend(hcd, false);
858                 tegra->bus_suspended = 1;
859         }
860         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
861
862         return error_status;
863 }
864
865 static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
866 {
867         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
868         int ehci_bus_resumed;
869
870         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
871         if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
872                 tegra_usb_resume(hcd, false);
873                 tegra->bus_suspended = 0;
874         }
875
876         ehci_bus_resumed = ehci_bus_resume(hcd);
877         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
878         return ehci_bus_resumed;
879 }
880 #endif
881
882 struct dma_aligned_buffer {
883         void *kmalloc_ptr;
884         void *old_xfer_buffer;
885         u8 data[0];
886 };
887
888 static void free_dma_aligned_buffer(struct urb *urb)
889 {
890         struct dma_aligned_buffer *temp = container_of(urb->transfer_buffer,
891                 struct dma_aligned_buffer, data);
892
893         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
894                 return;
895
896         if(usb_urb_dir_in(urb))
897                 memcpy(temp->old_xfer_buffer, temp->data,
898                        urb->transfer_buffer_length);
899         urb->transfer_buffer = temp->old_xfer_buffer;
900         kfree(temp->kmalloc_ptr);
901         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
902 }
903
904 static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
905 {
906         struct dma_aligned_buffer *temp, *kmalloc_ptr;
907         size_t kmalloc_size;
908
909         if (urb->num_sgs || urb->sg ||
910             urb->transfer_buffer_length == 0 ||
911             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
912                 return 0;
913
914         /* Allocate a buffer with enough padding for alignment */
915         kmalloc_size = urb->transfer_buffer_length +
916                 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
917
918         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
919         if (!kmalloc_ptr)
920                 return -ENOMEM;
921
922         /* Position our struct dma_aligned_buffer such that data is aligned */
923         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
924         temp->kmalloc_ptr = kmalloc_ptr;
925         temp->old_xfer_buffer = urb->transfer_buffer;
926         if (!usb_urb_dir_in(urb))
927                 memcpy(temp->data, urb->transfer_buffer,
928                        urb->transfer_buffer_length);
929         urb->transfer_buffer = temp->data;
930         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
931
932         return 0;
933 }
934
935 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
936                                       gfp_t mem_flags)
937 {
938         int ret;
939
940         ret = alloc_dma_aligned_buffer(urb, mem_flags);
941         if (ret)
942                 return ret;
943
944         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
945         if (ret)
946                 free_dma_aligned_buffer(urb);
947
948         return ret;
949 }
950
951 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
952 {
953         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
954
955         /* Fence read for coherency of AHB master intiated writes */
956         if (tegra->phy->instance == 0)
957                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
958         else if (tegra->phy->instance == 1)
959                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
960         else if (tegra->phy->instance == 2)
961                 readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
962
963         usb_hcd_unmap_urb_for_dma(hcd, urb);
964         free_dma_aligned_buffer(urb);
965 }
966
967 void clk_timer_callback(unsigned long data)
968 {
969         struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd*) data;
970         unsigned long flags;
971
972         if (!timer_pending(&tegra->clk_timer)) {
973                 spin_lock_irqsave(&tegra->ehci->lock, flags);
974                 tegra->timer_event = 1;
975                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
976                 schedule_work(&tegra->clk_timer_work);
977         }
978 }
979
980 static void clk_timer_work_handler(struct work_struct* clk_timer_work) {
981         struct tegra_ehci_hcd *tegra = container_of(clk_timer_work,
982                                                 struct tegra_ehci_hcd, clk_timer_work);
983         int ret;
984         unsigned long flags;
985         bool clock_enabled, timer_event;
986
987         spin_lock_irqsave(&tegra->ehci->lock, flags);
988         clock_enabled = tegra->clock_enabled;
989         timer_event = tegra->timer_event;
990         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
991
992         if (timer_event) {
993                 spin_lock_irqsave(&tegra->ehci->lock, flags);
994                 tegra->clock_enabled = 0;
995                 tegra->timer_event = 0;
996                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
997                 clk_disable(tegra->emc_clk);
998                 clk_disable(tegra->sclk_clk);
999                 return;
1000         }
1001
1002         if ((!clock_enabled)) {
1003                 ret = mod_timer(&tegra->clk_timer, jiffies + msecs_to_jiffies(2000));
1004                 if (ret)
1005                         pr_err("tegra_ehci_urb_enqueue timer modify failed \n");
1006                 clk_enable(tegra->emc_clk);
1007                 clk_enable(tegra->sclk_clk);
1008                 spin_lock_irqsave(&tegra->ehci->lock, flags);
1009                 tegra->clock_enabled = 1;
1010                 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
1011         } else {
1012                 if (timer_pending(&tegra->clk_timer)) {
1013                         mod_timer_pending (&tegra->clk_timer, jiffies
1014                                                 + msecs_to_jiffies(2000));
1015                 }
1016         }
1017 }
1018
1019 static int tegra_ehci_urb_enqueue (
1020         struct usb_hcd  *hcd,
1021         struct urb      *urb,
1022         gfp_t           mem_flags)
1023 {
1024         struct tegra_ehci_hcd *pdata;
1025         int xfertype;
1026         int transfer_buffer_length;
1027         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1028         unsigned long flags;
1029         pdata = dev_get_drvdata(hcd->self.controller);
1030
1031         xfertype = usb_endpoint_type(&urb->ep->desc);
1032         transfer_buffer_length = urb->transfer_buffer_length;
1033         spin_lock_irqsave(&ehci->lock,flags);
1034         /* Turn on the USB busy hints */
1035         switch (xfertype) {
1036                 case USB_ENDPOINT_XFER_INT:
1037                 if (transfer_buffer_length < 255) {
1038                 /* Do nothing for interrupt buffers < 255 */
1039                 } else {
1040                         /* signal to set the busy hints */
1041                         schedule_work(&pdata->clk_timer_work);
1042                 }
1043                 break;
1044                 case USB_ENDPOINT_XFER_ISOC:
1045                 case USB_ENDPOINT_XFER_BULK:
1046                         /* signal to set the busy hints */
1047                         schedule_work(&pdata->clk_timer_work);
1048                 break;
1049                 case USB_ENDPOINT_XFER_CONTROL:
1050                 default:
1051                         /* Do nothing special here */
1052                 break;
1053         }
1054         spin_unlock_irqrestore(&ehci->lock,flags);
1055         return ehci_urb_enqueue(hcd, urb, mem_flags);
1056 }
1057
1058 static const struct hc_driver tegra_ehci_hc_driver = {
1059         .description            = hcd_name,
1060         .product_desc           = "Tegra EHCI Host Controller",
1061         .hcd_priv_size          = sizeof(struct ehci_hcd),
1062         .flags                  = HCD_USB2 | HCD_MEMORY,
1063
1064         /* standard ehci functions */
1065         .start                  = ehci_run,
1066         .stop                   = ehci_stop,
1067         .urb_dequeue            = ehci_urb_dequeue,
1068         .endpoint_disable       = ehci_endpoint_disable,
1069         .endpoint_reset         = ehci_endpoint_reset,
1070         .get_frame_number       = ehci_get_frame,
1071         .hub_status_data        = ehci_hub_status_data,
1072         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1073         .relinquish_port        = ehci_relinquish_port,
1074         .port_handed_over       = ehci_port_handed_over,
1075
1076         /* modified ehci functions for tegra */
1077         .reset                  = tegra_ehci_setup,
1078         .irq                    = tegra_ehci_irq,
1079         .shutdown               = tegra_ehci_shutdown,
1080         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
1081         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
1082         .hub_control            = tegra_ehci_hub_control,
1083         .urb_enqueue            = tegra_ehci_urb_enqueue,
1084 #ifdef CONFIG_PM
1085         .bus_suspend            = tegra_ehci_bus_suspend,
1086         .bus_resume             = tegra_ehci_bus_resume,
1087 #endif
1088 };
1089
1090 static int setup_vbus_gpio(struct platform_device *pdev)
1091 {
1092         int err = 0;
1093         int gpio;
1094
1095         if (!pdev->dev.of_node)
1096                 return 0;
1097
1098         gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
1099         if (!gpio_is_valid(gpio))
1100                 return 0;
1101
1102         err = gpio_request(gpio, "vbus_gpio");
1103         if (err) {
1104                 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
1105                 return err;
1106         }
1107         err = gpio_direction_output(gpio, 1);
1108         if (err) {
1109                 dev_err(&pdev->dev, "can't enable vbus\n");
1110                 return err;
1111         }
1112         gpio_set_value(gpio, 1);
1113
1114         return err;
1115 }
1116
1117 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
1118
1119 static int tegra_ehci_probe(struct platform_device *pdev)
1120 {
1121         struct resource *res;
1122         struct usb_hcd *hcd;
1123         struct tegra_ehci_hcd *tegra;
1124         struct tegra_ehci_platform_data *pdata;
1125         int err = 0;
1126         int irq;
1127         int instance = pdev->id;
1128
1129         pdata = pdev->dev.platform_data;
1130         if (!pdata) {
1131                 dev_err(&pdev->dev, "Platform data missing\n");
1132                 return -EINVAL;
1133         }
1134
1135         /* Right now device-tree probed devices don't get dma_mask set.
1136          * Since shared usb code relies on it, set it here for now.
1137          * Once we have dma capability bindings this can go away.
1138          */
1139         if (!pdev->dev.dma_mask)
1140                 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
1141
1142         setup_vbus_gpio(pdev);
1143
1144         tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
1145         if (!tegra)
1146                 return -ENOMEM;
1147
1148         mutex_init(&tegra->tegra_ehci_hcd_mutex);
1149
1150         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
1151                                         dev_name(&pdev->dev));
1152         if (!hcd) {
1153                 dev_err(&pdev->dev, "Unable to create HCD\n");
1154                 err = -ENOMEM;
1155                 goto fail_hcd;
1156         }
1157
1158         platform_set_drvdata(pdev, tegra);
1159         tegra->default_enable = pdata->default_enable;
1160
1161         tegra->clk = clk_get(&pdev->dev, NULL);
1162         if (IS_ERR(tegra->clk)) {
1163                 dev_err(&pdev->dev, "Can't get ehci clock\n");
1164                 err = PTR_ERR(tegra->clk);
1165                 goto fail_clk;
1166         }
1167
1168         err = clk_enable(tegra->clk);
1169         if (err)
1170                 goto fail_clken;
1171
1172
1173         tegra->sclk_clk = clk_get(&pdev->dev, "sclk");
1174         if (IS_ERR(tegra->sclk_clk)) {
1175                 dev_err(&pdev->dev, "Can't get sclk clock\n");
1176                 err = PTR_ERR(tegra->sclk_clk);
1177                 goto fail_sclk_clk;
1178         }
1179
1180         clk_set_rate(tegra->sclk_clk, 80000000);
1181
1182         tegra->emc_clk = clk_get(&pdev->dev, "emc");
1183         if (IS_ERR(tegra->emc_clk)) {
1184                 dev_err(&pdev->dev, "Can't get emc clock\n");
1185                 err = PTR_ERR(tegra->emc_clk);
1186                 goto fail_emc_clk;
1187         }
1188         init_timer(&tegra->clk_timer);
1189         tegra->clk_timer.function = clk_timer_callback;
1190         tegra->clk_timer.data = (unsigned long) tegra;
1191
1192 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1193         /* Set DDR busy hints to 150MHz. For Tegra 2x SOC, DDR rate is half of EMC rate */
1194         clk_set_rate(tegra->emc_clk, 300000000);
1195 #else
1196         /* Set DDR busy hints to 100MHz. For Tegra 3x SOC DDR rate equals to EMC rate */
1197         clk_set_rate(tegra->emc_clk, 100000000);
1198 #endif
1199
1200         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201         if (!res) {
1202                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1203                 err = -ENXIO;
1204                 goto fail_io;
1205         }
1206         hcd->rsrc_start = res->start;
1207         hcd->rsrc_len = resource_size(res);
1208         hcd->regs = ioremap(res->start, resource_size(res));
1209         if (!hcd->regs) {
1210                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1211                 err = -ENOMEM;
1212                 goto fail_io;
1213         }
1214
1215         /* This is pretty ugly and needs to be fixed when we do only
1216          * device-tree probing. Old code relies on the platform_device
1217          * numbering that we lack for device-tree-instantiated devices.
1218          */
1219         if (instance < 0) {
1220                 switch (res->start) {
1221                 case TEGRA_USB_BASE:
1222                         instance = 0;
1223                         break;
1224                 case TEGRA_USB2_BASE:
1225                         instance = 1;
1226                         break;
1227                 case TEGRA_USB3_BASE:
1228                         instance = 2;
1229                         break;
1230                 default:
1231                         err = -ENODEV;
1232                         dev_err(&pdev->dev, "unknown usb instance\n");
1233                         goto fail_phy;
1234                 }
1235         }
1236
1237         INIT_WORK(&tegra->clk_timer_work, clk_timer_work_handler);
1238
1239         tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
1240                                         TEGRA_USB_PHY_MODE_HOST, pdata->phy_type);
1241         if (IS_ERR(tegra->phy)) {
1242                 dev_err(&pdev->dev, "Failed to open USB phy\n");
1243                 err = -ENXIO;
1244                 goto fail_phy;
1245         }
1246         tegra->phy->hotplug = pdata->hotplug;
1247
1248         err = tegra_usb_phy_power_on(tegra->phy, true);
1249         if (err) {
1250                 dev_err(&pdev->dev, "Failed to power on the phy\n");
1251                 goto fail;
1252         }
1253
1254         tegra->host_resumed = 1;
1255         tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
1256         tegra->ehci = hcd_to_ehci(hcd);
1257
1258         irq = platform_get_irq(pdev, 0);
1259         if (!irq) {
1260                 dev_err(&pdev->dev, "Failed to get IRQ\n");
1261                 err = -ENODEV;
1262                 goto fail;
1263         }
1264         set_irq_flags(irq, IRQF_VALID);
1265         tegra->irq = irq;
1266
1267 #ifdef CONFIG_USB_OTG_UTILS
1268         if (pdata->operating_mode == TEGRA_USB_OTG) {
1269                 tegra->transceiver = usb_get_transceiver();
1270                 if (tegra->transceiver)
1271                         otg_set_host(tegra->transceiver->otg, &hcd->self);
1272         }
1273 #endif
1274
1275         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
1276         if (err) {
1277                 dev_err(&pdev->dev, "Failed to add USB HCD error = %d\n", err);
1278                 goto fail;
1279         }
1280
1281         err = enable_irq_wake(tegra->irq);
1282         if (err < 0) {
1283                 dev_warn(&pdev->dev,
1284                         "Couldn't enable USB host mode wakeup, irq=%d, "
1285                         "error=%d\n", tegra->irq, err);
1286                 err = 0;
1287                 tegra->irq = 0;
1288         }
1289
1290         return err;
1291
1292 fail:
1293 #ifdef CONFIG_USB_OTG_UTILS
1294         if (tegra->transceiver) {
1295                 otg_set_host(tegra->transceiver->otg, NULL);
1296                 usb_put_transceiver(tegra->transceiver);
1297         }
1298 #endif
1299         tegra_usb_phy_close(tegra->phy);
1300 fail_phy:
1301         iounmap(hcd->regs);
1302 fail_io:
1303         clk_put(tegra->emc_clk);
1304 fail_emc_clk:
1305         clk_put(tegra->sclk_clk);
1306 fail_sclk_clk:
1307         clk_disable(tegra->clk);
1308 fail_clken:
1309         clk_put(tegra->clk);
1310 fail_clk:
1311         usb_put_hcd(hcd);
1312 fail_hcd:
1313         kfree(tegra);
1314         return err;
1315 }
1316
1317 #ifdef CONFIG_PM
1318 static int tegra_ehci_resume_noirq(struct device *dev)
1319 {
1320         struct platform_device *pdev = to_platform_device(dev);
1321         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1322         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1323         int ret;
1324
1325         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
1326         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1327                 if (tegra->default_enable)
1328                         clk_enable(tegra->clk);
1329                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1330                 return 0;
1331         }
1332
1333         if (tegra->default_enable)
1334                 clk_enable(tegra->clk);
1335
1336         ret = tegra_usb_resume(hcd, true);
1337         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1338         return ret;
1339 }
1340
1341 static int tegra_ehci_suspend_noirq(struct device *dev)
1342 {
1343         struct platform_device *pdev = to_platform_device(dev);
1344         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1345         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1346         int ret;
1347         u32 val;
1348
1349         mutex_lock(&tegra->tegra_ehci_hcd_mutex);
1350         /* if bus suspend is failed means there is remote wakeup resume,
1351                 then abort the PM suspend */
1352         if (tegra->bus_suspended_fail) {
1353                 tegra->bus_suspended_fail = false;
1354                 pr_err("%s: bus suspend failed, aborting driver suspend\n", __func__);
1355                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1356                 return -EBUSY;
1357         }
1358         if (tegra->phy->hotplug) {
1359                 /* Disable PHY clock valid interrupts while going into suspend*/
1360                 val = readl(hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET);
1361                 val &= ~TEGRA_USB_PHY_CLK_VALID_INT_ENB;
1362                 writel(val , (hcd->regs + TEGRA_USB_SUSP_CTRL_OFFSET));
1363         }
1364
1365         if ((tegra->bus_suspended) && (tegra->power_down_on_bus_suspend)) {
1366                 if (tegra->default_enable)
1367                         clk_disable(tegra->clk);
1368                 mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1369                 return 0;
1370         }
1371
1372         if (time_before(jiffies, tegra->ehci->next_statechange))
1373                 msleep(10);
1374
1375         ret = tegra_usb_suspend(hcd, true);
1376         if (tegra->default_enable)
1377                 clk_disable(tegra->clk);
1378         mutex_unlock(&tegra->tegra_ehci_hcd_mutex);
1379         return ret;
1380 }
1381
1382 static struct dev_pm_ops tegra_ehci_dev_pm_ops = {
1383         .suspend_noirq = tegra_ehci_suspend_noirq,
1384         .resume_noirq = tegra_ehci_resume_noirq,
1385 };
1386
1387 #endif
1388
1389 static int tegra_ehci_remove(struct platform_device *pdev)
1390 {
1391         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1392         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1393
1394         if (tegra == NULL || hcd == NULL)
1395                 return -EINVAL;
1396         /* make sure controller is on as we will touch its registers */
1397         if (!tegra->host_resumed)
1398                 tegra_ehci_power_up(hcd, true);
1399
1400 #ifdef CONFIG_USB_OTG_UTILS
1401         if (tegra->transceiver) {
1402                 otg_set_host(tegra->transceiver->otg, NULL);
1403                 usb_put_transceiver(tegra->transceiver);
1404         }
1405 #endif
1406
1407         /* Turn Off Interrupts */
1408         ehci_writel(tegra->ehci, 0, &tegra->ehci->regs->intr_enable);
1409         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1410         if (tegra->irq)
1411                 disable_irq_wake(tegra->irq);
1412         usb_remove_hcd(hcd);
1413         usb_put_hcd(hcd);
1414         tegra_usb_phy_power_off(tegra->phy, true);
1415         tegra_usb_phy_close(tegra->phy);
1416         iounmap(hcd->regs);
1417
1418         del_timer_sync(&tegra->clk_timer);
1419
1420         clk_disable(tegra->clk);
1421         clk_put(tegra->clk);
1422
1423         if (tegra->clock_enabled) {
1424                 clk_disable(tegra->sclk_clk);
1425                 clk_disable(tegra->emc_clk);
1426         }
1427         clk_put(tegra->sclk_clk);
1428         clk_put(tegra->emc_clk);
1429
1430         kfree(tegra);
1431         return 0;
1432 }
1433
1434 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
1435 {
1436         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
1437         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
1438
1439         if (hcd->driver->shutdown)
1440                 hcd->driver->shutdown(hcd);
1441 }
1442
1443 static struct of_device_id tegra_ehci_of_match[] __devinitdata = {
1444         { .compatible = "nvidia,tegra20-ehci", },
1445         { },
1446 };
1447
1448 static struct platform_driver tegra_ehci_driver = {
1449         .probe          = tegra_ehci_probe,
1450         .remove         = tegra_ehci_remove,
1451         .shutdown       = tegra_ehci_hcd_shutdown,
1452         .driver         = {
1453                 .name   = "tegra-ehci",
1454                 .of_match_table = tegra_ehci_of_match,
1455 #ifdef CONFIG_PM
1456                 .pm     = &tegra_ehci_dev_pm_ops,
1457 #endif
1458         }
1459 };